38909 lines
2.9 MiB
38909 lines
2.9 MiB
; --------------------------------------------------------------------------------
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; @Title: LPC181x/2x/3x/5x On-Chip Peripherals
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; @Props: Released
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; @Author: EMK, STR, TPP
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; @Changelog:
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; 2012-06-06
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; 2013-09-25
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: UM10430.pdf Rev. 1.3 - 2012-05-02
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; UM10430.pdf Rev 2.2 - 2013-01-25
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; @Core: Cortex-M3
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perlpc18xx.per 17736 2024-04-08 09:26:07Z kwisniewski $
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
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bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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textline " "
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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tree "CoreSight Identification Registers"
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width 6.
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "PID0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "PID1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "PID2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "PID3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "OTP (One-Time Programmable)"
|
|
base ad:0x40045000
|
|
width 10.
|
|
sif ((cpu()!="LPC4370FET100")&&(cpu()!="LPC4370FET256")&&(cpu()!="LPC4370FET100-M0")&&(cpu()!="LPC4370FET256-M0"))
|
|
group.long 0x10++0x1b
|
|
line.long 0x00 "OTPMB1W0,OTP memory bank 1,word 0"
|
|
line.long 0x04 "OTPMB1W1,OTP memory bank 1,word 1"
|
|
line.long 0x08 "OTPMB1W2,OTP memory bank 1,word 2"
|
|
line.long 0x0C "OTPMB1W3,OTP memory bank 1,word 3"
|
|
line.long 0x10 "OTPMB2W0,OTP memory bank 2,word 0"
|
|
line.long 0x14 "OTPMB2W1,OTP memory bank 2,word 1"
|
|
line.long 0x18 "OTPMB2W2,OTP memory bank 2,word 2"
|
|
sif (cpu()=="LPC1812"||cpu()=="LPC1813"||cpu()=="LPC1815"||cpu()=="LPC1817"||cpu()=="LPC1822"||cpu()=="LPC1823"||cpu()=="LPC1825"||cpu()=="LPC1827"||cpu()=="LPC1833"||cpu()=="LPC1837"||(cpu()=="LPC4312JBD144")||(cpu()=="LPC4312JET100")||(cpu()=="LPC4313JBD144")||(cpu()=="LPC4313JET100")||(cpu()=="LPC4315JBD144")||(cpu()=="LPC4315JET100")||(cpu()=="LPC4317JBD144")||(cpu()=="LPC4317JET100")||(cpu()=="LPC4312JBD144-M0")||(cpu()=="LPC4312JET100-M0")||(cpu()=="LPC4313JBD144-M0")||(cpu()=="LPC4313JET100-M0")||(cpu()=="LPC4315JBD144-M0")||(cpu()=="LPC4315JET100-M0")||(cpu()=="LPC4317JBD144-M0")||(cpu()=="LPC4317JET100-M0")||(cpu()=="LPC4322JBD144")||(cpu()=="LPC4322JET100")||(cpu()=="LPC4323JBD144")||(cpu()=="LPC4323JET100")||(cpu()=="LPC4325JBD144")||(cpu()=="LPC4325JET100")||(cpu()=="LPC4327JBD144")||(cpu()=="LPC4327JET100")||(cpu()=="LPC4322JBD144-M0")||(cpu()=="LPC4322JET100-M0")||(cpu()=="LPC4323JBD144-M0")||(cpu()=="LPC4323JET100-M0")||(cpu()=="LPC4325JBD144-M0")||(cpu()=="LPC4325JET100-M0")||(cpu()=="LPC4327JBD144-M0")||(cpu()=="LPC4327JET100-M0")||(cpu()=="LPC4333JBD144")||(cpu()=="LPC4333JET100")||(cpu()=="LPC4333JET256")||(cpu()=="LPC4337JBD144")||(cpu()=="LPC4337JET100")||(cpu()=="LPC4337JET256")||(cpu()=="LPC4333JBD144-M0")||(cpu()=="LPC4333JET100-M0")||(cpu()=="LPC4333JET256-M0")||(cpu()=="LPC4337JBD144-M0")||(cpu()=="LPC4337JET100-M0")||(cpu()=="LPC4337JET256-M0")||(cpu()=="LPC4353JBD208")||(cpu()=="LPC4353JET256")||(cpu()=="LPC4357JBD208")||(cpu()=="LPC4357JET256")||(cpu()=="LPC4353JBD208-M0")||(cpu()=="LPC4353JET256-M0")||(cpu()=="LPC4357JBD208-M0")||(cpu()=="LPC4357JET256-M0"))
|
|
group.long 0x2c++0x03
|
|
line.long 0x00 "OTPMB2W3,OTP memory bank 1,word 3"
|
|
endif
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "OTPMB3W0,OTP memory bank 3,word 0"
|
|
sif (cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850")
|
|
bitfld.long 0x00 31. " JTAG_DISABLE ,If this bit set JTAG cannot be enabled by software and remains disabled" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25.--28. " BOOT_SRC ,Boot source selection in OTP" "External pins,UART0,SPIFI,EMC 8-bit,EMC 16-bit,EMC 32-bit,USB0,USB1,SPI,UART3,?..."
|
|
bitfld.long 0x00 23. " USB_ID_ENABLE ,Setting this bit allows to enable OTP defined USB vendor and product IDs" "Disabled,Enabled"
|
|
line.long 0x04 "OTPMB3W1,OTP memory bank 3, word 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " USB_PRODUCT_ID ,USB product ID"
|
|
hexmask.long.word 0x04 0.--15. 1. " USB_VENDOR_ID ,USB vendor ID"
|
|
line.long 0x08 "OTPMB3W2,OTP memory bank 3, word 2"
|
|
sif (cpuis("LPC18*")||cpu()=="LPC1833"||cpu()=="LPC1837"||cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "OTPMB3W3,OTP memory bank 3,word 3"
|
|
endif
|
|
else
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "OTPMB3W1,OTP memory bank 3, word 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " USB_PRODUCT_ID ,USB product ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " USB_VENDOR_ID ,USB vendor ID"
|
|
line.long 0x04 "OTPMB3W2,OTP memory bank 3, word 2"
|
|
line.long 0x08 "OTPMB3W3,OTP memory bank 3,word 3"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E000
|
|
width 7.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ISER0,Interrupt Set-Enable 0 Register"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ISE_I2S1_set/clr ,I2S1 Interrup" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ISE_I2S0_set/clr ,I2S0 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ISE_USART3_set/clr ,USART3 and IrDA Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ISE_USART2_set/clr ,USART2 and IrDA Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ISE_UART1_set/clr ,UART and modem Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ISE_USART0_set/clr ,USART0 and IrDA Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ISE_SSP1_set/clr ,SSP1 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ISE_SSP0_set/clr ,SSP0 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ISE_ADC1_set/clr ,Analog-to-Digital Converter 1 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ISE_I2C1_set/clr ,I2C1 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ISE_I2C0_set/clr ,I2C0 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ISE_ADC0_set/clr ,Analog-to-Digital Converter 0 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ISE_MCPWM_set/clr ,Motor control PWM Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ISE_TIMER3_set/clr ,TIMER3 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ISE_TIMER2_set/clr ,TIMER2 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ISE_TIMER1_set/clr ,TIMER1 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ISE_TIMER0_set/clr ,TIMER0 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ISE_RITIMER_set/clr ,RITIMER Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ISE_SCT_set/clr ,SCT combined Interrupt" "Disabled,Enabled"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ISE_USB1_set/clr ,USB1 AHB_NEED_CLK Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?")||cpuis("LPC182?"))
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ISE_USB0_set/clr ,OTG Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC185?"))
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ISE_LCD_set/clr ,LCD Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ISE_SDIO_set/clr ,SD/MMC Interrupt" "Disabled,Enabled"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ISE_ETHERNET_set/clr ,Ethernet Interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ISE_FLASHEEPROM_set/clr ,ORed flash bank A/B/EEPROM interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ISE_DMA_set/clr ,Direct Memory Access Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ISE_DAC_set/clr ,Digital-to-Analog Converter Interrupt" "Disabled,Enabled"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ISER1,Interrupt Set-Enable 1 Register"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ISE_QEI_set/clr ,QEI Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ISE_C_CAN0_set/clr ,C_CAN0 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ISE_WWDT_set/clr ,WWDT Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ISE_RTC_set/clr ,Combined RTC and event router/monitor Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ISE_ATIMER_set/clr ,Alarm timer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ISE_C_CAN1_set/clr ,C_CAN1 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ISE_EVENT_ROUTER_set/clr ,Combined interrupt from the event router sources" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ISE_GINT1_set/clr ,GPIO global interrupt 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ISE_GINT0_set/clr ,GPIO global interrupt 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ISE_PIN_INT0_set/clr ,GPIO pin interrupt 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ISE_PIN_INT0_set/clr ,GPIO pin interrupt 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ISE_PIN_INT0_set/clr ,GPIO pin interrupt 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ISE_PIN_INT0_set/clr ,GPIO pin interrupt 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ISE_PIN_INT0_set/clr ,GPIO pin interrupt 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ISE_PIN_INT0_set/clr ,GPIO pin interrupt 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ISE_PIN_INT0_set/clr ,GPIO pin interrupt 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ISE_PIN_INT0_set/clr ,GPIO pin interrupt 0" "Disabled,Enabled"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "ISPR0,Interrupt Set-Pending Register 0 Register"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ISP_I2S1_set/clr ,I2S1 Interrup Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ISP_I2S0_set/clr ,I2S0 Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ISP_USART3_set/clr ,USART3 and IrDA Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ISP_USART2_set/clr ,USART2 and IrDA Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ISP_UART1_set/clr ,UART and modem Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ISP_USART0_set/clr ,USART0 and IrDA Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ISP_SSP1_set/clr ,SSP1 Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ISP_SSP0_set/clr ,SSP0 Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ISP_ADC1_set/clr ,Analog-to-Digital Converter 1 Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ISP_I2C1_set/clr ,I2C1 Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ISP_I2C0_set/clr ,I2C0 Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ISP_ADC0_set/clr ,Analog-to-Digital Converter 0 Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ISP_MCPWM_set/clr ,Motor control PWM Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ISP_TIMER3_set/clr ,TIMER3 Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ISP_TIMER2_set/clr ,TIMER2 Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ISP_TIMER1_set/clr ,TIMER1 Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ISP_TIMER0_set/clr ,TIMER0 Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ISP_RITIMER_set/clr ,RITIMER Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ISP_SCT_set/clr ,SCT combined Interrupt Pending" "Not pending,Pending"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ISP_USB1_set/clr ,USB1 AHB_NEED_CLK Interrupt Pending" "Not pending,Pending"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?")||cpuis("LPC182?"))
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ISP_USB0_set/clr ,OTG Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC185?"))
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ISP_LCD_set/clr ,LCD Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ISP_SDIO_set/clr ,SD/MMC Interrupt Pending" "Not pending,Pending"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ISP_ETHERNET_set/clr ,Ethernet Interrupt Pending" "Not pending,Pending"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ISP_FLASHEEPROM_set/clr ,ORed flash bank A/B/EEPROM interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ISP_DMA_set/clr ,Direct Memory Access Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ISP_DAC_set/clr ,Digital-to-Analog Converter Interrupt Pending" "Not pending,Pending"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ISPR1,Interrupt Set-Pending Register 1 Register"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ISP_QEI_set/clr ,QEI Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ISP_C_CAN0_set/clr ,C_CAN0 Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ISP_WWDT_set/clr ,WWDT Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ISP_RTC_set/clr ,Combined RTC and event router/monitor Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ISP_ATIMER_set/clr ,Alarm timer Interrupt Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ISP_C_CAN1_set/clr ,C_CAN1 Interrupt Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ISP_EVENT_ROUTER_set/clr ,Combined interrupt from the event router sources Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ISP_GINT1_set/clr ,GPIO global interrupt 1 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ISP_GINT0_set/clr ,GPIO global interrupt 0 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ISP_PIN_INT0_set/clr ,GPIO pin interrupt 7 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ISP_PIN_INT0_set/clr ,GPIO pin interrupt 6 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ISP_PIN_INT0_set/clr ,GPIO pin interrupt 5 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ISP_PIN_INT0_set/clr ,GPIO pin interrupt 4 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ISP_PIN_INT0_set/clr ,GPIO pin interrupt 3 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ISP_PIN_INT0_set/clr ,GPIO pin interrupt 2 Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ISP_PIN_INT0_set/clr ,GPIO pin interrupt 1 Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ISP_PIN_INT0_set/clr ,GPIO pin interrupt 0 Pending" "Not pending,Pending"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "IABR0,Interrupt Active Bit Register 0"
|
|
bitfld.long 0x00 29. " IAB_I2S1_set/clr ,I2S1 Interrup Active" "Not active,Active"
|
|
bitfld.long 0x00 28. " IAB_I2S0_set/clr ,I2S0 Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IAB_USART3_set/clr ,USART3 and IrDA Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 26. " IAB_USART2_set/clr ,USART2 and IrDA Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IAB_UART1_set/clr ,UART and modem Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 24. " IAB_USART0_set/clr ,USART0 and IrDA Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IAB_SSP1_set/clr ,SSP1 Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 22. " IAB_SSP0_set/clr ,SSP0 Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IAB_ADC1_set/clr ,Analog-to-Digital Converter 1 Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 19. " IAB_I2C1_set/clr ,I2C1 Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IAB_I2C0_set/clr ,I2C0 Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 17. " IAB_ADC0_set/clr ,Analog-to-Digital Converter 0 Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
bitfld.long 0x00 16. " IAB_MCPWM_set/clr ,Motor control PWM Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " IAB_TIMER3_set/clr ,TIMER3 Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 14. " IAB_TIMER2_set/clr ,TIMER2 Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 13. " IAB_TIMER1_set/clr ,TIMER1 Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IAB_TIMER0_set/clr ,TIMER0 Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 11. " IAB_RITIMER_set/clr ,RITIMER Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IAB_SCT_set/clr ,SCT combined Interrupt Active" "Not active,Active"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
textline " "
|
|
bitfld.long 0x00 9. " IAB_USB1_set/clr ,USB1 AHB_NEED_CLK Interrupt Active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?")||cpuis("LPC182?"))
|
|
bitfld.long 0x00 8. " IAB_USB0_set/clr ,OTG Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC185?"))
|
|
bitfld.long 0x00 7. " IAB_LCD_set/clr ,LCD Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " IAB_SDIO_set/clr ,SD/MMC Interrupt Active" "Not active,Active"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
textline " "
|
|
bitfld.long 0x00 5. " IAB_ETHERNET_set/clr ,Ethernet Interrupt Active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
bitfld.long 0x00 4. " IAB_FLASHEEPROM_set/clr ,ORed flash bank A/B/EEPROM interrupt Active" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " IAB_DMA_set/clr ,Direct Memory Access Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 0. " IAB_DAC_set/clr ,Digital-to-Analog Converter Interrupt Active" "Not active,Active"
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "IABR1,Interrupt Active Bit Register 1"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
bitfld.long 0x00 21. " IAB_QEI_set/clr ,QEI Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " IAB_C_CAN0_set/clr ,C_CAN0 Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IAB_WWDT_set/clr ,WWDT Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 15. " IAB_RTC_set/clr ,Combined RTC and event router/monitor Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 14. " IAB_ATIMER_set/clr ,Alarm timer Interrupt Active" "Not active,Active"
|
|
bitfld.long 0x00 11. " IAB_C_CAN1_set/clr ,C_CAN1 Interrupt Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IAB_EVENT_ROUTER_set/clr ,Combined interrupt from the event router sources Active" "Not active,Active"
|
|
bitfld.long 0x00 9. " IAB_GINT1_set/clr ,GPIO global interrupt 1 Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IAB_GINT0_set/clr ,GPIO global interrupt 0 Active" "Not active,Active"
|
|
bitfld.long 0x00 7. " IAB_PIN_INT0_set/clr ,GPIO pin interrupt 7 Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAB_PIN_INT0_set/clr ,GPIO pin interrupt 6 Active" "Not active,Active"
|
|
bitfld.long 0x00 5. " IAB_PIN_INT0_set/clr ,GPIO pin interrupt 5 Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IAB_PIN_INT0_set/clr ,GPIO pin interrupt 4 Active" "Not active,Active"
|
|
bitfld.long 0x00 3. " IAB_PIN_INT0_set/clr ,GPIO pin interrupt 3 Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IAB_PIN_INT0_set/clr ,GPIO pin interrupt 2 Active" "Not active,Active"
|
|
bitfld.long 0x00 1. " IAB_PIN_INT0_set/clr ,GPIO pin interrupt 1 Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IAB_PIN_INT0_set/clr ,GPIO pin interrupt 0 Active" "Not active,Active"
|
|
group.long 0x400++0x37
|
|
line.long 0x00 "IPR0,Interrupt Priority Register 0"
|
|
bitfld.long 0x00 21.--23. " IP_DMA ,Direct Memory Access Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 5.--7. " IP_DAC ,Digital-to-Analog Converter Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x04 "IPR1,Interrupt Priority Register 1"
|
|
sif (cpuis("LPC185?"))
|
|
bitfld.long 0x04 29.--31. " IP_LCD ,LCD Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 21.--23. " IP_SDIO ,SD/MMC Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
textline " "
|
|
bitfld.long 0x04 13.--15. " IP_ETHERNET ,Ethernet Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
endif
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
textline " "
|
|
bitfld.long 0x04 5.--7. " IP_FLASHEEPROM ,ORed flash bank A/B/EEPROM Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
endif
|
|
line.long 0x08 "IPR2,Interrupt Priority Register 2"
|
|
bitfld.long 0x08 29.--31. " IP_RITIMER ,RITIMER Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x08 21.--23. " IP_SCT ,SCT combined Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
bitfld.long 0x08 13.--15. " IP_USB1 ,USB1 AHB_NEED_CLK Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
endif
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?")||cpuis("LPC182?"))
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " IP_USB0 ,OTG Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
endif
|
|
line.long 0x0c "IPR3,Interrupt Priority Register 3"
|
|
bitfld.long 0x0c 29.--31. " IP_TIMER3 ,TIMER3 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x0c 21.--23. " IP_TIMER2 ,TIMER2 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x0c 13.--15. " IP_TIMER1 ,TIMER1 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x0c 5.--7. " IP_TIMER0 ,TIMER0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register 4"
|
|
bitfld.long 0x10 29.--31. " IP_I2C1 ,I2C1 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x10 21.--23. " IP_I2C0 ,I2C0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x10 13.--15. " IP_ADC0 ,Analog-to-Digital Converter 0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " IP_MCPWM ,Motor control PWM Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
endif
|
|
line.long 0x14 "IPR5,Interrupt Priority Register 5"
|
|
bitfld.long 0x14 29.--31. " IP_SSP1 ,SSP1 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x14 21.--23. " IP_SSP0 ,SSP0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x14 13.--15. " IP_ADC1 ,Analog-to-Digital Converter 1 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register 6"
|
|
bitfld.long 0x18 29.--31. " IP_USART3 ,USART3 and IrDA Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x18 21.--23. " IP_USART2 ,USART2 and IrDA Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x18 13.--15. " IP_UART1 ,UART1 and modem Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x18 5.--7. " IP_USART0 ,USART0 and IrDA Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x1c "IPR7 , Interrupt Priority Register 7"
|
|
bitfld.long 0x1c 13.--15. " IP_I2S1 ,I2S0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x1c 5.--7. " IP_I2S0 ,I2S0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x20 "IPR8, Interrupt Priority Register 8"
|
|
bitfld.long 0x20 29.--31. " IP_PIN_INT3 ,GPIO pin interrupt 0 Interrupt priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x20 21.--23. " IP_PIN_INT2 ,GPIO pin interrupt 2 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x20 13.--15. " IP_PIN_INT1 ,GPIO pin interrupt 1 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x20 5.--7. " IP_PIN_INT0 ,GPIO pin interrupt 0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x24 "IPR9, Interrupt Priority Register 9"
|
|
bitfld.long 0x24 29.--31. " IP_PIN_INT7 ,GPIO pin interrupt 7 Interrupt priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x24 21.--23. " IP_PIN_INT6 ,GPIO pin interrupt 6 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x24 13.--15. " IP_PIN_INT5 ,GPIO pin interrupt 5 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x24 5.--7. " IP_PIN_INT4 ,GPIO pin interrupt 4 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x28 "IPR10, Interrupt Priority Register 10"
|
|
bitfld.long 0x28 29.--31. " IP_C_CAN1 ,C_CAN1 Interrupt priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x28 21.--23. " IP_EVENT_ROUTER ,Combined interrupt from the event router sources Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x28 13.--15. " IP_GINT1 ,GPIO global interrupt 1 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x28 5.--7. " IP_GINT0 ,GPIO global interrupt 0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x2c "IPR11, Interrupt Priority Register 11"
|
|
bitfld.long 0x2c 29.--31. " IP_RTC ,RTC Interrupt priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x2c 21.--23. " IP_ATIMER ,Alarm timer Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x30 "IPR12, Interrupt Priority Register 12"
|
|
bitfld.long 0x30 21.--23. " IP_WWDT ,WWDT Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x30 13.--15. " IP_GINT1 ,GPIO global interrupt 1 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x34 "IPR13, Interrupt Priority Register 13"
|
|
sif (cpuis("LPC185?")||cpuis("LPC183?"))
|
|
bitfld.long 0x34 13.--15. " IP_QEI ,QEI Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 5.--7. " IP_C_CAN0 ,C_CAN0 Interrupt Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
wgroup.long 0xf00++0x3
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Generates an interrupt for the specified the interrupt number"
|
|
width 0xb
|
|
tree.end
|
|
tree "ER (Event router)"
|
|
base ad:0x40044000
|
|
width 8.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "HILO,Level configuration register"
|
|
bitfld.long 0x00 19. " RESET_L ,Level detect mode for Reset" "Low,High"
|
|
bitfld.long 0x00 16. " TIM14_L ,Level detect mode for combined timer output 14 event" "Low,High"
|
|
bitfld.long 0x00 15. " QEI_L ,Level detect mode for QEI event" "Low,High"
|
|
bitfld.long 0x00 14. " TIM6_L ,Level detect mode for combined timer output 6 event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TIM2_L ,Level detect mode for combined timer output 2 event" "Low,High"
|
|
bitfld.long 0x00 12. " CAN_L ,Level detect mode for C_CAN event" "Low,High"
|
|
bitfld.long 0x00 11. " SDMMC_L ,Level detect mode for SD/MMC event" "Low,High"
|
|
textline " "
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
bitfld.long 0x00 10. " USB1_L ,Level detect mode for USB1 event" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC182?")||cpuis("LPC183?")||cpuis("LPC185?"))
|
|
bitfld.long 0x00 9. " USB0_L ,Level detect mode for USB0 event" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
bitfld.long 0x00 8. " ETH_L ,Level detect mode for Ethernet event" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " WWDT_L ,Level detect mode for WWDT event" "Low,High"
|
|
bitfld.long 0x00 6. " BOD_L ,Level detect mode for BOD event" "Low,High"
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
bitfld.long 0x00 5. " RTC_L ,Level detect mode for RTC event" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ATIMER_L ,Level detect mode for alarm timer event" "Low,High"
|
|
bitfld.long 0x00 3. " WAKEUP3_L ,Level detect mode for WAKEUP3 event" "Low,High"
|
|
bitfld.long 0x00 2. " WAKEUP2_L ,Level detect mode for WAKEUP2 event" "Low,High"
|
|
bitfld.long 0x00 1. " WAKEUP1_L ,Level detect mode for WAKEUP1 event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKEUP0_L ,Level detect mode for WAKEUP0 event" "Low,High"
|
|
line.long 0x04 "EDGE,Edge configuration register"
|
|
bitfld.long 0x04 19. " RESET_E ,The corresponding bit in the EDGE register must be 0" "Level,Edge"
|
|
bitfld.long 0x04 16. " TIM14_E ,Edge/level detect mode for combined timer output 14" "Level,Edge"
|
|
bitfld.long 0x04 15. " QEI_E ,Edge/level detect mode for QEI interrupt signal" "Level,Edge"
|
|
bitfld.long 0x04 14. " TIM6_E ,Edge/level detect mode for combined timer output 6" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TIM2_E ,Edge/level detect mode for combined timer output 2" "Level,Edge"
|
|
bitfld.long 0x04 12. " CAN_E ,Edge/level detect mode for C_CAN event" "Level,Edge"
|
|
bitfld.long 0x04 11. " SDMMC_E ,Edge/level detect mode for SD/MMC event" "Level,Edge"
|
|
textline " "
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
bitfld.long 0x04 10. " USB1_E ,Edge/level detect mode for USB1 event" "Level,Edge"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC182?")||cpuis("LPC183?")||cpuis("LPC185?"))
|
|
bitfld.long 0x04 9. " USB0_E ,Edge/level detect mode for USB0 event" "Level,Edge"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
bitfld.long 0x04 8. " ETH_E ,Edge/level detect mode for ethernet event" "Level,Edge"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 7. " WWDT_E ,Edge/level detect mode for WWDTD event" "Level,Edge"
|
|
bitfld.long 0x04 6. " BOD_E ,Edge/level detect mode for BOD event" "Level,Edge"
|
|
textline " "
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
bitfld.long 0x04 5. " RTC_E ,Edge/level detect mode for RTC event" "Level,Edge"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " ATIMER_E ,Edge/level detect mode for alarm timer event" "Level,Edge"
|
|
bitfld.long 0x04 3. " WAKEUP3_E ,Edge/level detect mode for WAKEUP3 event" "Level,Edge"
|
|
bitfld.long 0x04 2. " WAKEUP2_E ,Edge/level detect mode for WAKEUP2 event" "Level,Edge"
|
|
bitfld.long 0x04 1. " WAKEUP1_E ,Edge/level detect mode for WAKEUP1 event" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAKEUP0_E ,Edge detect mode for WAKEUP0 event" "Level,Edge"
|
|
group.long 0xFE0++0x7
|
|
line.long 0x00 "STATUS,Event status register"
|
|
setclrfld.long 0x00 19. 0x0C 19. 0x08 19. " RESET_set/clr ,The reset event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 16. 0x0C 16. 0x08 16. " TIM14_set/clr ,The combined timer 14 output event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " QEI_set/clr ,QEI event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 14. 0x0C 14. 0x08 14. " TIM6_set/clr ,The combined timer 6 output event has been raised" "Not detected,Detected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " TIM2_set/clr ,The combined timer 2 output event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 12. 0x0C 12. 0x08 12. " CAN_set/clr ,C_CAN event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 11. 0x0C 11. 0x08 11. " SDMMC_set/clr ,SDMMC event has been raised" "Not detected,Detected"
|
|
textline " "
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
setclrfld.long 0x00 10. 0x0C 10. 0x08 10. " USB1_set/clr ,USB1 event has been raised" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC182?")||cpuis("LPC183?")||cpuis("LPC185?"))
|
|
setclrfld.long 0x00 9. 0x0C 9. 0x08 9. " USB0_set/clr ,USB0 event has been raised" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ETH_set/clr ,ETHERNET event has been raised" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " WWDT_set/clr ,WWDT event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " BOD_set/clr ,BOD event has been raised" "Not detected,Detected"
|
|
textline " "
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " RTC_set/clr ,RTC event has been raised" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 4. 0x0C 4. 0x08 4. " ATIMER_set/clr ,ATIMER event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 3. 0x0C 3. 0x08 3. " WAKEUP3_set/clr ,WAKEUP3 event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 2. 0x0C 2. 0x08 2. " WAKEUP2_set/clr ,WAKEUP2 event has been raised" "Not detected,Detected"
|
|
setclrfld.long 0x00 1. 0x0C 1. 0x08 1. " WAKEUP1_set/clr ,WAKEUP1 event has been raised" "Not detected,Detected"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x0C 0. 0x08 0. " WAKEUP0_set/clr ,WAKEUP0 event has been raised" "Not detected,Detected"
|
|
line.long 0x04 "ENABLE,Event enable register"
|
|
setclrfld.long 0x04 19. -0x04 19. -0x08 19. " RESET_set/clr ,The reset event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. -0x04 16. -0x08 16. " TIM14_set/clr ,The combined timer 14 output event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. -0x04 15. -0x08 15. " QEI_set/clr ,QEI event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. -0x04 14. -0x08 14. " TIM6_set/clr ,The combined timer 6 output event has been enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. -0x04 13. -0x08 13. " TIM2_set/clr ,The combined timer 2 output event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. -0x04 12. -0x08 12. " CAN_set/clr ,C_CAN event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. -0x04 11. -0x08 11. " SDMMC_set/clr ,SDMMC event has been enabled" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
setclrfld.long 0x04 10. -0x04 10. -0x08 10. " USB1_set/clr ,USB1 event has been enabled" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC182?")||cpuis("LPC183?")||cpuis("LPC185?"))
|
|
setclrfld.long 0x04 9. -0x04 9. -0x08 9. " USB0_set/clr ,USB0 event has been enabled" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
setclrfld.long 0x04 8. -0x04 8. -0x08 8. " ETH_set/clr ,ETHERNET event has been enabled" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x04 7. -0x04 7. -0x08 7. " WWDT_set/clr ,WWDT event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. -0x04 6. -0x08 6. " BOD_set/clr ,BOD event has been enabled" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
setclrfld.long 0x04 5. -0x04 5. -0x08 5. " RTC_set/clr ,RTC event has been enabled" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x04 4. -0x04 4. -0x08 4. " ATIMER_set/clr ,ATIMER event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. -0x04 3. -0x08 3. " WAKEUP3_set/clr ,WAKEUP3 event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. -0x04 2. -0x08 2. " WAKEUP2_set/clr ,WAKEUP2 event has been enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. -0x04 1. -0x08 1. " WAKEUP1_set/clr ,WAKEUP1 event has been enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 0. -0x04 0. -0x08 0. " WAKEUP0_set/clr ,WAKEUP0 event has been enabled" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "CREG (Configuration Registers)"
|
|
base ad:0x40043000
|
|
width 11.
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CREG0,CREG0 register"
|
|
bitfld.long 0x00 16.--17. " WAKEUP1CTRL ,WAKEUP1 pin input/output control" "Input to event router,Output from event router,Reserved,Input to event router"
|
|
bitfld.long 0x00 14.--15. " WAKEUP0CTRL ,WAKEUP0 pin input/output control" "Input to event router,Output from event router,Reserved,Input to event router"
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
bitfld.long 0x00 12.--13. " SAMPLECTRL ,SAMPLE pin input/output control" "Reserved,Output from event monitor/recorder,Output from event router,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " BODLVL2 ,BOD trip level to generate a reset" "Level 0,Level 1,Level 2,Level 3"
|
|
bitfld.long 0x00 8.--9. " BODLVL1 ,BOD trip level to generate an interrupt" "Level 0,Level 1,Level 2,Level 3"
|
|
bitfld.long 0x00 6.--7. " ALARMCTRL ,RTC_ALARM pin output control" "RTC alarm,Event router,Reserved,Inactive"
|
|
textline " "
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")||cpuis("LPC182*")
|
|
bitfld.long 0x00 5. " USB0PHY ,USB0 PHY power control" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PD32KHZ ,32 kHz power control" "Powered,Powered-down"
|
|
bitfld.long 0x00 2. " RESET32KHZ ,32 kHz oscillator reset" "Clear,Reset"
|
|
bitfld.long 0x00 1. " EN32KHZ ,Enable 32 kHz output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1KHZ ,Enable 1 kHz output" "Disabled,Enabled"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "M3MEMMAP,Memory mapping register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " M3MAP ,Shadow address when accessing memory at address 0x0000 0000"
|
|
group.long 0x118++0x07
|
|
line.long 0x00 "CREG5,CREG5 control register"
|
|
bitfld.long 0x00 6. " M3TAPSEL ,JTAG debug select" "Bypass,Enabled"
|
|
;section
|
|
line.long 0x04 "DMAMUX,DMA mux control register"
|
|
bitfld.long 0x04 30.--31. " DMAMUXPER15 ,Select DMA to peripheral connection for DMA peripheral 15" "DAC,SCT match 3,Reserved,Timer 3 match 0"
|
|
bitfld.long 0x04 28.--29. " DMAMUXPER14 ,Select DMA to peripheral connection for DMA peripheral 14" "ADC1,Reserved,SSP1 transmit,USART3 transmit"
|
|
bitfld.long 0x04 26.--27. " DMAMUXPER13 ,Select DMA to peripheral connection for DMA peripheral 13" "ADC0,Reserved,SSP1 receive,USART3 receive"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " DMAMUXPER12 ,Select DMA to peripheral connection for DMA peripheral 12" "SSP1 transmit,Reserved,USART0 receive,?..."
|
|
bitfld.long 0x04 22.--23. " DMAMUXPER11 ,Select DMA to peripheral connection for DMA peripheral 11" "SSP1 receive,Reserved,USART0 transmit,?..."
|
|
bitfld.long 0x04 20.--21. " DMAMUXPER10 ,Select DMA to peripheral connection for DMA peripheral 10" "SSP0 transmit,I2S0 DMA request 2,SCT DMA request 0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " DMAMUXPER9 ,Select DMA to peripheral connection for DMA peripheral 9" "SSP0 receive,I2S0 DMA request 1,SCT DMA request 1,?..."
|
|
bitfld.long 0x04 16.--17. " DMAMUXPER8 ,Select DMA to peripheral connection for DMA peripheral 8" "Timer 3 match 1,USART3 receive,SCT DMA request 1,?..."
|
|
bitfld.long 0x04 14.--15. " DMAMUXPER7 ,Select DMA to peripheral connection for DMA peripheral 7" "Timer 3 match 0,USART3 transmit,SCT DMA request 0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " DMAMUXPER6 ,Select DMA to peripheral connection for DMA peripheral 6" "Timer 2 match 1,USART2 receive,SSP1 receive,?..."
|
|
bitfld.long 0x04 10.--11. " DMAMUXPER5 ,Select DMA to peripheral connection for DMA peripheral 5" "Timer 2 match 0,USART2 transmit,SSP1 transmit,?..."
|
|
bitfld.long 0x04 8.--9. " DMAMUXPER4 ,Select DMA to peripheral connection for DMA peripheral 4" "Timer 1 match 1,UART1 receive,I2S1 DMA request 2,SSP1 receive"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " DMAMUXPER3 ,Select DMA to peripheral connection for DMA peripheral 3" "Timer 1 match 0,UART1 transmit,I2S1 DMA request 1,SSP1 transmit"
|
|
bitfld.long 0x04 4.--5. " DMAMUXPER2 ,Select DMA to peripheral connection for DMA peripheral 2" "Timer 0 match 1,USART0 receive,?..."
|
|
bitfld.long 0x04 2.--3. " DMAMUXPER1 ,Select DMA to peripheral connection for DMA peripheral 1" "Timer 0 match 0,USART0 transmit,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " DMAMUXPER0 ,Select DMA to peripheral connection for DMA peripheral 0" "SPIFI,SCT match 2,Reserved,T3 match 1"
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "FLASHCFGA,Flash Accelerator Configuration for flash bank A register"
|
|
bitfld.long 0x00 31. " POW ,Flash bank A power control" "Power-down,Active"
|
|
bitfld.long 0x00 12.--15. " FLASHTIM ,Flash access time" "1,2,3,4,5,6,7,8,9,?..."
|
|
sif (cpu()!="LPC1812"&&cpu()!="LPC1822")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "FLASHCFGB,Flash Accelerator Configuration for flash bank B register"
|
|
bitfld.long 0x00 31. " POW ,Flash bank B power control" "Power-down,Active"
|
|
bitfld.long 0x00 12.--15. " FLASHTIM ,Flash access time" "1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
endif
|
|
group.long 0x128++0x07
|
|
line.long 0x00 "ETBCFG,ETB SRAM configuration register"
|
|
bitfld.long 0x00 0. " ETB ,Select SRAM interface" "ETB,AHB"
|
|
;section
|
|
line.long 0x04 "CREG6,CREG6 control register"
|
|
bitfld.long 0x04 16. " EMC_CLK_SEL ,EMC_CLK divided clock select" "Not divided,Divided"
|
|
bitfld.long 0x04 15. " I2S1_RX_SCK_IN_SEL ,I2S1_RX_SCK input select" "I2S,Audio PLL"
|
|
bitfld.long 0x04 14. " I2S1_TX_SCK_IN_SEL ,I2S1_TX_SCK input select" "I2S,Audio PLL"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I2S0_RX_SCK_IN_SEL ,I2S0_RX_SCK input select" "I2S,Audio PLL"
|
|
bitfld.long 0x04 12. " I2S0_TX_SCK_IN_SEL ,I2S0_TX_SCK input select" "I2S,Audio PLL"
|
|
bitfld.long 0x04 4. " CTOUTCTRL ,Selects the functionality of the SCT output" "SCT and timer match outputs,SCT only"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " ETHMODE ,Selects the Ethernet mode" "MII,Reserved,Reserved,Reserved,RMII,?..."
|
|
endif
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "CHIPID,Part ID register"
|
|
sif (!cpuis("LPC181?")&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
;section
|
|
group.long 0x500++0x3
|
|
line.long 0x00 "USB0FLADJ,USB0 frame length adjust register"
|
|
bitfld.long 0x00 0.--5. " FLTV ,Frame length timing value" "59488,59504,59520,59536,59552,59568,59584,59600,59616,59632,59648,59664,59680,59696,59712,59728,59744,59760,59776,59792,59808,59824,59840,59856,59872,59888,59904,59920,59936,59952,59968,59984,60000,60016,60032,60048,60064,60080,60096,60112,60128,60144,60160,60176,60192,60208,60224,60240,60256,60272,60288,60304,60320,60336,60352,60368,60384,60400,60416,60432,60448,60464,60480,60496"
|
|
sif (!cpuis("LPC182?"))
|
|
group.long 0x600++0x3
|
|
line.long 0x00 "USB1FLADJ,USB1 frame length adjust register"
|
|
bitfld.long 0x00 0.--5. " FLTV ,Frame length timing value" "59488,59504,59520,59536,59552,59568,59584,59600,59616,59632,59648,59664,59680,59696,59712,59728,59744,59760,59776,59792,59808,59824,59840,59856,59872,59888,59904,59920,59936,59952,59968,59984,60000,60016,60032,60048,60064,60080,60096,60112,60128,60144,60160,60176,60192,60208,60224,60240,60256,60272,60288,60304,60320,60336,60352,60368,60384,60400,60416,60432,60448,60464,60480,60496"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x40042000
|
|
width 19.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PD0_SLEEP0_HW_ENA,Hardware sleep event enable register"
|
|
bitfld.long 0x00 0. " ENA_EVENT0 ,Writing a 1 enables the Power-down modes for the Cortex-M3" "Disabled,Enable"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "PD0_SLEEP0_MODE,Power-down modes register"
|
|
width 0xB
|
|
tree.end
|
|
tree "CGU (Clock Generation Unit)"
|
|
base ad:0x40050000
|
|
width 19.
|
|
tree "PLL0"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "FREQ_MON,Frequency monitor register"
|
|
sif cpuis("LCP181?")
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock-source selection for the clock to be measured" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
else
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock-source selection for the clock to be measured" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,PLL0USB,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " MEAS ,Measure frequency" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 9.--22. 1. " FCNT ,14-bit selected clock-counter value"
|
|
hexmask.long.word 0x00 0.--8. 1. " RCNT ,9-bit reference clock-counter value"
|
|
line.long 0x04 "XTAL_OSC_CTRL,Crystal oscillator control register"
|
|
bitfld.long 0x04 2. " HF ,Select frequency range" "Low,High"
|
|
bitfld.long 0x04 1. " BYPASS ,Configure crystal operation or external-clock input pin XTAL1" "Not bypassed,Bypassed"
|
|
bitfld.long 0x04 0. " ENABLE ,Oscillator-pad enable" "Yes,No"
|
|
sif !cpuis("LPC181?")
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "PLL0USB_STAT,PLL0USB status register"
|
|
bitfld.long 0x00 1. " FR ,PLL0 free running indicator" "No,Yes"
|
|
bitfld.long 0x00 0. " LOCK ,PLL0 lock indicator" "Unlock,Lock"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "PLL0USB_CTRL,PLL0USB control register"
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,Reserved,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FRM ,Free running mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLKEN ,PLL0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DIRECTO ,PLL0 direct output" "No,Yes"
|
|
bitfld.long 0x00 2. " DIRECTI ,PLL0 direct input" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BYPASS ,Input clock bypass control" "CCO,PLL0"
|
|
bitfld.long 0x00 0. " PD ,PLL0 power down" "Not powered down,Powered down"
|
|
line.long 0x04 "PLL0USB_MDIV,PLL0USB M-divider register"
|
|
bitfld.long 0x04 28.--31. " SELR ,Bandwidth select R value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 22.--27. " SELI ,Bandwidth select I value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 17.--21. " SELP ,Bandwidth select P value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " MDEC ,Decoded M-divider coefficient value"
|
|
line.long 0x08 "PLL0USB_NP_DIV,PLL0USB NP-divider register"
|
|
hexmask.long.word 0x08 12.--21. 1. " NDEC ,Decoded N-divider coefficient value"
|
|
hexmask.long.byte 0x08 0.--6. 1. " PDEC ,Decoded P-divider coefficient value"
|
|
endif
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "PLL0AUDIO_STAT,PLL0AUDIO status register"
|
|
bitfld.long 0x00 1. " FR ,PLL0 free running indicator" "No,Yes"
|
|
bitfld.long 0x00 0. " LOCK ,PLL0 lock indicator" "Not locked,Locked"
|
|
group.long 0x30++0xF
|
|
line.long 0x00 "PLL0AUDIO_CTRL,PLL0AUDIO control register"
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,Reserved,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x00 14. " MOD_PD ,Sigma-Delta modulator power-down" "No,Yes"
|
|
bitfld.long 0x00 13. " SEL_EXT ,Select fractional divider" "Fractional divider,MDEC"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PLLFRACT_REQ ,Fractional PLL word write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FRM ,Free running mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLKEN ,PLL0 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DIRECTO ,PLL0 direct output" "No,Yes"
|
|
bitfld.long 0x00 2. " DIRECTI ,PLL0 direct input" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BYPASS ,Input clock bypass control" "CCO,PLL0"
|
|
bitfld.long 0x00 0. " PD ,PLL0 power down" "Not powered down,Powered down"
|
|
line.long 0x04 "PLL0AUDIO_MDIV,PLL0AUDIO M-divider register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " MDEC ,Decoded M-divider coefficient value"
|
|
line.long 0x08 "PLL0AUDIO_NP_DIV,PLL0 AUDIO NP-divider register"
|
|
hexmask.long.word 0x08 12.--21. 1. " NDEC ,Decoded N-divider coefficient value"
|
|
hexmask.long.byte 0x08 0.--6. 1. " PDEC ,Decoded P-divider coefficient value"
|
|
line.long 0x0C "PLL0AUDIO_FRAC,PLL0AUDIO fractional divider register"
|
|
hexmask.long.tbyte 0x0C 0.--21. 1. " PLLFRACT_CTRL ,PLL fractional divider control word"
|
|
tree.end
|
|
width 11.
|
|
tree "PLL1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "PLL1_STAT,PLL1 status register"
|
|
bitfld.long 0x00 0. " LOCK ,PLL1 lock indicator" "Not locked,Locked"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "PLL1_CTRL,PLL1_CTRL register"
|
|
sif cpuis("LCP181?")
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
else
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,PLL0USB,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " MSEL ,Feedback-divider division ratio"
|
|
bitfld.long 0x00 12.--13. " NSEL ,Pre-divider division ratio" "1,2,3,4"
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PSEL ,Post-divider division ratio P" "1,2,4,8"
|
|
bitfld.long 0x00 7. " DIRECT ,PLL direct CCO output" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FBSEL ,PLL feedback select" "CCO,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BYPASS ,Input clock bypass control" "CCO,PLL1"
|
|
bitfld.long 0x00 0. " PD ,PLL1 power down" "Not Powered down,Powered down"
|
|
tree.end
|
|
width 17.
|
|
tree "Integer divider registers"
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "IDIVA_CTRL,IDIVA control register"
|
|
sif cpuis("LCP1810")
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,?..."
|
|
else
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,PLL0USB,PLL0AUDIO,PLL1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " IDIV ,Integer divider A divider values" "1,2,3,4"
|
|
bitfld.long 0x00 0. " PD ,Integer divider A power down" "Not powered down,Powered down"
|
|
line.long 0x04 "IDIVB_CTRL,IDIVB control register"
|
|
bitfld.long 0x04 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,?..."
|
|
bitfld.long 0x04 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x04 2.--5. " IDIV ,Integer divider B divider values" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PD ,Integer divider B power down" "Not powered down,Powered down"
|
|
line.long 0x08 "IDIVC_CTRL,IDIVC control register"
|
|
bitfld.long 0x08 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,?..."
|
|
bitfld.long 0x08 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x08 2.--5. " IDIV ,Integer divider C divider values" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PD ,Integer divider C power down" "Not Powered down,Powered down"
|
|
line.long 0x0C "IDIVD_CTRL,IDIVD control register"
|
|
bitfld.long 0x0c 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,?..."
|
|
bitfld.long 0x0C 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2.--5. " IDIV ,Integer divider D divider values" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PD ,Integer divider D power down" "Not Powered down,Powered down"
|
|
line.long 0x10 "IDIVE_CTRL,IDIVE control register"
|
|
bitfld.long 0x10 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,?..."
|
|
bitfld.long 0x10 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 2.--9. 1. " IDIV ,Integer divider E divider values"
|
|
textline " "
|
|
bitfld.long 0x10 0. " PD ,Integer divider E power down" "Not Powered down,Powered down"
|
|
tree.end
|
|
tree "BASE control registers"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "BASE_SAFE_CLK,BASE_SAFE_CLK control register"
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "Reserved,IRC,?..."
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
sif !cpuis("LCP181?")
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "BASE_USB0_CLK,BASE_USB0_CLK control register"
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,PLL0USB,?..."
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
endif
|
|
sif (!cpuis("LCP181?")&&!cpuis("LCP182?"))
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "BASE_USB1_CLK,BASE_USB1_CLK control register"
|
|
bitfld.long 0x0 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,PLL0USB,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x0 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
endif
|
|
group.long 0x6c++0x07
|
|
line.long 0x00 "BASE_M3_CLK,BASE_M3_CLK control registers"
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x04 "BASE_SPIFI_CLK,BASE_SPIFI_CLK control registers"
|
|
bitfld.long 0x04 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x04 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
group.long 0x78++0x0f
|
|
line.long 0x00 "BASE_PHY_RX_CLK,BASE_PHY_RX_CLK control registers"
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x04 "BASE_PHY_TX_CLK,BASE_PHY_TX_CLK control registers"
|
|
bitfld.long 0x04 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x04 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x08 "BASE_APB1_CLK,BBASE_APB1_CLK control registers"
|
|
bitfld.long 0x08 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x08 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x0c "BASE_APB3_CLK,BBASE_APB3_CLK control registers"
|
|
bitfld.long 0x0c 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x0c 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
sif (cpuis("LPC1850")||cpuis("LPC1853")||cpuis("LPC1857"))
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "BASE_LCD_CLK,BASE_LCD_CLK control registers"
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
endif
|
|
group.long 0x90++0x1f
|
|
line.long 0x00 "BASE_SDIO_CLK,BASE_SDIO_CLK control registers"
|
|
bitfld.long 0x00 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x00 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x04 "BASE_SSP0_CLK,BASE_SSP0_CLK control registers"
|
|
bitfld.long 0x04 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x04 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x08 "BASE_SSP1_CLK,BASE_SSP1_CLK control registers"
|
|
bitfld.long 0x08 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x08 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x0c "BASE_UART0_CLK,BASE_UART0_CLK control registers"
|
|
bitfld.long 0x0c 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x0c 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x10 "BASE_UART1_CLK,BASE_UART1_CLK control registers"
|
|
bitfld.long 0x10 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x10 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x14 "BASE_UART2_CLK,BASE_UART2_CLK control registers"
|
|
bitfld.long 0x14 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x14 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x18 "BASE_UART3_CLK,BASE_UART3_CLK control registers"
|
|
bitfld.long 0x18 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x18 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x1c "BASE_OUT_CLK,BASE_OUT_CLK control register"
|
|
sif (cpuis("LCP181?"))
|
|
bitfld.long 0x1c 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
else
|
|
bitfld.long 0x1c 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,PLL0USB,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1c 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x1c 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
width 19.
|
|
group.long 0xC0++0xB
|
|
line.long 0x00 "BASE_APLL_CLK,BASE_APLL_CLK control register"
|
|
bitfld.long 0x0 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
bitfld.long 0x0 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x04 "BASE_CGU_OUT0_CLK,BASE_CGU_OUT0_CLK control register"
|
|
sif (cpuis("LCP181?"))
|
|
bitfld.long 0x4 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
else
|
|
bitfld.long 0x4 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,PLL0USB,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x4 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
line.long 0x08 "BASE_CGU_OUT1_CLK,BASE_CGU_OUT1_CLK control register"
|
|
sif (cpuis("LCP181?"))
|
|
bitfld.long 0x8 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,Reserved,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
else
|
|
bitfld.long 0x8 24.--28. " CLK_SEL ,Clock source selection" "32 kHz oscillator,IRC,ENET_RX_CLK,ENET_TX_CLK,GP_CLKIN,Reserved,Crystal oscillator,PLL0USB,PLL0AUDIO,PLL1,Reserved,Reserved,IDIVA,IDIVB,IDIVC,IDIVD,IDIVE,?..."
|
|
endif
|
|
bitfld.long 0x8 11. " AUTOBLOCK ,Block clock automatically during frequency change" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " PD ,Output stage power down" "Not powered down,Powered down"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.open "CCU (Clock Control Unit)"
|
|
tree "CCU1"
|
|
base ad:0x40051000
|
|
width 25.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CCU1_PM,CCU1 power mode register"
|
|
bitfld.long 0x00 0. " PD ,Initiate power-down mode" "Normal,Powered-down"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "CCU1_BASE_STAT,CCU1 base clock status register"
|
|
sif !cpuis("LPC181?")&&!cpuis("LPC182?")
|
|
bitfld.long 0x00 8. " BASE_USB1_CLK_IND ,Base clock indicator for BASE_USB1_CLK" "Switched off,Running"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("LPC181?")
|
|
bitfld.long 0x00 7. " BASE_USB0_CLK_IND ,Base clock indicator for BASE_USB0_CLK" "Switched off,Running"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " BASE_M3_CLK_IND ,Base clock indicator for BASE_M3_CLK" "Switched off,Running"
|
|
bitfld.long 0x00 2. " BASE_SPIFI_CLK_IND ,Base clock indicator for BASE_SPIFI_CLK" "Switched off,Running"
|
|
bitfld.long 0x00 1. " BASE_APB1_CLK_IND ,Base clock indicator for BASE_APB1_CLK" "Switched off,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BASE_APB3_CLK_IND ,Base clock indicator for BASE_APB3_CLK" "Switched off,Running"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "CLK_APB3_BUS_CFG,CLK_APB3_BUS clock configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x00 "CLK_APB3_BUS_STAT,CLK_APB3_BUS clock status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "CLK_APB3_I2C1_CFG,CLK_APB3_I2C1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x00 "CLK_APB3_I2C1_STAT,CLK_APB3_I2C1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "CLK_APB3_DAC_CFG,CLK_APB3_DAC configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "CLK_APB3_DAC_STAT,CLK_APB3_DAC status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "CLK_APB3_ADC0_CFG,CLK_APB3_ADC0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "CLK_APB3_ADC0_STAT,CLK_APB3_ADC0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "CLK_APB3_ADC1_CFG,CLK_APB3_ADC1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "CLK_APB3_ADC1_STAT,CLK_APB3_ADC1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "CLK_APB3_CAN0_CFG,CLK_APB3_CAN0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x12C++0x3
|
|
line.long 0x00 "CLK_APB3_CAN0_STAT,CLK_APB3_CAN0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "CLK_APB1_BUS_CFG,CLK_APB1_BUS configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x00 "CLK_APB1_BUS_STAT,CLK_APB1_BUS status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "CLK_APB1_MOTOCONPWM_CFG,CLK_APB1_MOTOCON configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x00 "CLK_APB1_MOTOCONPWM_STAT,CLK_APB1_MOTOCON status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x210++0x3
|
|
line.long 0x00 "CLK_APB1_I2C0_CFG,CLK_APB1_I2C0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x00 "CLK_APB1_I2C0_STAT,CLK_APB1_I2C0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x218++0x3
|
|
line.long 0x00 "CLK_APB1_I2S_CFG,CLK_APB1_I2S configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x21C++0x3
|
|
line.long 0x00 "CLK_APB1_I2S_STAT,CLK_APB1_I2S status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "CLK_APB1_CAN1_CFG,CLK_APB3_CAN1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "CLK_APB1_CAN1_STAT,CLK_APB3_CAN1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "CLK_SPIFI_CFG,CLK_SPIFI configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x304++0x3
|
|
line.long 0x00 "CLK_SPIFI_STAT,CLK_SPIFI status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x400++0x3
|
|
line.long 0x00 "CLK_M3_BUS_CFG,CLK_M3_BUS configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x404++0x3
|
|
line.long 0x00 "CLK_M3_BUS_STAT,CLK_M3_BUS status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x408++0x3
|
|
line.long 0x00 "CLK_M3_SPIFI_CFG,CLK_M3_SPIFI configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x40C++0x3
|
|
line.long 0x00 "CLK_M3_SPIFI_STAT,CLK_M3_SPIFI status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x410++0x3
|
|
line.long 0x00 "CLK_M3_GPIO_CFG,CLK_M3_GPIO configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x414++0x3
|
|
line.long 0x00 "CLK_M3_GPIO_STAT,CLK_M3_GPIO status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
sif cpuis("LPC185?")
|
|
group.long 0x418++0x3
|
|
line.long 0x00 "CLK_M3_LCD_CFG,CLK_M3_LCD configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x00 "CLK_M3_LCD_STAT,CLK_M3_LCD status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("LPC181?")&&!cpuis("LPC182?")
|
|
group.long 0x420++0x3
|
|
line.long 0x00 "CLK_M3_ETHERNET_CFG,CLK_M3_ETHERNET configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x424++0x3
|
|
line.long 0x00 "CLK_M3_ETHERNET_STAT,CLK_M3_ETHERNET status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("LPC181?")
|
|
group.long 0x428++0x3
|
|
line.long 0x00 "CLK_M3_USB0_CFG,CLK_M3_USB0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x42C++0x3
|
|
line.long 0x00 "CLK_M3_USB0_STAT,CLK_M3_USB0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x430++0x3
|
|
line.long 0x00 "CLK_M3_EMC_CFG,CLK_M3_EMC configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x434++0x3
|
|
line.long 0x00 "CLK_M3_EMC_STAT,CLK_M3_EMC status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x438++0x3
|
|
line.long 0x00 "CLK_M3_SDIO_CFG,CLK_M3_SDIO configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x43C++0x3
|
|
line.long 0x00 "CLK_M3_SDIO_STAT,CLK_M3_SDIO status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x440++0x3
|
|
line.long 0x00 "CLK_M3_DMA_CFG,CLK_M3_DMA configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x00 "CLK_M3_DMA_STAT,CLK_M3_DMA status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x448++0x3
|
|
line.long 0x00 "CLK_M3_M3CORE_CFG,CLK_M3_M3CORE configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x44C++0x3
|
|
line.long 0x00 "CLK_M3_M3CORE_STAT,CLK_M3_M3CORE status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x468++0x3
|
|
line.long 0x00 "CLK_M3_SCT_CFG,CLK_M3_SCT configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x46C++0x3
|
|
line.long 0x00 "CLK_M3_SCT_STAT,CLK_M3_SCT status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
sif !cpuis("LPC181?")&&!cpuis("LPC182?")
|
|
group.long 0x470++0x3
|
|
line.long 0x00 "CLK_M3_USB1_CFG,CLK_M3_USB1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x474++0x3
|
|
line.long 0x00 "CLK_M3_USB1_STAT,CLK_M3_USB1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x478++0x3
|
|
line.long 0x00 "CLK_EMCDIV_CFG,CLK_EMCDIV clock configuration register"
|
|
bitfld.long 0x00 5.--7. " DIV ,Clock divider value" "/1,/2,?..."
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x47C++0x3
|
|
line.long 0x00 "CLK_M3_EMCDIV_STAT,CLK_M3_EMCDIV status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
group.long 0x480++0x3
|
|
line.long 0x00 "CLK_M3_FLASHA_CFG,CLK_M3_FLASHA configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x484++0x3
|
|
line.long 0x00 "CLK_M3_FLASHA_STAT,CLK_M3_FLASHA status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1812"&&cpu()!="LPC1822")
|
|
group.long 0x488++0x3
|
|
line.long 0x00 "CLK_M3_FLASHB_CFG,CLK_M3_FLASHB configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x48C++0x3
|
|
line.long 0x00 "CLK_M3_FLASHB_STAT,CLK_M3_FLASHB status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
group.long 0x4A0++0x3
|
|
line.long 0x00 "CLK_M3_EEPROM_CFG,CLK_M3_EEPROM configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x4A4++0x3
|
|
line.long 0x00 "CLK_M3_EEPROM_STAT,CLK_M3_EEPROM status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x500++0x3
|
|
line.long 0x00 "CLK_M3_WWDT_CFG,CLK_M3_WWDT configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x504++0x3
|
|
line.long 0x00 "CLK_M3_WWDT_STAT,CLK_M3_WWDT status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x508++0x3
|
|
line.long 0x00 "CLK_M3_USART0_CFG,CLK_M3_UART0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x50C++0x3
|
|
line.long 0x00 "CLK_M3_USART0_STAT,CLK_M3_UART0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x510++0x3
|
|
line.long 0x00 "CLK_M3_UART1_CFG,CLK_M3_UART1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x514++0x3
|
|
line.long 0x00 "CLK_M3_UART1_STAT,CLK_M3_UART1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x518++0x3
|
|
line.long 0x00 "CLK_M3_SSP0_CFG,CLK_M3_SSP0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x51C++0x3
|
|
line.long 0x00 "CLK_M3_SSP0_STAT,CLK_M3_SSP0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x520++0x3
|
|
line.long 0x00 "CLK_M3_TIMER0_CFG,CLK_M3_TIMER0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x524++0x3
|
|
line.long 0x00 "CLK_M3_TIMER0_STAT,CLK_M3_TIMER0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x528++0x3
|
|
line.long 0x00 "CLK_M3_TIMER1_CFG,CLK_M3_TIMER1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x52C++0x3
|
|
line.long 0x00 "CLK_M3_TIMER1_STAT,CLK_M3_TIMER1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x530++0x3
|
|
line.long 0x00 "CLK_M3_SCU_CFG,CLK_M3_SCU configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x534++0x3
|
|
line.long 0x00 "CLK_M3_SCU_STAT,CLK_M3_SCU status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x538++0x3
|
|
line.long 0x00 "CLK_M3_CREG_CFG,CLK_M3_CREG configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x53C++0x3
|
|
line.long 0x00 "CLK_M3_CREG_STAT,CLK_M3_CREG status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x600++0x3
|
|
line.long 0x00 "CLK_M3_RITIMER_CFG,CLK_M3_RITIMER configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x604++0x3
|
|
line.long 0x00 "CLK_M3_RITIMER_STAT,CLK_M3_RITIMER status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x608++0x3
|
|
line.long 0x00 "CLK_M3_USART2_CFG,CLK_M3_UART2 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x60C++0x3
|
|
line.long 0x00 "CLK_M3_USART2_STAT,CLK_M3_UART2 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x610++0x3
|
|
line.long 0x00 "CLK_M3_USART3_CFG,CLK_M3_UART3 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x614++0x3
|
|
line.long 0x00 "CLK_M3_USART3_STAT,CLK_M3_UART3 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x618++0x3
|
|
line.long 0x00 "CLK_M3_TIMER2_CFG,CLK_M3_TIMER2 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x61C++0x3
|
|
line.long 0x00 "CLK_M3_TIMER2_STAT,CLK_M3_TIMER2 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x620++0x3
|
|
line.long 0x00 "CLK_M3_TIMER3_CFG,CLK_M3_TIMER3 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x624++0x3
|
|
line.long 0x00 "CLK_M3_TIMER3_STAT,CLK_M3_TIMER3 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x628++0x3
|
|
line.long 0x00 "CLK_M3_SSP1_CFG,CLK_M3_SSP1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x62C++0x3
|
|
line.long 0x00 "CLK_M3_SSP1_STAT,CLK_M3_SSP1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x630++0x3
|
|
line.long 0x00 "CLK_M3_QEI_CFG,CLK_M3_QEI configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x634++0x3
|
|
line.long 0x00 "CLK_M3_QEI_STAT,CLK_M3_QEI status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
sif (!cpuis("LPC181?"))
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "CLK_USB0_CFG,CLK_USB0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x00 "CLK_USB0_STAT,CLK_USB0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
group.long 0x900++0x3
|
|
line.long 0x00 "CLK_USB1_CFG,CLK_USB1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x904++0x3
|
|
line.long 0x00 "CLK_USB1_STAT,CLK_USB1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CCU2"
|
|
base ad:0x40052000
|
|
width 25.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CCU2_PM,CCU2 power mode register"
|
|
bitfld.long 0x00 0. " PD ,Initiate power-down mode" "Normal,Powered-down"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "CCU2_BASE_STAT,CCU2 base clock status register"
|
|
bitfld.long 0x00 6. " BASE_SSP0_CLK ,Base clock indicator for BASE_SSP0_CLK" "Switched off,Running"
|
|
bitfld.long 0x00 5. " BASE_SSP1_CLK ,Base clock indicator for BASE_SSP1_CLK" "Switched off,Running"
|
|
bitfld.long 0x00 4. " BASE_UART0_CLK ,Base clock indicator for BASE_UART0_CLK" "Switched off,Running"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BASE_UART1_CLK ,Base clock indicator for BASE_UART1_CLK" "Switched off,Running"
|
|
bitfld.long 0x00 2. " BASE_UART2_CLK ,Base clock indicator for BASE_UART2_CLK" "Switched off,Running"
|
|
bitfld.long 0x00 1. " BASE_UART3_CLK ,Base clock indicator for BASE_UART3_CLK" "Switched off,Running"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "CLK_APLL_CFG,CLK_APLL configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x00 "CLK_APLL_STAT,CLK_APLL status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "CLK_APB2_USART3_CFG,CLK_APB2_UART3 config register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x00 "CLK_APB2_USART3_STAT,CLK_APB2_UART3 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "CLK_APB2_USART2_CFG,CLK_APB2_UART2 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x304++0x3
|
|
line.long 0x00 "CLK_APB2_USART2_STAT,CLK_APB2_UART2 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x400++0x3
|
|
line.long 0x00 "CLK_APB0_UART1_CFG,CLK_APB0_UART1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x404++0x3
|
|
line.long 0x00 "CLK_APB0_UART1_STAT,CLK_APB0_UART1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x500++0x3
|
|
line.long 0x00 "CLK_APB0_USART0_CFG,CLK_APB0_UART0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x504++0x3
|
|
line.long 0x00 "CLK_APB0_USART0_STAT,CLK_APB0_UART0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x600++0x3
|
|
line.long 0x00 "CLK_APB2_SSP1_CFG,CLK_APB2_SSP1 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
rgroup.long 0x604++0x3
|
|
line.long 0x00 "CLK_APB2_SSP1_STAT,CLK_APB2_SSP1 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x700++0x3
|
|
line.long 0x00 "CLK_APB0_SSP0_CFG,CLK_APB0_SSP0 configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x704++0x3
|
|
line.long 0x00 "CLK_APB0_SSP0_STAT,CLK_APB0_SSP0 status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "CLK_SDIO_CFG,CLK_SDIO configuration register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enable"
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x00 "CLK_SDIO_STAT,CLK_SDIO status register"
|
|
bitfld.long 0x00 2. " WAKEUP ,Wake-up mechanism enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AUTO ,Auto (AHB disable mechanism) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RUN ,Run enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "RGU (Reset Generation Unit)"
|
|
base ad:0x40053000
|
|
width 22.
|
|
wgroup.long 0x100++0x7
|
|
line.long 0x00 "RESET_CTRL0,Reset control register 0"
|
|
sif (cpu()=="LPC4310FBD144")&&(cpu()=="LPC4320FET100")&&(cpu()=="LPC4330FET100")&&(cpu()=="LPC4330FET256")&&(cpu()=="LPC4350FET180")&&(cpu()=="LPC4310FET100")&&(cpu()=="LPC4320FBD144")&&(cpu()=="LPC4330FBD144")&&(cpu()=="LPC4330FET180")&&(cpu()=="LPC4350FBD208")&&(cpu()=="LPC4350FET256")&&(cpu()=="LPC4310FBD144-M0")&&(cpu()=="LPC4320FET100-M0")&&(cpu()=="LPC4330FET100-M0")&&(cpu()=="LPC4330FET256-M0")&&(cpu()=="LPC4350FET180-M0")&&(cpu()=="LPC4310FET100-M0")&&(cpu()=="LPC4320FBD144-M0")&&(cpu()=="LPC4330FBD144-M0")&&(cpu()=="LPC4330FET180-M0")&&(cpu()=="LPC4350FBD208-M0")&&(cpu()=="LPC4350FET256-M0")
|
|
bitfld.long 0x00 28. " GPIO_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
else
|
|
sif (cpu()=="LPC1813"||cpu()=="LPC1815"||cpu()=="LPC1817"||cpu()=="LPC1823"||cpu()=="LPC1825"||cpu()=="LPC1827"||cpu()=="LPC1833"||cpu()=="LPC1837"||cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
bitfld.long 0x00 29. " FLASHB_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " GPIO_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
sif (cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
textline " "
|
|
bitfld.long 0x00 27. " EEPROM_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
endif
|
|
sif (cpu()=="LPC1812"||cpu()=="LPC1813"||cpu()=="LPC1815"||cpu()=="LPC1817"||cpu()=="LPC1822"||cpu()=="LPC1823"||cpu()=="LPC1825"||cpu()=="LPC1827"||cpu()=="LPC1833"||cpu()=="LPC1837"||cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
bitfld.long 0x00 25. " FLASHA_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC4350FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4357FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4357FET180-M0")||(cpu()=="LPC4357FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4353FBD208-M0")
|
|
bitfld.long 0x00 22. " ETHERNET_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 21. " EMC_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SDIO_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " DMA_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 18. " USB1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " USB0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 16. " LCD_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 13. " M4_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCU_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " BUS_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WWDT_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
bitfld.long 0x00 2. " MASTER_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORE_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
elif (cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")
|
|
bitfld.long 0x00 21. " EMC_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 20. " SDIO_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DMA_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 17. " USB0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 13. " M4_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCU_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " BUS_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WWDT_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
bitfld.long 0x00 2. " MASTER_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORE_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
elif (cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4320FBD144-M0")
|
|
bitfld.long 0x00 22. " ETHERNET_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 21. " EMC_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SDIO_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " DMA_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 18. " USB1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " USB0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 13. " M4_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 9. " SCU_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BUS_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
bitfld.long 0x00 4. " WWDT_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MASTER_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CORE_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
elif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4310FET100-M0")
|
|
bitfld.long 0x00 21. " EMC_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 20. " SDIO_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DMA_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 13. " M4_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 9. " SCU_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BUS_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
bitfld.long 0x00 4. " WWDT_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MASTER_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CORE_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
else
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
bitfld.long 0x00 22. " ETHERNET_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " EMC_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SDIO_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " DMA_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
bitfld.long 0x00 18. " USB1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("LPC181?"))
|
|
bitfld.long 0x00 17. " USB0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
endif
|
|
sif (cpuis("LPC185?"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " LCD_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " M3_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCU_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " BUS_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WWDT_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
bitfld.long 0x00 2. " MASTER_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORE_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
endif
|
|
line.long 0x04 "RESET_CTRL1,Reset control register 1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x04 26. " SPI_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 25. " SGPIO_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 24. " M0APP_RST ,Bit must be cleared by software" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CAN0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 22. " CAN1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 21. " SPIFI_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 20. " I2S_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 19. " SSP1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 18. " SSP0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I2C1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 16. " I2C0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 15. " UART3_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 14. " UART2_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 13. " UART1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 12. " UART0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DAC_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 9. " ADC1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 8. " ADC0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " QEI_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 6. " MOTOCONPWM_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 5. " SCT_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RITIMER_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
bitfld.long 0x04 3. " TIMER3_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
bitfld.long 0x04 2. " TIMER2_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TIMER1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " TIMER0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x04 23. " CAN0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 22. " CAN1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 21. " SPIFI_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 20. " I2S_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 19. " SSP1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 18. " SSP0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I2C1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 16. " I2C0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 15. " UART3_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 14. " UART2_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 13. " UART1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 12. " UART0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DAC_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 9. " ADC1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 8. " ADC0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
bitfld.long 0x04 7. " QEI_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " MOTOCONPWM_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 5. " SCT_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 4. " RITIMER_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TIMER3_RST ,Writing a one to this bit has no effect" "No reset,Reset"
|
|
bitfld.long 0x04 2. " TIMER2_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
bitfld.long 0x04 1. " TIMER1_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TIMER0_RST ,Writing a one activates the reset" "No reset,Reset"
|
|
endif
|
|
group.long 0x110++0xF
|
|
line.long 0x00 "RESET_STATUS0,Reset status register 0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x00 26.--27. " M4_RST ,Status of the M4_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x00 18.--19. " SCU_RST ,Status of the SCU_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x00 16.--17. " BUS_RST ,Status of the BUS_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CREG_RST ,Status of the CREG_RST reset generator output" "No reset,Input,?..."
|
|
bitfld.long 0x00 8.--9. " WWDT_RST ,Status of the WWDT_RST reset generator output" "No reset,Input,?..."
|
|
bitfld.long 0x00 4.--5. " MASTER_RST ,Status of the MASTER_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PERIPH_RST ,Status of the PERIPH_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x00 0.--1. " CORE_RST ,Status of the CORE_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
else
|
|
bitfld.long 0x00 26.--27. " M3_RST ,Status of the M3_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x00 18.--19. " SCU_RST ,Status of the SCU_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x00 16.--17. " BUS_RST ,Status of the BUS_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CREG_RST ,Status of the CREG_RST reset generator output" "No reset,Input,?..."
|
|
bitfld.long 0x00 8.--9. " WWDT_RST ,Status of the WWDT_RST reset generator output" "No reset,Input,?..."
|
|
bitfld.long 0x00 4.--5. " MASTER_RST ,Status of the MASTER_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PERIPH_RST ,Status of the PERIPH_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
sif (!cpuis("LPC18*"))
|
|
bitfld.long 0x00 0.--1. " CORE_RST ,Status of the CORE_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
endif
|
|
line.long 0x04 "RESET_STATUS1,Reset status register 1"
|
|
sif (cpu()=="LPC4310FBD144")&&(cpu()=="LPC4320FET100")&&(cpu()=="LPC4330FET100")&&(cpu()=="LPC4330FET256")&&(cpu()=="LPC4350FET180")&&(cpu()=="LPC4310FET100")&&(cpu()=="LPC4320FBD144")&&(cpu()=="LPC4330FBD144")&&(cpu()=="LPC4330FET180")&&(cpu()=="LPC4350FBD208")&&(cpu()=="LPC4350FET256")&&(cpu()=="LPC4310FBD144-M0")&&(cpu()=="LPC4320FET100-M0")&&(cpu()=="LPC4330FET100-M0")&&(cpu()=="LPC4330FET256-M0")&&(cpu()=="LPC4350FET180-M0")&&(cpu()=="LPC4310FET100-M0")&&(cpu()=="LPC4320FBD144-M0")&&(cpu()=="LPC4330FBD144-M0")&&(cpu()=="LPC4330FET180-M0")&&(cpu()=="LPC4350FBD208-M0")&&(cpu()=="LPC4350FET256-M0")
|
|
bitfld.long 0x04 24.--25. " GPIO_RST ,Status of the GPIO_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
else
|
|
sif (cpu()=="LPC1813"||cpu()=="LPC1815"||cpu()=="LPC1817"||cpu()=="LPC1823"||cpu()=="LPC1825"||cpu()=="LPC1827"||cpu()=="LPC1833"||cpu()=="LPC1837"||cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
bitfld.long 0x04 26.--27. " FLASHB_RST ,Status of the FLASHB_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " GPIO_RST ,Status of the GPIO_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
sif (cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " EEPROM_RST ,Status of the EEPROM_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
sif (cpu()=="LPC1812"||cpu()=="LPC1813"||cpu()=="LPC1815"||cpu()=="LPC1817"||cpu()=="LPC1822"||cpu()=="LPC1823"||cpu()=="LPC1825"||cpu()=="LPC1827"||cpu()=="LPC1833"||cpu()=="LPC1837"||cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
bitfld.long 0x04 18.--19. " FLASHA_RST ,Status of the FLASHA_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC4350FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4357FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4357FET180-M0")||(cpu()=="LPC4357FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4353FBD208-M0")
|
|
bitfld.long 0x04 12.--13. " ETHERNET_RST ,Status of the ETHERNET_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 10.--11. " EMC_RST ,Status of the EMC_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " SDIO_RST ,Status of the SDIO_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 6.--7. " DMA_RST ,Status of the DMA_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 4.--5. " USB1_RST ,Status of the USB1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " USB0_RST ,Status of the USB0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 0.--1. " LCD_RST ,Status of the LCD_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
elif (cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")
|
|
bitfld.long 0x04 12.--13. " ETHERNET_RST ,Status of the ETHERNET_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 10.--11. " EMC_RST ,Status of the EMC_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " SDIO_RST ,Status of the SDIO_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 6.--7. " DMA_RST ,Status of the DMA_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 4.--5. " USB1_RST ,Status of the USB1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " USB0_RST ,Status of the USB0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
elif (cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4320FBD144-M0")
|
|
bitfld.long 0x04 10.--11. " EMC_RST ,Status of the EMC_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 8.--9. " SDIO_RST ,Status of the SDIO_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " DMA_RST ,Status of the DMA_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 2.--3. " USB0_RST ,Status of the USB0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
elif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4310FET100-M0")
|
|
bitfld.long 0x04 10.--11. " EMC_RST ,Status of the EMC_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 8.--9. " SDIO_RST ,Status of the SDIO_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " DMA_RST ,Status of the DMA_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
else
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
bitfld.long 0x04 12.--13. " ETHERNET_RST ,Status of the ETHERNET_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EMC_RST ,Status of the EMC_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " SDIO_RST ,Status of the SDIO_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x04 6.--7. " DMA_RST ,Status of the DMA_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
bitfld.long 0x04 4.--5. " USB1_RST ,Status of the USB1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("LPC181?"))
|
|
bitfld.long 0x04 2.--3. " USB0_RST ,Status of the USB0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?")&&!cpuis("LPC183?"))
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " LCD_RST ,Status of the LCD_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
endif
|
|
line.long 0x08 "RESET_STATUS2,Reset status register 2"
|
|
bitfld.long 0x08 30.--31. " UART3_RST ,Status of the UART3_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x08 28.--29. " UART2_RST ,Status of the UART2_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x08 26.--27. " UART1_RST ,Status of the UART1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " UART0_RST ,Status of the UART0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x08 20.--21. " DAC_RST ,Status of the DAC_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x08 18.--19. " ADC1_RST ,Status of the ADC1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x08 16.--17. " ADC0_RST ,Status of the ADC0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
bitfld.long 0x08 14.--15. " QEI_RST ,Status of the QEI_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " MOTOCONPWM_RST ,Status of the MOTOCONPWM_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " SCT_RST ,Status of the SCT_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x08 8.--9. " RITIMER_RST ,Status of the RITIMER_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x08 6.--7. " TIMER3_RST ,Status of the TIMER3_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " TIMER2_RST ,Status of the TIMER2_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x08 2.--3. " TIMER1_RST ,Status of the TIMER1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x08 0.--1. " TIMER0_RST ,Status of the TIMER0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
line.long 0x0C "RESET_STATUS3,Reset status register 3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0C 20.--21. " SPI_RST ,Status of the SPI_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 18.--19. " SGPIO_RST ,Status of the SGPIO_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 16.--17. " M0APP_RST ,Status of the M0APP_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " CAN0_RST ,Status of the CAN0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 12.--13. " CAN1_RST ,Status of the CAN1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 10.--11. " SPIFI_RST ,Status of the SPIFI_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " I2S_RST ,Status of the I2S_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 6.--7. " SSP1_RST ,Status of the SSP1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 4.--5. " SSP0_RST ,Status of the SSP0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " I2C1_RST ,Status of the I2C1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 0.--1. " I2C0_RST ,Status of the I2C0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
else
|
|
bitfld.long 0x0C 14.--15. " CAN0_RST ,Status of the CAN0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 12.--13. " CAN1_RST ,Status of the CAN1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 10.--11. " SPIFI_RST ,Status of the SPIFI_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " I2S_RST ,Status of the I2S_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 6.--7. " SSP1_RST ,Status of the SSP1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 4.--5. " SSP0_RST ,Status of the SSP0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " I2C1_RST ,Status of the I2C1_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
bitfld.long 0x0C 0.--1. " I2C0_RST ,Status of the I2C0_RST reset generator output" "No reset,Input,Reserved,Software"
|
|
endif
|
|
rgroup.long 0x150++0x7
|
|
line.long 0x00 "RESET_ACTIVE_STATUS0,Reset active status register 0"
|
|
sif (cpu()=="LPC4310FBD144")&&(cpu()=="LPC4320FET100")&&(cpu()=="LPC4330FET100")&&(cpu()=="LPC4330FET256")&&(cpu()=="LPC4350FET180")&&(cpu()=="LPC4310FET100")&&(cpu()=="LPC4320FBD144")&&(cpu()=="LPC4330FBD144")&&(cpu()=="LPC4330FET180")&&(cpu()=="LPC4350FBD208")&&(cpu()=="LPC4350FET256")&&(cpu()=="LPC4310FBD144-M0")&&(cpu()=="LPC4320FET100-M0")&&(cpu()=="LPC4330FET100-M0")&&(cpu()=="LPC4330FET256-M0")&&(cpu()=="LPC4350FET180-M0")&&(cpu()=="LPC4310FET100-M0")&&(cpu()=="LPC4320FBD144-M0")&&(cpu()=="LPC4330FBD144-M0")&&(cpu()=="LPC4330FET180-M0")&&(cpu()=="LPC4350FBD208-M0")&&(cpu()=="LPC4350FET256-M0")
|
|
bitfld.long 0x00 28. " GPIO_RST ,Current status of the GPIO_RST" "Reset,No reset"
|
|
textline " "
|
|
else
|
|
sif (cpu()=="LPC1813"||cpu()=="LPC1815"||cpu()=="LPC1817"||cpu()=="LPC1823"||cpu()=="LPC1825"||cpu()=="LPC1827"||cpu()=="LPC1833"||cpu()=="LPC1837"||cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
bitfld.long 0x00 29. " FLASHB_RST ,Current status of the FLASHB_RST" "Reset,No reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " GPIO_RST ,Current status of the GPIO_RST" "Reset,No reset"
|
|
sif (cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
textline " "
|
|
bitfld.long 0x00 27. " EEPROM_RST ,Current status of the EEPROM_RST" "Reset,No reset"
|
|
endif
|
|
sif (cpu()=="LPC1812"||cpu()=="LPC1813"||cpu()=="LPC1815"||cpu()=="LPC1817"||cpu()=="LPC1822"||cpu()=="LPC1823"||cpu()=="LPC1825"||cpu()=="LPC1827"||cpu()=="LPC1833"||cpu()=="LPC1837"||cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
bitfld.long 0x00 25. " FLASHA_RST ,Current status of the FLASHA_RST" "Reset,No reset"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC4350FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4357FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4357FET180-M0")||(cpu()=="LPC4357FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4353FBD208-M0")
|
|
bitfld.long 0x00 22. " ETHERNET_RST ,Current status of the ETHERNET_RST" "Reset,No reset"
|
|
bitfld.long 0x00 21. " EMC_RST ,Current status of the EMC_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SDIO_RST ,Current status of the SDIO_RST" "Reset,No reset"
|
|
bitfld.long 0x00 19. " DMA_RST ,Current status of the DMA_RST" "Reset,No reset"
|
|
bitfld.long 0x00 18. " USB1_RST ,Current status of the USB1_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " USB0_RST ,USB0_RST" "Reset,No reset"
|
|
bitfld.long 0x00 16. " LCD_RST ,Current status of the LCD_RST" "Reset,No reset"
|
|
bitfld.long 0x00 13. " M4_RST ,Current status of the M4_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCU_RST ,Current status of the SCU_RST" "Reset,No reset"
|
|
bitfld.long 0x00 8. " BUS_RST ,Current status of the BUS_RST" "Reset,No reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Current status of the CREG_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WWDT_RST ,Current status of the WWDT_RS" "Reset,No reset"
|
|
bitfld.long 0x00 2. " MASTER_RST ,Current status of the MASTER_RST" "Reset,No reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Current status of the PERIPH_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORE_RST ,Current status of the CORE_RST" "Reset,No reset"
|
|
elif (cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")
|
|
bitfld.long 0x00 22. " ETHERNET_RST ,Current status of the ETHERNET_RST" "Reset,No reset"
|
|
bitfld.long 0x00 21. " EMC_RST ,Current status of the EMC_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SDIO_RST ,Current status of the SDIO_RST" "Reset,No reset"
|
|
bitfld.long 0x00 19. " DMA_RST ,Current status of the DMA_RST" "Reset,No reset"
|
|
bitfld.long 0x00 18. " USB1_RST ,Current status of the USB1_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " USB0_RST ,USB0_RST" "Reset,No reset"
|
|
bitfld.long 0x00 13. " M4_RST ,Current status of the M4_RST" "Reset,No reset"
|
|
bitfld.long 0x00 9. " SCU_RST ,Current status of the SCU_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BUS_RST ,Current status of the BUS_RST" "Reset,No reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Current status of the CREG_RST" "Reset,No reset"
|
|
bitfld.long 0x00 4. " WWDT_RST ,Current status of the WWDT_RS" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MASTER_RST ,Current status of the MASTER_RST" "Reset,No reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Current status of the PERIPH_RST" "Reset,No reset"
|
|
bitfld.long 0x00 0. " CORE_RST ,Current status of the CORE_RST" "Reset,No reset"
|
|
elif (cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4320FBD144-M0")
|
|
bitfld.long 0x00 21. " EMC_RST ,Current status of the EMC_RST" "Reset,No reset"
|
|
bitfld.long 0x00 20. " SDIO_RST ,Current status of the SDIO_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DMA_RST ,Current status of the DMA_RST" "Reset,No reset"
|
|
bitfld.long 0x00 17. " USB0_RST ,USB0_RST" "Reset,No reset"
|
|
bitfld.long 0x00 13. " M4_RST ,Current status of the M4_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCU_RST ,Current status of the SCU_RST" "Reset,No reset"
|
|
bitfld.long 0x00 8. " BUS_RST ,Current status of the BUS_RST" "Reset,No reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Current status of the CREG_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WWDT_RST ,Current status of the WWDT_RS" "Reset,No reset"
|
|
bitfld.long 0x00 2. " MASTER_RST ,Current status of the MASTER_RST" "Reset,No reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Current status of the PERIPH_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORE_RST ,Current status of the CORE_RST" "Reset,No reset"
|
|
elif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4310FET100-M0")
|
|
bitfld.long 0x00 21. " EMC_RST ,Current status of the EMC_RST" "Reset,No reset"
|
|
bitfld.long 0x00 20. " SDIO_RST ,Current status of the SDIO_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DMA_RST ,Current status of the DMA_RST" "Reset,No reset"
|
|
bitfld.long 0x00 13. " M4_RST ,Current status of the M4_RST" "Reset,No reset"
|
|
bitfld.long 0x00 9. " SCU_RST ,Current status of the SCU_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BUS_RST ,Current status of the BUS_RST" "Reset,No reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Current status of the CREG_RST" "Reset,No reset"
|
|
bitfld.long 0x00 4. " WWDT_RST ,Current status of the WWDT_RS" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MASTER_RST ,Current status of the MASTER_RST" "Reset,No reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Current status of the PERIPH_RST" "Reset,No reset"
|
|
bitfld.long 0x00 0. " CORE_RST ,Current status of the CORE_RST" "Reset,No reset"
|
|
else
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
bitfld.long 0x00 22. " ETHERNET_RST ,Current status of the ETHERNET_RST" "Reset,No reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " EMC_RST ,Current status of the EMC_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SDIO_RST ,Current status of the SDIO_RST" "Reset,No reset"
|
|
bitfld.long 0x00 19. " DMA_RST ,Current status of the DMA_RST" "Reset,No reset"
|
|
textline " "
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
bitfld.long 0x00 18. " USB1_RST ,Current status of the USB1_RST" "Reset,No reset"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("LPC181?"))
|
|
bitfld.long 0x00 17. " USB0_RST ,USB0_RST" "Reset,No reset"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("LPC185?"))
|
|
bitfld.long 0x00 16. " LCD_RST ,Current status of the LCD_RST" "Reset,No reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " M3_RST ,Current status of the M3_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCU_RST ,Current status of the SCU_RST" "Reset,No reset"
|
|
bitfld.long 0x00 8. " BUS_RST ,Current status of the BUS_RST" "Reset,No reset"
|
|
bitfld.long 0x00 5. " CREG_RST ,Current status of the CREG_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WWDT_RST ,Current status of the WWDT_RS" "Reset,No reset"
|
|
bitfld.long 0x00 2. " MASTER_RST ,Current status of the MASTER_RST" "Reset,No reset"
|
|
bitfld.long 0x00 1. " PERIPH_RST ,Current status of the PERIPH_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORE_RST ,Current status of the CORE_RST" "Reset,No reset"
|
|
endif
|
|
line.long 0x04 "RESET_ACTIVE_STATUS1,Reset active status register 1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x04 26. " SPI_RST ,Writing a one activates the reset" "Reset,No reset"
|
|
bitfld.long 0x04 25. " SGPIO_RST ,Writing a one activates the reset" "Reset,No reset"
|
|
bitfld.long 0x04 24. " M0APP_RST ,Bit must be cleared by software" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CAN0_RST ,Current status of the CAN0_RST" "Reset,No reset"
|
|
bitfld.long 0x04 22. " CAN1_RST ,Current status of the CAN1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 21. " SPIFI_RST ,Current status of the SPIFI_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 20. " I2S_RST ,Current status of the I2S_RST" "Reset,No reset"
|
|
bitfld.long 0x04 19. " SSP1_RST ,Current status of the SSP1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 18. " SSP0_RST ,Current status of the SSP0_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I2C1_RST ,Current status of the I2C1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 16. " I2C0_RST ,Current status of the I2C0_RST" "Reset,No reset"
|
|
bitfld.long 0x04 15. " UART3_RST ,Current status of the UART3_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 14. " UART2_RST ,Current status of the UART2_RST" "Reset,No reset"
|
|
bitfld.long 0x04 13. " UART1_RST ,Current status of the UART1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 12. " UART0_RST ,Current status of the UART0_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DAC_RST ,Current status of the DAC_RST" "Reset,No reset"
|
|
bitfld.long 0x04 9. " ADC1_RST ,Current status of the ADC1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 8. " ADC0_RST ,Current status of the ADC0_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " QEI_RST ,Current status of the QEI_RST" "Reset,No reset"
|
|
bitfld.long 0x04 6. " MOTOCONPWM_RST ,Current status of the MOTOCONPWM_RST" "Reset,No reset"
|
|
bitfld.long 0x04 5. " SCT_RST ,Current status of the SCT_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RITIMER_RST ,Current status of the RITIMER_RST" "Reset,No reset"
|
|
bitfld.long 0x04 3. " TIMER3_RST ,Current status of the TIMER3_RST" "Reset,No reset"
|
|
bitfld.long 0x04 2. " TIMER2_RST ,Current status of the TIMER2_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TIMER1_RST ,Current status of the TIMER1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 0. " TIMER0_RST ,Current status of the TIMER0_RST" "Reset,No reset"
|
|
else
|
|
bitfld.long 0x04 23. " CAN0_RST ,Current status of the CAN0_RST" "Reset,No reset"
|
|
bitfld.long 0x04 22. " CAN1_RST ,Current status of the CAN1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 21. " SPIFI_RST ,Current status of the SPIFI_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 20. " I2S_RST ,Current status of the I2S_RST" "Reset,No reset"
|
|
bitfld.long 0x04 19. " SSP1_RST ,Current status of the SSP1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 18. " SSP0_RST ,Current status of the SSP0_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 17. " I2C1_RST ,Current status of the I2C1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 16. " I2C0_RST ,Current status of the I2C0_RST" "Reset,No reset"
|
|
bitfld.long 0x04 15. " UART3_RST ,Current status of the UART3_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 14. " UART2_RST ,Current status of the UART2_RST" "Reset,No reset"
|
|
bitfld.long 0x04 13. " UART1_RST ,Current status of the UART1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 12. " UART0_RST ,Current status of the UART0_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DAC_RST ,Current status of the DAC_RST" "Reset,No reset"
|
|
bitfld.long 0x04 9. " ADC1_RST ,Current status of the ADC1_RST" "Reset,No reset"
|
|
bitfld.long 0x04 8. " ADC0_RST ,Current status of the ADC0_RST" "Reset,No reset"
|
|
textline " "
|
|
sif (cpuis("LPC183?")||cpuis("LPC185?"))
|
|
bitfld.long 0x04 7. " QEI_RST ,Current status of the QEI_RST" "Reset,No reset"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 6. " MOTOCONPWM_RST ,Current status of the MOTOCONPWM_RST" "Reset,No reset"
|
|
bitfld.long 0x04 5. " SCT_RST ,Current status of the SCT_RST" "Reset,No reset"
|
|
bitfld.long 0x04 4. " RITIMER_RST ,Current status of the RITIMER_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TIMER3_RST ,Current status of the TIMER3_RST" "Reset,No reset"
|
|
bitfld.long 0x04 2. " TIMER2_RST ,Current status of the TIMER2_RST" "Reset,No reset"
|
|
bitfld.long 0x04 1. " TIMER1_RST ,Current status of the TIMER1_RST" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TIMER0_RST ,Current status of the TIMER0_RST" "Reset,No reset"
|
|
endif
|
|
sif (!cpuis("LPC18*"))
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "RESET_EXT_STAT0,Reset external status register 0 for CORE_RST"
|
|
bitfld.long 0x00 5. " WWDT_RESET ,Reset activated by WWDT time-out" "Not activated,Activated"
|
|
bitfld.long 0x00 4. " BOD_RESET ,Reset activated by BOD reset" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " EXT_RESET ,Reset activated by external reset from reset pin" "Not activated,Activated"
|
|
endif
|
|
group.long 0x404++0x07
|
|
line.long 0x00 "RESET_EXT_STAT1,Reset external status register 1 for PERIPH_RST"
|
|
bitfld.long 0x00 1. " CORE_RESET ,Reset activated by CORE_RST output" "Not activated,Activated"
|
|
line.long 0x00 "RESET_EXT_STAT2,Reset external status register 2 for MASTER_RST"
|
|
bitfld.long 0x00 2. " PERIPHERAL_RESET ,Reset activated by output" "Not activated,Activated"
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4333FET100")&&(cpu()!="LPC4333FET256")&&(cpu()!="LPC4337FET100")&&(cpu()!="LPC4337FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4353FBD208")&&(cpu()!="LPC4353FET256")&&(cpu()!="LPC4357FET256")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4333FBD144")&&(cpu()!="LPC4333FET180")&&(cpu()!="LPC4337FBD144")&&(cpu()!="LPC4337FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4353FET180")&&(cpu()!="LPC4357FBD208")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4333FET100-M0")&&(cpu()!="LPC4333FET256-M0")&&(cpu()!="LPC4337FET100-M0")&&(cpu()!="LPC4337FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4353FBD208-M0")&&(cpu()!="LPC4353FET256-M0")&&(cpu()!="LPC4357FET256-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4333FBD144-M0")&&(cpu()!="LPC4333FET180-M0")&&(cpu()!="LPC4337FBD144-M0")&&(cpu()!="LPC4337FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4353FET180-M0")&&(cpu()!="LPC4357FBD208-M0")&&(!cpuis("LPC18*"))
|
|
hgroup.long 0x40C++0x3
|
|
hide.long 0x00 "RESET_EXT_STAT3,Reset external status register 3"
|
|
endif
|
|
group.long 0x410++0x7
|
|
line.long 0x00 "RESET_EXT_STAT4,Reset external status register 4 for WWDT_RST"
|
|
bitfld.long 0x00 1. " CORE_RESET ,Reset activated by CORE_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT5,Reset external status register 5 for CREG_RST"
|
|
bitfld.long 0x04 1. " CORE_RESET ,Reset activated by CORE_RST output" "Not activated,Activated"
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4333FET100")&&(cpu()!="LPC4333FET256")&&(cpu()!="LPC4337FET100")&&(cpu()!="LPC4337FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4353FBD208")&&(cpu()!="LPC4353FET256")&&(cpu()!="LPC4357FET256")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4333FBD144")&&(cpu()!="LPC4333FET180")&&(cpu()!="LPC4337FBD144")&&(cpu()!="LPC4337FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4353FET180")&&(cpu()!="LPC4357FBD208")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4333FET100-M0")&&(cpu()!="LPC4333FET256-M0")&&(cpu()!="LPC4337FET100-M0")&&(cpu()!="LPC4337FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4353FBD208-M0")&&(cpu()!="LPC4353FET256-M0")&&(cpu()!="LPC4357FET256-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4333FBD144-M0")&&(cpu()!="LPC4333FET180-M0")&&(cpu()!="LPC4337FBD144-M0")&&(cpu()!="LPC4337FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4353FET180-M0")&&(cpu()!="LPC4357FBD208-M0")&&(!cpuis("LPC18*"))
|
|
hgroup.long 0x418++0x3
|
|
hide.long 0x00 "RESET_EXT_STAT6,Reset external status register 6"
|
|
hide.long 0x04 "RESET_EXT_STAT7,Reset external status register 7"
|
|
endif
|
|
group.long 0x420++0x7
|
|
line.long 0x00 "RESET_EXT_STAT8,Reset external status registers 8 for BUS_RST"
|
|
bitfld.long 0x00 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT9,Reset external status registers 9 for SCU_RST"
|
|
bitfld.long 0x04 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4333FET100")&&(cpu()!="LPC4333FET256")&&(cpu()!="LPC4337FET100")&&(cpu()!="LPC4337FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4353FBD208")&&(cpu()!="LPC4353FET256")&&(cpu()!="LPC4357FET256")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4333FBD144")&&(cpu()!="LPC4333FET180")&&(cpu()!="LPC4337FBD144")&&(cpu()!="LPC4337FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4353FET180")&&(cpu()!="LPC4357FBD208")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4333FET100-M0")&&(cpu()!="LPC4333FET256-M0")&&(cpu()!="LPC4337FET100-M0")&&(cpu()!="LPC4337FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4353FBD208-M0")&&(cpu()!="LPC4353FET256-M0")&&(cpu()!="LPC4357FET256-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4333FBD144-M0")&&(cpu()!="LPC4333FET180-M0")&&(cpu()!="LPC4337FBD144-M0")&&(cpu()!="LPC4337FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4353FET180-M0")&&(cpu()!="LPC4357FBD208-M0")&&(!cpuis("LPC18*"))
|
|
hgroup.long 0x428++0xB
|
|
hide.long 0x00 "RESET_EXT_STAT10,Reset external status register 10"
|
|
hide.long 0x04 "RESET_EXT_STAT11,Reset external status register 11"
|
|
hide.long 0x08 "RESET_EXT_STAT12,Reset external status register 12"
|
|
endif
|
|
group.long 0x434++0x3
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
line.long 0x00 "RESET_EXT_STAT13,Reset external status register 13 for M4_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
else
|
|
line.long 0x00 "RESET_EXT_STAT13,Reset external status register 13 for M3_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4333FET100")&&(cpu()!="LPC4333FET256")&&(cpu()!="LPC4337FET100")&&(cpu()!="LPC4337FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4353FBD208")&&(cpu()!="LPC4353FET256")&&(cpu()!="LPC4357FET256")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4333FBD144")&&(cpu()!="LPC4333FET180")&&(cpu()!="LPC4337FBD144")&&(cpu()!="LPC4337FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4353FET180")&&(cpu()!="LPC4357FBD208")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4333FET100-M0")&&(cpu()!="LPC4333FET256-M0")&&(cpu()!="LPC4337FET100-M0")&&(cpu()!="LPC4337FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4353FBD208-M0")&&(cpu()!="LPC4353FET256-M0")&&(cpu()!="LPC4357FET256-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4333FBD144-M0")&&(cpu()!="LPC4333FET180-M0")&&(cpu()!="LPC4337FBD144-M0")&&(cpu()!="LPC4337FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4353FET180-M0")&&(cpu()!="LPC4357FBD208-M0")&&(!cpuis("LPC18*"))
|
|
hgroup.long 0x438++0x7
|
|
hide.long 0x00 "RESET_EXT_STAT14,Reset external status register 14"
|
|
hide.long 0x04 "RESET_EXT_STAT15,Reset external status register 15"
|
|
endif
|
|
sif (cpu()=="LPC4350FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4357FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4357FET180-M0")||(cpu()=="LPC4357FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4353FBD208-M0")
|
|
group.long 0x440++0x1B
|
|
line.long 0x00 "RESET_EXT_STAT16,Reset external status register 16 for LCD_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT17,Reset external status register 17 for USB0_RST"
|
|
bitfld.long 0x04 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x08 "RESET_EXT_STAT18,Reset external status register 18 for USB1_RST"
|
|
bitfld.long 0x08 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x0C "RESET_EXT_STAT19,Reset external status register 19 for DMA_RST"
|
|
bitfld.long 0x0C 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x10 "RESET_EXT_STAT20,Reset external status register 20 for SDIO_RST"
|
|
bitfld.long 0x10 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x14 "RESET_EXT_STAT21,Reset external status register 21 for EMC_RST"
|
|
bitfld.long 0x14 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x18 "RESET_EXT_STAT22,Reset external status register 22 for ETHERNET_RST"
|
|
bitfld.long 0x18 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
elif (cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")
|
|
group.long 0x444++0x17
|
|
line.long 0x00 "RESET_EXT_STAT17,Reset external status register 17 for USB0_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT18,Reset external status register 18 for USB1_RST"
|
|
bitfld.long 0x04 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x08 "RESET_EXT_STAT19,Reset external status register 19 for DMA_RST"
|
|
bitfld.long 0x08 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x0C "RESET_EXT_STAT20,Reset external status register 20 for SDIO_RST"
|
|
bitfld.long 0x0C 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x10 "RESET_EXT_STAT21,Reset external status register 21 for EMC_RST"
|
|
bitfld.long 0x10 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x14 "RESET_EXT_STAT22,Reset external status register 22 for ETHERNET_RST"
|
|
bitfld.long 0x14 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
elif (cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4320FBD144-M0")
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "RESET_EXT_STAT17,Reset external status register 17 for USB0_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
group.long 0x44C++0x0B
|
|
line.long 0x00 "RESET_EXT_STAT19,Reset external status register 19 for DMA_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT20,Reset external status register 20 for SDIO_RST"
|
|
bitfld.long 0x04 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x08 "RESET_EXT_STAT21,Reset external status register 21 for EMC_RST"
|
|
bitfld.long 0x08 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
elif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4310FET100-M0")
|
|
group.long 0x44C++0x0B
|
|
line.long 0x00 "RESET_EXT_STAT19,Reset external status register 19 for DMA_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT20,Reset external status register 20 for SDIO_RST"
|
|
bitfld.long 0x04 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x08 "RESET_EXT_STAT21,Reset external status register 21 for EMC_RST"
|
|
bitfld.long 0x08 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
else
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?")&&!cpuis("LPC183?"))
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "RESET_EXT_STAT16,Reset external status register 16 for LCD_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
endif
|
|
sif (!cpuis("LPC181?"))
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "RESET_EXT_STAT17,Reset external status register 17 for USB0_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
endif
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
group.long 0x448++0x03
|
|
line.long 0x0 "RESET_EXT_STAT18,Reset external status register 18 for USB1_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
endif
|
|
group.long 0x44c++0x0b
|
|
line.long 0x0 "RESET_EXT_STAT19,Reset external status register 19 for DMA_RST"
|
|
bitfld.long 0x0 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT20,Reset external status register 20 for SDIO_RST"
|
|
bitfld.long 0x04 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
line.long 0x08 "RESET_EXT_STAT21,Reset external status register 21 for EMC_RST"
|
|
bitfld.long 0x08 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
group.long 0x458++0x03
|
|
line.long 0x0 "RESET_EXT_STAT22,Reset external status register 22 for ETHERNET_RST"
|
|
bitfld.long 0x0 3. " MASTER_RESET ,Reset activated by MASTER_RST output" "Not activated,Activated"
|
|
endif
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4333FET100")&&(cpu()!="LPC4333FET256")&&(cpu()!="LPC4337FET100")&&(cpu()!="LPC4337FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4353FBD208")&&(cpu()!="LPC4353FET256")&&(cpu()!="LPC4357FET256")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4333FBD144")&&(cpu()!="LPC4333FET180")&&(cpu()!="LPC4337FBD144")&&(cpu()!="LPC4337FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4353FET180")&&(cpu()!="LPC4357FBD208")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4333FET100-M0")&&(cpu()!="LPC4333FET256-M0")&&(cpu()!="LPC4337FET100-M0")&&(cpu()!="LPC4337FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4353FBD208-M0")&&(cpu()!="LPC4353FET256-M0")&&(cpu()!="LPC4357FET256-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4333FBD144-M0")&&(cpu()!="LPC4333FET180-M0")&&(cpu()!="LPC4337FBD144-M0")&&(cpu()!="LPC4337FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4353FET180-M0")&&(cpu()!="LPC4357FBD208-M0")&&(!cpuis("LPC18*"))
|
|
hgroup.long 0x45C++0x7
|
|
hide.long 0x00 "RESET_EXT_STAT23,Reset external status register 23"
|
|
hide.long 0x04 "RESET_EXT_STAT24,Reset external status register 24"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850")
|
|
group.long 0x464++0x3
|
|
line.long 0x00 "RESET_EXT_STAT25,Reset external status registers 25 for FLASHA_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
endif
|
|
sif (cpu()=="LPC1853"||cpu()=="LPC1857")
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "RESET_EXT_STAT27,Reset external status registers 27 for EEPROM_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
endif
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "RESET_EXT_STAT28,Reset external status registers 28 for GPIO_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
sif (!cpuis("LPC18?0")&&cpu()!="LPC1812"&&cpu()!="LPC1822")
|
|
group.long 0x474++0x3
|
|
line.long 0x0 "RESET_EXT_STAT29,Reset external status registers 29 for FLASHB_RST"
|
|
bitfld.long 0x0 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144")&&(cpu()=="LPC4320FET100")&&(cpu()=="LPC4330FET100")&&(cpu()=="LPC4330FET256")&&(cpu()=="LPC4350FET180")&&(cpu()=="LPC4310FET100")&&(cpu()=="LPC4320FBD144")&&(cpu()=="LPC4330FBD144")&&(cpu()=="LPC4330FET180")&&(cpu()=="LPC4350FBD208")&&(cpu()=="LPC4350FET256")&&(cpu()=="LPC4310FBD144-M0")&&(cpu()=="LPC4320FET100-M0")&&(cpu()=="LPC4330FET100-M0")&&(cpu()=="LPC4330FET256-M0")&&(cpu()=="LPC4350FET180-M0")&&(cpu()=="LPC4310FET100-M0")&&(cpu()=="LPC4320FBD144-M0")&&(cpu()=="LPC4330FBD144-M0")&&(cpu()=="LPC4330FET180-M0")&&(cpu()=="LPC4350FBD208-M0")&&(cpu()=="LPC4350FET256-M0")
|
|
group.long 0x470++0x3
|
|
line.long 0x00 "RESET_EXT_STAT28,Reset external status registers 28 for GPIO_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4333FET100")&&(cpu()!="LPC4333FET256")&&(cpu()!="LPC4337FET100")&&(cpu()!="LPC4337FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4353FBD208")&&(cpu()!="LPC4353FET256")&&(cpu()!="LPC4357FET256")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4333FBD144")&&(cpu()!="LPC4333FET180")&&(cpu()!="LPC4337FBD144")&&(cpu()!="LPC4337FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4353FET180")&&(cpu()!="LPC4357FBD208")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4333FET100-M0")&&(cpu()!="LPC4333FET256-M0")&&(cpu()!="LPC4337FET100-M0")&&(cpu()!="LPC4337FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4353FBD208-M0")&&(cpu()!="LPC4353FET256-M0")&&(cpu()!="LPC4357FET256-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4333FBD144-M0")&&(cpu()!="LPC4333FET180-M0")&&(cpu()!="LPC4337FBD144-M0")&&(cpu()!="LPC4337FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4353FET180-M0")&&(cpu()!="LPC4357FBD208-M0")&&!cpuis("LPC18*")
|
|
hgroup.long 0x478++0x7
|
|
hide.long 0x00 "RESET_EXT_STAT30,Reset external status register 30"
|
|
hide.long 0x04 "RESET_EXT_STAT31,Reset external status register 31"
|
|
endif
|
|
group.long 0x480++0x1b
|
|
line.long 0x00 "RESET_EXT_STAT32,Reset external status registers 32 for TIMER0_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT33,Reset external status registers 33 for TIMER1_RST"
|
|
bitfld.long 0x04 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x08 "RESET_EXT_STAT34,Reset external status registers 34 for TIMER2_RST"
|
|
bitfld.long 0x08 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x0C "RESET_EXT_STAT35,Reset external status registers 35 for TIMER3_RST"
|
|
bitfld.long 0x0C 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x10 "RESET_EXT_STAT36,Reset external status registers 36 for RITIMER_RST"
|
|
bitfld.long 0x10 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x14 "RESET_EXT_STAT37,Reset external status registers 37 for SCT_RST"
|
|
bitfld.long 0x14 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x18 "RESET_EXT_STAT38,Reset external status registers 38 for MOTOCONPWM_RST"
|
|
bitfld.long 0x18 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
sif (!cpuis("LPC181?")&&!cpuis("LPC182?"))
|
|
group.long 0x49c++0x3
|
|
line.long 0x0 "RESET_EXT_STAT39,Reset external status registers 39 for QEI_RST"
|
|
bitfld.long 0x0 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
endif
|
|
group.long 0x4a0++0xb
|
|
line.long 0x0 "RESET_EXT_STAT40,Reset external status registers 40 for ADC0_RST"
|
|
bitfld.long 0x0 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x4 "RESET_EXT_STAT41,Reset external status registers 41 for ADC1_RST"
|
|
bitfld.long 0x4 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x8 "RESET_EXT_STAT42,Reset external status registers 42 for DAC_RST"
|
|
bitfld.long 0x8 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4333FET100")&&(cpu()!="LPC4333FET256")&&(cpu()!="LPC4337FET100")&&(cpu()!="LPC4337FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4353FBD208")&&(cpu()!="LPC4353FET256")&&(cpu()!="LPC4357FET256")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4333FBD144")&&(cpu()!="LPC4333FET180")&&(cpu()!="LPC4337FBD144")&&(cpu()!="LPC4337FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4353FET180")&&(cpu()!="LPC4357FBD208")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4333FET100-M0")&&(cpu()!="LPC4333FET256-M0")&&(cpu()!="LPC4337FET100-M0")&&(cpu()!="LPC4337FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4353FBD208-M0")&&(cpu()!="LPC4353FET256-M0")&&(cpu()!="LPC4357FET256-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4333FBD144-M0")&&(cpu()!="LPC4333FET180-M0")&&(cpu()!="LPC4337FBD144-M0")&&(cpu()!="LPC4337FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4353FET180-M0")&&(cpu()!="LPC4357FBD208-M0")&&!cpuis("LPC18*")
|
|
hgroup.long 0x4AC++0x3
|
|
hide.long 0x00 "RESET_EXT_STAT43,Reset external status register 43"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
group.long 0x4B0++0x3B
|
|
line.long 0x00 "RESET_EXT_STAT44,Reset external status registers 44 for UART0_RST"
|
|
bitfld.long 0x00 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT45,Reset external status registers 45 for UART1_RST"
|
|
bitfld.long 0x04 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x08 "RESET_EXT_STAT46,Reset external status registers 46 for UART2_RST"
|
|
bitfld.long 0x08 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x0C "RESET_EXT_STAT47,Reset external status registers 47 for UART3_RST"
|
|
bitfld.long 0x0C 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x10 "RESET_EXT_STAT48,Reset external status registers 48 for I2C0_RST"
|
|
bitfld.long 0x10 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x14 "RESET_EXT_STAT49,Reset external status registers 49 for I2C1_RST"
|
|
bitfld.long 0x14 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x18 "RESET_EXT_STAT50,Reset external status registers 50 for SSP0_RST"
|
|
bitfld.long 0x18 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x1C "RESET_EXT_STAT51,Reset external status registers 51 for SSP1_RST"
|
|
bitfld.long 0x1C 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x20 "RESET_EXT_STAT52,Reset external status registers 52 for I2S_RST"
|
|
bitfld.long 0x20 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x24 "RESET_EXT_STAT53,Reset external status registers 53 for SPIFI_RST"
|
|
bitfld.long 0x24 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x28 "RESET_EXT_STAT54,Reset external status registers 54 for CAN1_RST"
|
|
bitfld.long 0x28 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x2C "RESET_EXT_STAT55,Reset external status registers 55 for CAN0_RST"
|
|
bitfld.long 0x2C 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x30 "RESET_EXT_STAT56,Reset external status register 56 for M0APP_RST"
|
|
bitfld.long 0x30 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x34 "RESET_EXT_STAT57,Reset external status register 57 for SGPIO_RST"
|
|
bitfld.long 0x34 3. " MASTER_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x38 "RESET_EXT_STAT58,Reset external status register 58 for SPI_RST"
|
|
bitfld.long 0x38 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
else
|
|
group.long 0x4B0++0x2F
|
|
line.long 0x00 "RESET_EXT_STAT44,Reset external status registers 44 for UART0_RST"
|
|
bitfld.long 0x00 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x04 "RESET_EXT_STAT45,Reset external status registers 45 for UART1_RST"
|
|
bitfld.long 0x04 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x08 "RESET_EXT_STAT46,Reset external status registers 46 for UART2_RST"
|
|
bitfld.long 0x08 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x0C "RESET_EXT_STAT47,Reset external status registers 47 for UART3_RST"
|
|
bitfld.long 0x0C 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x10 "RESET_EXT_STAT48,Reset external status registers 48 for I2C0_RST"
|
|
bitfld.long 0x10 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x14 "RESET_EXT_STAT49,Reset external status registers 49 for I2C1_RST"
|
|
bitfld.long 0x14 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x18 "RESET_EXT_STAT50,Reset external status registers 50 for SSP0_RST"
|
|
bitfld.long 0x18 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x1C "RESET_EXT_STAT51,Reset external status registers 51 for SSP1_RST"
|
|
bitfld.long 0x1C 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x20 "RESET_EXT_STAT52,Reset external status registers 52 for I2S_RST"
|
|
bitfld.long 0x20 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x24 "RESET_EXT_STAT53,Reset external status registers 53 for SPIFI_RST"
|
|
bitfld.long 0x24 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x28 "RESET_EXT_STAT54,Reset external status registers 54 for CAN1_RST"
|
|
bitfld.long 0x28 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
line.long 0x2C "RESET_EXT_STAT55,Reset external status registers 55 for CAN0_RST"
|
|
bitfld.long 0x2C 2. " PERIPHERAL_RESET ,Reset activated by PERIPHERAL_RST output" "Not activated,Activated"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4330FET100")&&(cpu()!="LPC4330FET256")&&(cpu()!="LPC4333FET100")&&(cpu()!="LPC4333FET256")&&(cpu()!="LPC4337FET100")&&(cpu()!="LPC4337FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4353FBD208")&&(cpu()!="LPC4353FET256")&&(cpu()!="LPC4357FET256")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4330FBD144")&&(cpu()!="LPC4330FET180")&&(cpu()!="LPC4333FBD144")&&(cpu()!="LPC4333FET180")&&(cpu()!="LPC4337FBD144")&&(cpu()!="LPC4337FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4353FET180")&&(cpu()!="LPC4357FBD208")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4330FET100-M0")&&(cpu()!="LPC4330FET256-M0")&&(cpu()!="LPC4333FET100-M0")&&(cpu()!="LPC4333FET256-M0")&&(cpu()!="LPC4337FET100-M0")&&(cpu()!="LPC4337FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4353FBD208-M0")&&(cpu()!="LPC4353FET256-M0")&&(cpu()!="LPC4357FET256-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&(cpu()!="LPC4330FBD144-M0")&&(cpu()!="LPC4330FET180-M0")&&(cpu()!="LPC4333FBD144-M0")&&(cpu()!="LPC4333FET180-M0")&&(cpu()!="LPC4337FBD144-M0")&&(cpu()!="LPC4337FET180-M0")&&(cpu()!="LPC4350FBD208-M0")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4353FET180-M0")&&(cpu()!="LPC4357FBD208-M0")&&!cpuis("LPC18*")
|
|
hgroup.long 0x4E0++0x1F
|
|
hide.long 0x0 "RESET_EXT_STAT56,Reset external status register 56"
|
|
hide.long 0x4 "RESET_EXT_STAT57,Reset external status register 57"
|
|
hide.long 0x8 "RESET_EXT_STAT58,Reset external status register 58"
|
|
hide.long 0xC "RESET_EXT_STAT59,Reset external status register 59"
|
|
hide.long 0x10 "RESET_EXT_STAT60,Reset external status register 60"
|
|
hide.long 0x14 "RESET_EXT_STAT61,Reset external status register 61"
|
|
hide.long 0x18 "RESET_EXT_STAT62,Reset external status register 62"
|
|
hide.long 0x1C "RESET_EXT_STAT63,Reset external status register 63"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SCU (System Control Unit / IO configuration)"
|
|
base ad:0x40086000
|
|
width 13.
|
|
tree "Pins P0_n"
|
|
group.long 0x00++0x7
|
|
line.long 0x0 "SFSP0_0,Pin configuration register for pin P0_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO0[0],SSP1_MISO,ENET_RXD1,Reserved,Reserved,Reserved,I2S0_TX_WS,I2S1_TX_WS"
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO0[0],SSP1_MISO,Reserved,Reserved,Reserved,Reserved,I2S0_TX_WS,I2S1_TX_WS"
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSP0_1,Pin configuration register for pin P0_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO0[1],SSP1_MOSI,ENET_COL,Reserved,Reserved,Reserved,ENET_TX_EN,I2S1_TX_SDA"
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO0[1],SSP1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,I2S1_TX_SDA"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins P1_n"
|
|
group.long 0x80++0x53
|
|
line.long 0x0 "SFSP1_0,Pin configuration register for pin P1_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO0[4],CTIN_3,EMC_A5,Reserved,Reserved,SSP0_SSEL,Reserved,EMC_D12"
|
|
endif
|
|
line.long 0x4 "SFSP1_1,Pin configuration register for pin P1_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO0[8],CTOUT_7,EMC_A6,Reserved,Reserved,SSP0_MISO,Reserved,EMC_D13"
|
|
endif
|
|
line.long 0x8 "SFSP1_2,Pin configuration register for pin P1_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO0[9],CTOUT_6,EMC_A7,Reserved,Reserved,SSP0_MOSI,Reserved,EMC_D14"
|
|
endif
|
|
line.long 0xC "SFSP1_3,Pin configuration register for pin P1_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO0[10],CTOUT_8,Reserved,EMC_OE,USB0_IND1,SSP1_MISO,Reserved,SD_RST"
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO0[10],CTOUT_8,Reserved,EMC_OE,Reserved,SSP1_MISO,Reserved,SD_RST"
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSP1_4,Pin configuration register for pin P1_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO0[11],CTOUT_9,Reserved,EMC_BLS0,USB0_IND0,SSP1_MOSI,EMC_D15,SD_VOLT1"
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO0[11],CTOUT_9,Reserved,EMC_BLS0,Reserved,SSP1_MOSI,EMC_D15,SD_VOLT1"
|
|
endif
|
|
endif
|
|
line.long 0x14 "SFSP1_5,Pin configuration register for pin P1_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO1[8],CTOUT_10,Reserved,EMC_CS0,USB0_PWR_FAULT,SSP1_SSEL,Reserved,SD_POW"
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO1[8],CTOUT_10,Reserved,EMC_CS0,Reserved,SSP1_SSEL,Reserved,SD_POW"
|
|
endif
|
|
endif
|
|
line.long 0x18 "SFSP1_6,Pin configuration register for pin P1_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO1[9],CTIN_5,Reserved,EMC_WE,Reserved,EMC_BLS0,Reserved,SD_CMD"
|
|
endif
|
|
line.long 0x1C "SFSP1_7,Pin configuration register for pin P1_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO1[0],U1_DSR,CTOUT_13,EMC_D0,USB0_PWR_EN,?..."
|
|
else
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO1[0],U1_DSR,CTOUT_13,EMC_D0,?..."
|
|
endif
|
|
endif
|
|
line.long 0x20 "SFSP1_8,Pin configuration register for pin P1_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "GPIO1[1],U1_DTR,CTOUT_12,EMC_D1,Reserved,Reserved,Reserved,CD_VOLT0"
|
|
endif
|
|
line.long 0x24 "SFSP1_9,Pin configuration register for pin P1_9"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "GPIO1[2],U1_RTS,CTOUT_11,EMC_D2,Reserved,Reserved,Reserved,SD_DAT0"
|
|
endif
|
|
line.long 0x28 "SFSP1_10,Pin configuration register for pin P1_10"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "GPIO1[3],U1_RI,CTOUT_14,EMC_D3,Reserved,Reserved,Reserved,SD_DAT1"
|
|
endif
|
|
line.long 0x2C "SFSP1_11,Pin configuration register for pin P1_11"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "GPIO1[4],U1_CTS,CTOUT_15,EMC_D4,Reserved,Reserved,Reserved,SD_DAT2"
|
|
endif
|
|
line.long 0x30 "SFSP1_12,Pin configuration register for pin P1_12"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "GPIO1[5],U1_DCD,Reserved,EMC_D5,T0_CAP1,Reserved,Reserved,SD_DAT3"
|
|
endif
|
|
line.long 0x34 "SFSP1_13,Pin configuration register for pin P1_13"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "GPIO1[6],U1_TXD,Reserved,EMC_D6,T0_CAP0,Reserved,Reserved,SD_CD"
|
|
endif
|
|
line.long 0x38 "SFSP1_14,Pin configuration register for pin P1_14"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x38 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x38 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x38 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x38 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x38 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x38 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x38 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x38 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "GPIO1[7],U1_RXD,Reserved,EMC_D7,T0_MAT2,?..."
|
|
endif
|
|
line.long 0x3C "SFSP1_15,Pin configuration register for pin P1_15"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x3C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x3C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x3C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x3C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x3C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x3C 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x3C 0.--2. " MODE ,Select pin function" "GPIO0[2],U2_TXD,Reserved,ENET_RXD0,T0_MAT1,Reserved,EMC_D8,?..."
|
|
else
|
|
bitfld.long 0x3C 0.--2. " MODE ,Select pin function" "GPIO0[2],U2_TXD,Reserved,Reserved,T0_MAT1,Reserved,EMC_D8,?..."
|
|
endif
|
|
endif
|
|
line.long 0x40 "SFSP1_16,Pin configuration register for pin P1_16"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x40 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x40 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x40 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x40 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x40 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x40 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x40 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x40 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x40 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x40 0.--2. " MODE ,Select pin function" "GPIO0[3],U2_RXD,Reserved,ENET_CRS,T0_MAT0,Reserved,EMC_D9,ENET_RX_DV"
|
|
else
|
|
bitfld.long 0x40 0.--2. " MODE ,Select pin function" "GPIO0[3],U2_RXD,Reserved,Reserved,T0_MAT0,Reserved,EMC_D9,?..."
|
|
endif
|
|
endif
|
|
line.long 0x44 "SFSP1_17,Pin configuration register for pin P1_17"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x44 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0x44 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x44 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x44 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x44 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x44 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0x44 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x44 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x44 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x44 0.--2. " MODE ,Select pin function" "GPIO0[12],U2_UCLK,Reserved,ENET_MDIO,T0_CAP3,CAN1_TD,?..."
|
|
else
|
|
bitfld.long 0x44 0.--2. " MODE ,Select pin function" "GPIO0[12],U2_UCLK,Reserved,Reserved,T0_CAP3,CAN1_TD,?..."
|
|
endif
|
|
endif
|
|
line.long 0x48 "SFSP1_18,Pin configuration register for pin P1_18"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x48 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x48 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x48 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x48 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x48 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x48 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x48 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x48 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x48 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x48 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x48 0.--2. " MODE ,Select pin function" "GPIO0[13],U2_DIR,Reserved,ENET_TXD0,T0_MAT3,CAN1_RD,Reserved,EMC_D10"
|
|
else
|
|
bitfld.long 0x48 0.--2. " MODE ,Select pin function" "GPIO0[13],U2_DIR,Reserved,Reserved,T0_MAT3,CAN1_RD,Reserved,EMC_D10"
|
|
endif
|
|
endif
|
|
line.long 0x4C "SFSP1_19,Pin configuration register for pin P1_19"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4C 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x4C 0.--2. " MODE ,Select pin function" "ENET_TX_CLK,SSP1_SCK,Reserved,Reserved,CLKOUT,Reserved,I2S0_RX_MCLK,I2S1_TX_SCK"
|
|
else
|
|
bitfld.long 0x4C 0.--2. " MODE ,Select pin function" "Reserved,SSP1_SCK,Reserved,Reserved,CLKOUT,Reserved,I2S0_RX_MCLK,I2S1_TX_SCK"
|
|
endif
|
|
endif
|
|
line.long 0x50 "SFSP1_20,Pin configuration register for pin P1_20"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x50 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x50 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x50 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x50 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x50 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x50 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x50 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x50 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x50 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x50 3. " EPD ,Enable pull-down resistor at pad" "No,Yes"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x50 0.--2. " MODE ,Select pin function" "GPIO0[15],SSP1_SSEL,Reserved,ENET_TXD1,T0_CAP2,Reserved,Reserved,EMC_D11"
|
|
else
|
|
bitfld.long 0x50 0.--2. " MODE ,Select pin function" "GPIO0[15],SSP1_SSEL,Reserved,Reserved,T0_CAP2,Reserved,Reserved,EMC_D11"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins P2_n"
|
|
group.long 0x100++0x37
|
|
line.long 0x0 "SFSP2_0,Pin configuration register for pin P2_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,U0_TXD,EMC_A13,USB0_PWR_EN,GPIO5[0],Reserved,T3_CAP0,ENET_MDC"
|
|
elif cpuis("LPC182*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,U0_TXD,EMC_A13,USB0_PWR_EN,GPIO5[0],Reserved,T3_CAP0,?..."
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,U0_TXD,EMC_A13,Reserved,GPIO5[0],Reserved,T3_CAP0,?..."
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSP2_1,Pin configuration register for pin P2_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,U0_RXD,EMC_A12,USB0_PWR_FAULT,GPIO5[1],Reserved,T3_CAP1,?..."
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,U0_RXD,EMC_A12,Reserved,GPIO5[1],Reserved,T3_CAP1,?..."
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSP2_2,Pin configuration register for pin P2_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Reserved,U0_UCLK,EMC_A11,USB0_IND1,GPIO5[2],CTIN_6,T3_CAP2,EMC_CS1"
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Reserved,U0_UCLK,EMC_A11,Reserved,GPIO5[2],CTIN_6,T3_CAP2,EMC_CS1"
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSP2_3,Pin configuration register for pin P2_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,I2C1_SDA,U3_TXD,CTIN_1,GPIO5[3],Reserved,T3_MAT0,USB0_PWR_EN"
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,I2C1_SDA,U3_TXD,CTIN_1,GPIO5[3],Reserved,T3_MAT0,?..."
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSP2_4,Pin configuration register for pin P2_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,I2C1_SCL,U3_RXD,CTIN_0,GPIO5[4],Reserved,T3_MAT1,USB0_PWR_FAULT"
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,I2C1_SCL,U3_RXD,CTIN_0,GPIO5[4],Reserved,T3_MAT1,?..."
|
|
endif
|
|
endif
|
|
line.long 0x14 "SFSP2_5,Pin configuration register for pin P2_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,CTIN_2,USB1_VBUS,ADCTRIG1,GPIO5[5],Reserved,T3_MAT2,USB0_IND0"
|
|
elif cpuis("LPC182*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,CTIN_2,Reserved,ADCTRIG1,GPIO5[5],Reserved,T3_MAT2,USB0_IND0"
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,CTIN_2,Reserved,ADCTRIG1,GPIO5[5],Reserved,T3_MAT2,?..."
|
|
endif
|
|
endif
|
|
line.long 0x18 "SFSP2_6,Pin configuration register for pin P2_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,U0_DIR,EMC_A10,USB0_IND0,GPIO5[6],CTIN_7,T3_CAP3,EMC_BLS1"
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,U0_DIR,EMC_A10,Reserved,GPIO5[6],CTIN_7,T3_CAP3,EMC_BLS1"
|
|
endif
|
|
endif
|
|
line.long 0x1C "SFSP2_7,Pin configuration register for pin P2_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO0[7],CTOUT_1,U3_UCLK,EMC_A9,Reserved,Reserved,T3_MAT3,?..."
|
|
endif
|
|
line.long 0x20 "SFSP2_8,Pin configuration register for pin P2_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_0,U3_DIR,EMC_A8,GPIO5[7],?..."
|
|
endif
|
|
line.long 0x24 "SFSP2_9,Pin configuration register for pin P2_9"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "GPIO1[10],CTOUT_3,U3_BAUD,EMC_A0,?..."
|
|
endif
|
|
line.long 0x28 "SFSP2_10,Pin configuration register for pin P2_10"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "GPIO0[14],CTOUT_2,U2_TXD,EMC_A1,?..."
|
|
endif
|
|
line.long 0x2C "SFSP2_11,Pin configuration register for pin P2_11"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "GPIO1[11],CTOUT_5,U2_RXD,EMC_A2,?..."
|
|
endif
|
|
line.long 0x30 "SFSP2_12,Pin configuration register for pin P2_12"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "GPIO1[12],CTOUT_4,Reserved,EMC_A3,Reserved,Reserved,Reserved,U2_UCLK"
|
|
endif
|
|
line.long 0x34 "SFSP2_13,Pin configuration register for pin P2_13"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "GPIO1[13],CTIN_4,Reserved,EMC_A4,Reserved,Reserved,Reserved,U2_DIR"
|
|
endif
|
|
tree.end
|
|
tree "Pins P3_n"
|
|
group.long 0x180++0x23
|
|
line.long 0x0 "SFSP3_0,Pin configuration register for pin P3_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "I2S0_RX_SCK,I2S0_RX_MCLK,I2S0_TX_SCK,I2S0_TX_MCLK,SSP0_SCK,?..."
|
|
endif
|
|
line.long 0x4 "SFSP3_1,Pin configuration register for pin P3_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "I2S0_TX_WS,I2S0_RX_WS,CAN0_RD,USB1_IND1,GPIO5[8],Reserved,LCD_VD15,?..."
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "I2S0_TX_WS,I2S0_RX_WS,CAN0_RD,Reserved,GPIO5[8],?..."
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSP3_2,Pin configuration register for pin P3_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "I2S0_TX_SDA,I2S0_RX_SDA,CAN0_TD,USB1_IND0,GPIO5[9],Reserved,LCD_VD14,?..."
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "I2S0_TX_SDA,I2S0_RX_SDA,CAN0_TD,Reserved,GPIO5[9],Reserved,LCD_VD14,?..."
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSP3_3,Pin configuration register for pin P3_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,Reserved,SSP0_SCK,SPIFI_SCK,CGU_OUT1,Reserved,I2S0_TX_MCLK,I2S1_TX_SCK"
|
|
endif
|
|
line.long 0x10 "SFSP3_4,Pin configuration register for pin P3_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO1[14],Reserved,Reserved,SPIFI_SIO3,U1_TXD,I2S0_TX_WS,I2S1_RX_SDA,LCD_VD13"
|
|
endif
|
|
line.long 0x14 "SFSP3_5,Pin configuration register for pin P3_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO1[15],Reserved,Reserved,SPIFI_SIO2,U1_RXD,I2S0_TX_SDA,I2S1_RX_WS,LCD_VD12"
|
|
endif
|
|
line.long 0x18 "SFSP3_6,Pin configuration register for pin P3_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO0[6],Reserved,SSP0_SSEL,SPIFI_MISO,Reserved,SSP0_MISO,?..."
|
|
endif
|
|
line.long 0x1C "SFSP3_7,Pin configuration register for pin P3_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,Reserved,SSP0_MISO,SPIFI_MOSI,GPIO[10],SSP0_MOSI,?..."
|
|
endif
|
|
line.long 0x20 "SFSP3_8,Pin configuration register for pin P3_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,Reserved,SSP0_MOSI,SPIFI_CS,GPIO5[11],SSP0_SSEL,?..."
|
|
endif
|
|
tree.end
|
|
tree "Pins P4_n"
|
|
group.long 0x200++0x2B
|
|
line.long 0x0 "SFSP4_0,Pin configuration register for pin P4_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO2[0],MCOA0,NMI,Reserved,Reserved,LCD_VD13,U3_UCLK,?..."
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO2[0],MCOA0,NMI,Reserved,Reserved,Reserved,U3_UCLK,?..."
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSP4_1,Pin configuration register for pin P4_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO2[1],CTOUT_1,LCD_VD0,Reserved,Reserved,LCD_VD19,U3_TXD,ENET_COL"
|
|
else
|
|
sif cpuis("LPC183*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO2[1],CTOUT_1,Reserved,Reserved,Reserved,Reserved,U3_TXD,ENET_COL"
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO2[1],CTOUT_1,Reserved,Reserved,Reserved,Reserved,U3_TXD,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSP4_2,Pin configuration register for pin P4_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO2[2],CTOUT_0,LCD_VD3,Reserved,Reserved,LCD_VD12,U3_RXD,?..."
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO2[2],CTOUT_0,Reserved,Reserved,Reserved,Reserved,U3_RXD,?..."
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSP4_3,Pin configuration register for pin P4_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO2[3],CTOUT_3,LCD_VD2,Reserved,Reserved,LCD_VD21,U3_BAUD,?..."
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO2[3],CTOUT_3,Reserved,Reserved,Reserved,Reserved,U3_BAUD,?..."
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSP4_4,Pin configuration register for pin P4_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO2[4],CTOUT_2,LCD_VD1,Reserved,LCD_VD20,U3_DIR,Reserved,DAC"
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO2[4],CTOUT_2,Reserved,Reserved,Reserved,U3_DIR,Reserved,DAC"
|
|
endif
|
|
endif
|
|
line.long 0x14 "SFSP4_5,Pin configuration register for pin P4_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO2[5],CTOUT_5,LCD_FP,?..."
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO2[5],CTOUT_5,?..."
|
|
endif
|
|
endif
|
|
line.long 0x18 "SFSP4_6,Pin configuration register for pin P4_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO2[6],CTOUT_4,LCD_ENAB/LCDM,?..."
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO2[6],CTOUT_4,?..."
|
|
endif
|
|
endif
|
|
line.long 0x1C "SFSP4_7,Pin configuration register for pin P4_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "LCD_DCLK,GP_CLKIN,Reserved,Reserved,Reserved,Reserved,I2S1_TX_SCK,I2S0_TX_SCK"
|
|
else
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,GP_CLKIN,Reserved,Reserved,Reserved,Reserved,I2S1_TX_SCK,I2S0_TX_SCK"
|
|
endif
|
|
endif
|
|
line.long 0x20 "SFSP4_8,Pin configuration register for pin P4_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,CTIN_5,LCD_VD9,Reserved,GPIO5[12],LCD_VD22,CAN1_TD,?..."
|
|
else
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,CTIN_5,Reserved,Reserved,GPIO5[12],Reserved,CAN1_TD,?..."
|
|
endif
|
|
endif
|
|
line.long 0x24 "SFSP4_9,Pin configuration register for pin P4_9"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Reserved,CTIN_6,LCD_VD11,Reserved,GPIO5[13],LCD_VD15,CAN1_RD,?..."
|
|
else
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Reserved,CTIN_6,Reserved,Reserved,GPIO5[13],Reserved,CAN1_RD,?..."
|
|
endif
|
|
endif
|
|
line.long 0x28 "SFSP4_10,Pin configuration register for pin P4_10"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Reserved,CTIN_2,LCD_VD10,Reserved,GPIO5[14],LCD_VD14,?..."
|
|
else
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Reserved,CTIN_2,Reserved,Reserved,GPIO5[14],?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins P5_n"
|
|
group.long 0x280++0x1F
|
|
line.long 0x0 "SFSP5_0,Pin configuration register for pin P5_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO2[9],MCOB2,EMC_D12,Reserved,U1_DSR,T1_CAP0,?..."
|
|
endif
|
|
line.long 0x4 "SFSP5_1,Pin configuration register for pin P5_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO2[10],MCI2,EMC_D13,Reserved,U1_DTR,T1_CAP1,?..."
|
|
endif
|
|
line.long 0x8 "SFSP5_2,Pin configuration register for pin P5_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO2[11],MCI1,EMC_D14,Reserved,U1_RTS,T1_CAP2,?..."
|
|
endif
|
|
line.long 0xC "SFSP5_3,Pin configuration register for pin P5_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO2[12],MCI0,EMC_D15,Reserved,U1_RI,T1_CAP3,?..."
|
|
endif
|
|
line.long 0x10 "SFSP5_4,Pin configuration register for pin P5_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO2[13],MCOB0,EMC_D8,Reserved,U1_CTS,T1_MAT0,?..."
|
|
endif
|
|
line.long 0x14 "SFSP5_5,Pin configuration register for pin P5_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO2[14],MCOA1,EMC_D9,Reserved,U1_DCD,T1_MAT1,?..."
|
|
endif
|
|
line.long 0x18 "SFSP5_6,Pin configuration register for pin P5_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO2[15],MCOB1,EMC_D10,Reserved,U1_TXD,T1_MAT2,?..."
|
|
endif
|
|
line.long 0x1C "SFSP5_7,Pin configuration register for pin P5_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO2[7],MCOA2,EMC_D11,Reserved,U1_RXD,T1_MAT3,?..."
|
|
endif
|
|
tree.end
|
|
tree "Pins P6_n"
|
|
group.long 0x300++0x33
|
|
line.long 0x0 "SFSP6_0,Pin configuration register for pin P6_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,I2S0_RX_MCLK,Reserved,Reserved,I2S0_RX_SCK,?..."
|
|
endif
|
|
line.long 0x4 "SFSP6_1,Pin configuration register for pin P6_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO3[0],EMC_DYCS1,U0_UCLK,I2S0_RX_WS,Reserved,T2_CAP0,?..."
|
|
endif
|
|
line.long 0x8 "SFSP6_2,Pin configuration register for pin P6_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO3[1],EMC_CKEOUT1,U0_DIR,I2S0_RX_SDA,Reserved,T1_CAP1,?..."
|
|
endif
|
|
line.long 0xC "SFSP6_3,Pin configuration register for pin P6_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO3[2],USB0_PWR_EN,Reserved,EMC_CS1,Reserved,T2_CAP2,?..."
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO3[2],Reserved,Reserved,EMC_CS1,Reserved,T2_CAP2,?..."
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSP6_4,Pin configuration register for pin P6_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO3[3],CTIN_6,U0_TXD,EMC_CAS,?..."
|
|
endif
|
|
line.long 0x14 "SFSP6_5,Pin configuration register for pin P6_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO3[4],CTOUT_6,U0_RXD,EMC_RAS,?..."
|
|
endif
|
|
line.long 0x18 "SFSP6_6,Pin configuration register for pin P6_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO0[5],EMC_BLS1,Reserved,USB0_PWR_FAULT,Reserved,T2_CAP3,?..."
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO0[5],EMC_BLS1,Reserved,Reserved,Reserved,T2_CAP3,?..."
|
|
endif
|
|
endif
|
|
line.long 0x1C "SFSP6_7,Pin configuration register for pin P6_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,EMC_A15,Reserved,USB0_IND1,GPIO5[15],T2_MAT0,?..."
|
|
else
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,EMC_A15,Reserved,Reserved,GPIO5[15],T2_MAT0,?..."
|
|
endif
|
|
endif
|
|
line.long 0x20 "SFSP6_8,Pin configuration register for pin P6_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,EMC_A14,Reserved,USB0_IND0,GPIO5[16],T2_MAT1,?..."
|
|
else
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,EMC_A14,Reserved,Reserved,GPIO5[16],T2_MAT1,?..."
|
|
endif
|
|
endif
|
|
line.long 0x24 "SFSP6_9,Pin configuration register for pin P6_9"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "GPIO3[5],Reserved,Reserved,EMC_DYCS0,Reserved,T2_MAT2,?..."
|
|
endif
|
|
line.long 0x28 "SFSP6_10,Pin configuration register for pin P6_10"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "GPIO3[6],MCABORT,Reserved,EMC_DQMOUT1,?..."
|
|
endif
|
|
line.long 0x2C "SFSP6_11,Pin configuration register for pin P6_11"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "GPIO3[7],Reserved,Reserved,EMC_CKEOUT0,Reserved,T2_MAT3,?..."
|
|
endif
|
|
line.long 0x30 "SFSP6_12,Pin configuration register for pin P6_12"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "GPIO2[8],CTOUT_7,Reserved,EMC_DQMOUT0,?..."
|
|
endif
|
|
tree.end
|
|
tree "Pins P7_n"
|
|
group.long 0x380++0x1F
|
|
line.long 0x0 "SFSP7_0,Pin configuration register for pin P7_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO3[8],CTOUT_14,Reserved,LCD_LE,?..."
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO3[8],CTOUT_14,?..."
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSP7_1,Pin configuration register for pin P7_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO3[9],CTOUT_15,I2S0_TX_WS,LCD_VD19,LCD_VD7,Reserved,U2_TXD,?..."
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO3[9],CTOUT_15,I2S0_TX_WS,Reserved,Reserved,Reserved,U2_TXD,?..."
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSP7_2,Pin configuration register for pin P7_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO3[10],CTIN_4,I2S0_TX_SDA,LCD_VD18,LCD_VD6,Reserved,U2_RXD,?..."
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO3[10],CTIN_4,I2S0_TX_SDA,Reserved,Reserved,Reserved,U2_RXD,?..."
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSP7_3,Pin configuration register for pin P7_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO3[11],CTIN_3,Reserved,LCD_VD17,LCD_VD5,?..."
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO3[11],CTIN_3,?..."
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSP7_4,Pin configuration register for pin P7_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO3[12],CTOUT_13,Reserved,LCD_VD16,LCD_VD4,TRACEDATA[0],?..."
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO3[12],CTOUT_13,Reserved,Reserved,Reserved,TRACEDATA[0],?..."
|
|
endif
|
|
endif
|
|
line.long 0x14 "SFSP7_5,Pin configuration register for pin P7_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO3[13],CTOUT_12,Reserved,LCD_VD8,LCD_VD23,TRACEDATA[1],?..."
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO3[13],CTOUT_12,Reserved,Reserved,Reserved,TRACEDATA[1],?..."
|
|
endif
|
|
endif
|
|
line.long 0x18 "SFSP7_6,Pin configuration register for pin P7_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO3[14],CTOUT_11,Reserved,LCD_LP,Reserved,TRACEDATA[2],?..."
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO3[14],CTOUT_11,Reserved,Reserved,Reserved,TRACEDATA[2],?..."
|
|
endif
|
|
endif
|
|
line.long 0x1C "SFSP7_7,Pin configuration register for pin P7_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO3[15],CTOUT_8,Reserved,LCD_PWR,Reserved,TRACEDATA[3],ENET_MDC,?..."
|
|
else
|
|
sif cpuis("LPC183*")
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO3[15],CTOUT_8,Reserved,Reserved,Reserved,TRACEDATA[3],ENET_MDC,?..."
|
|
else
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO3[15],CTOUT_8,Reserved,Reserved,Reserved,TRACEDATA[3],?..."
|
|
endif
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins P8_n"
|
|
group.long 0x400++0x23
|
|
line.long 0x0 "SFSP8_0,Pin configuration register for pin P8_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO4[0],USB0_PWR_FAULT,Reserved,MCI2,Reserved,Reserved,Reserved,T0_MAT0"
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO4[0],Reserved,Reserved,MCI2,Reserved,Reserved,Reserved,T0_MAT0"
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSP8_1,Pin configuration register for pin P8_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO4[1],USB0_IND1,Reserved,MCI1,Reserved,Reserved,Reserved,T0_MAT1"
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO4[1],Reserved,Reserved,MCI1,Reserved,Reserved,Reserved,T0_MAT1"
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSP8_2,Pin configuration register for pin P8_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO4[2],USB0_IND0,Reserved,MCI0,Reserved,Reserved,Reserved,T0_MAT2"
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO4[2],Reserved,Reserved,MCI0,Reserved,Reserved,Reserved,T0_MAT2"
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSP8_3,Pin configuration register for pin P8_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO4[3],USB1_ULPI_D2,Reserved,LCD_VD12,LCD_VD19,Reserved,Reserved,T0_MAT3"
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO4[3],USB1_ULPI_D2,Reserved,Reserved,Reserved,Reserved,Reserved,T0_MAT3"
|
|
endif
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO4[3],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T0_MAT3"
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSP8_4,Pin configuration register for pin P8_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO4[4],USB1_ULPI_D1,Reserved,LCD_VD7,LCD_VD16,Reserved,Reserved,T0_CAP0"
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO4[4],USB1_ULPI_D1,Reserved,Reserved,Reserved,Reserved,Reserved,T0_CAP0"
|
|
endif
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "GPIO4[4],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T0_CAP0"
|
|
endif
|
|
endif
|
|
line.long 0x14 "SFSP8_5,Pin configuration register for pin P8_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO4[5],USB1_ULPI_D0,Reserved,LCD_VD6,LCD_VD8,Reserved,Reserved,T0_CAP1"
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO4[5],USB1_ULPI_D0,Reserved,Reserved,Reserved,Reserved,Reserved,T0_CAP1"
|
|
endif
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "GPIO4[5],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T0_CAP1"
|
|
endif
|
|
endif
|
|
line.long 0x18 "SFSP8_6,Pin configuration register for pin P8_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO4[6],USB1_ULPI_NXT,Reserved,LCD_VD5,LCD_LP,Reserved,Reserved,T0_CAP2"
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO4[6],USB1_ULPI_NXT,Reserved,Reserved,Reserved,Reserved,Reserved,T0_CAP2"
|
|
endif
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO4[6],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T0_CAP2"
|
|
endif
|
|
endif
|
|
line.long 0x1C "SFSP8_7,Pin configuration register for pin P8_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO4[7],USB1_ULPI_STP,Reserved,LCD_VD4,LCD_PWR,Reserved,Reserved,T0_CAP3"
|
|
else
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO4[7],USB1_ULPI_STP,Reserved,Reserved,Reserved,Reserved,Reserved,T0_CAP3"
|
|
endif
|
|
else
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "GPIO4[7],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T0_CAP3"
|
|
endif
|
|
endif
|
|
line.long 0x20 "SFSP8_8,Pin configuration register for pin P8_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_CLK,Reserved,Reserved,Reserved,Reserved,CGU_OUT0,I2S1_TX_MCLK"
|
|
else
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CGU_OUT0,I2S1_TX_MCLK"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins P9_n"
|
|
group.long 0x480++0x1B
|
|
line.long 0x0 "SFSP9_0,Pin configuration register for pin P9_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO4[12],MCABORT,Reserved,Reserved,Reserved,ENET_CRS,Reserved,SSP0_SSEL"
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "GPIO4[12],MCABORT,Reserved,Reserved,Reserved,Reserved,Reserved,SSP0_SSEL"
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSP9_1,Pin configuration register for pin P9_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO4[13],MCOA2,Reserved,Reserved,I2S0_TX_WS,ENET_RX_ER,Reserved,SSP0_MISO"
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO4[13],MCOA2,Reserved,Reserved,I2S0_TX_WS,Reserved,Reserved,SSP0_MISO"
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSP9_2,Pin configuration register for pin P9_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO4[14],MCOB2,Reserved,Reserved,I2S0_TX_SDA,ENET_RXD3,Reserved,SSP0_MOSI"
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO4[14],MCOB2,Reserved,Reserved,I2S0_TX_SDA,Reserved,Reserved,SSP0_MOSI"
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSP9_3,Pin configuration register for pin P9_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO4[15],MCOA0,USB1_IND1,Reserved,Reserved,ENET_RXD2,Reserved,U3_TXD"
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO4[15],MCOA0,Reserved,Reserved,Reserved,Reserved,Reserved,U3_TXD"
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSP9_4,Pin configuration register for pin P9_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,MCOB0,USB1_IND0,Reserved,GPIO5[17],ENET_TXD2,Reserved,U3_RXD"
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,MCOB0,Reserved,Reserved,GPIO5[17],Reserved,Reserved,U3_RXD"
|
|
endif
|
|
endif
|
|
line.long 0x14 "SFSP9_5,Pin configuration register for pin P9_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,MCOA1,USB1_VBUS_EN,Reserved,GPIO5[18],ENET_TXD3,Reserved,U0_TXD"
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,MCOA1,Reserved,Reserved,GPIO5[18],Reserved,Reserved,U0_TXD"
|
|
endif
|
|
endif
|
|
line.long 0x18 "SFSP9_6,Pin configuration register for pin P9_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO4[11],MCOB1,USB1_PWR_FAULT,Reserved,Reserved,ENET_COL,Reserved,U0_RXD"
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "GPIO4[11],MCOB1,Reserved,Reserved,Reserved,Reserved,Reserved,U0_RXD"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins PA_n"
|
|
group.long 0x500++0x13
|
|
line.long 0x0 "SFSPA_0,Pin configuration register for pin PA_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,Reserved,I2S1_RX_MCLK,CGU_OUT1,?..."
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,Reserved,I2S1_RX_MCLK,CGU_OUT1,?..."
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSPA_1,Pin configuration register for pin PA_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO4[8],QEI_IDX,Reserved,U2_TXD,?..."
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "GPIO4[8],Reserved,Reserved,U2_TXD,?..."
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSPA_2,Pin configuration register for pin PA_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO4[9],QEI_PHB,Reserved,U2_RXD,?..."
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "GPIO4[9],Reserved,Reserved,U2_RXD,?..."
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSPA_3,Pin configuration register for pin PA_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 8.--9. " EHD ,Select drive strength" "4 mA,8 mA,14 mA,20 mA"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 8.--9. " EHD ,Select drive strength" "Normal,Medium,High,Ultra high"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO4[10],QEI_PHA,?..."
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "GPIO4[10],?..."
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSPA_4,Pin configuration register for pin PA_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_9,Reserved,EMC_A23,GPIO5[19],?..."
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_9,Reserved,EMC_A23,GPIO5[19],?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins PB_n"
|
|
group.long 0x580++0x1B
|
|
line.long 0x0 "SFSPB_0,Pin configuration register for pin PB_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_10,LCD_VD23,Reserved,GPIO5[20],?..."
|
|
elif cpuis("LPC183*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_10,Reserved,Reserved,GPIO5[20],?..."
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_10,Reserved,Reserved,GPIO5[20],?..."
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSPB_1,Pin configuration register for pin PB_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_DIR,LCD_VD22,Reserved,GPIO5[21],CTOUT_6,?..."
|
|
elif cpuis("LPC183*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_DIR,Reserved,Reserved,GPIO5[21],CTOUT_6,?..."
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO5[21],CTOUT_6,?..."
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSPB_2,Pin configuration register for pin PB_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D7,LCD_VD21,Reserved,GPIO5[22],CTOUT_7,?..."
|
|
elif cpuis("LPC183*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D7,Reserved,Reserved,GPIO5[22],CTOUT_7,?..."
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO5[22],CTOUT_7,?..."
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSPB_3,Pin configuration register for pin PB_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D6,LCD_VD20,Reserved,GPIO5[23],CTOUT_8,?..."
|
|
elif cpuis("LPC183*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D6,Reserved,Reserved,GPIO5[23],CTOUT_8,?..."
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO5[23],CTOUT_8,?..."
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSPB_4,Pin configuration register for pin PB_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D5,LCD_VD15,Reserved,GPIO5[24],CTIN_5,?..."
|
|
elif cpuis("LPC183*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D5,Reserved,Reserved,GPIO5[24],CTIN_5,?..."
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO5[24],CTIN_5,?..."
|
|
endif
|
|
endif
|
|
line.long 0x14 "SFSPB_5,Pin configuration register for pin PB_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D4,LCD_VD14,Reserved,GPIO5[25],CTIN_7,LCD_PWR,?..."
|
|
elif cpuis("LPC183*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D4,Reserved,Reserved,GPIO5[25],CTIN_7,?..."
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO5[25],CTIN_7,?..."
|
|
endif
|
|
endif
|
|
line.long 0x18 "SFSPB_6,Pin configuration register for pin PB_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D3,LCD_VD13,Reserved,GPIO5[26],CTIN_6,LCD_VD19,?..."
|
|
elif cpuis("LPC183*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D3,Reserved,Reserved,GPIO5[26],CTIN_6,?..."
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO5[26],CTIN_6,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins PC_n"
|
|
group.long 0x600++0x3B
|
|
line.long 0x0 "SFSPC_0,Pin configuration register for pin PC_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
sif cpuis("LPC185*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_CLK,Reserved,ENET_RX_CLK,LCD_DCLK,Reserved,Reserved,SD_CLK"
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_CLK,Reserved,ENET_RX_CLK,Reserved,Reserved,Reserved,SD_CLK"
|
|
endif
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD_CLK"
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSPC_1,Pin configuration register for pin PC_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "USB1_ULPI_D7,Reserved,U1_RI,EENET_MDC,GPIO6[0],Reserved,T3_CAP0,SD_VLOT0"
|
|
else
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_RI,Reserved,GPIO6[0],Reserved,T3_CAP0,SD_VLOT0"
|
|
endif
|
|
endif
|
|
line.long 0x8 "SFSPC_2,Pin configuration register for pin PC_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "USB1_ULPI_D6,Reserved,U1_CTS,EENET_TXD2,GPIO6[1],Reserved,Reserved,SD_RST"
|
|
else
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_CTS,EENET_TXD2,GPIO6[1],Reserved,Reserved,SD_RST"
|
|
endif
|
|
endif
|
|
line.long 0xC "SFSPC_3,Pin configuration register for pin PC_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "USB1_ULPI_D5,Reserved,U1_RTS,EENET_TXD3,GPIO6[2],Reserved,Reserved,SD_VOLT1"
|
|
else
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_RTS,Reserved,GPIO6[2],Reserved,Reserved,SD_VOLT1"
|
|
endif
|
|
endif
|
|
line.long 0x10 "SFSPC_4,Pin configuration register for pin PC_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D4,Reserved,ENET_TX_EN,GPIO6[3],Reserved,T3_CAP1,SD_DAT0"
|
|
else
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO6[3],Reserved,T3_CAP1,SD_DAT0"
|
|
endif
|
|
endif
|
|
line.long 0x14 "SFSPC_5,Pin configuration register for pin PC_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D3,Reserved,ENET_TX_ER,GPIO6[4],Reserved,T3_CAP2,SD_DAT1"
|
|
else
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO6[4],Reserved,T3_CAP2,SD_DAT1"
|
|
endif
|
|
endif
|
|
line.long 0x18 "SFSPC_6,Pin configuration register for pin PC_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D2,Reserved,ENET_RXD2,GPIO6[5],Reserved,T3_CAP3,SD_DAT2"
|
|
else
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO6[5],Reserved,T3_CAP3,SD_DAT2"
|
|
endif
|
|
endif
|
|
line.long 0x1C "SFSPC_7,Pin configuration register for pin PC_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D1,Reserved,ENET_RXD3,GPIO6[6],Reserved,T3_MAT0,SD_DAT3"
|
|
else
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO6[6],Reserved,T3_MAT0,SD_DAT3"
|
|
endif
|
|
endif
|
|
line.long 0x20 "SFSPC_8,Pin configuration register for pin PC_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_D0,Reserved,ENET_RX_DV,GPIO6[7],Reserved,T3_MAT1,SD_CD"
|
|
else
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO6[7],Reserved,T3_MAT1,SD_CD"
|
|
endif
|
|
endif
|
|
line.long 0x24 "SFSPC_9,Pin configuration register for pin PC_9"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_NXT,Reserved,ENET_RX_ER,GPIO6[8],Reserved,T3_MAT2,SD_POW"
|
|
else
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,Reserved,GPIO6[8],Reserved,T3_MAT2,SD_POW"
|
|
endif
|
|
endif
|
|
line.long 0x28 "SFSPC_10,Pin configuration register for pin PC_10"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_STP,U1_DSR,Reserved,GPIO6[9],Reserved,T3_MAT3,SD_CMD"
|
|
else
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_DSR,Reserved,GPIO6[9],Reserved,T3_MAT3,SD_CMD"
|
|
endif
|
|
endif
|
|
line.long 0x2C "SFSPC_11,Pin configuration register for pin PC_11"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Reserved,USB1_ULPI_DIR,U1_DCD,Reserved,GPIO6[10],Reserved,Reserved,SD_DAT4"
|
|
else
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_DCD,Reserved,GPIO6[10],Reserved,Reserved,SD_DAT4"
|
|
endif
|
|
endif
|
|
line.long 0x30 "SFSPC_12,Pin configuration register for pin PC_12"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_DTR,Reserved,GPIO6[11],Reserved,I2S0_TX_SDA,SD_DAT5"
|
|
else
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_DTR,Reserved,GPIO6[11],Reserved,I2S0_TX_SDA,SD_DAT5"
|
|
endif
|
|
endif
|
|
line.long 0x34 "SFSPC_13,Pin configuration register for pin PC_13"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_TXD,Reserved,GPIO6[12],Reserved,I2S0_TX_WS,SD_DAT6"
|
|
else
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_TXD,Reserved,GPIO6[12],Reserved,I2S0_TX_WS,SD_DAT6"
|
|
endif
|
|
endif
|
|
line.long 0x38 "SFSPC_14,Pin configuration register for pin PC_14"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x38 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x38 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x38 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x38 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x38 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x38 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x38 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x38 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC185*")||cpuis("LPC183*")
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_RXD,Reserved,GPIO6[13],Reserved,ENET_TX_ER,SD_DAT7"
|
|
else
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "Reserved,Reserved,U1_RXD,Reserved,GPIO6[13],Reserved,Reserved,SD_DAT7"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Pins PD_n"
|
|
group.long 0x680++0x43
|
|
line.long 0x0 "SFSPD_0,Pin configuration register for pin PD_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_15,EMC_DQMOUT2,Reserved,GPIO6[14],?..."
|
|
endif
|
|
line.long 0x4 "SFSPD_1,Pin configuration register for pin PD_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,Reserved,EMC_CKEOUT2,Reserved,GPIO6[15],SD_POW,?..."
|
|
endif
|
|
line.long 0x8 "SFSPD_2,Pin configuration register for pin PD_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_7,EMC_D16,Reserved,GPIO6[16],?..."
|
|
endif
|
|
line.long 0xC "SFSPD_3,Pin configuration register for pin PD_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_6,EMC_D17,Reserved,GPIO6[17],?..."
|
|
endif
|
|
line.long 0x10 "SFSPD_4,Pin configuration register for pin PD_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_8,EMC_D18,Reserved,GPIO6[18],?..."
|
|
endif
|
|
line.long 0x14 "SFSPD_5,Pin configuration register for pin PD_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_9,EMC_D19,Reserved,GPIO6[19],?..."
|
|
endif
|
|
line.long 0x18 "SFSPD_6,Pin configuration register for pin PD_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_10,EMC_D20,Reserved,GPIO6[20],?..."
|
|
endif
|
|
line.long 0x1C "SFSPD_7,Pin configuration register for pin PD_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,CTIN_5,EMC_D21,Reserved,GPIO6[21],?..."
|
|
endif
|
|
line.long 0x20 "SFSPD_8,Pin configuration register for pin PD_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,CTIN_6,EMC_D22,Reserved,GPIO6[22],?..."
|
|
endif
|
|
line.long 0x24 "SFSPD_9,Pin configuration register for pin PD_9"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_13,EMC_D23,Reserved,GPIO6[23],?..."
|
|
endif
|
|
line.long 0x28 "SFSPD_10,Pin configuration register for pin PD_10"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Reserved,CTIN_1,EMC_BLS3,Reserved,GPIO6[24],?..."
|
|
endif
|
|
line.long 0x2C "SFSPD_11,Pin configuration register for pin PD_11"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Reserved,Reserved,EMC_CS3,Reserved,GPIO6[25],USB1_ULPI_D0,CTOUT_14,?..."
|
|
else
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Reserved,Reserved,EMC_CS3,Reserved,GPIO6[25],Reserved,CTOUT_14,?..."
|
|
endif
|
|
endif
|
|
line.long 0x30 "SFSPD_12,Pin configuration register for pin PD_12"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Reserved,Reserved,EMC_CS2,Reserved,GPIO6[26],Reserved,CTOUT_10,?..."
|
|
endif
|
|
line.long 0x34 "SFSPD_13,Pin configuration register for pin PD_13"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Reserved,CTIN_0,EMC_BLS2,Reserved,GPIO6[27],Reserved,CTOUT_13,?..."
|
|
endif
|
|
line.long 0x38 "SFSPD_14,Pin configuration register for pin PD_14"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x38 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x38 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x38 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x38 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x38 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x38 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x38 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x38 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "Reserved,Reserved,EMC_DYCS2,Reserved,GPIO6[28],Reserved,CTOUT_11,?..."
|
|
endif
|
|
line.long 0x3C "SFSPD_15,Pin configuration register for pin PD_15"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x3C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x3C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x3C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x3C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x3C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x3C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0.--2. " MODE ,Select pin function" "Reserved,Reserved,EMC_A17,Reserved,GPIO6[29],SD_WP,CTOUT_8,?..."
|
|
endif
|
|
line.long 0x40 "SFSPD_16,Pin configuration register for pin PD_16"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x40 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x40 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x40 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x40 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x40 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x40 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x40 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x40 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x40 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x40 0.--2. " MODE ,Select pin function" "Reserved,Reserved,EMC_A16,Reserved,GPIO6[30],SD_VOLT2,CTOUT_12,?..."
|
|
endif
|
|
tree.end
|
|
tree "Pins PE_n"
|
|
group.long 0x700++0x3F
|
|
line.long 0x0 "SFSPE_0,Pin configuration register for pin PE_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,EMC_A18,GPIO7[0],CAN1_TD,?..."
|
|
endif
|
|
line.long 0x4 "SFSPE_1,Pin configuration register for pin PE_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,EMC_A19,GPIO7[1],CAN1_RD,?..."
|
|
endif
|
|
line.long 0x8 "SFSPE_2,Pin configuration register for pin PE_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "ADCTRIG0,CAN0_RD,Reserved,EMC_A20,GPIO7[2],?..."
|
|
endif
|
|
line.long 0xC "SFSPE_3,Pin configuration register for pin PE_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,CAN0_TD,ADCTRIG1,EMC_A21,GPIO7[3],?..."
|
|
endif
|
|
line.long 0x10 "SFSPE_4,Pin configuration register for pin PE_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Reserved,NMI,Reserved,EMC_A22,GPIO7[4],?..."
|
|
endif
|
|
line.long 0x14 "SFSPE_5,Pin configuration register for pin PE_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_3,U1_RTS,EMC_D24,GPIO7[5],?..."
|
|
endif
|
|
line.long 0x18 "SFSPE_6,Pin configuration register for pin PE_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_2,U1_RI,EMC_D25,GPIO7[6],?..."
|
|
endif
|
|
line.long 0x1C "SFSPE_7,Pin configuration register for pin PE_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_5,U1_CTS,EMC_D26,GPIO7[7],?..."
|
|
endif
|
|
line.long 0x20 "SFSPE_8,Pin configuration register for pin PE_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_4,U1_DSR,EMC_D27,GPIO7[8],?..."
|
|
endif
|
|
line.long 0x24 "SFSPE_9,Pin configuration register for pin PE_9"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Reserved,CTIN_4,U1_DCD,EMC_D28,GPIO7[9],?..."
|
|
endif
|
|
line.long 0x28 "SFSPE_10,Pin configuration register for pin PE_10"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Reserved,CTIN_3,U1_DTR,EMC_D29,GPIO7[10],?..."
|
|
endif
|
|
line.long 0x2C "SFSPE_11,Pin configuration register for pin PE_11"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_12,U1_TXD,EMC_D30,GPIO7[11],?..."
|
|
endif
|
|
line.long 0x30 "SFSPE_12,Pin configuration register for pin PE_12"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x30 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x30 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x30 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x30 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_11,U1_RXD,EMC_D31,GPIO7[12],?..."
|
|
endif
|
|
line.long 0x34 "SFSPE_13,Pin configuration register for pin PE_13"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x34 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x34 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x34 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x34 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_14,I2C1_SDA,EMC_DQMOUT3,GPIO7[13],?..."
|
|
endif
|
|
line.long 0x38 "SFSPE_14,Pin configuration register for pin PE_14"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x38 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x38 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x38 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x38 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x38 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x38 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x38 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x38 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x38 0.--2. " MODE ,Select pin function" "Reserved,Reserved,Reserved,EMC_DYCS3,GPIO7[14],?..."
|
|
endif
|
|
line.long 0x3C "SFSPE_15,Pin configuration register for pin PE_15"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x3C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x3C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x3C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x3C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x3C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x3C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0.--2. " MODE ,Select pin function" "Reserved,CTOUT_0,I2C1_SCL,EMC_CKEOUT3,GPIO7[15],?..."
|
|
endif
|
|
tree.end
|
|
tree "Pins PF_n"
|
|
group.long 0x780++0x2F
|
|
line.long 0x0 "SFSPF_0,Pin configuration register for pin PF_0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "SSP0_SCK,GP_CLKIN,Reserved,Reserved,Reserved,Reserved,Reserved,I2S1_TX_MCLK"
|
|
endif
|
|
line.long 0x4 "SFSPF_1,Pin configuration register for pin PF_1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Reserved,Reserved,SSP0_SSEL,Reserved,GPIO7[16],?..."
|
|
endif
|
|
line.long 0x8 "SFSPF_2,Pin configuration register for pin PF_2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Reserved,U3_TXD,SSP0_MISO,Reserved,GPIO7[17],?..."
|
|
endif
|
|
line.long 0xC "SFSPF_3,Pin configuration register for pin PF_3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Reserved,U3_RXD,SSP0_MOSI,Reserved,GPIO7[18],?..."
|
|
endif
|
|
line.long 0x10 "SFSPF_4,Pin configuration register for pin PF_4"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x10 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x10 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x10 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--2. " MODE ,Select pin function" "SSP1_SCK,GP_CLKIN,TRACECLK,Reserved,Reserved,Reserved,I2S0_TX_MCLK,I2S0_RX_SCK"
|
|
endif
|
|
line.long 0x14 "SFSPF_5,Pin configuration register for pin PF_5"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x14 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x14 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x14 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x14 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--2. " MODE ,Select pin function" "Reserved,U3_UCLK,SSP1_SSEL,TRACEDATA[0],GPIO7[19],?..."
|
|
endif
|
|
line.long 0x18 "SFSPF_6,Pin configuration register for pin PF_6"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x18 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x18 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x18 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x18 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MODE ,Select pin function" "Reserved,U3_DIR,SSP1_MISO,TRACEDATA[1],GPIO7[20],Reserved,Reserved,I2S1_TX_SDA"
|
|
endif
|
|
line.long 0x1C "SFSPF_7,Pin configuration register for pin PF_7"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x1C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x1C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x1C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--2. " MODE ,Select pin function" "Reserved,U3_BAUD,SSP1_MOSI,TRACEDATA[2],GPIO7[21],Reserved,Reserved,I2S1_TX_WS"
|
|
endif
|
|
line.long 0x20 "SFSPF_8,Pin configuration register for pin PF_8"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x20 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x20 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x20 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x20 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--2. " MODE ,Select pin function" "Reserved,U0_UCLK,CTIN_2,TRACEDATA[3],GPIO7[22],?..."
|
|
endif
|
|
line.long 0x24 "SFSPF_9,Pin configuration register for pin PF_9"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x24 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x24 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x24 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x24 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " MODE ,Select pin function" "Reserved,U0_DIR,CTOUT_1,Reserved,GPIO7[23],?..."
|
|
endif
|
|
line.long 0x28 "SFSPF_10,Pin configuration register for pin PF_10"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x28 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x28 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x28 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x28 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--2. " MODE ,Select pin function" "Reserved,U0_TXD,Reserved,Reserved,GPIO7[24],Reserved,SD_WP,?..."
|
|
endif
|
|
line.long 0x2C "SFSPF_11,Pin configuration register for pin PF_11"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x2C 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x2C 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " EHS ,Slew rate" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x2C 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--2. " MODE ,Select pin function" "Reserved,U0_RXD,Reserved,Reserved,GPIO7[25],Reserved,SD_VOLT2,?..."
|
|
endif
|
|
tree.end
|
|
tree "CLKn pins"
|
|
group.long 0xC00++0xF
|
|
line.long 0x0 "SFSCLK0,Pin configuration register for CLK0"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x0 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x0 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "EMC_CLK0,CLKOUT,Reserved,Reserved,SD_CLK,EMC_CLK01,SSP1_SCK,ENET_TX_CLK"
|
|
else
|
|
bitfld.long 0x0 0.--2. " MODE ,Select pin function" "EMC_CLK0,CLKOUT,Reserved,Reserved,SD_CLK,EMC_CLK01,SSP1_SCK,?..."
|
|
endif
|
|
endif
|
|
line.long 0x4 "SFSCLK1,Pin configuration register for CLK1"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x4 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x4 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x4 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " MODE ,Select pin function" "EMC_CLK1,CLKOUT,Reserved,Reserved,Reserved,CGU_OUT0,Reserved,I2S1_TX_MCLK"
|
|
endif
|
|
line.long 0x8 "SFSCLK2,Pin configuration register for CLK2"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x8 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0x8 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0x8 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0x8 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " MODE ,Select pin function" "EMC_CLK3,CLKOUT,Reserved,Reserved,SD_CLK,EMC_CLK23,I2S0_TX_MCLK,I2S1_RX_SCK"
|
|
endif
|
|
line.long 0xC "SFSCLK3,Pin configuration register for CLK3"
|
|
sif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4330FET100")||(cpu()=="LPC4330FET256")||(cpu()=="LPC4333FET100")||(cpu()=="LPC4333FET256")||(cpu()=="LPC4337FET100")||(cpu()=="LPC4337FET256")||(cpu()=="LPC4350FET180")||(cpu()=="LPC4353FBD208")||(cpu()=="LPC4353FET256")||(cpu()=="LPC4357FET256")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4330FBD144")||(cpu()=="LPC4330FET180")||(cpu()=="LPC4333FBD144")||(cpu()=="LPC4333FET180")||(cpu()=="LPC4337FBD144")||(cpu()=="LPC4337FET180")||(cpu()=="LPC4350FBD208")||(cpu()=="LPC4350FET256")||(cpu()=="LPC4353FET180")||(cpu()=="LPC4357FBD208")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4330FET100-M0")||(cpu()=="LPC4330FET256-M0")||(cpu()=="LPC4333FET100-M0")||(cpu()=="LPC4333FET256-M0")||(cpu()=="LPC4337FET100-M0")||(cpu()=="LPC4337FET256-M0")||(cpu()=="LPC4350FET180-M0")||(cpu()=="LPC4353FBD208-M0")||(cpu()=="LPC4353FET256-M0")||(cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4310FET100-M0")||(cpu()=="LPC4320FBD144-M0")||(cpu()=="LPC4330FBD144-M0")||(cpu()=="LPC4330FET180-M0")||(cpu()=="LPC4333FBD144-M0")||(cpu()=="LPC4333FET180-M0")||(cpu()=="LPC4337FBD144-M0")||(cpu()=="LPC4337FET180-M0")||(cpu()=="LPC4350FBD208-M0")||(cpu()=="LPC4350FET256-M0")||(cpu()=="LPC4353FET180-M0")||(cpu()=="LPC4357FBD208-M0")
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "Enabled,Disabled"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "Default,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0xC 7. " ZIF ,Input glitch filter" "Enabled,Disabled"
|
|
bitfld.long 0xC 6. " EZI ,Input buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " EHS ,Slew rate" "Fast,High-speed"
|
|
textline " "
|
|
bitfld.long 0xC 4. " EPUN ,Disable pull-up resistor at pad" "No,Yes"
|
|
bitfld.long 0xC 3. " EPD ,Enable pull-down resistor at pad" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " MODE ,Select pin function" "EMC_CLK2,CLKOUT,Reserved,Reserved,Reserved,CGU_OUT1,Reserved,I2S1_RX_SCK"
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="LPC4310FBD144")&&(cpu()!="LPC4320FBD100")&&(cpu()!="LPC4320FET100")&&(cpu()!="LPC4310FET100")&&(cpu()!="LPC4320FBD144")&&(cpu()!="LPC4310FBD144-M0")&&(cpu()!="LPC4320FBD100-M0")&&(cpu()!="LPC4320FET100-M0")&&(cpu()!="LPC4310FET100-M0")&&(cpu()!="LPC4320FBD144-M0")&&!cpuis("LPC181*")&&!cpuis("LPC182*")
|
|
tree "USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins"
|
|
group.long 0xC80++0x07
|
|
line.long 0x00 "SFSUSB,Pin configuration for pins USB1_DP/USB1_DM register"
|
|
bitfld.long 0x00 5. " USB_VBUS ,Enable the vbus_valid signal" "Inactive,Active"
|
|
bitfld.long 0x00 4. " USB_EPWR ,Power mode" "Suspend,Normal"
|
|
bitfld.long 0x00 2. " USB_EPD ,Enable pull-down connect" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " USB_ESEA ,Control signal for differential input or single input" "Reserved,Single input"
|
|
bitfld.long 0x00 0. " USB_AIM ,Differential data input AIP/AIM" "Low,High"
|
|
line.long 0x04 "SFSI2C0,Pin configuration for open-drain I2C-bus pins register"
|
|
bitfld.long 0x04 15. " SDA_ZIF ,Enable or disable input glitch filter for the SDA pin" "Enabled,Disabled"
|
|
bitfld.long 0x04 11. " SDA_EZI ,Enable the input receiver for the SDA pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " SDA_EHD ,Select I2C mode for the SDA pin" "Standard/Fast,Fast-mode Plus"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SDA_EFP ,Select input glitch filter time constant for the SDA pin" "50 ns,3 ns"
|
|
bitfld.long 0x04 7. " SCL_ZIF ,Enable or disable input glitch filter for the SCL pin" "Enabled,Disabled"
|
|
bitfld.long 0x04 3. " SCL_EZI ,Enable the input receiver for the SCL pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SCL_EHD ,Select I2C mode for the SCL pin" "Standard/Fast,Fast-mode Plus"
|
|
bitfld.long 0x04 0. " SCL_EFP ,Select input glitch filter time constant for the SCL pin" "50 ns,3 ns"
|
|
tree.end
|
|
endif
|
|
tree "ADC pin select registers"
|
|
group.long 0xC88++0xB
|
|
line.long 0x00 "ENAIO0,ADC0 function select register"
|
|
bitfld.long 0x00 6. " ADC0_6 ,Select ADC0_6 on PB_6" "Digital,Analog"
|
|
bitfld.long 0x00 5. " ADC0_5 ,Select ADC0_5 on PF_10" "Digital,Analog"
|
|
bitfld.long 0x00 4. " ADC0_4 ,Select ADC0_4 on P7_4" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADC0_3 ,Select ADC0_3 on P7_5" "Digital,Analog"
|
|
bitfld.long 0x00 2. " ADC0_2 ,Select ADC0_2 on PF_8" "Digital,Analog"
|
|
bitfld.long 0x00 1. " ADC0_1 ,Select ADC0_1 on P4_1" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADC0_0 ,Select ADC0_0 on P4_3" "Digital,Analog"
|
|
line.long 0x04 "ENAIO1,ADC1 function select register"
|
|
bitfld.long 0x04 7. " ADC1_7 ,Select ADC1_7 on PF_7" "Digital,Analog"
|
|
bitfld.long 0x04 6. " ADC1_6 ,Select ADC1_6 on P7_7" "Digital,Analog"
|
|
bitfld.long 0x04 5. " ADC1_5 ,Select ADC1_5 on PF_11" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ADC1_4 ,Select ADC1_4 on PF_5" "Digital,Analog"
|
|
bitfld.long 0x04 3. " ADC1_3 ,Select ADC1_3 on PF_6" "Digital,Analog"
|
|
bitfld.long 0x04 2. " ADC1_2 ,Select ADC1_2 on PF_9" "Digital,Analog"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ADC1_1 ,Select ADC1_1 on PC_0" "Digital,Analog"
|
|
bitfld.long 0x04 0. " ADC1_0 ,Select ADC1_0 on PC_3" "Digital,Analog"
|
|
line.long 0x8 "ENAIO2,Analog function select register"
|
|
bitfld.long 0x08 4. " BG ,Select band gap output on PF_7" "Digital,Band gap"
|
|
bitfld.long 0x08 0. " DAC ,Select DAC on P4_4" "Digital,Analog"
|
|
tree.end
|
|
tree "EMC delay register"
|
|
group.long 0xD00++0x3
|
|
line.long 0x00 "EMCDELAYCLK,EMC clock delay register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLK_DELAY ,EMC_CLKn SDRAM clock output delay"
|
|
tree.end
|
|
width 10.
|
|
tree "Pin interrupt select registers"
|
|
group.long 0xE00++0x7
|
|
line.long 0x00 "PINTSEL0,Pin interrupt select register 0"
|
|
bitfld.long 0x00 29.--31. " PORTSEL3 ,Port for pin selected in the INTPIN3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " INTPIN3 ,Pint interrupt 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " PORTSEL2 ,Port for pin selected in the INTPIN2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " INTPIN2 ,Pint interrupt 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " PORTSEL1 ,Port for pin selected in the INTPIN1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " INTPIN1 ,Pint interrupt 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " PORTSEL0 ,Port for pin selected in the INTPIN0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " INTPIN0 ,Pint interrupt 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "PINTSEL1,Pin interrupt select register 1"
|
|
bitfld.long 0x04 29.--31. " PORTSEL7 ,Port for pin selected in the INTPIN7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 24.--28. " INTPIN7 ,Pint interrupt 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 21.--23. " PORTSEL6 ,Port for pin selected in the INTPIN6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 16.--20. " INTPIN6 ,Pint interrupt 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 13.--15. " PORTSEL5 ,Port for pin selected in the INTPIN5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--12. " INTPIN5 ,Pint interrupt 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 5.--7. " PORTSEL4 ,Port for pin selected in the INTPIN4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--4. " INTPIN4 ,Pint interrupt 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "GIMA (Global Input Multiplexer Array)"
|
|
base ad:0x400C7000
|
|
width 19.
|
|
group.long 0x00++0x5F
|
|
line.long 0x00 "CAP0_0_IN,Timer 0 CAP0_0 capture input multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 4.--7. " SELECT ,Select input" "CTIN_0,,T0_CAP0,?..."
|
|
else
|
|
bitfld.long 0x00 4.--7. " SELECT ,Select input" "CTIN_0,SGPIO3,T0_CAP0,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x04 "CAP0_1_IN,Timer 0 CAP0_1 capture input multiplexer"
|
|
bitfld.long 0x04 4.--7. " SELECT ,Select input" "CTIN_1,USART2 TX,T0_CAP1,?..."
|
|
bitfld.long 0x04 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x08 "CAP0_2_IN,Timer 0 CAP0_2 capture input multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x08 4.--7. " SELECT ,Select input" "CTIN_2,,T0_CAP2,?..."
|
|
else
|
|
bitfld.long 0x08 4.--7. " SELECT ,Select input" "CTIN_2,SGPIO3_DIV,T0_CAP2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x0C "CAP0_3_IN,Timer 0 CAP0_3 capture input multiplexer"
|
|
bitfld.long 0x0C 4.--7. " SELECT ,Select input" "CTOUT_15/T3_MAT3,T0_CAP3,T3_MAT3,?..."
|
|
bitfld.long 0x0C 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x10 "CAP1_0_IN,Timer 1 CAP1_0 capture input multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x10 4.--7. " SELECT ,Select input" "CTIN_0,,T1_CAP0,?..."
|
|
else
|
|
bitfld.long 0x10 4.--7. " SELECT ,Select input" "CTIN_0,SGPIO12,T1_CAP0,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x14 "CAP1_1_IN,Timer 1 CAP1_1 capture input multiplexer"
|
|
bitfld.long 0x14 4.--7. " SELECT ,Select input" "CTIN_3,USART0 TX,T1_CAP1,?..."
|
|
bitfld.long 0x14 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x18 "CAP1_2_IN,Timer 1 CAP1_2 capture input multiplexer"
|
|
bitfld.long 0x18 4.--7. " SELECT ,Select input" "CTIN_4,USART0 RX,T1_CAP2,?..."
|
|
bitfld.long 0x18 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x1C "CAP1_3_IN,Timer 1 CAP1_3 capture input multiplexer"
|
|
bitfld.long 0x1C 4.--7. " SELECT ,Select input" "CTOUT_3/T0_MAT3,T1_CAP3,T0_MAT3,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x20 "CAP2_0_IN,Timer 2 CAP2_0 capture input multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x20 4.--7. " SELECT ,Select input" "CTIN_0,,T2_CAP0,?..."
|
|
else
|
|
bitfld.long 0x20 4.--7. " SELECT ,Select input" "CTIN_0,SGPIO12_DIV,T2_CAP0,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x24 "CAP2_1_IN,Timer 2 CAP2_1 capture input multiplexer"
|
|
bitfld.long 0x24 4.--7. " SELECT ,Select input" "CTIN_1,USART2 TX,I2S1_RX_MWS,T2_CAP1,?..."
|
|
bitfld.long 0x24 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x24 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x28 "CAP2_2_IN,Timer 2 CAP2_2 capture input multiplexer"
|
|
bitfld.long 0x28 4.--7. " SELECT ,Select input" "CTIN_5,USART2 RX,I2S1_TX_MWS,T2_CAP2,?..."
|
|
bitfld.long 0x28 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x28 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x2C "CAP2_3_IN,Timer 2 CAP2_3 capture input multiplexer"
|
|
bitfld.long 0x2C 4.--7. " SELECT ,Select input" "CTOUT_7/T1_MAT3,T2_CAP3,T1_MAT3,?..."
|
|
bitfld.long 0x2C 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x2C 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x30 "CAP3_0_IN,Timer 3 CAP3_0 capture input multiplexer"
|
|
bitfld.long 0x30 4.--7. " SELECT ,Select input" "CTIN_0,I2S0_RX_MWS,T3_CAP0,?..."
|
|
bitfld.long 0x30 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x30 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x34 "CAP3_1_IN,Timer 3 CAP3_1 capture input multiplexer"
|
|
bitfld.long 0x34 4.--7. " SELECT ,Select input" "CTIN_6,USART3 TX,I2S0_TX_MWS,T3_CAP1,?..."
|
|
bitfld.long 0x34 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x34 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x38 "CAP3_2_IN,Timer 3 CAP3_2 capture input multiplexer"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC4325*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4327*")||cpuis("LPC4337*")||cpuis("LPC4333*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC4370*")||cpuis("LPC43S70*")
|
|
bitfld.long 0x38 4.--7. " SELECT ,Select input" "CTIN_7,USART3 RX,SOF0,T3_CAP2,?..."
|
|
else
|
|
bitfld.long 0x38 4.--7. " SELECT ,Select input" "CTIN_7,USART3 RX,,T3_CAP2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x38 3. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 2. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x3C "CAP3_3_IN,Timer 3 CAP3_3 capture input multiplexer"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC4370*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC43S70*")
|
|
bitfld.long 0x3C 4.--7. " SELECT ,Select input" "CTOUT11/T2_MAT3,SOF1,T3_CAP3,T2_MAT3,?..."
|
|
else
|
|
bitfld.long 0x3C 4.--7. " SELECT ,Select input" "CTOUT11/T2_MAT3,,T3_CAP3,T2_MAT3,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x3C 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x40 "CTIN_0_IN,SCT CTIN_0 capture input multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x40 4.--7. " SELECT ,Select input" "CTIN_0,?..."
|
|
else
|
|
bitfld.long 0x40 4.--7. " SELECT ,Select input" "CTIN_0,SGPIO3,SGPIO3_DIV,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x40 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x40 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x40 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x44 "CTIN_1_IN,SCT CTIN_1 capture input multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x44 4.--7. " SELECT ,Select input" "CTIN_1,USART2 TX,?..."
|
|
else
|
|
bitfld.long 0x44 4.--7. " SELECT ,Select input" "CTIN_1,USART2 TX,SGPIO12,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x44 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x44 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x44 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x48 "CTIN_2_IN,SCT CTIN_2 capture input multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x48 4.--7. " SELECT ,Select input" "CTIN_2,?..."
|
|
else
|
|
bitfld.long 0x48 4.--7. " SELECT ,Select input" "CTIN_2,SGPIO12,SGPIO12_DIV,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x48 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x48 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x48 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x4C "CTIN_3_IN,SCT CTIN_3 capture input multiplexer"
|
|
sif cpuis("LPC43*")||cpuis("LPC43S*")
|
|
bitfld.long 0x4C 4.--7. " SELECT ,Select input" "CTIN3,USART0 TX,I2S1_RX_MWS,I2S1_TX_MWS,?..."
|
|
else
|
|
bitfld.long 0x4C 4.--7. " SELECT ,Select input" "CTIN3,USART0 TX,?..."
|
|
endif
|
|
bitfld.long 0x4C 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x4C 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x50 "CTIN_4_IN,SCT CTIN_4 capture input multiplexer"
|
|
sif cpuis("LPC43*")||cpuis("LPC43S*")
|
|
bitfld.long 0x50 4.--7. " SELECT ,Select input" "CTIN4,USART0 RX,I2S1_RX_MWS,I2S1_TX_MWS,?..."
|
|
else
|
|
bitfld.long 0x50 4.--7. " SELECT ,Select input" "CTIN4,USART0 RX,I2S1_RX_MWS1,I2S1_TX_MWS1,-,-,?..."
|
|
endif
|
|
bitfld.long 0x50 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x50 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x54 "CTIN_5_IN,SCT CTIN_5 capture input multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x54 4.--7. " SELECT ,Select input" "CTIN_5,USART2 RX,?..."
|
|
else
|
|
bitfld.long 0x54 4.--7. " SELECT ,Select input" "CTIN_5,USART2 RX,SGPIO12_DIV,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x54 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x54 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x54 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x58 "CTIN_6_IN,SCT CTIN_6 capture input multiplexer"
|
|
bitfld.long 0x58 4.--7. " SELECT ,Select input" "CTIN6,USART3 TX,I2S0_RX_MWS,I2S0_TX_MWS,?..."
|
|
bitfld.long 0x58 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x58 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x5C "CTIN_7_IN,SCT CTIN_7 capture input multiplexer"
|
|
sif (cpu()=="LPC4320FBD100")||(cpu()=="LPC4320FET100")||(cpu()=="LPC4320FBD144")||(cpu()=="LPC4320FBD100-M0")||(cpu()=="LPC4320FET100-M0")||(cpu()=="LPC4320FBD144-M0")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")
|
|
bitfld.long 0x5C 4.--7. " SELECT ,Select input" "CTIN_7,USART3 RX,SOF0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4310FBD144")||(cpu()=="LPC4310FET100")||(cpu()=="LPC4310FBD144-M0")||(cpu()=="LPC4310FET100-M0")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")
|
|
bitfld.long 0x5C 4.--7. " SELECT ,Select input" "CTIN_7,USART3 RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x5C 4.--7. " SELECT ,Select input" "CTIN7,USART3 RX,SOF0,SOF1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x5C 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x5C 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x5C 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
sif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "ADCHS_TRIGGER_IN,ADCHS trigger input multiplexer"
|
|
bitfld.long 0x00 4.--7. " SELECT ,Select input" "GPIO6,GPIO5,SGPIO10,SGPIO12,,MCOB2,CTOUT_0/T0_MAT0,CTOUT_8/T2_MAT0,T0_MAT0,T2_MAT0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
endif
|
|
group.long 0x64++0x13
|
|
line.long 0x00 "EVENTROUTER_13_IN,Event router input 13 multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 4.--7. " SELECT ,Select input" "CTOUT_2/T0_MAT2,,T0_MAT2,?..."
|
|
else
|
|
bitfld.long 0x00 4.--7. " SELECT ,Select input" "CTOUT_2/T0_MAT2,SGPIO3,T0_MAT2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x04 "EVENTROUTER_14_IN,Event router input 14 multiplexer"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x04 4.--7. " SELECT ,Select input" "CTOUT_6/T1_MAT2,,T1_MAT2,?..."
|
|
else
|
|
bitfld.long 0x04 4.--7. " SELECT ,Select input" "CTOUT_6/T1_MAT2,SGPIO12,T1_MAT2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x08 "EVENTROUTER_16_IN,Event router input 16 multiplexer"
|
|
bitfld.long 0x08 4.--7. " SELECT ,Select input" "CTOUT_14/T3_MAT2,T3_MAT2,?..."
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x0C "ADCSTART0_IN,ADC start0 input multiplexer"
|
|
bitfld.long 0x0C 4.--7. " SELECT ,Select input" "CTOUT_15/T3_MAT3,T0_MAT0,?..."
|
|
bitfld.long 0x0C 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x10 "ADCSTART1_IN,ADC start1 input multiplexer"
|
|
bitfld.long 0x10 4.--7. " SELECT ,Select input" "CTOUT_8/T2_MAT0,T2_MAT0,?..."
|
|
bitfld.long 0x10 3. " PULSE ,Enable single pulse generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SYNCH ,Enable synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " EDGE ,Enable rising edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " INV ,Invert input" "Not inverted,Inverted"
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO (General Purpose Input/Output)"
|
|
base ad:0x40088000
|
|
tree "GPIO pin interrupts"
|
|
base ad:0x40087000
|
|
width 0x6
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "ISEL,Pin Interrupt Mode register"
|
|
bitfld.long 0x00 7. " PMODE[7] ,PINTSEL7 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 6. " PMODE[6] ,PINTSEL6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 5. " PMODE[5] ,PINTSEL5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PMODE[4] ,PINTSEL4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 3. " PMODE[3] ,PINTSEL3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 2. " PMODE[2] ,PINTSEL2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PMODE[1] ,PINTSEL1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 0. " PMODE[0] ,PINTSEL0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
line.long 0x04 "IENR,Pin Interrupt Enable (Rising) register"
|
|
setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " IENR.7_set/clr ,Rising edge or level interrupt for pin 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " IENR.6_set/clr ,Rising edge or level interrupt for pin 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " IENR.5_set/clr ,Rising edge or level interrupt for pin 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " IENR.4_set/clr ,Rising edge or level interrupt for pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " IENR.3_set/clr ,Rising edge or level interrupt for pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " IENR.2_set/clr ,Rising edge or level interrupt for pin 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " IENR.1_set/clr ,Rising edge or level interrupt for pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " IENR.0_set/clr ,Rising edge or level interrupt for pin 0 enable" "Disabled,Enabled"
|
|
line.long 0x10 "IENF,Pin Interrupt Enable Falling Edge / Active Level register"
|
|
setclrfld.long 0x10 7. 0x14 7. 0x18 7. " IENF.7_set/clr ,Rising edge or level interrupt for pin 7 enable / Active interrupt level" "Disabled/Low,Enabled/High"
|
|
setclrfld.long 0x10 6. 0x14 6. 0x18 6. " IENF.6_set/clr ,Rising edge or level interrupt for pin 6 enable / Active interrupt level" "Disabled/Low,Enabled/High"
|
|
setclrfld.long 0x10 5. 0x14 5. 0x18 5. " IENF.5_set/clr ,Rising edge or level interrupt for pin 5 enable / Active interrupt level" "Disabled/Low,Enabled/High"
|
|
textline " "
|
|
setclrfld.long 0x10 4. 0x14 4. 0x18 4. " IENF.4_set/clr ,Rising edge or level interrupt for pin 4 enable / Active interrupt level" "Disabled/Low,Enabled/High"
|
|
setclrfld.long 0x10 3. 0x14 3. 0x18 3. " IENF.3_set/clr ,Rising edge or level interrupt for pin 3 enable / Active interrupt level" "Disabled/Low,Enabled/High"
|
|
setclrfld.long 0x10 2. 0x14 2. 0x18 2. " IENF.2_set/clr ,Rising edge or level interrupt for pin 2 enable / Active interrupt level" "Disabled/Low,Enabled/High"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x14 1. 0x18 1. " IENF.1_set/clr ,Rising edge or level interrupt for pin 1 enable / Active interrupt level" "Disabled/Low,Enabled/High"
|
|
setclrfld.long 0x10 0. 0x14 0. 0x18 0. " IENF.0_set/clr ,Rising edge or level interrupt for pin 0 enable / Active interrupt level" "Disabled/Low,Enabled/High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "RISE,Pin Interrupt Rising Edge register"
|
|
eventfld.long 0x00 7. " RDET[7] ,PINTSEL7 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 6. " RDET[6] ,PINTSEL6 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDET[5] ,PINTSEL5 rising edge detect" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RDET[4] ,PINTSEL4 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 3. " RDET[3] ,PINTSEL3 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 2. " RDET[2] ,PINTSEL2 rising edge detect" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RDET[1] ,PINTSEL1 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " RDET[0] ,PINTSEL0 rising edge detect" "Not detected,Detected"
|
|
line.long 0x04 "FALL,Pin Interrupt Falling Edge register"
|
|
eventfld.long 0x04 7. " FDET[7] ,PINTSEL7 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 6. " FDET[6] ,PINTSEL6 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 5. " FDET[5] ,PINTSEL5 falling edge detect" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x04 4. " FDET[4] ,PINTSEL4 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 3. " FDET[3] ,PINTSEL3 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 2. " FDET[2] ,PINTSEL2 falling edge detect" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x04 1. " FDET[1] ,PINTSEL1 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 0. " FDET[0] ,PINTSEL0 falling edge detect" "Not detected,Detected"
|
|
line.long 0x08 "IST,Pin Interrupt Status register"
|
|
eventfld.long 0x08 7. " PSTAT[7] ,PINTSEL7 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 6. " PSTAT[6] ,PINTSEL6 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 5. " PSTAT[5] ,PINTSEL5 interrupt status" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 4. " PSTAT[4] ,PINTSEL4 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 3. " PSTAT[3] ,PINTSEL3 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 2. " PSTAT[2] ,PINTSEL2 interrupt status" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 1. " PSTAT[1] ,PINTSEL1 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 0. " PSTAT[0] ,PINTSEL0 interrupt status" "Not requested,Requested"
|
|
tree.end
|
|
tree "GPIO GROUP0 interrupt"
|
|
base ad:0x40088000
|
|
width 0xB
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CTRL,GPIO grouped interrupt control register"
|
|
bitfld.long 0x00 2. " TRIG ,Group interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "Or,And"
|
|
bitfld.long 0x00 0. " INT ,Group interrupt trigger" "Edge,Level"
|
|
tree "Port 0"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "PORT_POL0,GPIO grouped interrupt port 0 polarity register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()=="LPC11A11"&&cpu()=="LPC11A13")
|
|
bitfld.long 0x00 27. " POL0[27] ,Pin P0_27 polarity" "Low,High"
|
|
bitfld.long 0x00 26. " POL0[26] ,Pin P0_26 polarity" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " POL0[31] ,Pin P0_31 polarity" "Low,High"
|
|
bitfld.long 0x00 30. " POL0[30] ,Pin P0_30 polarity" "Low,High"
|
|
bitfld.long 0x00 29. " POL0[29] ,Pin P0_29 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " POL0[28] ,Pin P0_28 polarity" "Low,High"
|
|
bitfld.long 0x00 27. " POL0[27] ,Pin P0_27 polarity" "Low,High"
|
|
bitfld.long 0x00 26. " POL0[26] ,Pin P0_26 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " POL0[25] ,Pin P0_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL0[24] ,Pin P0_24 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 15. " POL0[15] ,Pin P0_15 polarity" "Low,High"
|
|
textline " "
|
|
else
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04")
|
|
bitfld.long 0x00 23. " POL0[23] ,Pin P0_23 polarity" "Low,High"
|
|
bitfld.long 0x00 22. " POL0[22] ,Pin P0_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL0[21] ,Pin P0_21 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " POL0[20] ,Pin P0_20 polarity" "Low,High"
|
|
bitfld.long 0x00 19. " POL0[19] ,Pin P0_19 polarity" "Low,High"
|
|
bitfld.long 0x00 18. " POL0[18] ,Pin P0_18 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " POL0[17] ,Pin P0_17 polarity" "Low,High"
|
|
bitfld.long 0x00 16. " POL0[16] ,Pin P0_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL0[15] ,Pin P0_15 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " POL0[14] ,Pin P0_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL0[13] ,Pin P0_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL0[12] ,Pin P0_12 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " POL0[11] ,Pin P0_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL0[10] ,Pin P0_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL0[9] ,Pin P0_9 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POL0[8] ,Pin P0_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL0[7] ,Pin P0_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL0[6] ,Pin P0_6 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " POL0[5] ,Pin P0_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL0[4] ,Pin P0_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL0[3] ,Pin P0_3 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " POL0[2] ,Pin P0_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL0[1] ,Pin P0_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL0[0] ,Pin P0_0 polarity" "Low,High"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "PORT_ENA0,GPIO grouped interrupt port 0 enable register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()=="LPC11A11"&&cpu()=="LPC11A13")
|
|
bitfld.long 0x00 27. " ENA0[27] ,Pin P0_27 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA0[26] ,Pin P0_26 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " ENA0[31] ,Pin P0_31 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ENA0[30] ,Pin P0_30 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ENA0[29] ,Pin P0_29 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ENA0[28] ,Pin P0_28 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ENA0[27] ,Pin P0_27 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA0[26] ,Pin P0_26 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " ENA0[25] ,Pin P0_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA0[24] ,Pin P0_24 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 15. " ENA0[15] ,Pin P0_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04")
|
|
bitfld.long 0x00 23. " ENA0[23] ,Pin P0_23 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENA0[22] ,Pin P0_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA0[21] ,Pin P0_21 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENA0[20] ,Pin P0_20 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENA0[19] ,Pin P0_19 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENA0[18] ,Pin P0_18 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " ENA0[17] ,Pin P0_17 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENA0[16] ,Pin P0_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA0[15] ,Pin P0_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " ENA0[14] ,Pin P0_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA0[13] ,Pin P0_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA0[12] ,Pin P0_12 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA0[11] ,Pin P0_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA0[10] ,Pin P0_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA0[9] ,Pin P0_9 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENA0[8] ,Pin P0_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA0[7] ,Pin P0_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA0[6] ,Pin P0_6 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA0[5] ,Pin P0_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA0[4] ,Pin P0_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA0[3] ,Pin P0_3 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA0[2] ,Pin P0_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA0[1] ,Pin P0_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA0[0] ,Pin P0_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
sif (cpuis("LPC11U*")||cpuis("LPC11E*")||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
tree "Port 1"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "PORT_POL1,GPIO grouped interrupt port 1 polarity register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
bitfld.long 0x00 15. " POL1[15] ,Pin P1_15 polarity" "Low,High"
|
|
textline " "
|
|
elif cpu()=="LPC11E11"
|
|
bitfld.long 0x00 24. " POL1[24] ,Pin P1_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL1[23] ,Pin P1_23 polarity" "Low,High"
|
|
bitfld.long 0x00 19. " POL1[19] ,Pin P1_19 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL1[15] ,Pin P1_15 polarity" "Low,High"
|
|
else
|
|
bitfld.long 0x00 31. " POL1[31] ,Pin P1_31 polarity" "Low,High"
|
|
sif (!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 30. " POL1[30] ,Pin P1_30 polarity" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 29. " POL1[29] ,Pin P1_29 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " POL1[28] ,Pin P1_28 polarity" "Low,High"
|
|
bitfld.long 0x00 27. " POL1[27] ,Pin P1_27 polarity" "Low,High"
|
|
bitfld.long 0x00 26. " POL1[26] ,Pin P1_26 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " POL1[25] ,Pin P1_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL1[24] ,Pin P1_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL1[23] ,Pin P1_23 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL1[22] ,Pin P1_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL1[21] ,Pin P1_21 polarity" "Low,High"
|
|
bitfld.long 0x00 20. " POL1[20] ,Pin P1_20 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL1[19] ,Pin P1_19 polarity" "Low,High"
|
|
sif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U14*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")&&cpu()!="LPC11E12"&&cpu()!="LPC11E13")
|
|
bitfld.long 0x00 18. " POL1[18] ,Pin P1_18 polarity" "Low,High"
|
|
bitfld.long 0x00 17. " POL1[17] ,Pin P1_17 polarity" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL1[16] ,Pin P1_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL1[15] ,Pin P1_15 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="LPC11E11"
|
|
sif cpuis("LPC11E*")||cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U14*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")
|
|
bitfld.long 0x00 14. " POL1[14] ,Pin P1_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL1[13] ,Pin P1_13 polarity" "Low,High"
|
|
sif cpuis("LPC11U14*")
|
|
bitfld.long 0x00 5. " POL1[5] ,Pin P1_5 polarity" "Low,High"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 14. " POL1[14] ,Pin P1_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL1[13] ,Pin P1_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL1[12] ,Pin P1_12 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " POL1[11] ,Pin P1_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL1[10] ,Pin P1_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL1[9] ,Pin P1_9 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POL1[8] ,Pin P1_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL1[7] ,Pin P1_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL1[6] ,Pin P1_6 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " POL1[5] ,Pin P1_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL1[4] ,Pin P1_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL1[3] ,Pin P1_3 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " POL1[2] ,Pin P1_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL1[1] ,Pin P1_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL1[0] ,Pin P1_0 polarity" "Low,High"
|
|
endif
|
|
endif
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "PORT_ENA1,GPIO grouped interrupt port 1 enable register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
bitfld.long 0x00 15. " ENA1_15 ,Pin P1_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpu()=="LPC11E11"
|
|
bitfld.long 0x00 24. " ENA1_24 ,Pin P1_24 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENA1_23 ,Pin P1_23 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENA1_19 ,Pin P1_19 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENA1_15 ,Pin P1_15 for group interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 31. " ENA1_31 ,Pin P1_31 for group interrupt enable" "Disabled,Enabled"
|
|
sif (!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 30. " ENA1_30 ,Pin P1_30 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 29. " ENA1_29 ,Pin P1_29 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ENA1_28 ,Pin P1_28 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ENA1_27 ,Pin P1_27 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA1_26 ,Pin P1_26 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ENA1_25 ,Pin P1_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA1_24 ,Pin P1_24 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENA1_23 ,Pin P1_23 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ENA1_22 ,Pin P1_22 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA1_21 ,Pin P1_21 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENA1_20 ,Pin P1_20 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ENA1_19 ,Pin P1_19 for group interrupt enable" "Disabled,Enabled"
|
|
sif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U14*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")&&cpu()!="LPC11E12"&&cpu()!="LPC11E13")
|
|
bitfld.long 0x00 18. " ENA1_18 ,Pin P1_18 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENA1_17 ,Pin P1_17 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENA1_16 ,Pin P1_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA1_15 ,Pin P1_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="LPC11E11"
|
|
sif cpuis("LPC11E*")||cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U14*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")
|
|
bitfld.long 0x00 14. " ENA1_14 ,Pin P1_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA1_13 ,Pin P1_13 for group interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("LPC11U14*")
|
|
bitfld.long 0x00 5. " ENA1_5 ,Pin P1_5 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 14. " ENA1_14 ,Pin P1_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA1_13 ,Pin P1_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA1_12 ,Pin P1_12 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA1_11 ,Pin P1_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA1_10 ,Pin P1_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA1_9 ,Pin P1_9 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENA1_8 ,Pin P1_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA1_7 ,Pin P1_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA1_6 ,Pin P1_6 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA1_5 ,Pin P1_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA1_4 ,Pin P1_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA1_3 ,Pin P1_3 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA1_2 ,Pin P1_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA1_1 ,Pin P1_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA1_0 ,Pin P1_0 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
tree "Port 2"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PORT_POL2,GPIO grouped interrupt port 2 polarity register"
|
|
bitfld.long 0x00 15. " POL2[15] ,Pin P2_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL2[14] ,Pin P2_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL2[13] ,Pin P2_13 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " POL2[12] ,Pin P2_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL2[11] ,Pin P2_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL2[10] ,Pin P2_10 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POL2[9] ,Pin P2_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL2[8] ,Pin P2_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL2[7] ,Pin P2_7 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " POL2[6] ,Pin P2_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL2[5] ,Pin P2_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL2[4] ,Pin P2_4 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL2[3] ,Pin P2_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL2[2] ,Pin P2_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL2[1] ,Pin P2_1 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POL2[0] ,Pin P2_0 polarity" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PORT_ENA2,GPIO grouped interrupt port 2 enable register"
|
|
bitfld.long 0x00 15. " ENA2[15] ,Pin P2_15 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA2[14] ,Pin P2_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA2[13] ,Pin P2_13 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENA2[12] ,Pin P2_12 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENA2[11] ,Pin P2_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA2[10] ,Pin P2_10 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENA2[9] ,Pin P2_9 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA2[8] ,Pin P2_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA2[7] ,Pin P2_7 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENA2[6] ,Pin P2_6 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA2[5] ,Pin P2_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA2[4] ,Pin P2_4 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA2[3] ,Pin P2_3 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA2[2] ,Pin P2_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA2[1] ,Pin P2_1 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA2[0] ,Pin P2_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Port 3"
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "PORT_POL3,GPIO grouped interrupt port 1 polarity register"
|
|
bitfld.long 0x00 15. " POL3[15] ,Pin P3_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL3[14] ,Pin P3_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL3[13] ,Pin P3_13 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " POL3[12] ,Pin P3_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL3[11] ,Pin P3_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL3[10] ,Pin P3_10 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POL3[9] ,Pin P3_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL3[8] ,Pin P3_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL3[7] ,Pin P3_7 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " POL3[6] ,Pin P3_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL3[5] ,Pin P3_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL3[4] ,Pin P3_4 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL3[3] ,Pin P3_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL3[2] ,Pin P3_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL3[1] ,Pin P3_1 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POL3[0] ,Pin P3_0 polarity" "Low,High"
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "PORT_ENA3,GPIO grouped interrupt port 3 enable register"
|
|
bitfld.long 0x00 15. " ENA3[15] ,Pin P3_15 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA3[14] ,Pin P3_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA3[13] ,Pin P3_13 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENA3[12] ,Pin P3_12 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENA3[11] ,Pin P3_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA3[10] ,Pin P3_10 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENA3[9] ,Pin P3_9 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA3[8] ,Pin P3_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA3[7] ,Pin P3_7 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENA3[6] ,Pin P3_6 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA3[5] ,Pin P3_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA3[4] ,Pin P3_4 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA3[3] ,Pin P3_3 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA3[2] ,Pin P3_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA3[1] ,Pin P3_1 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA3[0] ,Pin P3_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Port 4"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PORT_POL4,GPIO grouped interrupt port 1 polarity register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " POL4[11] ,Pin P4_11 polarity" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 15. " POL4[15] ,Pin P4_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL4[14] ,Pin P4_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL4[13] ,Pin P4_13 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " POL4[12] ,Pin P4_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL4[11] ,Pin P4_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL4[10] ,Pin P4_10 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POL4[9] ,Pin P4_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL4[8] ,Pin P4_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL4[7] ,Pin P4_7 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " POL4[6] ,Pin P4_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL4[5] ,Pin P4_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL4[4] ,Pin P4_4 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL4[3] ,Pin P4_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL4[2] ,Pin P4_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL4[1] ,Pin P4_1 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POL4[0] ,Pin P4_0 polarity" "Low,High"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "PORT_ENA4,GPIO grouped interrupt port 4 enable register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " ENA4[11] ,Pin P0_11 for group interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " ENA4[15] ,Pin P0_15 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA4[14] ,Pin P0_14 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENA4[13] ,Pin P0_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA4[12] ,Pin P0_12 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENA4[11] ,Pin P0_11 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ENA4[10] ,Pin P0_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA4[9] ,Pin P0_9 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA4[8] ,Pin P0_8 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENA4[7] ,Pin P0_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA4[6] ,Pin P0_6 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA4[5] ,Pin P0_5 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA4[4] ,Pin P0_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA4[3] ,Pin P0_3 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA4[2] ,Pin P0_2 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENA4[1] ,Pin P0_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA4[0] ,Pin P0_0 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Port 5"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "PORT_POL5,GPIO grouped interrupt port 1 polarity register"
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
bitfld.long 0x00 26. " POL5[26] ,Pin P5_26 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " POL5[25] ,Pin P5_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL5[24] ,Pin P5_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL5[23] ,Pin P5_23 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL5[22] ,Pin P5_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL5[21] ,Pin P5_21 polarity" "Low,High"
|
|
bitfld.long 0x00 20. " POL5[20] ,Pin P5_20 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL5[19] ,Pin P5_19 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " POL5[18] ,Pin P5_18 polarity" "Low,High"
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
bitfld.long 0x00 17. " POL5[17] ,Pin P5_17 polarity" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL5[16] ,Pin P5_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL5[15] ,Pin P5_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL5[14] ,Pin P5_14 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POL5[13] ,Pin P5_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL5[12] ,Pin P5_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL5[11] ,Pin P5_11 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POL5[10] ,Pin P5_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL5[9] ,Pin P5_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL5[8] ,Pin P5_8 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL5[7] ,Pin P5_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL5[6] ,Pin P5_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL5[5] ,Pin P5_5 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POL5[4] ,Pin P5_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL5[3] ,Pin P5_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL5[2] ,Pin P5_2 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL5[1] ,Pin P5_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL5[0] ,Pin P5_0 polarity" "Low,High"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "PORT_ENA5,GPIO grouped interrupt port 4 enable register"
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
bitfld.long 0x00 26. " ENA5[26] ,Pin P5_26 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ENA5[25] ,Pin P5_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA5[24] ,Pin P5_24 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ENA5[23] ,Pin P5_23 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENA5[22] ,Pin P5_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA5[21] ,Pin P5_21 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENA5[20] ,Pin P5_20 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENA5[19] ,Pin P5_19 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " ENA5[18] ,Pin P5_18 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
bitfld.long 0x00 17. " ENA5[17] ,Pin P5_17 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENA5[16] ,Pin P5_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA5[15] ,Pin P5_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ENA5[14] ,Pin P5_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA5[13] ,Pin P5_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA5[12] ,Pin P5_12 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA5[11] ,Pin P5_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA5[10] ,Pin P5_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA5[9] ,Pin P5_9 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENA5[8] ,Pin P5_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA5[7] ,Pin P5_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA5[6] ,Pin P5_6 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA5[5] ,Pin P5_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA5[4] ,Pin P5_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA5[3] ,Pin P5_3 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA5[2] ,Pin P5_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA5[1] ,Pin P5_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA5[0] ,Pin P5_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
tree "Port 6"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "PORT_POL6,GPIO grouped interrupt port 1 polarity register"
|
|
bitfld.long 0x00 30. " POL6[30] ,Pin P6_30 polarity" "Low,High"
|
|
bitfld.long 0x00 29. " POL6[29] ,Pin P6_29 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " POL6[28] ,Pin P6_28 polarity" "Low,High"
|
|
bitfld.long 0x00 27. " POL6[27] ,Pin P6_27 polarity" "Low,High"
|
|
bitfld.long 0x00 26. " POL6[26] ,Pin P6_26 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " POL6[25] ,Pin P6_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL6[24] ,Pin P6_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL6[23] ,Pin P6_23 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL6[22] ,Pin P6_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL6[21] ,Pin P6_21 polarity" "Low,High"
|
|
bitfld.long 0x00 20. " POL6[20] ,Pin P6_20 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL6[19] ,Pin P6_19 polarity" "Low,High"
|
|
bitfld.long 0x00 18. " POL6[18] ,Pin P6_18 polarity" "Low,High"
|
|
bitfld.long 0x00 17. " POL6[17] ,Pin P6_17 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL6[16] ,Pin P6_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL6[15] ,Pin P6_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL6[14] ,Pin P6_14 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POL6[13] ,Pin P6_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL6[12] ,Pin P6_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL6[11] ,Pin P6_11 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POL6[10] ,Pin P6_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL6[9] ,Pin P6_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL6[8] ,Pin P6_8 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL6[7] ,Pin P6_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL6[6] ,Pin P6_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL6[5] ,Pin P6_5 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POL6[4] ,Pin P6_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL6[3] ,Pin P6_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL6[2] ,Pin P6_2 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL6[1] ,Pin P6_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL6[0] ,Pin P6_0 polarity" "Low,High"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "PORT_ENA6,GPIO grouped interrupt port 6 enable register"
|
|
bitfld.long 0x00 30. " ENA6[30] ,Pin P6_30 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ENA6[29] ,Pin P6_29 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ENA6[28] ,Pin P6_28 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ENA6[27] ,Pin P6_27 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA6[26] ,Pin P6_26 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ENA6[25] ,Pin P6_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA6[24] ,Pin P6_24 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENA6[23] ,Pin P6_23 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ENA6[22] ,Pin P6_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA6[21] ,Pin P6_21 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENA6[20] ,Pin P6_20 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ENA6[19] ,Pin P6_19 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENA6[18] ,Pin P6_18 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENA6[17] ,Pin P6_17 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENA6[16] ,Pin P6_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA6[15] ,Pin P6_15 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA6[14] ,Pin P6_14 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENA6[13] ,Pin P6_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA6[12] ,Pin P6_12 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENA6[11] ,Pin P6_11 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ENA6[10] ,Pin P6_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA6[9] ,Pin P6_9 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA6[8] ,Pin P6_8 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENA6[7] ,Pin P6_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA6[6] ,Pin P6_6 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA6[5] ,Pin P6_5 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA6[4] ,Pin P6_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA6[3] ,Pin P6_3 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA6[2] ,Pin P6_2 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENA6[1] ,Pin P6_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA6[0] ,Pin P6_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Port 7"
|
|
group.long 0x3c++0x3
|
|
line.long 0x00 "PORT_POL7,GPIO grouped interrupt port 1 polarity register"
|
|
bitfld.long 0x00 25. " POL7[25] ,Pin P7_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL7[24] ,Pin P7_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL7[23] ,Pin P7_23 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL7[22] ,Pin P7_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL7[21] ,Pin P7_21 polarity" "Low,High"
|
|
bitfld.long 0x00 20. " POL7[20] ,Pin P7_20 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL7[19] ,Pin P7_19 polarity" "Low,High"
|
|
bitfld.long 0x00 18. " POL7[18] ,Pin P7_18 polarity" "Low,High"
|
|
bitfld.long 0x00 17. " POL7[17] ,Pin P7_17 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL7[16] ,Pin P7_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL7[15] ,Pin P7_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL7[14] ,Pin P7_14 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POL7[13] ,Pin P7_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL7[12] ,Pin P7_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL7[11] ,Pin P7_11 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POL7[10] ,Pin P7_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL7[9] ,Pin P7_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL7[8] ,Pin P7_8 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL7[7] ,Pin P7_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL7[6] ,Pin P7_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL7[5] ,Pin P7_5 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POL7[4] ,Pin P7_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL7[3] ,Pin P7_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL7[2] ,Pin P7_2 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL7[1] ,Pin P7_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL7[0] ,Pin P7_0 polarity" "Low,High"
|
|
group.long 0x5c++0x3
|
|
line.long 0x00 "PORT_ENA7,GPIO grouped interrupt port 7 enable register"
|
|
bitfld.long 0x00 25. " ENA7[25] ,Pin P7_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA7[24] ,Pin P7_24 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ENA7[23] ,Pin P7_23 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENA7[22] ,Pin P7_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA7[21] ,Pin P7_21 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENA7[20] ,Pin P7_20 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENA7[19] ,Pin P7_19 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENA7[18] ,Pin P7_18 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ENA7[17] ,Pin P7_17 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENA7[16] ,Pin P7_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA7[15] ,Pin P7_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ENA7[14] ,Pin P7_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA7[13] ,Pin P7_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA7[12] ,Pin P7_12 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA7[11] ,Pin P7_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA7[10] ,Pin P7_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA7[9] ,Pin P7_9 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENA7[8] ,Pin P7_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA7[7] ,Pin P7_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA7[6] ,Pin P7_6 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA7[5] ,Pin P7_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA7[4] ,Pin P7_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA7[3] ,Pin P7_3 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA7[2] ,Pin P7_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA7[1] ,Pin P7_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA7[0] ,Pin P7_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "GPIO GROUP1 interrupt"
|
|
base ad:0x40089000
|
|
width 0xB
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CTRL,GPIO grouped interrupt control register"
|
|
bitfld.long 0x00 2. " TRIG ,Group interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "Or,And"
|
|
bitfld.long 0x00 0. " INT ,Group interrupt trigger" "Edge,Level"
|
|
tree "Port 0"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "PORT_POL0,GPIO grouped interrupt port 0 polarity register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()=="LPC11A11"&&cpu()=="LPC11A13")
|
|
bitfld.long 0x00 27. " POL0[27] ,Pin P0_27 polarity" "Low,High"
|
|
bitfld.long 0x00 26. " POL0[26] ,Pin P0_26 polarity" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " POL0[31] ,Pin P0_31 polarity" "Low,High"
|
|
bitfld.long 0x00 30. " POL0[30] ,Pin P0_30 polarity" "Low,High"
|
|
bitfld.long 0x00 29. " POL0[29] ,Pin P0_29 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " POL0[28] ,Pin P0_28 polarity" "Low,High"
|
|
bitfld.long 0x00 27. " POL0[27] ,Pin P0_27 polarity" "Low,High"
|
|
bitfld.long 0x00 26. " POL0[26] ,Pin P0_26 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " POL0[25] ,Pin P0_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL0[24] ,Pin P0_24 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 15. " POL0[15] ,Pin P0_15 polarity" "Low,High"
|
|
textline " "
|
|
else
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04")
|
|
bitfld.long 0x00 23. " POL0[23] ,Pin P0_23 polarity" "Low,High"
|
|
bitfld.long 0x00 22. " POL0[22] ,Pin P0_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL0[21] ,Pin P0_21 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " POL0[20] ,Pin P0_20 polarity" "Low,High"
|
|
bitfld.long 0x00 19. " POL0[19] ,Pin P0_19 polarity" "Low,High"
|
|
bitfld.long 0x00 18. " POL0[18] ,Pin P0_18 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " POL0[17] ,Pin P0_17 polarity" "Low,High"
|
|
bitfld.long 0x00 16. " POL0[16] ,Pin P0_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL0[15] ,Pin P0_15 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " POL0[14] ,Pin P0_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL0[13] ,Pin P0_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL0[12] ,Pin P0_12 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " POL0[11] ,Pin P0_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL0[10] ,Pin P0_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL0[9] ,Pin P0_9 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POL0[8] ,Pin P0_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL0[7] ,Pin P0_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL0[6] ,Pin P0_6 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " POL0[5] ,Pin P0_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL0[4] ,Pin P0_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL0[3] ,Pin P0_3 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " POL0[2] ,Pin P0_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL0[1] ,Pin P0_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL0[0] ,Pin P0_0 polarity" "Low,High"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "PORT_ENA0,GPIO grouped interrupt port 0 enable register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()=="LPC11A11"&&cpu()=="LPC11A13")
|
|
bitfld.long 0x00 27. " ENA0[27] ,Pin P0_27 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA0[26] ,Pin P0_26 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " ENA0[31] ,Pin P0_31 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ENA0[30] ,Pin P0_30 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ENA0[29] ,Pin P0_29 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ENA0[28] ,Pin P0_28 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ENA0[27] ,Pin P0_27 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA0[26] ,Pin P0_26 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " ENA0[25] ,Pin P0_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA0[24] ,Pin P0_24 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 15. " ENA0[15] ,Pin P0_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04")
|
|
bitfld.long 0x00 23. " ENA0[23] ,Pin P0_23 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENA0[22] ,Pin P0_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA0[21] ,Pin P0_21 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENA0[20] ,Pin P0_20 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENA0[19] ,Pin P0_19 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENA0[18] ,Pin P0_18 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " ENA0[17] ,Pin P0_17 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENA0[16] ,Pin P0_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA0[15] ,Pin P0_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " ENA0[14] ,Pin P0_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA0[13] ,Pin P0_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA0[12] ,Pin P0_12 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA0[11] ,Pin P0_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA0[10] ,Pin P0_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA0[9] ,Pin P0_9 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENA0[8] ,Pin P0_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA0[7] ,Pin P0_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA0[6] ,Pin P0_6 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA0[5] ,Pin P0_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA0[4] ,Pin P0_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA0[3] ,Pin P0_3 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA0[2] ,Pin P0_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA0[1] ,Pin P0_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA0[0] ,Pin P0_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
sif (cpuis("LPC11U*")||cpuis("LPC11E*")||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
tree "Port 1"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "PORT_POL1,GPIO grouped interrupt port 1 polarity register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
bitfld.long 0x00 15. " POL1[15] ,Pin P1_15 polarity" "Low,High"
|
|
textline " "
|
|
elif cpu()=="LPC11E11"
|
|
bitfld.long 0x00 24. " POL1[24] ,Pin P1_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL1[23] ,Pin P1_23 polarity" "Low,High"
|
|
bitfld.long 0x00 19. " POL1[19] ,Pin P1_19 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL1[15] ,Pin P1_15 polarity" "Low,High"
|
|
else
|
|
bitfld.long 0x00 31. " POL1[31] ,Pin P1_31 polarity" "Low,High"
|
|
sif (!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 30. " POL1[30] ,Pin P1_30 polarity" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 29. " POL1[29] ,Pin P1_29 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " POL1[28] ,Pin P1_28 polarity" "Low,High"
|
|
bitfld.long 0x00 27. " POL1[27] ,Pin P1_27 polarity" "Low,High"
|
|
bitfld.long 0x00 26. " POL1[26] ,Pin P1_26 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " POL1[25] ,Pin P1_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL1[24] ,Pin P1_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL1[23] ,Pin P1_23 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL1[22] ,Pin P1_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL1[21] ,Pin P1_21 polarity" "Low,High"
|
|
bitfld.long 0x00 20. " POL1[20] ,Pin P1_20 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL1[19] ,Pin P1_19 polarity" "Low,High"
|
|
sif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U14*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")&&cpu()!="LPC11E12"&&cpu()!="LPC11E13")
|
|
bitfld.long 0x00 18. " POL1[18] ,Pin P1_18 polarity" "Low,High"
|
|
bitfld.long 0x00 17. " POL1[17] ,Pin P1_17 polarity" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL1[16] ,Pin P1_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL1[15] ,Pin P1_15 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="LPC11E11"
|
|
sif cpuis("LPC11E*")||cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U14*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")
|
|
bitfld.long 0x00 14. " POL1[14] ,Pin P1_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL1[13] ,Pin P1_13 polarity" "Low,High"
|
|
sif cpuis("LPC11U14*")
|
|
bitfld.long 0x00 5. " POL1[5] ,Pin P1_5 polarity" "Low,High"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 14. " POL1[14] ,Pin P1_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL1[13] ,Pin P1_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL1[12] ,Pin P1_12 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " POL1[11] ,Pin P1_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL1[10] ,Pin P1_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL1[9] ,Pin P1_9 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POL1[8] ,Pin P1_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL1[7] ,Pin P1_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL1[6] ,Pin P1_6 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " POL1[5] ,Pin P1_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL1[4] ,Pin P1_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL1[3] ,Pin P1_3 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " POL1[2] ,Pin P1_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL1[1] ,Pin P1_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL1[0] ,Pin P1_0 polarity" "Low,High"
|
|
endif
|
|
endif
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "PORT_ENA1,GPIO grouped interrupt port 1 enable register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
bitfld.long 0x00 15. " ENA1_15 ,Pin P1_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpu()=="LPC11E11"
|
|
bitfld.long 0x00 24. " ENA1_24 ,Pin P1_24 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENA1_23 ,Pin P1_23 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENA1_19 ,Pin P1_19 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENA1_15 ,Pin P1_15 for group interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 31. " ENA1_31 ,Pin P1_31 for group interrupt enable" "Disabled,Enabled"
|
|
sif (!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 30. " ENA1_30 ,Pin P1_30 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 29. " ENA1_29 ,Pin P1_29 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ENA1_28 ,Pin P1_28 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ENA1_27 ,Pin P1_27 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA1_26 ,Pin P1_26 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ENA1_25 ,Pin P1_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA1_24 ,Pin P1_24 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENA1_23 ,Pin P1_23 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ENA1_22 ,Pin P1_22 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA1_21 ,Pin P1_21 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENA1_20 ,Pin P1_20 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ENA1_19 ,Pin P1_19 for group interrupt enable" "Disabled,Enabled"
|
|
sif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U14*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")&&cpu()!="LPC11E12"&&cpu()!="LPC11E13")
|
|
bitfld.long 0x00 18. " ENA1_18 ,Pin P1_18 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENA1_17 ,Pin P1_17 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENA1_16 ,Pin P1_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA1_15 ,Pin P1_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="LPC11E11"
|
|
sif cpuis("LPC11E*")||cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U14*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")
|
|
bitfld.long 0x00 14. " ENA1_14 ,Pin P1_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA1_13 ,Pin P1_13 for group interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("LPC11U14*")
|
|
bitfld.long 0x00 5. " ENA1_5 ,Pin P1_5 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 14. " ENA1_14 ,Pin P1_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA1_13 ,Pin P1_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA1_12 ,Pin P1_12 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA1_11 ,Pin P1_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA1_10 ,Pin P1_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA1_9 ,Pin P1_9 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENA1_8 ,Pin P1_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA1_7 ,Pin P1_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA1_6 ,Pin P1_6 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA1_5 ,Pin P1_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA1_4 ,Pin P1_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA1_3 ,Pin P1_3 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA1_2 ,Pin P1_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA1_1 ,Pin P1_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA1_0 ,Pin P1_0 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
tree "Port 2"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PORT_POL2,GPIO grouped interrupt port 2 polarity register"
|
|
bitfld.long 0x00 15. " POL2[15] ,Pin P2_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL2[14] ,Pin P2_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL2[13] ,Pin P2_13 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " POL2[12] ,Pin P2_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL2[11] ,Pin P2_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL2[10] ,Pin P2_10 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POL2[9] ,Pin P2_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL2[8] ,Pin P2_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL2[7] ,Pin P2_7 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " POL2[6] ,Pin P2_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL2[5] ,Pin P2_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL2[4] ,Pin P2_4 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL2[3] ,Pin P2_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL2[2] ,Pin P2_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL2[1] ,Pin P2_1 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POL2[0] ,Pin P2_0 polarity" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PORT_ENA2,GPIO grouped interrupt port 2 enable register"
|
|
bitfld.long 0x00 15. " ENA2[15] ,Pin P2_15 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA2[14] ,Pin P2_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA2[13] ,Pin P2_13 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENA2[12] ,Pin P2_12 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENA2[11] ,Pin P2_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA2[10] ,Pin P2_10 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENA2[9] ,Pin P2_9 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA2[8] ,Pin P2_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA2[7] ,Pin P2_7 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENA2[6] ,Pin P2_6 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA2[5] ,Pin P2_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA2[4] ,Pin P2_4 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA2[3] ,Pin P2_3 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA2[2] ,Pin P2_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA2[1] ,Pin P2_1 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA2[0] ,Pin P2_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Port 3"
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "PORT_POL3,GPIO grouped interrupt port 1 polarity register"
|
|
bitfld.long 0x00 15. " POL3[15] ,Pin P3_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL3[14] ,Pin P3_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL3[13] ,Pin P3_13 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " POL3[12] ,Pin P3_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL3[11] ,Pin P3_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL3[10] ,Pin P3_10 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POL3[9] ,Pin P3_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL3[8] ,Pin P3_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL3[7] ,Pin P3_7 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " POL3[6] ,Pin P3_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL3[5] ,Pin P3_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL3[4] ,Pin P3_4 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL3[3] ,Pin P3_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL3[2] ,Pin P3_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL3[1] ,Pin P3_1 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POL3[0] ,Pin P3_0 polarity" "Low,High"
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "PORT_ENA3,GPIO grouped interrupt port 3 enable register"
|
|
bitfld.long 0x00 15. " ENA3[15] ,Pin P3_15 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA3[14] ,Pin P3_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA3[13] ,Pin P3_13 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENA3[12] ,Pin P3_12 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENA3[11] ,Pin P3_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA3[10] ,Pin P3_10 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENA3[9] ,Pin P3_9 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA3[8] ,Pin P3_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA3[7] ,Pin P3_7 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENA3[6] ,Pin P3_6 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA3[5] ,Pin P3_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA3[4] ,Pin P3_4 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA3[3] ,Pin P3_3 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA3[2] ,Pin P3_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA3[1] ,Pin P3_1 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA3[0] ,Pin P3_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Port 4"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PORT_POL4,GPIO grouped interrupt port 1 polarity register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " POL4[11] ,Pin P4_11 polarity" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 15. " POL4[15] ,Pin P4_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL4[14] ,Pin P4_14 polarity" "Low,High"
|
|
bitfld.long 0x00 13. " POL4[13] ,Pin P4_13 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " POL4[12] ,Pin P4_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL4[11] ,Pin P4_11 polarity" "Low,High"
|
|
bitfld.long 0x00 10. " POL4[10] ,Pin P4_10 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POL4[9] ,Pin P4_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL4[8] ,Pin P4_8 polarity" "Low,High"
|
|
bitfld.long 0x00 7. " POL4[7] ,Pin P4_7 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " POL4[6] ,Pin P4_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL4[5] ,Pin P4_5 polarity" "Low,High"
|
|
bitfld.long 0x00 4. " POL4[4] ,Pin P4_4 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL4[3] ,Pin P4_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL4[2] ,Pin P4_2 polarity" "Low,High"
|
|
bitfld.long 0x00 1. " POL4[1] ,Pin P4_1 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POL4[0] ,Pin P4_0 polarity" "Low,High"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "PORT_ENA4,GPIO grouped interrupt port 4 enable register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " ENA4[11] ,Pin P0_11 for group interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " ENA4[15] ,Pin P0_15 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA4[14] ,Pin P0_14 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENA4[13] ,Pin P0_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA4[12] ,Pin P0_12 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENA4[11] ,Pin P0_11 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ENA4[10] ,Pin P0_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA4[9] ,Pin P0_9 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA4[8] ,Pin P0_8 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENA4[7] ,Pin P0_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA4[6] ,Pin P0_6 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA4[5] ,Pin P0_5 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA4[4] ,Pin P0_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA4[3] ,Pin P0_3 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA4[2] ,Pin P0_2 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENA4[1] ,Pin P0_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA4[0] ,Pin P0_0 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Port 5"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "PORT_POL5,GPIO grouped interrupt port 1 polarity register"
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
bitfld.long 0x00 26. " POL5[26] ,Pin P5_26 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " POL5[25] ,Pin P5_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL5[24] ,Pin P5_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL5[23] ,Pin P5_23 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL5[22] ,Pin P5_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL5[21] ,Pin P5_21 polarity" "Low,High"
|
|
bitfld.long 0x00 20. " POL5[20] ,Pin P5_20 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL5[19] ,Pin P5_19 polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " POL5[18] ,Pin P5_18 polarity" "Low,High"
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
bitfld.long 0x00 17. " POL5[17] ,Pin P5_17 polarity" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL5[16] ,Pin P5_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL5[15] ,Pin P5_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL5[14] ,Pin P5_14 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POL5[13] ,Pin P5_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL5[12] ,Pin P5_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL5[11] ,Pin P5_11 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POL5[10] ,Pin P5_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL5[9] ,Pin P5_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL5[8] ,Pin P5_8 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL5[7] ,Pin P5_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL5[6] ,Pin P5_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL5[5] ,Pin P5_5 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POL5[4] ,Pin P5_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL5[3] ,Pin P5_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL5[2] ,Pin P5_2 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL5[1] ,Pin P5_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL5[0] ,Pin P5_0 polarity" "Low,High"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "PORT_ENA5,GPIO grouped interrupt port 4 enable register"
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
bitfld.long 0x00 26. " ENA5[26] ,Pin P5_26 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ENA5[25] ,Pin P5_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA5[24] ,Pin P5_24 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ENA5[23] ,Pin P5_23 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENA5[22] ,Pin P5_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA5[21] ,Pin P5_21 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENA5[20] ,Pin P5_20 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENA5[19] ,Pin P5_19 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " ENA5[18] ,Pin P5_18 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
bitfld.long 0x00 17. " ENA5[17] ,Pin P5_17 for group interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENA5[16] ,Pin P5_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA5[15] ,Pin P5_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ENA5[14] ,Pin P5_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA5[13] ,Pin P5_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA5[12] ,Pin P5_12 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA5[11] ,Pin P5_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA5[10] ,Pin P5_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA5[9] ,Pin P5_9 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENA5[8] ,Pin P5_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA5[7] ,Pin P5_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA5[6] ,Pin P5_6 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA5[5] ,Pin P5_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA5[4] ,Pin P5_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA5[3] ,Pin P5_3 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA5[2] ,Pin P5_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA5[1] ,Pin P5_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA5[0] ,Pin P5_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*"))
|
|
tree "Port 6"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "PORT_POL6,GPIO grouped interrupt port 1 polarity register"
|
|
bitfld.long 0x00 30. " POL6[30] ,Pin P6_30 polarity" "Low,High"
|
|
bitfld.long 0x00 29. " POL6[29] ,Pin P6_29 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " POL6[28] ,Pin P6_28 polarity" "Low,High"
|
|
bitfld.long 0x00 27. " POL6[27] ,Pin P6_27 polarity" "Low,High"
|
|
bitfld.long 0x00 26. " POL6[26] ,Pin P6_26 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " POL6[25] ,Pin P6_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL6[24] ,Pin P6_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL6[23] ,Pin P6_23 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL6[22] ,Pin P6_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL6[21] ,Pin P6_21 polarity" "Low,High"
|
|
bitfld.long 0x00 20. " POL6[20] ,Pin P6_20 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL6[19] ,Pin P6_19 polarity" "Low,High"
|
|
bitfld.long 0x00 18. " POL6[18] ,Pin P6_18 polarity" "Low,High"
|
|
bitfld.long 0x00 17. " POL6[17] ,Pin P6_17 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL6[16] ,Pin P6_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL6[15] ,Pin P6_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL6[14] ,Pin P6_14 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POL6[13] ,Pin P6_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL6[12] ,Pin P6_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL6[11] ,Pin P6_11 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POL6[10] ,Pin P6_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL6[9] ,Pin P6_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL6[8] ,Pin P6_8 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL6[7] ,Pin P6_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL6[6] ,Pin P6_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL6[5] ,Pin P6_5 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POL6[4] ,Pin P6_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL6[3] ,Pin P6_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL6[2] ,Pin P6_2 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL6[1] ,Pin P6_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL6[0] ,Pin P6_0 polarity" "Low,High"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "PORT_ENA6,GPIO grouped interrupt port 6 enable register"
|
|
bitfld.long 0x00 30. " ENA6[30] ,Pin P6_30 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ENA6[29] ,Pin P6_29 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ENA6[28] ,Pin P6_28 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ENA6[27] ,Pin P6_27 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA6[26] ,Pin P6_26 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ENA6[25] ,Pin P6_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA6[24] ,Pin P6_24 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENA6[23] ,Pin P6_23 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ENA6[22] ,Pin P6_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA6[21] ,Pin P6_21 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENA6[20] ,Pin P6_20 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ENA6[19] ,Pin P6_19 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENA6[18] ,Pin P6_18 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENA6[17] ,Pin P6_17 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENA6[16] ,Pin P6_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA6[15] ,Pin P6_15 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA6[14] ,Pin P6_14 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENA6[13] ,Pin P6_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA6[12] ,Pin P6_12 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENA6[11] ,Pin P6_11 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ENA6[10] ,Pin P6_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA6[9] ,Pin P6_9 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA6[8] ,Pin P6_8 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENA6[7] ,Pin P6_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA6[6] ,Pin P6_6 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA6[5] ,Pin P6_5 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA6[4] ,Pin P6_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA6[3] ,Pin P6_3 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA6[2] ,Pin P6_2 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENA6[1] ,Pin P6_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA6[0] ,Pin P6_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Port 7"
|
|
group.long 0x3c++0x3
|
|
line.long 0x00 "PORT_POL7,GPIO grouped interrupt port 1 polarity register"
|
|
bitfld.long 0x00 25. " POL7[25] ,Pin P7_25 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " POL7[24] ,Pin P7_24 polarity" "Low,High"
|
|
bitfld.long 0x00 23. " POL7[23] ,Pin P7_23 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL7[22] ,Pin P7_2 polarity" "Low,High"
|
|
bitfld.long 0x00 21. " POL7[21] ,Pin P7_21 polarity" "Low,High"
|
|
bitfld.long 0x00 20. " POL7[20] ,Pin P7_20 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL7[19] ,Pin P7_19 polarity" "Low,High"
|
|
bitfld.long 0x00 18. " POL7[18] ,Pin P7_18 polarity" "Low,High"
|
|
bitfld.long 0x00 17. " POL7[17] ,Pin P7_17 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL7[16] ,Pin P7_16 polarity" "Low,High"
|
|
bitfld.long 0x00 15. " POL7[15] ,Pin P7_15 polarity" "Low,High"
|
|
bitfld.long 0x00 14. " POL7[14] ,Pin P7_14 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POL7[13] ,Pin P7_13 polarity" "Low,High"
|
|
bitfld.long 0x00 12. " POL7[12] ,Pin P7_12 polarity" "Low,High"
|
|
bitfld.long 0x00 11. " POL7[11] ,Pin P7_11 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POL7[10] ,Pin P7_10 polarity" "Low,High"
|
|
bitfld.long 0x00 9. " POL7[9] ,Pin P7_9 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " POL7[8] ,Pin P7_8 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL7[7] ,Pin P7_7 polarity" "Low,High"
|
|
bitfld.long 0x00 6. " POL7[6] ,Pin P7_6 polarity" "Low,High"
|
|
bitfld.long 0x00 5. " POL7[5] ,Pin P7_5 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POL7[4] ,Pin P7_4 polarity" "Low,High"
|
|
bitfld.long 0x00 3. " POL7[3] ,Pin P7_3 polarity" "Low,High"
|
|
bitfld.long 0x00 2. " POL7[2] ,Pin P7_2 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL7[1] ,Pin P7_1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " POL7[0] ,Pin P7_0 polarity" "Low,High"
|
|
group.long 0x5c++0x3
|
|
line.long 0x00 "PORT_ENA7,GPIO grouped interrupt port 7 enable register"
|
|
bitfld.long 0x00 25. " ENA7[25] ,Pin P7_25 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA7[24] ,Pin P7_24 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ENA7[23] ,Pin P7_23 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENA7[22] ,Pin P7_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA7[21] ,Pin P7_21 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENA7[20] ,Pin P7_20 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENA7[19] ,Pin P7_19 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENA7[18] ,Pin P7_18 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ENA7[17] ,Pin P7_17 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENA7[16] ,Pin P7_16 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ENA7[15] ,Pin P7_15 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ENA7[14] ,Pin P7_14 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA7[13] ,Pin P7_13 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA7[12] ,Pin P7_12 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA7[11] ,Pin P7_11 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA7[10] ,Pin P7_10 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA7[9] ,Pin P7_9 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENA7[8] ,Pin P7_8 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA7[7] ,Pin P7_7 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA7[6] ,Pin P7_6 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA7[5] ,Pin P7_5 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA7[4] ,Pin P7_4 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA7[3] ,Pin P7_3 for group interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENA7[2] ,Pin P7_2 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA7[1] ,Pin P7_1 for group interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA7[0] ,Pin P7_0 for group interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
base ad:0x400F4000
|
|
tree "GPIO Ports Registers"
|
|
tree "Port 0"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A13")
|
|
group.byte 0x00++0x27
|
|
line.byte 0x0 "B0 ,GPIO port 0 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P0_0 " "0,1"
|
|
line.byte 0x1 "B1 ,GPIO port 0 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P0_1 " "0,1"
|
|
line.byte 0x2 "B2 ,GPIO port 0 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P0_2 " "0,1"
|
|
line.byte 0x3 "B3 ,GPIO port 0 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P0_3 " "0,1"
|
|
line.byte 0x4 "B4 ,GPIO port 0 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P0_4 " "0,1"
|
|
line.byte 0x5 "B5 ,GPIO port 0 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P0_5 " "0,1"
|
|
line.byte 0x6 "B6 ,GPIO port 0 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P0_6 " "0,1"
|
|
line.byte 0x7 "B7 ,GPIO port 0 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P0_7 " "0,1"
|
|
line.byte 0x8 "B8 ,GPIO port 0 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P0_8 " "0,1"
|
|
line.byte 0x9 "B9 ,GPIO port 0 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P0_9 " "0,1"
|
|
line.byte 0xA "B10,GPIO port 0 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P0_10" "0,1"
|
|
line.byte 0xB "B11,GPIO port 0 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P0_11" "0,1"
|
|
line.byte 0xC "B12,GPIO port 0 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P0_12" "0,1"
|
|
line.byte 0xD "B13,GPIO port 0 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P0_13" "0,1"
|
|
line.byte 0xE "B14,GPIO port 0 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P0_14" "0,1"
|
|
line.byte 0xF "B15,GPIO port 0 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P0_15" "0,1"
|
|
line.byte 0x10 "B16,GPIO port 0 byte pin 16 register"
|
|
bitfld.byte 0x10 0. " PBYTE_16 ,State of the pin P0_16" "0,1"
|
|
line.byte 0x11 "B17,GPIO port 0 byte pin 17 register"
|
|
bitfld.byte 0x11 0. " PBYTE_17 ,State of the pin P0_17" "0,1"
|
|
line.byte 0x12 "B18,GPIO port 0 byte pin 18 register"
|
|
bitfld.byte 0x12 0. " PBYTE_18 ,State of the pin P0_18" "0,1"
|
|
line.byte 0x13 "B19,GPIO port 0 byte pin 19 register"
|
|
bitfld.byte 0x13 0. " PBYTE_19 ,State of the pin P0_19" "0,1"
|
|
line.byte 0x14 "B20,GPIO port 0 byte pin 20 register"
|
|
bitfld.byte 0x14 0. " PBYTE_20 ,State of the pin P0_20" "0,1"
|
|
line.byte 0x15 "B21,GPIO port 0 byte pin 21 register"
|
|
bitfld.byte 0x15 0. " PBYTE_21 ,State of the pin P0_21" "0,1"
|
|
line.byte 0x16 "B22,GPIO port 0 byte pin 22 register"
|
|
bitfld.byte 0x16 0. " PBYTE_22 ,State of the pin P0_22" "0,1"
|
|
line.byte 0x17 "B23,GPIO port 0 byte pin 23 register"
|
|
bitfld.byte 0x17 0. " PBYTE_23 ,State of the pin P0_23" "0,1"
|
|
line.byte 0x18 "B24,GPIO port 0 byte pin 24 register"
|
|
bitfld.byte 0x18 0. " PBYTE_24 ,State of the pin P0_24" "0,1"
|
|
line.byte 0x19 "B25,GPIO port 0 byte pin 25 register"
|
|
bitfld.byte 0x19 0. " PBYTE_25 ,State of the pin P0_25" "0,1"
|
|
line.byte 0x1A "B26,GPIO port 0 byte pin 26 register"
|
|
bitfld.byte 0x1A 0. " PBYTE_26 ,State of the pin P0_26" "0,1"
|
|
line.byte 0x1B "B27,GPIO port 0 byte pin 27 register"
|
|
bitfld.byte 0x1B 0. " PBYTE_27 ,State of the pin P0_27" "0,1"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04")
|
|
group.byte 0x00++0x17
|
|
line.byte 0x0 "B0 ,GPIO port 0 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P0_0 " "0,1"
|
|
line.byte 0x1 "B1 ,GPIO port 0 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P0_1 " "0,1"
|
|
line.byte 0x2 "B2 ,GPIO port 0 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P0_2 " "0,1"
|
|
line.byte 0x3 "B3 ,GPIO port 0 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P0_3 " "0,1"
|
|
line.byte 0x4 "B4 ,GPIO port 0 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P0_4 " "0,1"
|
|
line.byte 0x5 "B5 ,GPIO port 0 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P0_5 " "0,1"
|
|
line.byte 0x6 "B6 ,GPIO port 0 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P0_6 " "0,1"
|
|
line.byte 0x7 "B7 ,GPIO port 0 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P0_7 " "0,1"
|
|
line.byte 0x8 "B8 ,GPIO port 0 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P0_8 " "0,1"
|
|
line.byte 0x9 "B9 ,GPIO port 0 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P0_9 " "0,1"
|
|
line.byte 0xA "B10,GPIO port 0 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P0_10" "0,1"
|
|
line.byte 0xB "B11,GPIO port 0 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P0_11" "0,1"
|
|
line.byte 0xC "B12,GPIO port 0 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P0_12" "0,1"
|
|
line.byte 0xD "B13,GPIO port 0 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P0_13" "0,1"
|
|
line.byte 0xE "B14,GPIO port 0 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P0_14" "0,1"
|
|
line.byte 0xF "B15,GPIO port 0 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P0_15" "0,1"
|
|
line.byte 0x10 "B16,GPIO port 0 byte pin 16 register"
|
|
bitfld.byte 0x10 0. " PBYTE_16 ,State of the pin P0_16" "0,1"
|
|
line.byte 0x11 "B17,GPIO port 0 byte pin 17 register"
|
|
bitfld.byte 0x11 0. " PBYTE_17 ,State of the pin P0_17" "0,1"
|
|
elif (cpu()=="LPC11A12"||cpu()=="LPC11A14")
|
|
group.byte 0x00++0x31
|
|
line.byte 0x0 "B0 ,GPIO port 0 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P0_0 " "0,1"
|
|
line.byte 0x1 "B1 ,GPIO port 0 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P0_1 " "0,1"
|
|
line.byte 0x2 "B2 ,GPIO port 0 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P0_2 " "0,1"
|
|
line.byte 0x3 "B3 ,GPIO port 0 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P0_3 " "0,1"
|
|
line.byte 0x4 "B4 ,GPIO port 0 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P0_4 " "0,1"
|
|
line.byte 0x5 "B5 ,GPIO port 0 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P0_5 " "0,1"
|
|
line.byte 0x6 "B6 ,GPIO port 0 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P0_6 " "0,1"
|
|
line.byte 0x7 "B7 ,GPIO port 0 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P0_7 " "0,1"
|
|
line.byte 0x8 "B8 ,GPIO port 0 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P0_8 " "0,1"
|
|
line.byte 0x9 "B9 ,GPIO port 0 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P0_9 " "0,1"
|
|
line.byte 0xA "B10,GPIO port 0 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P0_10" "0,1"
|
|
line.byte 0xB "B11,GPIO port 0 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P0_11" "0,1"
|
|
line.byte 0xC "B12,GPIO port 0 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P0_12" "0,1"
|
|
line.byte 0xD "B13,GPIO port 0 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P0_13" "0,1"
|
|
line.byte 0xE "B14,GPIO port 0 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P0_14" "0,1"
|
|
line.byte 0xF "B15,GPIO port 0 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P0_15" "0,1"
|
|
line.byte 0x10 "B16,GPIO port 0 byte pin 16 register"
|
|
bitfld.byte 0x10 0. " PBYTE_16 ,State of the pin P0_16" "0,1"
|
|
line.byte 0x11 "B17,GPIO port 0 byte pin 17 register"
|
|
bitfld.byte 0x11 0. " PBYTE_17 ,State of the pin P0_17" "0,1"
|
|
line.byte 0x12 "B18,GPIO port 0 byte pin 18 register"
|
|
bitfld.byte 0x12 0. " PBYTE_18 ,State of the pin P0_18" "0,1"
|
|
line.byte 0x13 "B19,GPIO port 0 byte pin 19 register"
|
|
bitfld.byte 0x13 0. " PBYTE_19 ,State of the pin P0_19" "0,1"
|
|
line.byte 0x14 "B20,GPIO port 0 byte pin 20 register"
|
|
bitfld.byte 0x14 0. " PBYTE_20 ,State of the pin P0_20" "0,1"
|
|
line.byte 0x15 "B21,GPIO port 0 byte pin 21 register"
|
|
bitfld.byte 0x15 0. " PBYTE_21 ,State of the pin P0_21" "0,1"
|
|
line.byte 0x16 "B22,GPIO port 0 byte pin 22 register"
|
|
bitfld.byte 0x16 0. " PBYTE_22 ,State of the pin P0_22" "0,1"
|
|
line.byte 0x17 "B23,GPIO port 0 byte pin 23 register"
|
|
bitfld.byte 0x17 0. " PBYTE_23 ,State of the pin P0_23" "0,1"
|
|
line.byte 0x18 "B24,GPIO port 0 byte pin 24 register"
|
|
bitfld.byte 0x18 0. " PBYTE_24 ,State of the pin P0_24" "0,1"
|
|
line.byte 0x19 "B25,GPIO port 0 byte pin 25 register"
|
|
bitfld.byte 0x19 0. " PBYTE_25 ,State of the pin P0_25" "0,1"
|
|
line.byte 0x1A "B26,GPIO port 0 byte pin 26 register"
|
|
bitfld.byte 0x1A 0. " PBYTE_26 ,State of the pin P0_26" "0,1"
|
|
line.byte 0x1B "B27,GPIO port 0 byte pin 27 register"
|
|
bitfld.byte 0x1B 0. " PBYTE_27 ,State of the pin P0_27" "0,1"
|
|
line.byte 0x1C "B28,GPIO port 0 byte pin 28 register"
|
|
bitfld.byte 0x1C 0. " PBYTE_28 ,State of the pin P0_28" "0,1"
|
|
line.byte 0x1D "B29,GPIO port 0 byte pin 29 register"
|
|
bitfld.byte 0x1D 0. " PBYTE_29 ,State of the pin P0_29" "0,1"
|
|
line.byte 0x1E "B30,GPIO port 0 byte pin 30 register"
|
|
bitfld.byte 0x1E 0. " PBYTE_30 ,State of the pin P0_30" "0,1"
|
|
line.byte 0x1F "B31,GPIO port 0 byte pin 31 register"
|
|
bitfld.byte 0x1F 0. " PBYTE_31 ,State of the pin P0_31" "0,1"
|
|
elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U14*")||cpuis("LPC11U23*")||cpuis("LPC11U24*")||cpuis("LPC11U34*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*"))
|
|
group.byte 0x00++0x23
|
|
line.byte 0x0 "B0 ,GPIO port 0 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P0_0 " "0,1"
|
|
line.byte 0x1 "B1 ,GPIO port 0 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P0_1 " "0,1"
|
|
line.byte 0x2 "B2 ,GPIO port 0 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P0_2 " "0,1"
|
|
line.byte 0x3 "B3 ,GPIO port 0 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P0_3 " "0,1"
|
|
line.byte 0x4 "B4 ,GPIO port 0 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P0_4 " "0,1"
|
|
line.byte 0x5 "B5 ,GPIO port 0 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P0_5 " "0,1"
|
|
line.byte 0x6 "B6 ,GPIO port 0 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P0_6 " "0,1"
|
|
line.byte 0x7 "B7 ,GPIO port 0 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P0_7 " "0,1"
|
|
line.byte 0x8 "B8 ,GPIO port 0 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P0_8 " "0,1"
|
|
line.byte 0x9 "B9 ,GPIO port 0 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P0_9 " "0,1"
|
|
line.byte 0xA "B10,GPIO port 0 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P0_10" "0,1"
|
|
line.byte 0xB "B11,GPIO port 0 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P0_11" "0,1"
|
|
line.byte 0xC "B12,GPIO port 0 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P0_12" "0,1"
|
|
line.byte 0xD "B13,GPIO port 0 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P0_13" "0,1"
|
|
line.byte 0xE "B14,GPIO port 0 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P0_14" "0,1"
|
|
line.byte 0xF "B15,GPIO port 0 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P0_15" "0,1"
|
|
line.byte 0x10 "B16,GPIO port 0 byte pin 16 register"
|
|
bitfld.byte 0x10 0. " PBYTE_16 ,State of the pin P0_16" "0,1"
|
|
line.byte 0x11 "B17,GPIO port 0 byte pin 17 register"
|
|
bitfld.byte 0x11 0. " PBYTE_17 ,State of the pin P0_17" "0,1"
|
|
line.byte 0x12 "B18,GPIO port 0 byte pin 18 register"
|
|
bitfld.byte 0x12 0. " PBYTE_18 ,State of the pin P0_18" "0,1"
|
|
line.byte 0x13 "B19,GPIO port 0 byte pin 19 register"
|
|
bitfld.byte 0x13 0. " PBYTE_19 ,State of the pin P0_19" "0,1"
|
|
line.byte 0x14 "B20,GPIO port 0 byte pin 20 register"
|
|
bitfld.byte 0x14 0. " PBYTE_20 ,State of the pin P0_20" "0,1"
|
|
line.byte 0x15 "B21,GPIO port 0 byte pin 21 register"
|
|
bitfld.byte 0x15 0. " PBYTE_21 ,State of the pin P0_21" "0,1"
|
|
line.byte 0x16 "B22,GPIO port 0 byte pin 22 register"
|
|
bitfld.byte 0x16 0. " PBYTE_22 ,State of the pin P0_22" "0,1"
|
|
line.byte 0x17 "B23,GPIO port 0 byte pin 23 register"
|
|
bitfld.byte 0x17 0. " PBYTE_23 ,State of the pin P0_23" "0,1"
|
|
elif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
group.byte 0x00++0x15
|
|
line.byte 0x0 "B0 ,GPIO port 0 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P0_0 " "0,1"
|
|
line.byte 0x1 "B1 ,GPIO port 0 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P0_1 " "0,1"
|
|
line.byte 0x2 "B2 ,GPIO port 0 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P0_2 " "0,1"
|
|
line.byte 0x3 "B3 ,GPIO port 0 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P0_3 " "0,1"
|
|
line.byte 0x4 "B4 ,GPIO port 0 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P0_4 " "0,1"
|
|
line.byte 0x5 "B5 ,GPIO port 0 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P0_5 " "0,1"
|
|
line.byte 0x6 "B6 ,GPIO port 0 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P0_6 " "0,1"
|
|
line.byte 0x7 "B7 ,GPIO port 0 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P0_7 " "0,1"
|
|
line.byte 0x8 "B8 ,GPIO port 0 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P0_8 " "0,1"
|
|
line.byte 0x9 "B9 ,GPIO port 0 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P0_9 " "0,1"
|
|
line.byte 0xA "B10,GPIO port 0 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P0_10" "0,1"
|
|
line.byte 0xB "B11,GPIO port 0 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P0_11" "0,1"
|
|
line.byte 0xC "B12,GPIO port 0 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P0_12" "0,1"
|
|
line.byte 0xD "B13,GPIO port 0 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P0_13" "0,1"
|
|
line.byte 0xE "B14,GPIO port 0 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P0_14" "0,1"
|
|
line.byte 0xF "B15,GPIO port 0 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P0_15" "0,1"
|
|
endif
|
|
sif (cpuis("LPC11E*")||cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U14*")||cpuis("LPC11U23*")||cpuis("LPC11U24*")||cpuis("LPC11U34*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*"))
|
|
group.long 0x1000++0x63
|
|
line.long 0x0 "W0 ,GPIO port 0 word pin 0 register"
|
|
line.long 0x4 "W1 ,GPIO port 0 word pin 1 register"
|
|
line.long 0x8 "W2 ,GPIO port 0 word pin 2 register"
|
|
line.long 0xC "W3 ,GPIO port 0 word pin 3 register"
|
|
line.long 0x10 "W4 ,GPIO port 0 word pin 4 register"
|
|
line.long 0x14 "W5 ,GPIO port 0 word pin 5 register"
|
|
line.long 0x18 "W6 ,GPIO port 0 word pin 6 register"
|
|
line.long 0x1C "W7 ,GPIO port 0 word pin 7 register"
|
|
line.long 0x20 "W8 ,GPIO port 0 word pin 8 register"
|
|
line.long 0x24 "W9 ,GPIO port 0 word pin 9 register"
|
|
line.long 0x28 "W10,GPIO port 0 word pin 10 register"
|
|
line.long 0x2C "W11,GPIO port 0 word pin 11 register"
|
|
line.long 0x30 "W12,GPIO port 0 word pin 12 register"
|
|
line.long 0x34 "W13,GPIO port 0 word pin 13 register"
|
|
line.long 0x38 "W14,GPIO port 0 word pin 14 register"
|
|
line.long 0x3C "W15,GPIO port 0 word pin 15 register"
|
|
line.long 0x40 "W16,GPIO port 0 word pin 16 register"
|
|
line.long 0x44 "W17,GPIO port 0 word pin 17 register"
|
|
line.long 0x48 "W18,GPIO port 0 word pin 18 register"
|
|
line.long 0x4C "W19,GPIO port 0 word pin 19 register"
|
|
line.long 0x50 "W20,GPIO port 0 word pin 20 register"
|
|
line.long 0x54 "W21,GPIO port 0 word pin 21 register"
|
|
line.long 0x58 "W22,GPIO port 0 word pin 22 register"
|
|
line.long 0x5C "W23,GPIO port 0 word pin 23 register"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04")
|
|
group.long 0x1000++0x4B
|
|
line.long 0x0 "W0 ,GPIO port 0 word pin 0 register"
|
|
line.long 0x4 "W1 ,GPIO port 0 word pin 1 register"
|
|
line.long 0x8 "W2 ,GPIO port 0 word pin 2 register"
|
|
line.long 0xC "W3 ,GPIO port 0 word pin 3 register"
|
|
line.long 0x10 "W4 ,GPIO port 0 word pin 4 register"
|
|
line.long 0x14 "W5 ,GPIO port 0 word pin 5 register"
|
|
line.long 0x18 "W6 ,GPIO port 0 word pin 6 register"
|
|
line.long 0x1C "W7 ,GPIO port 0 word pin 7 register"
|
|
line.long 0x20 "W8 ,GPIO port 0 word pin 8 register"
|
|
line.long 0x24 "W9 ,GPIO port 0 word pin 9 register"
|
|
line.long 0x28 "W10,GPIO port 0 word pin 10 register"
|
|
line.long 0x2C "W11,GPIO port 0 word pin 11 register"
|
|
line.long 0x30 "W12,GPIO port 0 word pin 12 register"
|
|
line.long 0x34 "W13,GPIO port 0 word pin 13 register"
|
|
line.long 0x38 "W14,GPIO port 0 word pin 14 register"
|
|
line.long 0x3C "W15,GPIO port 0 word pin 15 register"
|
|
line.long 0x40 "W16,GPIO port 0 word pin 16 register"
|
|
line.long 0x44 "W17,GPIO port 0 word pin 17 register"
|
|
elif (cpu()=="LPC11A13"||cpu()=="LPC11A11")
|
|
group.long 0x1000++0x73
|
|
line.long 0x0 "W0 ,GPIO port 0 word pin 0 register"
|
|
line.long 0x4 "W1 ,GPIO port 0 word pin 1 register"
|
|
line.long 0x8 "W2 ,GPIO port 0 word pin 2 register"
|
|
line.long 0xC "W3 ,GPIO port 0 word pin 3 register"
|
|
line.long 0x10 "W4 ,GPIO port 0 word pin 4 register"
|
|
line.long 0x14 "W5 ,GPIO port 0 word pin 5 register"
|
|
line.long 0x18 "W6 ,GPIO port 0 word pin 6 register"
|
|
line.long 0x1C "W7 ,GPIO port 0 word pin 7 register"
|
|
line.long 0x20 "W8 ,GPIO port 0 word pin 8 register"
|
|
line.long 0x24 "W9 ,GPIO port 0 word pin 9 register"
|
|
line.long 0x28 "W10,GPIO port 0 word pin 10 register"
|
|
line.long 0x2C "W11,GPIO port 0 word pin 11 register"
|
|
line.long 0x30 "W12,GPIO port 0 word pin 12 register"
|
|
line.long 0x34 "W13,GPIO port 0 word pin 13 register"
|
|
line.long 0x38 "W14,GPIO port 0 word pin 14 register"
|
|
line.long 0x3C "W15,GPIO port 0 word pin 15 register"
|
|
line.long 0x40 "W16,GPIO port 0 word pin 16 register"
|
|
line.long 0x44 "W17,GPIO port 0 word pin 17 register"
|
|
line.long 0x48 "W18,GPIO port 0 word pin 18 register"
|
|
line.long 0x4C "W19,GPIO port 0 word pin 19 register"
|
|
line.long 0x50 "W20,GPIO port 0 word pin 20 register"
|
|
line.long 0x54 "W21,GPIO port 0 word pin 21 register"
|
|
line.long 0x58 "W22,GPIO port 0 word pin 22 register"
|
|
line.long 0x5C "W23,GPIO port 0 word pin 23 register"
|
|
line.long 0x60 "W24,GPIO port 0 word pin 24 register"
|
|
line.long 0x64 "W25,GPIO port 0 word pin 25 register"
|
|
line.long 0x68 "W26,GPIO port 0 word pin 26 register"
|
|
line.long 0x6C "W27,GPIO port 0 word pin 27 register"
|
|
elif (cpu()=="LPC11A12"||cpu()=="LPC11A14")
|
|
group.long 0x1000++0x73
|
|
line.long 0x0 "W0 ,GPIO port 0 word pin 0 register"
|
|
line.long 0x4 "W1 ,GPIO port 0 word pin 1 register"
|
|
line.long 0x8 "W2 ,GPIO port 0 word pin 2 register"
|
|
line.long 0xC "W3 ,GPIO port 0 word pin 3 register"
|
|
line.long 0x10 "W4 ,GPIO port 0 word pin 4 register"
|
|
line.long 0x14 "W5 ,GPIO port 0 word pin 5 register"
|
|
line.long 0x18 "W6 ,GPIO port 0 word pin 6 register"
|
|
line.long 0x1C "W7 ,GPIO port 0 word pin 7 register"
|
|
line.long 0x20 "W8 ,GPIO port 0 word pin 8 register"
|
|
line.long 0x24 "W9 ,GPIO port 0 word pin 9 register"
|
|
line.long 0x28 "W10,GPIO port 0 word pin 10 register"
|
|
line.long 0x2C "W11,GPIO port 0 word pin 11 register"
|
|
line.long 0x30 "W12,GPIO port 0 word pin 12 register"
|
|
line.long 0x34 "W13,GPIO port 0 word pin 13 register"
|
|
line.long 0x38 "W14,GPIO port 0 word pin 14 register"
|
|
line.long 0x3C "W15,GPIO port 0 word pin 15 register"
|
|
line.long 0x40 "W16,GPIO port 0 word pin 16 register"
|
|
line.long 0x44 "W17,GPIO port 0 word pin 17 register"
|
|
line.long 0x48 "W18,GPIO port 0 word pin 18 register"
|
|
line.long 0x4C "W19,GPIO port 0 word pin 19 register"
|
|
line.long 0x50 "W20,GPIO port 0 word pin 20 register"
|
|
line.long 0x54 "W21,GPIO port 0 word pin 21 register"
|
|
line.long 0x58 "W22,GPIO port 0 word pin 22 register"
|
|
line.long 0x5C "W23,GPIO port 0 word pin 23 register"
|
|
line.long 0x60 "W24,GPIO port 0 word pin 24 register"
|
|
line.long 0x64 "W25,GPIO port 0 word pin 25 register"
|
|
line.long 0x68 "W26,GPIO port 0 word pin 26 register"
|
|
line.long 0x6C "W27,GPIO port 0 word pin 27 register"
|
|
elif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
group.long 0x1000++0x43
|
|
line.long 0x0 "W0 ,GPIO port 0 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P0_0 "
|
|
line.long 0x4 "W1 ,GPIO port 0 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P0_1 "
|
|
line.long 0x8 "W2 ,GPIO port 0 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P0_2 "
|
|
line.long 0xC "W3 ,GPIO port 0 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P0_3 "
|
|
line.long 0x10 "W4 ,GPIO port 0 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P0_4 "
|
|
line.long 0x14 "W5 ,GPIO port 0 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P0_5 "
|
|
line.long 0x18 "W6 ,GPIO port 0 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P0_6 "
|
|
line.long 0x1C "W7 ,GPIO port 0 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P0_7 "
|
|
line.long 0x20 "W8 ,GPIO port 0 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P0_8 "
|
|
line.long 0x24 "W9 ,GPIO port 0 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P0_9 "
|
|
line.long 0x28 "W10,GPIO port 0 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P0_10"
|
|
line.long 0x2C "W11,GPIO port 0 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P0_11"
|
|
line.long 0x30 "W12,GPIO port 0 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P0_12"
|
|
line.long 0x34 "W13,GPIO port 0 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P0_13"
|
|
line.long 0x38 "W14,GPIO port 0 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P0_14"
|
|
line.long 0x3C "W15,GPIO port 0 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P0_15"
|
|
else
|
|
group.long 0x1000++0x63
|
|
line.long 0x0 "W0 ,GPIO port 0 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P0_0 "
|
|
line.long 0x4 "W1 ,GPIO port 0 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P0_1 "
|
|
line.long 0x8 "W2 ,GPIO port 0 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P0_2 "
|
|
line.long 0xC "W3 ,GPIO port 0 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P0_3 "
|
|
line.long 0x10 "W4 ,GPIO port 0 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P0_4 "
|
|
line.long 0x14 "W5 ,GPIO port 0 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P0_5 "
|
|
line.long 0x18 "W6 ,GPIO port 0 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P0_6 "
|
|
line.long 0x1C "W7 ,GPIO port 0 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P0_7 "
|
|
line.long 0x20 "W8 ,GPIO port 0 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P0_8 "
|
|
line.long 0x24 "W9 ,GPIO port 0 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P0_9 "
|
|
line.long 0x28 "W10,GPIO port 0 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P0_10"
|
|
line.long 0x2C "W11,GPIO port 0 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P0_11"
|
|
line.long 0x30 "W12,GPIO port 0 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P0_12"
|
|
line.long 0x34 "W13,GPIO port 0 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P0_13"
|
|
line.long 0x38 "W14,GPIO port 0 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P0_14"
|
|
line.long 0x3C "W15,GPIO port 0 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P0_15"
|
|
line.long 0x40 "W16,GPIO port 0 word pin 16 register"
|
|
hexmask.long 0x40 0.--31. 1. " PWORD_16 ,State of the pin P0_16"
|
|
line.long 0x44 "W17,GPIO port 0 word pin 17 register"
|
|
hexmask.long 0x44 0.--31. 1. " PWORD_17 ,State of the pin P0_17"
|
|
line.long 0x48 "W18,GPIO port 0 word pin 18 register"
|
|
hexmask.long 0x48 0.--31. 1. " PWORD_18 ,State of the pin P0_18"
|
|
line.long 0x4C "W19,GPIO port 0 word pin 19 register"
|
|
hexmask.long 0x4C 0.--31. 1. " PWORD_19 ,State of the pin P0_19"
|
|
line.long 0x50 "W20,GPIO port 0 word pin 20 register"
|
|
hexmask.long 0x50 0.--31. 1. " PWORD_20 ,State of the pin P0_20"
|
|
line.long 0x54 "W21,GPIO port 0 word pin 21 register"
|
|
hexmask.long 0x54 0.--31. 1. " PWORD_21 ,State of the pin P0_21"
|
|
line.long 0x58 "W22,GPIO port 0 word pin 22 register"
|
|
hexmask.long 0x58 0.--31. 1. " PWORD_22 ,State of the pin P0_22"
|
|
line.long 0x5C "W23,GPIO port 0 word pin 23 register"
|
|
hexmask.long 0x5C 0.--31. 1. " PWORD_23 ,State of the pin P0_23"
|
|
endif
|
|
group.long 0x2000++0x3
|
|
line.long 0x00 "DIR0,GPIO direction port 0 register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()!="LPC11A13"&&cpu()!="LPC11A13")
|
|
bitfld.long 0x00 31. " DIRP0[31] ,Pin direction for pin P0_31" "Input,Output"
|
|
bitfld.long 0x00 30. " DIRP0[30] ,Pin direction for pin P0_30" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DIRP0[29] ,Pin direction for pin P0_29" "Input,Output"
|
|
bitfld.long 0x00 28. " DIRP0[28] ,Pin direction for pin P0_28" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " DIRP0[27] ,Pin direction for pin P0_27" "Input,Output"
|
|
bitfld.long 0x00 26. " DIRP0[26] ,Pin direction for pin P0_26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DIRP0[25] ,Pin direction for pin P0_25" "Input,Output"
|
|
bitfld.long 0x00 24. " DIRP0[24] ,Pin direction for pin P0_24" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 23. " DIRP0[23] ,Pin direction for pin P0_23" "Input,Output"
|
|
bitfld.long 0x00 22. " DIRP0[22] ,Pin direction for pin P0_22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DIRP0[21] ,Pin direction for pin P0_21" "Input,Output"
|
|
bitfld.long 0x00 20. " DIRP0[20] ,Pin direction for pin P0_20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIRP0[19] ,Pin direction for pin P0_19" "Input,Output"
|
|
bitfld.long 0x00 18. " DIRP0[18] ,Pin direction for pin P0_18" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 17. " DIRP0[17] ,Pin direction for pin P0_17" "Input,Output"
|
|
bitfld.long 0x00 16. " DIRP0[16] ,Pin direction for pin P0_16" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " DIRP0[15] ,Pin direction for pin P0_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP0[14] ,Pin direction for pin P0_14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRP0[13] ,Pin direction for pin P0_13" "Input,Output"
|
|
bitfld.long 0x00 12. " DIRP0[12] ,Pin direction for pin P0_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP0[11] ,Pin direction for pin P0_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP0[10] ,Pin direction for pin P0_10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIRP0[9] ,Pin direction for pin P0_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP0[8] ,Pin direction for pin P0_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP0[7] ,Pin direction for pin P0_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP0[6] ,Pin direction for pin P0_6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DIRP0[5] ,Pin direction for pin P0_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP0[4] ,Pin direction for pin P0_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP0[3] ,Pin direction for pin P0_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP0[2] ,Pin direction for pin P0_2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIRP0[1] ,Pin direction for pin P0_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP0[0] ,Pin direction for pin P0_0" "Input,Output"
|
|
group.long 0x2080++0x3
|
|
line.long 0x00 "MASK0,GPIO mask port 0 register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()!="LPC11A13"&&cpu()!="LPC11A11")
|
|
bitfld.long 0x00 31. " MASKP0[31] ,Mask for pin P0_31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " MASKP0[30] ,Mask for pin P0_30" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MASKP0[29] ,Mask for pin P0_29" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " MASKP0[28] ,Mask for pin P0_28" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " MASKP0[27] ,Mask for pin P0_27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " MASKP0[26] ,Mask for pin P0_26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MASKP0[25] ,Mask for pin P0_25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " MASKP0[24] ,Mask for pin P0_24" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 23. " MASKP0[23] ,Mask for pin P0_23" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " MASKP0[22] ,Mask for pin P0_22" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MASKP0[21] ,Mask for pin P0_21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " MASKP0[20] ,Mask for pin P0_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MASKP0[19] ,Mask for pin P0_19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " MASKP0[18] ,Mask for pin P0_18" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 17. " MASKP0[17] ,Mask for pin P0_17" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " MASKP0[16] ,Mask for pin P0_16" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MASKP0[15] ,Mask for pin P0_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP0[14] ,Mask for pin P0_14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASKP0[13] ,Mask for pin P0_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASKP0[12] ,Mask for pin P0_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP0[11] ,Mask for pin P0_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP0[10] ,Mask for pin P0_10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MASKP0[9] ,Mask for pin P0_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP0[8] ,Mask for pin P0_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP0[7] ,Mask for pin P0_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP0[6] ,Mask for pin P0_6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MASKP0[5] ,Mask for pin P0_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP0[4] ,Mask for pin P0_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP0[3] ,Mask for pin P0_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP0[2] ,Mask for pin P0_2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASKP0[1] ,Mask for pin P0_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP0[0] ,Mask for pin P0_0" "Not masked,Masked"
|
|
group.long 0x2100++0x3
|
|
line.long 0x00 "PIN0,GPIO port 0 pin register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()!="LPC11A13"&&cpu()!="LPC11A11")
|
|
bitfld.long 0x00 31. " PORT0[31] ,P0_31 pin state" "Low,High"
|
|
bitfld.long 0x00 30. " PORT0[30] ,P0_30 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PORT0[29] ,P0_29 pin state" "Low,High"
|
|
bitfld.long 0x00 28. " PORT0[28] ,P0_28 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " PORT0[27] ,P0_27 pin state" "Low,High"
|
|
bitfld.long 0x00 26. " PORT0[26] ,P0_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PORT0[25] ,P0_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " PORT0[24] ,P0_24 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 23. " PORT0[23] ,P0_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " PORT0[22] ,P0_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PORT0[21] ,P0_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " PORT0[20] ,P0_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PORT0[19] ,P0_19 pin state" "Low,High"
|
|
bitfld.long 0x00 18. " PORT0[18] ,P0_18 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 17. " PORT0[17] ,P0_17 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " PORT0[16] ,P0_16 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PORT0[15] ,P0_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " PORT0[14] ,P0_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PORT0[13] ,P0_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " PORT0[12] ,P0_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT0[11] ,P0_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " PORT0[10] ,P0_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PORT0[9] ,P0_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " PORT0[8] ,P0_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT0[7] ,P0_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " PORT0[6] ,P0_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PORT0[5] ,P0_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " PORT0[4] ,P0_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT0[3] ,P0_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " PORT0[2] ,P0_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PORT0[1] ,P0_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " PORT0[0] ,P0_0 pin state" "Low,High"
|
|
group.long 0x2180++0x3
|
|
line.long 0x00 "MPIN0,GPIO masked port 0 pin register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()!="LPC11A13"&&cpu()!="LPC11A11")
|
|
bitfld.long 0x00 31. " MPORTP0[31] ,Masked P0_31 pin state" "Low,High"
|
|
bitfld.long 0x00 30. " MPORTP0[30] ,Masked P0_30 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MPORTP0[29] ,Masked P0_29 pin state" "Low,High"
|
|
bitfld.long 0x00 28. " MPORTP0[28] ,Masked P0_28 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " MPORTP0[27] ,Masked P0_27 pin state" "Low,High"
|
|
bitfld.long 0x00 26. " MPORTP0[26] ,Masked P0_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MPORTP0[25] ,Masked P0_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " MPORTP0[24] ,Masked P0_24 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 23. " MPORTP0[23] ,Masked P0_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " MPORTP0[22] ,Masked P0_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MPORTP0[21] ,Masked P0_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " MPORTP0[20] ,Masked P0_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MPORTP0[19] ,Masked P0_19 pin state" "Low,High"
|
|
bitfld.long 0x00 18. " MPORTP0[18] ,Masked P0_18 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 17. " MPORTP0[17] ,Masked P0_17 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " MPORTP0[16] ,Masked P0_16 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MPORTP0[15] ,Masked P0_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " MPORTP0[14] ,Masked P0_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MPORTP0[13] ,Masked P0_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " MPORTP0[12] ,Masked P0_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP0[11] ,Masked P0_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " MPORTP0[10] ,Masked P0_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPORTP0[9] ,Masked P0_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " MPORTP0[8] ,Masked P0_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP0[7] ,Masked P0_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " MPORTP0[6] ,Masked P0_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPORTP0[5] ,Masked P0_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " MPORTP0[4] ,Masked P0_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP0[3] ,Masked P0_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " MPORTP0[2] ,Masked P0_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MPORTP0[1] ,Masked P0_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " MPORTP0[0] ,Masked P0_0 pin state" "Low,High"
|
|
group.long 0x2200++0x3
|
|
line.long 0x00 "SET0,GPIO set port 0 register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()!="LPC11A13"&&cpu()!="LPC11A11")
|
|
bitfld.long 0x00 31. " SETP0[31] ,State/Set P0_31 pin state" "Low,High"
|
|
bitfld.long 0x00 30. " SETP0[30] ,State/Set P0_30 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SETP0[29] ,State/Set P0_29 pin state" "Low,High"
|
|
bitfld.long 0x00 28. " SETP0[28] ,State/Set P0_28 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " SETP0[27] ,State/Set P0_27 pin state" "Low,High"
|
|
bitfld.long 0x00 26. " SETP0[26] ,State/Set P0_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SETP0[25] ,State/Set P0_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " SETP0[24] ,State/Set P0_24 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 23. " SETP0[23] ,State/Set P0_23" "Low,High"
|
|
bitfld.long 0x00 22. " SETP0[22] ,State/Set P0_22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SETP0[21] ,State/Set P0_21" "Low,High"
|
|
bitfld.long 0x00 20. " SETP0[20] ,State/Set P0_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SETP0[19] ,State/Set P0_19" "Low,High"
|
|
bitfld.long 0x00 18. " SETP0[18] ,State/Set P0_18" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 17. " SETP0[17] ,State/Set P0_17" "Low,High"
|
|
bitfld.long 0x00 16. " SETP0[16] ,State/Set P0_16" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " SETP0[15] ,State/Set P0_15" "Low,High"
|
|
bitfld.long 0x00 14. " SETP0[14] ,State/Set P0_14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SETP0[13] ,State/Set P0_13" "Low,High"
|
|
bitfld.long 0x00 12. " SETP0[12] ,State/Set P0_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETP0[11] ,State/Set P0_11" "Low,High"
|
|
bitfld.long 0x00 10. " SETP0[10] ,State/Set P0_10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SETP0[9] ,State/Set P0_9" "Low,High"
|
|
bitfld.long 0x00 8. " SETP0[8] ,State/Set P0_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SETP0[7] ,State/Set P0_7" "Low,High"
|
|
bitfld.long 0x00 6. " SETP0[6] ,State/Set P0_6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETP0[5] ,State/Set P0_5" "Low,High"
|
|
bitfld.long 0x00 4. " SETP0[4] ,State/Set P0_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SETP0[3] ,State/Set P0_3" "Low,High"
|
|
bitfld.long 0x00 2. " SETP0[2] ,State/Set P0_2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SETP0[1] ,State/Set P0_1" "Low,High"
|
|
bitfld.long 0x00 0. " SETP0[0] ,State/Set P0_0" "Low,High"
|
|
wgroup.long 0x2280++0x3
|
|
line.long 0x00 "CLR0,GPIO clear port 0 register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()!="LPC11A13"&&cpu()!="LPC11A11")
|
|
bitfld.long 0x00 31. " CLRP0[31] ,Clear P0_31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " CLRP0[30] ,Clear P0_30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CLRP0[29] ,Clear P0_29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " CLRP0[28] ,Clear P0_28" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " CLRP0[27] ,Clear P0_27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CLRP0[26] ,Clear P0_26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CLRP0[25] ,Clear P0_25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CLRP0[24] ,Clear P0_24" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 23. " CLRP0[23] ,Clear P0_23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CLRP0[22] ,Clear P0_22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CLRP0[21] ,Clear P0_21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CLRP0[20] ,Clear P0_20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLRP0[19] ,Clear P0_19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CLRP0[18] ,Clear P0_18" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 17. " CLRP0[17] ,Clear P0_17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CLRP0[16] ,Clear P0_16" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " CLRP0[15] ,Clear P0_15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLRP0[14] ,Clear P0_14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLRP0[13] ,Clear P0_13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLRP0[12] ,Clear P0_12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLRP0[11] ,Clear P0_11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLRP0[10] ,Clear P0_10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLRP0[9] ,Clear P0_9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLRP0[8] ,Clear P0_8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLRP0[7] ,Clear P0_7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLRP0[6] ,Clear P0_6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLRP0[5] ,Clear P0_5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLRP0[4] ,Clear P0_4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLRP0[3] ,Clear P0_3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLRP0[2] ,Clear P0_2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLRP0[1] ,Clear P0_1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLRP0[0] ,Clear P0_0" "No effect,Clear"
|
|
wgroup.long 0x2300++0x3
|
|
line.long 0x00 "NOT0,GPIO toggle port 0 register"
|
|
sif (cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
sif (cpu()!="LPC11A13"&&cpu()!="LPC11A11")
|
|
bitfld.long 0x00 31. " NOTP0[31] ,Toggle P0_31" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " NOTP0[30] ,Toggle P0_30" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 29. " NOTP0[29] ,Toggle P0_29" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " NOTP0[28] ,Toggle P0_28" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " NOTP0[27] ,Toggle P0_27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " NOTP0[26] ,Toggle P0_26" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOTP0[25] ,Toggle P0_25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " NOTP0[24] ,Toggle P0_24" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 23. " NOTP0[23] ,Toggle P0_23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " NOTP0[22] ,Toggle P0_22" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTP0[21] ,Toggle P0_21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " NOTP0[20] ,Toggle P0_20" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTP0[19] ,Toggle P0_19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " NOTP0[18] ,Toggle P0_18" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 17. " NOTP0[17] ,Toggle P0_17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " NOTP0[16] ,Toggle P0_16" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " NOTP0[15] ,Toggle P0_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP0[14] ,Toggle P0_14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTP0[13] ,Toggle P0_13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " NOTP0[12] ,Toggle P0_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP0[11] ,Toggle P0_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP0[10] ,Toggle P0_10" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTP0[9] ,Toggle P0_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP0[8] ,Toggle P0_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP0[7] ,Toggle P0_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP0[6] ,Toggle P0_6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTP0[5] ,Toggle P0_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP0[4] ,Toggle P0_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP0[3] ,Toggle P0_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP0[2] ,Toggle P0_2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTP0[1] ,Toggle P0_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP0[0] ,Toggle P0_0" "No effect,Toggle"
|
|
tree.end
|
|
sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A13")
|
|
tree "Port 1"
|
|
sif (cpu()=="LPC11A12"||cpu()=="LPC11A14")
|
|
group.byte 0x20++0x10
|
|
line.byte 0x0 "B32,GPIO port 1 byte pin 32 register"
|
|
bitfld.byte 0x0 0. " PBYTE_32 ,State of the pin P1_32" "0,1"
|
|
line.byte 0x1 "B33,GPIO port 1 byte pin 33 register"
|
|
bitfld.byte 0x1 0. " PBYTE_33 ,State of the pin P1_33" "0,1"
|
|
line.byte 0x2 "B34,GPIO port 1 byte pin 34 register"
|
|
bitfld.byte 0x2 0. " PBYTE_34 ,State of the pin P1_34" "0,1"
|
|
line.byte 0x3 "B35,GPIO port 1 byte pin 35 register"
|
|
bitfld.byte 0x3 0. " PBYTE_35 ,State of the pin P1_35" "0,1"
|
|
line.byte 0x4 "B36,GPIO port 1 byte pin 36 register"
|
|
bitfld.byte 0x4 0. " PBYTE_36 ,State of the pin P1_36" "0,1"
|
|
line.byte 0x5 "B37,GPIO port 1 byte pin 37 register"
|
|
bitfld.byte 0x5 0. " PBYTE_37 ,State of the pin P1_37" "0,1"
|
|
line.byte 0x6 "B38,GPIO port 1 byte pin 38 register"
|
|
bitfld.byte 0x6 0. " PBYTE_38 ,State of the pin P1_38" "0,1"
|
|
line.byte 0x7 "B39,GPIO port 1 byte pin 39 register"
|
|
bitfld.byte 0x7 0. " PBYTE_39 ,State of the pin P1_39" "0,1"
|
|
line.byte 0x8 "B40,GPIO port 1 byte pin 40 register"
|
|
bitfld.byte 0x8 0. " PBYTE_40 ,State of the pin P1_40" "0,1"
|
|
line.byte 0x9 "B41,GPIO port 1 byte pin 41 register"
|
|
bitfld.byte 0x9 0. " PBYTE_41 ,State of the pin P1_41" "0,1"
|
|
elif cpuis("LPC11E*")
|
|
sif (cpu()=="LPC11E11")
|
|
group.byte 0x35++0x1
|
|
line.byte 0x00 "B47,GPIO port 1 byte pin 15 register"
|
|
bitfld.byte 0x00 0. " PBYTE_47 ,State of the pin P1_15" "0,1"
|
|
group.byte 0x39++0x3
|
|
line.byte 0x00 "B51,GPIO port 1 byte pin 19 register"
|
|
bitfld.byte 0x00 0. " PBYTE_51 ,State of the pin P1_19" "0,1"
|
|
group.byte 0x43++0x1
|
|
line.byte 0x00 "B55,GPIO port 1 byte pin 23 register"
|
|
bitfld.byte 0x00 0. " PBYTE_55 ,State of the pin P1_23" "0,1"
|
|
group.byte 0x44++0x1
|
|
line.byte 0x00 "B56,GPIO port 1 byte pin 24 register"
|
|
bitfld.byte 0x00 0. " PBYTE_56 ,State of the pin P1_24" "0,1"
|
|
else
|
|
sif cpu()!="LPC11E12"&&cpu()!="LPC11E13"
|
|
group.byte 0x20++0x0B
|
|
line.byte 0x0 "B32,GPIO port 1 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P1_0 " "0,1"
|
|
line.byte 0x1 "B33,GPIO port 1 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P1_1 " "0,1"
|
|
line.byte 0x2 "B34,GPIO port 1 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P1_2 " "0,1"
|
|
line.byte 0x3 "B35,GPIO port 1 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P1_3 " "0,1"
|
|
line.byte 0x4 "B36,GPIO port 1 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P1_4 " "0,1"
|
|
line.byte 0x5 "B37,GPIO port 1 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P1_5 " "0,1"
|
|
line.byte 0x6 "B38,GPIO port 1 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P1_6 " "0,1"
|
|
line.byte 0x7 "B39,GPIO port 1 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P1_7 " "0,1"
|
|
line.byte 0x8 "B40,GPIO port 1 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P1_8 " "0,1"
|
|
line.byte 0x9 "B41,GPIO port 1 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P1_9 " "0,1"
|
|
line.byte 0xA "B42,GPIO port 1 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P1_10" "0,1"
|
|
line.byte 0xB "B43,GPIO port 1 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P1_11" "0,1"
|
|
endif
|
|
group.byte 0x2C++0x04
|
|
line.byte 0x0 "B44,GPIO port 1 byte pin 12 register"
|
|
bitfld.byte 0x0 0. " PBYTE_12 ,State of the pin P1_12" "0,1"
|
|
line.byte 0x1 "B45,GPIO port 1 byte pin 13 register"
|
|
bitfld.byte 0x1 0. " PBYTE_13 ,State of the pin P1_13" "0,1"
|
|
line.byte 0x2 "B46,GPIO port 1 byte pin 14 register"
|
|
bitfld.byte 0x2 0. " PBYTE_14 ,State of the pin P1_14" "0,1"
|
|
line.byte 0x3 "B47,GPIO port 1 byte pin 15 register"
|
|
bitfld.byte 0x3 0. " PBYTE_15 ,State of the pin P1_15" "0,1"
|
|
line.byte 0x4 "B48,GPIO port 1 byte pin 16 register"
|
|
bitfld.byte 0x4 0. " PBYTE_16 ,State of the pin P1_16" "0,1"
|
|
sif cpu()!="LPC11E12"&&cpu()!="LPC11E13"
|
|
group.byte 0x31++0x01
|
|
line.byte 0x0 "B49,GPIO port 1 byte pin 17 register"
|
|
bitfld.byte 0x0 0. " PBYTE_17 ,State of the pin P1_17" "0,1"
|
|
line.byte 0x1 "B50,GPIO port 1 byte pin 18 register"
|
|
bitfld.byte 0x1 0. " PBYTE_18 ,State of the pin P1_18" "0,1"
|
|
endif
|
|
group.byte 0x33++0x0A
|
|
line.byte 0x0 "B51,GPIO port 1 byte pin 19 register"
|
|
bitfld.byte 0x0 0. " PBYTE_19 ,State of the pin P1_19" "0,1"
|
|
line.byte 0x1 "B52,GPIO port 1 byte pin 20 register"
|
|
bitfld.byte 0x1 0. " PBYTE_20 ,State of the pin P1_20" "0,1"
|
|
line.byte 0x2 "B53,GPIO port 1 byte pin 21 register"
|
|
bitfld.byte 0x2 0. " PBYTE_21 ,State of the pin P1_21" "0,1"
|
|
line.byte 0x3 "B54,GPIO port 1 byte pin 22 register"
|
|
bitfld.byte 0x3 0. " PBYTE_22 ,State of the pin P1_22" "0,1"
|
|
line.byte 0x4 "B55,GPIO port 1 byte pin 23 register"
|
|
bitfld.byte 0x4 0. " PBYTE_23 ,State of the pin P1_23" "0,1"
|
|
line.byte 0x5 "B56,GPIO port 1 byte pin 24 register"
|
|
bitfld.byte 0x5 0. " PBYTE_24 ,State of the pin P1_24" "0,1"
|
|
line.byte 0x6 "B57,GPIO port 1 byte pin 25 register"
|
|
bitfld.byte 0x6 0. " PBYTE_25 ,State of the pin P1_25" "0,1"
|
|
line.byte 0x7 "B58,GPIO port 1 byte pin 26 register"
|
|
bitfld.byte 0x7 0. " PBYTE_26 ,State of the pin P1_26" "0,1"
|
|
line.byte 0x8 "B59,GPIO port 1 byte pin 27 register"
|
|
bitfld.byte 0x8 0. " PBYTE_27 ,State of the pin P1_27" "0,1"
|
|
line.byte 0x9 "B60,GPIO port 1 byte pin 28 register"
|
|
bitfld.byte 0x9 0. " PBYTE_28 ,State of the pin P1_28" "0,1"
|
|
line.byte 0xA "B61,GPIO port 1 byte pin 29 register"
|
|
bitfld.byte 0xA 0. " PBYTE_29 ,State of the pin P1_29" "0,1"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "B63,GPIO port 1 byte pin 31 register"
|
|
bitfld.byte 0x00 0. " PBYTE_31 ,State of the pin P1_31" "0,1"
|
|
endif
|
|
elif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
group.byte 0x20++0x16
|
|
line.byte 0x0 "B32,GPIO port 1 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P1_0 " "0,1"
|
|
line.byte 0x1 "B33,GPIO port 1 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P1_1 " "0,1"
|
|
line.byte 0x2 "B34,GPIO port 1 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P1_2 " "0,1"
|
|
line.byte 0x3 "B35,GPIO port 1 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P1_3 " "0,1"
|
|
line.byte 0x4 "B36,GPIO port 1 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P1_4 " "0,1"
|
|
line.byte 0x5 "B37,GPIO port 1 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P1_5 " "0,1"
|
|
line.byte 0x6 "B38,GPIO port 1 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P1_6 " "0,1"
|
|
line.byte 0x7 "B39,GPIO port 1 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P1_7 " "0,1"
|
|
line.byte 0x8 "B40,GPIO port 1 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P1_8 " "0,1"
|
|
line.byte 0x9 "B41,GPIO port 1 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P1_9 " "0,1"
|
|
line.byte 0xA "B42,GPIO port 1 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P1_10" "0,1"
|
|
line.byte 0xB "B43,GPIO port 1 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P1_11" "0,1"
|
|
line.byte 0xC "B44,GPIO port 1 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P1_12" "0,1"
|
|
line.byte 0xD "B45,GPIO port 1 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P1_13" "0,1"
|
|
line.byte 0xE "B46,GPIO port 1 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P1_14" "0,1"
|
|
line.byte 0xF "B47,GPIO port 1 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P1_15" "0,1"
|
|
elif (cpuis("LPC11U14*"))
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "B37,GPIO port 1 byte pin 5 register"
|
|
bitfld.byte 0x00 0. " PBYTE_37 ,State of the pin P1_5" "0,1"
|
|
group.byte 0x2d++0x00
|
|
line.byte 0x00 "B45,GPIO port 1 byte pin 13 register"
|
|
bitfld.byte 0x00 0. " PBYTE_45 ,State of the pin P1_13" "0,1"
|
|
group.byte 0x2e++0x00
|
|
line.byte 0x00 "B46,GPIO port 1 byte pin 14 register"
|
|
bitfld.byte 0x00 0. " PBYTE_46 ,State of the pin P1_14" "0,1"
|
|
group.byte 0x2f++0x00
|
|
line.byte 0x00 "B47,GPIO port 1 byte pin 15 register"
|
|
bitfld.byte 0x00 0. " PBYTE_47 ,State of the pin P1_15" "0,1"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "B48,GPIO port 1 byte pin 16 register"
|
|
bitfld.byte 0x00 0. " PBYTE_48 ,State of the pin P1_16" "0,1"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "B51,GPIO port 1 byte pin 19 register"
|
|
bitfld.byte 0x00 0. " PBYTE_51 ,State of the pin P1_19" "0,1"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "B52,GPIO port 1 byte pin 20 register"
|
|
bitfld.byte 0x00 0. " PBYTE_52 ,State of the pin P1_20" "0,1"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "B53,GPIO port 1 byte pin 21 register"
|
|
bitfld.byte 0x00 0. " PBYTE_53 ,State of the pin P1_21" "0,1"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "B54,GPIO port 1 byte pin 22 register"
|
|
bitfld.byte 0x00 0. " PBYTE_54 ,State of the pin P1_22" "0,1"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "B55,GPIO port 1 byte pin 23 register"
|
|
bitfld.byte 0x00 0. " PBYTE_55 ,State of the pin P1_23" "0,1"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "B56,GPIO port 1 byte pin 24 register"
|
|
bitfld.byte 0x00 0. " PBYTE_56 ,State of the pin P1_24" "0,1"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "B57,GPIO port 1 byte pin 25 register"
|
|
bitfld.byte 0x00 0. " PBYTE_57 ,State of the pin P1_25" "0,1"
|
|
group.byte 0x3a++0x00
|
|
line.byte 0x00 "B58,GPIO port 1 byte pin 26 register"
|
|
bitfld.byte 0x00 0. " PBYTE_58 ,State of the pin P1_26" "0,1"
|
|
group.byte 0x3b++0x00
|
|
line.byte 0x00 "B59,GPIO port 1 byte pin 27 register"
|
|
bitfld.byte 0x00 0. " PBYTE_59 ,State of the pin P1_27" "0,1"
|
|
group.byte 0x3c++0x00
|
|
line.byte 0x00 "B60,GPIO port 1 byte pin 28 register"
|
|
bitfld.byte 0x00 0. " PBYTE_60 ,State of the pin P1_28" "0,1"
|
|
group.byte 0x3d++0x00
|
|
line.byte 0x00 "B61,GPIO port 1 byte pin 29 register"
|
|
bitfld.byte 0x00 0. " PBYTE_61 ,State of the pin P1_29" "0,1"
|
|
group.byte 0x3e++0x00
|
|
line.byte 0x00 "B62,GPIO port 1 byte pin 30 register"
|
|
bitfld.byte 0x00 0. " PBYTE_62 ,State of the pin P1_30" "0,1"
|
|
group.byte 0x3f++0x00
|
|
line.byte 0x00 "B63,GPIO port 1 byte pin 31 register"
|
|
bitfld.byte 0x00 0. " PBYTE_63 ,State of the pin P1_31" "0,1"
|
|
elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*"))
|
|
group.byte 0x2d++0x00
|
|
line.byte 0x00 "B45,GPIO port 1 byte pin 13 register"
|
|
bitfld.byte 0x00 0. " PBYTE_45 ,State of the pin P1_13" "0,1"
|
|
group.byte 0x2e++0x00
|
|
line.byte 0x00 "B46,GPIO port 1 byte pin 14 register"
|
|
bitfld.byte 0x00 0. " PBYTE_46 ,State of the pin P1_14" "0,1"
|
|
group.byte 0x2f++0x00
|
|
line.byte 0x00 "B47,GPIO port 1 byte pin 15 register"
|
|
bitfld.byte 0x00 0. " PBYTE_47 ,State of the pin P1_15" "0,1"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "B48,GPIO port 1 byte pin 16 register"
|
|
bitfld.byte 0x00 0. " PBYTE_48 ,State of the pin P1_16" "0,1"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "B51,GPIO port 1 byte pin 19 register"
|
|
bitfld.byte 0x00 0. " PBYTE_51 ,State of the pin P1_19" "0,1"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "B52,GPIO port 1 byte pin 20 register"
|
|
bitfld.byte 0x00 0. " PBYTE_52 ,State of the pin P1_20" "0,1"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "B53,GPIO port 1 byte pin 21 register"
|
|
bitfld.byte 0x00 0. " PBYTE_53 ,State of the pin P1_21" "0,1"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "B54,GPIO port 1 byte pin 22 register"
|
|
bitfld.byte 0x00 0. " PBYTE_54 ,State of the pin P1_22" "0,1"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "B55,GPIO port 1 byte pin 23 register"
|
|
bitfld.byte 0x00 0. " PBYTE_55 ,State of the pin P1_23" "0,1"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "B56,GPIO port 1 byte pin 24 register"
|
|
bitfld.byte 0x00 0. " PBYTE_56 ,State of the pin P1_24" "0,1"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "B57,GPIO port 1 byte pin 25 register"
|
|
bitfld.byte 0x00 0. " PBYTE_57 ,State of the pin P1_25" "0,1"
|
|
group.byte 0x3a++0x00
|
|
line.byte 0x00 "B58,GPIO port 1 byte pin 26 register"
|
|
bitfld.byte 0x00 0. " PBYTE_58 ,State of the pin P1_26" "0,1"
|
|
group.byte 0x3b++0x00
|
|
line.byte 0x00 "B59,GPIO port 1 byte pin 27 register"
|
|
bitfld.byte 0x00 0. " PBYTE_59 ,State of the pin P1_27" "0,1"
|
|
group.byte 0x3c++0x00
|
|
line.byte 0x00 "B60,GPIO port 1 byte pin 28 register"
|
|
bitfld.byte 0x00 0. " PBYTE_60 ,State of the pin P1_28" "0,1"
|
|
group.byte 0x3d++0x00
|
|
line.byte 0x00 "B61,GPIO port 1 byte pin 29 register"
|
|
bitfld.byte 0x00 0. " PBYTE_61 ,State of the pin P1_29" "0,1"
|
|
group.byte 0x3e++0x00
|
|
line.byte 0x00 "B62,GPIO port 1 byte pin 30 register"
|
|
bitfld.byte 0x00 0. " PBYTE_62 ,State of the pin P1_30" "0,1"
|
|
group.byte 0x3f++0x00
|
|
line.byte 0x00 "B63,GPIO port 1 byte pin 31 register"
|
|
bitfld.byte 0x00 0. " PBYTE_63 ,State of the pin P1_31" "0,1"
|
|
else
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "B32,GPIO port 1 byte pin 0 register"
|
|
bitfld.byte 0x00 0. " PBYTE_32 ,State of the pin P1_0" "0,1"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "B33,GPIO port 1 byte pin 1 register"
|
|
bitfld.byte 0x00 0. " PBYTE_33 ,State of the pin P1_1" "0,1"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "B34,GPIO port 1 byte pin 2 register"
|
|
bitfld.byte 0x00 0. " PBYTE_34 ,State of the pin P1_2" "0,1"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "B35,GPIO port 1 byte pin 3 register"
|
|
bitfld.byte 0x00 0. " PBYTE_35 ,State of the pin P1_3" "0,1"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "B36,GPIO port 1 byte pin 4 register"
|
|
bitfld.byte 0x00 0. " PBYTE_36 ,State of the pin P1_4" "0,1"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "B37,GPIO port 1 byte pin 5 register"
|
|
bitfld.byte 0x00 0. " PBYTE_37 ,State of the pin P1_5" "0,1"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "B38,GPIO port 1 byte pin 6 register"
|
|
bitfld.byte 0x00 0. " PBYTE_38 ,State of the pin P1_6" "0,1"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "B39,GPIO port 1 byte pin 7 register"
|
|
bitfld.byte 0x00 0. " PBYTE_39 ,State of the pin P1_7" "0,1"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "B40,GPIO port 1 byte pin 8 register"
|
|
bitfld.byte 0x00 0. " PBYTE_40 ,State of the pin P1_8" "0,1"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "B41,GPIO port 1 byte pin 9 register"
|
|
bitfld.byte 0x00 0. " PBYTE_41 ,State of the pin P1_9" "0,1"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "B42,GPIO port 1 byte pin 10 register"
|
|
bitfld.byte 0x00 0. " PBYTE_42 ,State of the pin P1_10" "0,1"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "B43,GPIO port 1 byte pin 11 register"
|
|
bitfld.byte 0x00 0. " PBYTE_43 ,State of the pin P1_11" "0,1"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "B44,GPIO port 1 byte pin 12 register"
|
|
bitfld.byte 0x00 0. " PBYTE_44 ,State of the pin P1_12" "0,1"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "B45,GPIO port 1 byte pin 13 register"
|
|
bitfld.byte 0x00 0. " PBYTE_45 ,State of the pin P1_13" "0,1"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "B46,GPIO port 1 byte pin 14 register"
|
|
bitfld.byte 0x00 0. " PBYTE_46 ,State of the pin P1_14" "0,1"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "B47,GPIO port 1 byte pin 15 register"
|
|
bitfld.byte 0x00 0. " PBYTE_47 ,State of the pin P1_15" "0,1"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "B48,GPIO port 1 byte pin 16 register"
|
|
bitfld.byte 0x00 0. " PBYTE_48 ,State of the pin P1_16" "0,1"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "B49,GPIO port 1 byte pin 17 register"
|
|
bitfld.byte 0x00 0. " PBYTE_49 ,State of the pin P1_17" "0,1"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "B50,GPIO port 1 byte pin 18 register"
|
|
bitfld.byte 0x00 0. " PBYTE_50 ,State of the pin P1_18" "0,1"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "B51,GPIO port 1 byte pin 19 register"
|
|
bitfld.byte 0x00 0. " PBYTE_51 ,State of the pin P1_19" "0,1"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "B52,GPIO port 1 byte pin 20 register"
|
|
bitfld.byte 0x00 0. " PBYTE_52 ,State of the pin P1_20" "0,1"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "B53,GPIO port 1 byte pin 21 register"
|
|
bitfld.byte 0x00 0. " PBYTE_53 ,State of the pin P1_21" "0,1"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "B54,GPIO port 1 byte pin 22 register"
|
|
bitfld.byte 0x00 0. " PBYTE_54 ,State of the pin P1_22" "0,1"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "B55,GPIO port 1 byte pin 23 register"
|
|
bitfld.byte 0x00 0. " PBYTE_55 ,State of the pin P1_23" "0,1"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "B56,GPIO port 1 byte pin 24 register"
|
|
bitfld.byte 0x00 0. " PBYTE_56 ,State of the pin P1_24" "0,1"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "B57,GPIO port 1 byte pin 25 register"
|
|
bitfld.byte 0x00 0. " PBYTE_57 ,State of the pin P1_25" "0,1"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "B58,GPIO port 1 byte pin 26 register"
|
|
bitfld.byte 0x00 0. " PBYTE_58 ,State of the pin P1_26" "0,1"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "B59,GPIO port 1 byte pin 27 register"
|
|
bitfld.byte 0x00 0. " PBYTE_59 ,State of the pin P1_27" "0,1"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "B60,GPIO port 1 byte pin 28 register"
|
|
bitfld.byte 0x00 0. " PBYTE_60 ,State of the pin P1_28" "0,1"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "B61,GPIO port 1 byte pin 29 register"
|
|
bitfld.byte 0x00 0. " PBYTE_61 ,State of the pin P1_29" "0,1"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "B62,GPIO port 1 byte pin 30 register"
|
|
bitfld.byte 0x00 0. " PBYTE_62 ,State of the pin P1_30" "0,1"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "B63,GPIO port 1 byte pin 31 register"
|
|
bitfld.byte 0x00 0. " PBYTE_63 ,State of the pin P1_31" "0,1"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
sif cpu()=="LPC11E11"
|
|
group.long 0x10BC++0x3
|
|
line.long 0x00 "W47,GPIO port 1 word pin 15 register"
|
|
group.long 0x10CC++0x3
|
|
line.long 0x00 "W51,GPIO port 1 word pin 19 register"
|
|
group.long 0x10D4++0x3
|
|
line.long 0x00 "W55,GPIO port 1 word pin 23 register"
|
|
group.long 0x10D8++0x3
|
|
line.long 0x00 "W56,GPIO port 1 word pin 24 register"
|
|
else
|
|
sif cpu()!="LPC11E12"&&cpu()!="LPC11E13"
|
|
group.long 0x1000++0x7b
|
|
line.long 0x0 "W32,GPIO port 1 word pin 0 register"
|
|
line.long 0x4 "W33,GPIO port 1 word pin 1 register"
|
|
line.long 0x8 "W34,GPIO port 1 word pin 2 register"
|
|
line.long 0xC "W35,GPIO port 1 word pin 3 register"
|
|
line.long 0x10 "W36,GPIO port 1 word pin 4 register"
|
|
line.long 0x14 "W37,GPIO port 1 word pin 5 register"
|
|
line.long 0x18 "W38,GPIO port 1 word pin 6 register"
|
|
line.long 0x1C "W39,GPIO port 1 word pin 7 register"
|
|
line.long 0x20 "W40,GPIO port 1 word pin 8 register"
|
|
line.long 0x24 "W41,GPIO port 1 word pin 9 register"
|
|
line.long 0x28 "W42,GPIO port 1 word pin 10 register"
|
|
line.long 0x2C "W43,GPIO port 1 word pin 11 register"
|
|
endif
|
|
group.long 0x1030++0x13
|
|
line.long 0x0 "W44,GPIO port 1 word pin 12 register"
|
|
line.long 0x4 "W45,GPIO port 1 word pin 13 register"
|
|
line.long 0x8 "W46,GPIO port 1 word pin 14 register"
|
|
line.long 0xC "W47,GPIO port 1 word pin 15 register"
|
|
line.long 0x10 "W48,GPIO port 1 word pin 16 register"
|
|
sif cpu()!="LPC11E12"&&cpu()!="LPC11E13"
|
|
group.long 0x1044++0x07
|
|
line.long 0x0 "W49,GPIO port 1 word pin 17 register"
|
|
line.long 0x4 "W50,GPIO port 1 word pin 18 register"
|
|
endif
|
|
group.long 0x104C++0x2B
|
|
line.long 0x0 "W51,GPIO port 1 word pin 19 register"
|
|
line.long 0x4 "W52,GPIO port 1 word pin 20 register"
|
|
line.long 0x8 "W53,GPIO port 1 word pin 21 register"
|
|
line.long 0xC "W54,GPIO port 1 word pin 22 register"
|
|
line.long 0x10 "W55,GPIO port 1 word pin 23 register"
|
|
line.long 0x14 "W56,GPIO port 1 word pin 24 register"
|
|
line.long 0x18 "W57,GPIO port 1 word pin 25 register"
|
|
line.long 0x1C "W58,GPIO port 1 word pin 26 register"
|
|
line.long 0x20 "W59,GPIO port 1 word pin 27 register"
|
|
line.long 0x24 "W60,GPIO port 1 word pin 28 register"
|
|
line.long 0x28 "W61,GPIO port 1 word pin 29 register"
|
|
group.long 0x107C++0x3
|
|
line.long 0x00 "W63,GPIO port 1 word pin 31 register"
|
|
endif
|
|
elif (cpu()=="LPC11A12"||cpu()=="LPC11A14")
|
|
group.long 0x1080++0x2B
|
|
line.long 0x0 "W32,GPIO port 1 word pin 32 register"
|
|
line.long 0x4 "W33,GPIO port 1 word pin 33 register"
|
|
line.long 0x8 "W34,GPIO port 1 word pin 34 register"
|
|
line.long 0xC "W35,GPIO port 1 word pin 35 register"
|
|
line.long 0x10 "W36,GPIO port 1 word pin 36 register"
|
|
line.long 0x14 "W37,GPIO port 1 word pin 37 register"
|
|
line.long 0x18 "W38,GPIO port 1 word pin 38 register"
|
|
line.long 0x1C "W39,GPIO port 1 word pin 39 register"
|
|
line.long 0x20 "W40,GPIO port 1 word pin 40 register"
|
|
line.long 0x24 "W41,GPIO port 1 word pin 41 register"
|
|
elif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
group.long 0x1080++0x43
|
|
line.long 0x0 "W32,GPIO port 1 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P1_0 "
|
|
line.long 0x4 "W33,GPIO port 1 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P1_1 "
|
|
line.long 0x8 "W34,GPIO port 1 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P1_2 "
|
|
line.long 0xC "W35,GPIO port 1 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P1_3 "
|
|
line.long 0x10 "W36,GPIO port 1 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P1_4 "
|
|
line.long 0x14 "W37,GPIO port 1 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P1_5 "
|
|
line.long 0x18 "W38,GPIO port 1 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P1_6 "
|
|
line.long 0x1C "W39,GPIO port 1 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P1_7 "
|
|
line.long 0x20 "W40,GPIO port 1 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P1_8 "
|
|
line.long 0x24 "W41,GPIO port 1 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P1_9 "
|
|
line.long 0x28 "W42,GPIO port 1 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P1_10"
|
|
line.long 0x2C "W43,GPIO port 1 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P1_11"
|
|
line.long 0x30 "W44,GPIO port 1 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P1_12"
|
|
line.long 0x34 "W45,GPIO port 1 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P1_13"
|
|
line.long 0x38 "W46,GPIO port 1 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P1_14"
|
|
line.long 0x3C "W47,GPIO port 1 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P1_15"
|
|
elif (cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&!cpuis("LPC11U*"))
|
|
group.long 0x1094++0x3
|
|
line.long 0x00 "W37,GPIO port 1 word pin 5 register"
|
|
hexmask.long 0x00 0.--31. 1. " PWORD_37 ,State of the pin P1_5"
|
|
sif (cpu()!="LPC11E11")
|
|
group.long 0x10A8++0xF
|
|
line.long 0x00 "W45,GPIO port 1 word pin 13 register"
|
|
hexmask.long 0x00 0.--31. 1. " PWORD_46 ,State of the pin P1_14"
|
|
line.long 0x04 "W46,GPIO port 1 word pin 14 register"
|
|
hexmask.long 0x04 0.--31. 1. " PWORD_46 ,State of the pin P1_14"
|
|
line.long 0x08 "W47,GPIO port 1 word pin 15 register"
|
|
hexmask.long 0x08 0.--31. 1. " PWORD_47 ,State of the pin P1_15"
|
|
line.long 0x0C "W48,GPIO port 1 word pin 16 register"
|
|
hexmask.long 0x0C 0.--31. 1. " PWORD_48 ,State of the pin P1_16"
|
|
group.long 0x10CC++0x2B
|
|
line.long 0x00 "W51,GPIO port 1 word pin 19 register"
|
|
hexmask.long 0x00 0.--31. 1. " PWORD_51 ,State of the pin P1_19"
|
|
line.long 0x04 "W52,GPIO port 1 word pin 20 register"
|
|
hexmask.long 0x04 0.--31. 1. " PWORD_52 ,State of the pin P1_20"
|
|
line.long 0x08 "W53,GPIO port 1 word pin 21 register"
|
|
hexmask.long 0x08 0.--31. 1. " PWORD_53 ,State of the pin P1_21"
|
|
line.long 0x0C "W54,GPIO port 1 word pin 22 register"
|
|
hexmask.long 0x0C 0.--31. 1. " PWORD_54 ,State of the pin P1_22"
|
|
line.long 0x10 "W55,GPIO port 1 word pin 23 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_55 ,State of the pin P1_23"
|
|
line.long 0x14 "W56,GPIO port 1 word pin 24 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_56 ,State of the pin P1_24"
|
|
line.long 0x18 "W57,GPIO port 1 word pin 25 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_57 ,State of the pin P1_25"
|
|
line.long 0x1C "W58,GPIO port 1 word pin 26 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_58 ,State of the pin P1_26"
|
|
line.long 0x20 "W59,GPIO port 1 word pin 27 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_59 ,State of the pin P1_27"
|
|
line.long 0x24 "W60,GPIO port 1 word pin 28 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_60 ,State of the pin P1_28"
|
|
line.long 0x28 "W61,GPIO port 1 word pin 29 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_61 ,State of the pin P1_29"
|
|
group.long 0x10FC++0x3
|
|
line.long 0x00 "W63,GPIO port 1 word pin 31 register"
|
|
hexmask.long 0x00 0.--31. 1. " PWORD_61 ,State of the pin P1_31"
|
|
endif
|
|
elif (cpuis("LPC11U14*"))
|
|
group.byte 0x1094++0x03
|
|
line.long 0x00 "W37,GPIO port 1 word pin 5 register"
|
|
group.byte 0x10b4++0x03
|
|
line.long 0x00 "W45,GPIO port 1 word pin 13 register"
|
|
group.byte 0x10b8++0x03
|
|
line.long 0x00 "W46,GPIO port 1 word pin 14 register"
|
|
group.byte 0x10bc++0x03
|
|
line.long 0x00 "W47,GPIO port 1 word pin 15 register"
|
|
group.byte 0x10c0++0x03
|
|
line.long 0x00 "W48,GPIO port 1 word pin 16 register"
|
|
group.byte 0x10cc++0x03
|
|
line.long 0x00 "W51,GPIO port 1 word pin 19 register"
|
|
group.byte 0x10d0++0x03
|
|
line.long 0x00 "W52,GPIO port 1 word pin 20 register"
|
|
group.byte 0x10d4++0x03
|
|
line.long 0x00 "W53,GPIO port 1 word pin 21 register"
|
|
group.byte 0x10d8++0x03
|
|
line.long 0x00 "W54,GPIO port 1 word pin 22 register"
|
|
group.byte 0x10dc++0x03
|
|
line.long 0x00 "W55,GPIO port 1 word pin 23 register"
|
|
group.byte 0x10e0++0x03
|
|
line.long 0x00 "W56,GPIO port 1 word pin 24 register"
|
|
group.byte 0x10e4++0x03
|
|
line.long 0x00 "W57,GPIO port 1 word pin 25 register"
|
|
group.byte 0x10e8++0x03
|
|
line.long 0x00 "W58,GPIO port 1 word pin 26 register"
|
|
group.byte 0x10ec++0x03
|
|
line.long 0x00 "W59,GPIO port 1 word pin 27 register"
|
|
group.byte 0x10f0++0x03
|
|
line.long 0x00 "W60,GPIO port 1 word pin 28 register"
|
|
group.byte 0x10f4++0x03
|
|
line.long 0x00 "W61,GPIO port 1 word pin 29 register"
|
|
group.byte 0x10f8++0x03
|
|
line.long 0x00 "W62,GPIO port 1 word pin 30 register"
|
|
group.byte 0x10fc++0x03
|
|
line.long 0x00 "W63,GPIO port 1 word pin 31 register"
|
|
elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*"))
|
|
group.byte 0x10b4++0x03
|
|
line.long 0x00 "W45,GPIO port 1 word pin 13 register"
|
|
group.byte 0x10b8++0x03
|
|
line.long 0x00 "W46,GPIO port 1 word pin 14 register"
|
|
group.byte 0x10bc++0x03
|
|
line.long 0x00 "W47,GPIO port 1 word pin 15 register"
|
|
group.byte 0x10c0++0x03
|
|
line.long 0x00 "W48,GPIO port 1 word pin 16 register"
|
|
group.byte 0x10cc++0x03
|
|
line.long 0x00 "W51,GPIO port 1 word pin 19 register"
|
|
group.byte 0x10d0++0x03
|
|
line.long 0x00 "W52,GPIO port 1 word pin 20 register"
|
|
group.byte 0x10d4++0x03
|
|
line.long 0x00 "W53,GPIO port 1 word pin 21 register"
|
|
group.byte 0x10d8++0x03
|
|
line.long 0x00 "W54,GPIO port 1 word pin 22 register"
|
|
group.byte 0x10dc++0x03
|
|
line.long 0x00 "W55,GPIO port 1 word pin 23 register"
|
|
group.byte 0x10e0++0x03
|
|
line.long 0x00 "W56,GPIO port 1 word pin 24 register"
|
|
group.byte 0x10e4++0x03
|
|
line.long 0x00 "W57,GPIO port 1 word pin 25 register"
|
|
group.byte 0x10e8++0x03
|
|
line.long 0x00 "W58,GPIO port 1 word pin 26 register"
|
|
group.byte 0x10ec++0x03
|
|
line.long 0x00 "W59,GPIO port 1 word pin 27 register"
|
|
group.byte 0x10f0++0x03
|
|
line.long 0x00 "W60,GPIO port 1 word pin 28 register"
|
|
group.byte 0x10f4++0x03
|
|
line.long 0x00 "W61,GPIO port 1 word pin 29 register"
|
|
group.byte 0x10f8++0x03
|
|
line.long 0x00 "W62,GPIO port 1 word pin 30 register"
|
|
group.byte 0x10fc++0x03
|
|
line.long 0x00 "W63,GPIO port 1 word pin 31 register"
|
|
else
|
|
group.byte 0x1080++0x03
|
|
line.long 0x00 "W32,GPIO port 1 word pin 0 register"
|
|
group.byte 0x1084++0x03
|
|
line.long 0x00 "W33,GPIO port 1 word pin 1 register"
|
|
group.byte 0x1088++0x03
|
|
line.long 0x00 "W34,GPIO port 1 word pin 2 register"
|
|
group.byte 0x108C++0x03
|
|
line.long 0x00 "W35,GPIO port 1 word pin 3 register"
|
|
group.byte 0x1090++0x03
|
|
line.long 0x00 "W36,GPIO port 1 word pin 4 register"
|
|
group.byte 0x1094++0x03
|
|
line.long 0x00 "W37,GPIO port 1 word pin 5 register"
|
|
group.byte 0x1098++0x03
|
|
line.long 0x00 "W38,GPIO port 1 word pin 6 register"
|
|
group.byte 0x109C++0x03
|
|
line.long 0x00 "W39,GPIO port 1 word pin 7 register"
|
|
group.byte 0x10A0++0x03
|
|
line.long 0x00 "W40,GPIO port 1 word pin 8 register"
|
|
group.byte 0x10A4++0x03
|
|
line.long 0x00 "W41,GPIO port 1 word pin 9 register"
|
|
group.byte 0x10A8++0x03
|
|
line.long 0x00 "W42,GPIO port 1 word pin 10 register"
|
|
group.byte 0x10AC++0x03
|
|
line.long 0x00 "W43,GPIO port 1 word pin 11 register"
|
|
group.byte 0x10B0++0x03
|
|
line.long 0x00 "W44,GPIO port 1 word pin 12 register"
|
|
group.byte 0x10B4++0x03
|
|
line.long 0x00 "W45,GPIO port 1 word pin 13 register"
|
|
group.byte 0x10B8++0x03
|
|
line.long 0x00 "W46,GPIO port 1 word pin 14 register"
|
|
group.byte 0x10BC++0x03
|
|
line.long 0x00 "W47,GPIO port 1 word pin 15 register"
|
|
group.byte 0x10C0++0x03
|
|
line.long 0x00 "W48,GPIO port 1 word pin 16 register"
|
|
group.byte 0x10C4++0x03
|
|
line.long 0x00 "W49,GPIO port 1 word pin 17 register"
|
|
group.byte 0x10C8++0x03
|
|
line.long 0x00 "W50,GPIO port 1 word pin 18 register"
|
|
group.byte 0x10CC++0x03
|
|
line.long 0x00 "W51,GPIO port 1 word pin 19 register"
|
|
group.byte 0x10D0++0x03
|
|
line.long 0x00 "W52,GPIO port 1 word pin 20 register"
|
|
group.byte 0x10D4++0x03
|
|
line.long 0x00 "W53,GPIO port 1 word pin 21 register"
|
|
group.byte 0x10D8++0x03
|
|
line.long 0x00 "W54,GPIO port 1 word pin 22 register"
|
|
group.byte 0x10DC++0x03
|
|
line.long 0x00 "W55,GPIO port 1 word pin 23 register"
|
|
group.byte 0x10E0++0x03
|
|
line.long 0x00 "W56,GPIO port 1 word pin 24 register"
|
|
group.byte 0x10E4++0x03
|
|
line.long 0x00 "W57,GPIO port 1 word pin 25 register"
|
|
group.byte 0x10E8++0x03
|
|
line.long 0x00 "W58,GPIO port 1 word pin 26 register"
|
|
group.byte 0x10EC++0x03
|
|
line.long 0x00 "W59,GPIO port 1 word pin 27 register"
|
|
group.byte 0x10F0++0x03
|
|
line.long 0x00 "W60,GPIO port 1 word pin 28 register"
|
|
group.byte 0x10F4++0x03
|
|
line.long 0x00 "W61,GPIO port 1 word pin 29 register"
|
|
group.byte 0x10F8++0x03
|
|
line.long 0x00 "W62,GPIO port 1 word pin 30 register"
|
|
group.byte 0x10FC++0x03
|
|
line.long 0x00 "W63,GPIO port 1 word pin 31 register"
|
|
endif
|
|
group.long 0x2004++0x3
|
|
line.long 0x00 "DIR1,GPIO direction port 1 register"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11U14/201"&&cpu()!="LPC11U35/501")
|
|
bitfld.long 0x00 31. " DIRP1[31] ,Pin direction for pin P1_31" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " DIRP1[29] ,Pin direction for pin P1_29" "Input,Output"
|
|
bitfld.long 0x00 28. " DIRP1[28] ,Pin direction for pin P1_28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DIRP1[27] ,Pin direction for pin P1_27" "Input,Output"
|
|
bitfld.long 0x00 26. " DIRP1[26] ,Pin direction for pin P1_26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DIRP1[25] ,Pin direction for pin P1_25" "Input,Output"
|
|
bitfld.long 0x00 24. " DIRP1[24] ,Pin direction for pin P1_24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DIRP1[23] ,Pin direction for pin P1_23" "Input,Output"
|
|
bitfld.long 0x00 22. " DIRP1[22] ,Pin direction for pin P1_22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DIRP1[21] ,Pin direction for pin P1_21" "Input,Output"
|
|
bitfld.long 0x00 20. " DIRP1[20] ,Pin direction for pin P1_20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIRP1[19] ,Pin direction for pin P1_19" "Input,Output"
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37")
|
|
bitfld.long 0x00 18. " DIRP1[18] ,Pin direction for pin P1_18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DIRP1[17] ,Pin direction for pin P1_17" "Input,Output"
|
|
endif
|
|
bitfld.long 0x00 16. " DIRP1[16] ,Pin direction for pin P1_16" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " DIRP1[15] ,Pin direction for pin P1_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP1[14] ,Pin direction for pin P1_14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRP1[13] ,Pin direction for pin P1_13" "Input,Output"
|
|
endif
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37"||cpu()=="LPC11A12"||cpu()=="LPC11A14"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
bitfld.long 0x00 12. " DIRP1[12] ,Pin direction for pin P1_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP1[11] ,Pin direction for pin P1_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP1[10] ,Pin direction for pin P1_10" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " DIRP1[9] ,Pin direction for pin P1_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP1[8] ,Pin direction for pin P1_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP1[7] ,Pin direction for pin P1_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP1[6] ,Pin direction for pin P1_6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DIRP1[5] ,Pin direction for pin P1_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP1[4] ,Pin direction for pin P1_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP1[3] ,Pin direction for pin P1_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP1[2] ,Pin direction for pin P1_2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIRP1[1] ,Pin direction for pin P1_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP1[0] ,Pin direction for pin P1_0" "Input,Output"
|
|
elif (cpu()=="LPC11E11")
|
|
bitfld.long 0x00 24. " DIRP1[24] ,Pin direction for pin P1_24" "Input,Output"
|
|
bitfld.long 0x00 23. " DIRP1[23] ,Pin direction for pin P1_23" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIRP1[19] ,Pin direction for pin P1_19" "Input,Output"
|
|
bitfld.long 0x00 15. " DIRP1[15] ,Pin direction for pin P1_15" "Input,Output"
|
|
elif (cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U23/301"&&cpu()!="LPC11U34/311"&&cpu()!="LPC11U34/421"&&cpu()!="LPC11U37/401")
|
|
bitfld.long 0x00 5. " DIRP1[5] ,Pin direction for pin P1_5" "Input,Output"
|
|
endif
|
|
group.long 0x2084++0x3
|
|
line.long 0x00 "MASK1,GPIO mask port 1 register"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
sif (cpu()!="LPC11U14/201"&&cpu()!="LPC11U35/501"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 31. " MASKP1[31] ,Mask for pin P1_31" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 29. " MASKP1[29] ,Mask for pin P1_29" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " MASKP1[28] ,Mask for pin P1_28" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MASKP1[27] ,Mask for pin P1_27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " MASKP1[26] ,Mask for pin P1_26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MASKP1[25] ,Mask for pin P1_25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " MASKP1[24] ,Mask for pin P1_24" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MASKP1[23] ,Mask for pin P1_23" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " MASKP1[22] ,Mask for pin P1_22" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MASKP1[21] ,Mask for pin P1_21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " MASKP1[20] ,Mask for pin P1_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MASKP1[19] ,Mask for pin P1_19" "Not masked,Masked"
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37")
|
|
bitfld.long 0x00 18. " MASKP1[18] ,Mask for pin P1_18" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MASKP1[17] ,Mask for pin P1_17" "Not masked,Masked"
|
|
endif
|
|
bitfld.long 0x00 16. " MASKP1[16] ,Mask for pin P1_16" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MASKP1[15] ,Mask for pin P1_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP1[14] ,Mask for pin P1_14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASKP1[13] ,Mask for pin P1_13" "Not masked,Masked"
|
|
endif
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
bitfld.long 0x00 12. " MASKP1[12] ,Mask for pin P1_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP1[11] ,Mask for pin P1_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP1[10] ,Mask for pin P1_10" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " MASKP1[9] ,Mask for pin P1_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP1[8] ,Mask for pin P1_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP1[7] ,Mask for pin P1_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP1[6] ,Mask for pin P1_6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MASKP1[5] ,Mask for pin P1_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP1[4] ,Mask for pin P1_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP1[3] ,Mask for pin P1_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP1[2] ,Mask for pin P1_2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASKP1[1] ,Mask for pin P1_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP1[0] ,Mask for pin P1_0" "Not masked,Masked"
|
|
elif (cpu()=="LPC11E11")
|
|
bitfld.long 0x00 24. " MASKP1[24] ,Mask for pin P1_24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MASKP1[23] ,Mask for pin P1_23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MASKP1[19] ,Mask for pin P1_19" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MASKP1[15] ,Mask for pin P1_15" "Not masked,Masked"
|
|
elif (cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U23/301"&&cpu()!="LPC11U34/311"&&cpu()!="LPC11U34/421"&&cpu()!="LPC11U37/401")
|
|
bitfld.long 0x00 5. " MASKP1[5] ,Mask for pin P1_5" "Not masked,Masked"
|
|
endif
|
|
group.long 0x2104++0x3
|
|
line.long 0x00 "PIN1,GPIO port 1 pin register"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
sif (cpu()!="LPC11U14/201"&&cpu()!="LPC11U35/501"&&(!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")))
|
|
bitfld.long 0x00 31. " PORT1[31] ,P1_31 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
bitfld.long 0x00 29. " PORT1[29] ,P1_29 pin state" "Low,High"
|
|
bitfld.long 0x00 28. " PORT1[28] ,P1_28 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PORT1[27] ,P1_27 pin state" "Low,High"
|
|
bitfld.long 0x00 26. " PORT1[26] ,P1_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PORT1[25] ,P1_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " PORT1[24] ,P1_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PORT1[23] ,P1_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " PORT1[22] ,P1_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PORT1[21] ,P1_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " PORT1[20] ,P1_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PORT1[19] ,P1_19 pin state" "Low,High"
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37")
|
|
bitfld.long 0x00 18. " PORT1[18] ,P1_18 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PORT1[17] ,P1_17 pin state" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 16. " PORT1[16] ,P1_16 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PORT1[15] ,P1_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " PORT1[14] ,P1_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PORT1[13] ,P1_13 pin state" "Low,High"
|
|
endif
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11A12"||cpu()=="LPC11A14"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
bitfld.long 0x00 12. " PORT1[12] ,P1_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT1[11] ,P1_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " PORT1[10] ,P1_10 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " PORT1[9] ,P1_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " PORT1[8] ,P1_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT1[7] ,P1_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " PORT1[6] ,P1_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PORT1[5] ,P1_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " PORT1[4] ,P1_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT1[3] ,P1_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " PORT1[2] ,P1_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PORT1[1] ,P1_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " PORT1[0] ,P1_0 pin state" "Low,High"
|
|
elif (cpu()=="LPC11E11")
|
|
bitfld.long 0x00 23. " PORT1[23] ,P1_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " PORT1[22] ,P1_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PORT1[19] ,P1_19 pin state" "Low,High"
|
|
bitfld.long 0x00 5. " PORT1[5] ,P1_5 pin state" "Low,High"
|
|
elif (cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U23/301"&&cpu()!="LPC11U34/311"&&cpu()!="LPC11U34/421"&&cpu()!="LPC11U37/401")
|
|
bitfld.long 0x00 5. " PORT1[5] ,P1_5 pin state" "Low,High"
|
|
endif
|
|
group.long 0x2184++0x3
|
|
line.long 0x00 "MPIN1,GPIO masked port 1 pin register"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11U14/201"&&cpu()!="LPC11U35/501")
|
|
bitfld.long 0x00 31. " MPORTP1[31] ,Masked P1_31 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " MPORTP1[29] ,Masked P1_29 pin state" "Low,High"
|
|
bitfld.long 0x00 28. " MPORTP1[28] ,Masked P1_28 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MPORTP1[27] ,Masked P1_27 pin state" "Low,High"
|
|
bitfld.long 0x00 26. " MPORTP1[26] ,Masked P1_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MPORTP1[25] ,Masked P1_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " MPORTP1[24] ,Masked P1_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MPORTP1[23] ,Masked P1_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " MPORTP1[22] ,Masked P1_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MPORTP1[21] ,Masked P1_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " MPORTP1[20] ,Masked P1_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MPORTP1[19] ,Masked P1_19 pin state" "Low,High"
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37")
|
|
bitfld.long 0x00 18. " MPORTP1[18] ,Masked P1_18 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MPORTP1[17] ,Masked P1_17 pin state" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 16. " MPORTP1[16] ,Masked P1_16 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MPORTP1[15] ,Masked P1_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " MPORTP1[14] ,Masked P1_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MPORTP1[13] ,Masked P1_13 pin state" "Low,High"
|
|
endif
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11A12"||cpu()=="LPC11A14"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
bitfld.long 0x00 12. " MPORTP1[12] ,Masked P1_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP1[11] ,Masked P1_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " MPORTP1[10] ,Masked P1_10 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " MPORTP1[9] ,Masked P1_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " MPORTP1[8] ,Masked P1_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP1[7] ,Masked P1_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " MPORTP1[6] ,Masked P1_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPORTP1[5] ,Masked P1_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " MPORTP1[4] ,Masked P1_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP1[3] ,Masked P1_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " MPORTP1[2] ,Masked P1_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MPORTP1[1] ,Masked P1_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " MPORTP1[0] ,Masked P1_0 pin state" "Low,High"
|
|
elif (cpu()=="LPC11E11")
|
|
bitfld.long 0x00 24. " MPORTP1[24] ,Masked P1_24 pin state" "Low,High"
|
|
bitfld.long 0x00 23. " MPORTP1[23] ,Masked P1_23 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MPORTP1[19] ,Masked P1_19 pin state" "Low,High"
|
|
bitfld.long 0x00 5. " MPORTP1[5] ,Masked P1_5 pin state" "Low,High"
|
|
elif (cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U23/301"&&cpu()!="LPC11U34/311"&&cpu()!="LPC11U34/421"&&cpu()!="LPC11U37/401")
|
|
bitfld.long 0x00 5. " MPORTP1[5] ,Masked P1_5 pin state" "Low,High"
|
|
endif
|
|
group.long 0x2204++0x3
|
|
line.long 0x00 "SET1,GPIO set port 1 register"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11U14/201"&&cpu()!="LPC11U35/501")
|
|
bitfld.long 0x00 31. " SETP1[31] ,State/Set P1_31" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " SETP1[29] ,State/Set P1_29" "Low,High"
|
|
bitfld.long 0x00 28. " SETP1[28] ,State/Set P1_28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SETP1[27] ,State/Set P1_27" "Low,High"
|
|
bitfld.long 0x00 26. " SETP1[26] ,State/Set P1_26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SETP1[25] ,State/Set P1_25" "Low,High"
|
|
bitfld.long 0x00 24. " SETP1[24] ,State/Set P1_24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SETP1[23] ,State/Set P1_23" "Low,High"
|
|
bitfld.long 0x00 22. " SETP1[22] ,State/Set P1_22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SETP1[21] ,State/Set P1_21" "Low,High"
|
|
bitfld.long 0x00 20. " SETP1[20] ,State/Set P1_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SETP1[19] ,State/Set P1_19" "Low,High"
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37")
|
|
bitfld.long 0x00 18. " SETP1[18] ,State/Set P1_18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SETP1[17] ,State/Set P1_17" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 16. " SETP1[16] ,State/Set P1_16" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " SETP1[15] ,State/Set P1_15" "Low,High"
|
|
bitfld.long 0x00 14. " SETP1[14] ,State/Set P1_14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SETP1[13] ,State/Set P1_13" "Low,High"
|
|
endif
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11A12"||cpu()=="LPC11A14"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
bitfld.long 0x00 12. " SETP1[12] ,State/Set P1_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETP1[11] ,State/Set P1_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " SETP1[10] ,State/Set P1_10 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " SETP1[9] ,State/Set P1_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " SETP1[8] ,State/Set P1_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SETP1[7] ,State/Set P1_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " SETP1[6] ,State/Set P1_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETP1[5] ,State/Set P1_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " SETP1[4] ,State/Set P1_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SETP1[3] ,State/Set P1_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " SETP1[2] ,State/Set P1_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SETP1[1] ,State/Set P1_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " SETP1[0] ,State/Set P1_0 pin state" "Low,High"
|
|
elif (cpu()=="LPC11E11")
|
|
textline " "
|
|
bitfld.long 0x00 24. " SETP1[24] ,State/Set P1_24" "Low,High"
|
|
bitfld.long 0x00 23. " SETP1[23] ,State/Set P1_23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SETP1[19] ,State/Set P1_19" "Low,High"
|
|
bitfld.long 0x00 5. " SETP1[5] ,State/Set P1_5 pin state" "Low,High"
|
|
elif (cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U23/301"&&cpu()!="LPC11U34/311"&&cpu()!="LPC11U34/421"&&cpu()!="LPC11U37/401")
|
|
bitfld.long 0x00 5. " SETP1[5] ,State/Set P1_5" "Low,High"
|
|
endif
|
|
wgroup.long 0x2284++0x3
|
|
line.long 0x00 "CLR1,GPIO clear port 1 register"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11U14/201"&&cpu()!="LPC11U35/501")
|
|
bitfld.long 0x00 31. " CLRP1[31] ,Clear P1_31" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " CLRP1[29] ,Clear P1_29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " CLRP1[28] ,Clear P1_28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CLRP1[27] ,Clear P1_27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CLRP1[26] ,Clear P1_26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CLRP1[25] ,Clear P1_25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CLRP1[24] ,Clear P1_24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLRP1[23] ,Clear P1_23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CLRP1[22] ,Clear P1_22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CLRP1[21] ,Clear P1_21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CLRP1[20] ,Clear P1_20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLRP1[19] ,Clear P1_19" "No effect,Clear"
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37")
|
|
bitfld.long 0x00 18. " CLRP1[18] ,Clear P1_18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CLRP1[17] ,Clear P1_17" "No effect,Clear"
|
|
endif
|
|
bitfld.long 0x00 16. " CLRP1[16] ,Clear P1_16" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " CLRP1[15] ,Clear P1_15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLRP1[14] ,Clear P1_14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLRP1[13] ,Clear P1_13" "No effect,Clear"
|
|
endif
|
|
sif (cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37"||cpu()=="LPC11A12"||cpu()=="LPC11A14"||cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
bitfld.long 0x00 12. " CLRP1[12] ,Clear P1_12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLRP1[11] ,Clear P1_11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLRP1[10] ,Clear P1_10" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " CLRP1[9] ,Clear P1_9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLRP1[8] ,Clear P1_8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLRP1[7] ,Clear P1_7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLRP1[6] ,Clear P1_6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLRP1[5] ,Clear P1_5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLRP1[4] ,Clear P1_4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLRP1[3] ,Clear P1_3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLRP1[2] ,Clear P1_2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLRP1[1] ,Clear P1_1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLRP1[0] ,Clear P1_0" "No effect,Clear"
|
|
elif (cpu()=="LPC11E11")
|
|
bitfld.long 0x00 24. " CLRP1[24] ,Clear P1_24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " CLRP1[23] ,Clear P1_23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLRP1[19] ,Clear P1_19" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CLRP1[5] ,Clear P1_5" "No effect,Clear"
|
|
elif (cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U23/301"&&cpu()!="LPC11U34/311"&&cpu()!="LPC11U34/421"&&cpu()!="LPC11U37/401")
|
|
bitfld.long 0x00 5. " CLRP1[5] ,Clear P1_5" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x2304++0x3
|
|
line.long 0x0 "NOT1,GPIO toggle port 1 register"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11U14/201"&&cpu()!="LPC11U35/501")
|
|
bitfld.long 0x00 31. " NOTP1[31] ,Toggle P1_31" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " NOTP1[29] ,Toggle P1_29" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " NOTP1[28] ,Toggle P1_28" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NOTP1[27] ,Toggle P1_27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " NOTP1[26] ,Toggle P1_26" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOTP1[25] ,Toggle P1_25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " NOTP1[24] ,Toggle P1_24" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NOTP1[23] ,Toggle P1_23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " NOTP1[22] ,Toggle P1_22" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTP1[21] ,Toggle P1_21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " NOTP1[20] ,Toggle P1_20" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTP1[19] ,Toggle P1_19" "No effect,Toggle"
|
|
sif (cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37")
|
|
bitfld.long 0x00 18. " NOTP1[18] ,Toggle P1_18" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTP1[17] ,Toggle P1_17" "No effect,Toggle"
|
|
endif
|
|
bitfld.long 0x00 16. " NOTP1[16] ,Toggle P1_16" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " NOTP1[15] ,Toggle P1_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP1[14] ,Toggle P1_14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTP1[13] ,Toggle P1_13" "No effect,Toggle"
|
|
endif
|
|
sif (cpu()=="LPC11E14"||cpu()=="LPC11E36"||cpu()=="LPC11E37"||cpu()=="LPC11A12"||cpu()=="LPC11A14"||cpu()=="LPC11U24/401"||cpu()=="LPC11U35/401"||cpu()=="LPC11U36/401"||cpu()=="LPC11U37/501"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
sif (cpu()!="LPC11A12"&&cpu()!="LPC11A14")
|
|
bitfld.long 0x00 12. " NOTP1[12] ,Toggle P1_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP1[11] ,Toggle P1_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP1[10] ,Toggle P1_10" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " NOTP1[9] ,Toggle P1_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP1[8] ,Toggle P1_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP1[7] ,Toggle P1_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP1[6] ,Toggle P1_6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTP1[5] ,Toggle P1_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP1[4] ,Toggle P1_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP1[3] ,Toggle P1_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP1[2] ,Toggle P1_2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTP1[1] ,Toggle P1_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP1[0] ,Toggle P1_0" "No effect,Toggle"
|
|
elif (cpu()=="LPC11E11")
|
|
bitfld.long 0x00 24. " NOTP1[24] ,Toggle P1_24" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " NOTP1[23] ,Toggle P1_23" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTP1[19] ,Toggle P1_19" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " NOTP1[5] ,Toggle P1_5" "No effect,Toggle"
|
|
elif (cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U23/301"&&cpu()!="LPC11U34/311"&&cpu()!="LPC11U34/421"&&cpu()!="LPC11U37/401")
|
|
bitfld.long 0x00 5. " NOTP1[5] ,Toggle P1_5" "No effect,Toggle"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
tree "Port 2"
|
|
group.byte 0x40++0x16
|
|
line.byte 0x0 "B64,GPIO port 2 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P2_0 " "0,1"
|
|
line.byte 0x1 "B65,GPIO port 2 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P2_1 " "0,1"
|
|
line.byte 0x2 "B66,GPIO port 2 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P2_2 " "0,1"
|
|
line.byte 0x3 "B67,GPIO port 2 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P2_3 " "0,1"
|
|
line.byte 0x4 "B68,GPIO port 2 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P2_4 " "0,1"
|
|
line.byte 0x5 "B69,GPIO port 2 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P2_5 " "0,1"
|
|
line.byte 0x6 "B70,GPIO port 2 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P2_6 " "0,1"
|
|
line.byte 0x7 "B71,GPIO port 2 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P2_7 " "0,1"
|
|
line.byte 0x8 "B72,GPIO port 2 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P2_8 " "0,1"
|
|
line.byte 0x9 "B73,GPIO port 2 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P2_9 " "0,1"
|
|
line.byte 0xA "B74,GPIO port 2 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P2_10" "0,1"
|
|
line.byte 0xB "B75,GPIO port 2 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P2_11" "0,1"
|
|
line.byte 0xC "B76,GPIO port 2 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P2_12" "0,1"
|
|
line.byte 0xD "B77,GPIO port 2 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P2_13" "0,1"
|
|
line.byte 0xE "B78,GPIO port 2 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P2_14" "0,1"
|
|
line.byte 0xF "B79,GPIO port 2 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P2_15" "0,1"
|
|
group.long 0x1100++0x43
|
|
line.long 0x0 "W64,GPIO port 2 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P2_0 "
|
|
line.long 0x4 "W65,GPIO port 2 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P2_1 "
|
|
line.long 0x8 "W66,GPIO port 2 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P2_2 "
|
|
line.long 0xC "W67,GPIO port 2 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P2_3 "
|
|
line.long 0x10 "W68,GPIO port 2 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P2_4 "
|
|
line.long 0x14 "W69,GPIO port 2 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P2_5 "
|
|
line.long 0x18 "W70,GPIO port 2 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P2_6 "
|
|
line.long 0x1C "W71,GPIO port 2 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P2_7 "
|
|
line.long 0x20 "W72,GPIO port 2 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P2_8 "
|
|
line.long 0x24 "W73,GPIO port 2 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P2_9 "
|
|
line.long 0x28 "W74,GPIO port 2 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P2_10"
|
|
line.long 0x2C "W75,GPIO port 2 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P2_11"
|
|
line.long 0x30 "W76,GPIO port 2 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P2_12"
|
|
line.long 0x34 "W77,GPIO port 2 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P2_13"
|
|
line.long 0x38 "W78,GPIO port 2 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P2_14"
|
|
line.long 0x3C "W79,GPIO port 2 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P2_15"
|
|
group.long 0x2008++0x3
|
|
line.long 0x00 "DIR2,GPIO direction port 2 register"
|
|
bitfld.long 0x00 15. " DIRP2[15] ,Pin direction for pin P2_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP2[14] ,Pin direction for pin P2_14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRP2[13] ,Pin direction for pin P2_13" "Input,Output"
|
|
bitfld.long 0x00 12. " DIRP2[12] ,Pin direction for pin P2_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP2[11] ,Pin direction for pin P2_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP2[10] ,Pin direction for pin P2_10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIRP2[9] ,Pin direction for pin P2_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP2[8] ,Pin direction for pin P2_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP2[7] ,Pin direction for pin P2_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP2[6] ,Pin direction for pin P2_6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DIRP2[5] ,Pin direction for pin P2_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP2[4] ,Pin direction for pin P2_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP2[3] ,Pin direction for pin P2_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP2[2] ,Pin direction for pin P2_2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIRP2[1] ,Pin direction for pin P2_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP2[0] ,Pin direction for pin P2_0" "Input,Output"
|
|
group.long 0x2088++0x3
|
|
line.long 0x0 "MASK2,GPIO mask port 2 register"
|
|
bitfld.long 0x00 15. " MASKP2[15] ,Mask for pin P2_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP2[14] ,Mask for pin P2_14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASKP2[13] ,Mask for pin P2_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASKP2[12] ,Mask for pin P2_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP2[11] ,Mask for pin P2_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP2[10] ,Mask for pin P2_10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MASKP2[9] ,Mask for pin P2_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP2[8] ,Mask for pin P2_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP2[7] ,Mask for pin P2_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP2[6] ,Mask for pin P2_6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MASKP2[5] ,Mask for pin P2_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP2[4] ,Mask for pin P2_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP2[3] ,Mask for pin P2_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP2[2] ,Mask for pin P2_2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASKP2[1] ,Mask for pin P2_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP2[0] ,Mask for pin P2_0" "Not masked,Masked"
|
|
group.long 0x2108++0x3
|
|
line.long 0x00 "PIN2,GPIO port 2 pin register"
|
|
bitfld.long 0x00 15. " PORT2[15] ,P2_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " PORT2[14] ,P2_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PORT2[13] ,P2_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " PORT2[12] ,P2_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT2[11] ,P2_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " PORT2[10] ,P2_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PORT2[9] ,P2_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " PORT2[8] ,P2_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT2[7] ,P2_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " PORT2[6] ,P2_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PORT2[5] ,P2_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " PORT2[4] ,P2_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT2[3] ,P2_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " PORT2[2] ,P2_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PORT2[1] ,P2_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " PORT2[0] ,P2_0 pin state" "Low,High"
|
|
group.long 0x2188++0x3
|
|
line.long 0x00 "MPIN2,GPIO masked port 2 pin register"
|
|
bitfld.long 0x00 15. " MPORTP2[15] ,Masked P2_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " MPORTP2[14] ,Masked P2_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MPORTP2[13] ,Masked P2_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " MPORTP2[12] ,Masked P2_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP2[11] ,Masked P2_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " MPORTP2[10] ,Masked P2_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPORTP2[9] ,Masked P2_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " MPORTP2[8] ,Masked P2_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP2[7] ,Masked P2_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " MPORTP2[6] ,Masked P2_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPORTP2[5] ,Masked P2_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " MPORTP2[4] ,Masked P2_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP2[3] ,Masked P2_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " MPORTP2[2] ,Masked P2_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MPORTP2[1] ,Masked P2_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " MPORTP2[0] ,Masked P2_0 pin state" "Low,High"
|
|
group.long 0x2208++0x3
|
|
line.long 0x00 "SET2,GPIO set port 2 register"
|
|
bitfld.long 0x00 15. " SETP2[15] ,State/Set P2_15" "Low,High"
|
|
bitfld.long 0x00 14. " SETP2[14] ,State/Set P2_14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SETP2[13] ,State/Set P2_13" "Low,High"
|
|
bitfld.long 0x00 12. " SETP2[12] ,State/Set P2_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETP2[11] ,State/Set P2_11" "Low,High"
|
|
bitfld.long 0x00 10. " SETP2[10] ,State/Set P2_10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SETP2[9] ,State/Set P2_9" "Low,High"
|
|
bitfld.long 0x00 8. " SETP2[8] ,State/Set P2_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SETP2[7] ,State/Set P2_7" "Low,High"
|
|
bitfld.long 0x00 6. " SETP2[6] ,State/Set P2_6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETP2[5] ,State/Set P2_5" "Low,High"
|
|
bitfld.long 0x00 4. " SETP2[4] ,State/Set P2_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SETP2[3] ,State/Set P2_3" "Low,High"
|
|
bitfld.long 0x00 2. " SETP2[2] ,State/Set P2_2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SETP2[1] ,State/Set P2_1" "Low,High"
|
|
bitfld.long 0x00 0. " SETP2[0] ,State/Set P2_0" "Low,High"
|
|
wgroup.long 0x2288++0x3
|
|
line.long 0x00 "CLR2,GPIO clear port 2 register"
|
|
bitfld.long 0x00 15. " CLRP2[15] ,Clear P2_15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLRP2[14] ,Clear P2_14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLRP2[13] ,Clear P2_13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLRP2[12] ,Clear P2_12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLRP2[11] ,Clear P2_11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLRP2[10] ,Clear P2_10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLRP2[9] ,Clear P2_9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLRP2[8] ,Clear P2_8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLRP2[7] ,Clear P2_7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLRP2[6] ,Clear P2_6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLRP2[5] ,Clear P2_5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLRP2[4] ,Clear P2_4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLRP2[3] ,Clear P2_3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLRP2[2] ,Clear P2_2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLRP2[1] ,Clear P2_1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLRP2[0] ,Clear P2_0" "No effect,Clear"
|
|
wgroup.long 0x2308++0x3
|
|
line.long 0x00 "NOT2,GPIO toggle port 2 register"
|
|
bitfld.long 0x00 15. " NOTP2[15] ,Toggle P2_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP2[14] ,Toggle P2_14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTP2[13] ,Toggle P2_13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " NOTP2[12] ,Toggle P2_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP2[11] ,Toggle P2_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP2[10] ,Toggle P2_10" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTP2[9] ,Toggle P2_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP2[8] ,Toggle P2_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP2[7] ,Toggle P2_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP2[6] ,Toggle P2_6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTP2[5] ,Toggle P2_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP2[4] ,Toggle P2_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP2[3] ,Toggle P2_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP2[2] ,Toggle P2_2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTP2[1] ,Toggle P2_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP2[0] ,Toggle P2_0" "No effect,Toggle"
|
|
tree.end
|
|
tree "Port 3"
|
|
group.byte 0x60++0x16
|
|
line.byte 0x0 "B96,GPIO port 3 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P3_0 " "0,1"
|
|
line.byte 0x1 "B97,GPIO port 3 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P3_1 " "0,1"
|
|
line.byte 0x2 "B98,GPIO port 3 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P3_2 " "0,1"
|
|
line.byte 0x3 "B99,GPIO port 3 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P3_3 " "0,1"
|
|
line.byte 0x4 "B100,GPIO port 3 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P3_4 " "0,1"
|
|
line.byte 0x5 "B101,GPIO port 3 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P3_5 " "0,1"
|
|
line.byte 0x6 "B102,GPIO port 3 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P3_6 " "0,1"
|
|
line.byte 0x7 "B103,GPIO port 3 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P3_7 " "0,1"
|
|
line.byte 0x8 "B104,GPIO port 3 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P3_8 " "0,1"
|
|
line.byte 0x9 "B105,GPIO port 3 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P3_9 " "0,1"
|
|
line.byte 0xA "B106,GPIO port 3 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P3_10" "0,1"
|
|
line.byte 0xB "B107,GPIO port 3 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P3_11" "0,1"
|
|
line.byte 0xC "B108,GPIO port 3 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P3_12" "0,1"
|
|
line.byte 0xD "B109,GPIO port 3 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P3_13" "0,1"
|
|
line.byte 0xE "B110,GPIO port 3 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P3_14" "0,1"
|
|
line.byte 0xF "B111,GPIO port 3 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P3_15" "0,1"
|
|
group.byte 0x1180++0x43
|
|
line.long 0x0 "W96,GPIO port 3 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P3_0 "
|
|
line.long 0x4 "W97,GPIO port 3 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P3_1 "
|
|
line.long 0x8 "W98,GPIO port 3 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P3_2 "
|
|
line.long 0xC "W99,GPIO port 3 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P3_3 "
|
|
line.long 0x10 "W100,GPIO port 3 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P3_4 "
|
|
line.long 0x14 "W101,GPIO port 3 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P3_5 "
|
|
line.long 0x18 "W102,GPIO port 3 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P3_6 "
|
|
line.long 0x1C "W103,GPIO port 3 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P3_7 "
|
|
line.long 0x20 "W104,GPIO port 3 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P3_8 "
|
|
line.long 0x24 "W105,GPIO port 3 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P3_9 "
|
|
line.long 0x28 "W106,GPIO port 3 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P3_10"
|
|
line.long 0x2C "W107,GPIO port 3 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P3_11"
|
|
line.long 0x30 "W108,GPIO port 3 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P3_12"
|
|
line.long 0x34 "W109,GPIO port 3 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P3_13"
|
|
line.long 0x38 "W110,GPIO port 3 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P3_14"
|
|
line.long 0x3C "W111,GPIO port 3 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P3_15"
|
|
group.long 0x200c++0x3
|
|
line.long 0x00 "DIR3,GPIO direction port 3 register"
|
|
bitfld.long 0x00 15. " DIRP3[15] ,Pin direction for pin P3_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP3[14] ,Pin direction for pin P3_14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRP3[13] ,Pin direction for pin P3_13" "Input,Output"
|
|
bitfld.long 0x00 12. " DIRP3[12] ,Pin direction for pin P3_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP3[11] ,Pin direction for pin P3_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP3[10] ,Pin direction for pin P3_10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIRP3[9] ,Pin direction for pin P3_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP3[8] ,Pin direction for pin P3_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP3[7] ,Pin direction for pin P3_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP3[6] ,Pin direction for pin P3_6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DIRP3[5] ,Pin direction for pin P3_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP3[4] ,Pin direction for pin P3_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP3[3] ,Pin direction for pin P3_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP3[2] ,Pin direction for pin P3_2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIRP3[1] ,Pin direction for pin P3_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP3[0] ,Pin direction for pin P3_0" "Input,Output"
|
|
group.long 0x208c++0x3
|
|
line.long 0x00 "MASK3,GPIO mask port 3 register"
|
|
bitfld.long 0x00 15. " MASKP3[15] ,Mask for pin P3_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP3[14] ,Mask for pin P3_14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASKP3[13] ,Mask for pin P3_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASKP3[12] ,Mask for pin P3_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP3[11] ,Mask for pin P3_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP3[10] ,Mask for pin P3_10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MASKP3[9] ,Mask for pin P3_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP3[8] ,Mask for pin P3_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP3[7] ,Mask for pin P3_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP3[6] ,Mask for pin P3_6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MASKP3[5] ,Mask for pin P3_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP3[4] ,Mask for pin P3_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP3[3] ,Mask for pin P3_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP3[2] ,Mask for pin P3_2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASKP3[1] ,Mask for pin P3_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP3[0] ,Mask for pin P3_0" "Not masked,Masked"
|
|
group.long 0x210c++0x3
|
|
line.long 0x00 "PIN3,GPIO port 3 pin register"
|
|
bitfld.long 0x00 15. " PORT3[15] ,P3_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " PORT3[14] ,P3_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PORT3[13] ,P3_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " PORT3[12] ,P3_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT3[11] ,P3_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " PORT3[10] ,P3_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PORT3[9] ,P3_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " PORT3[8] ,P3_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT3[7] ,P3_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " PORT3[6] ,P3_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PORT3[5] ,P3_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " PORT3[4] ,P3_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT3[3] ,P3_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " PORT3[2] ,P3_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PORT3[1] ,P3_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " PORT3[0] ,P3_0 pin state" "Low,High"
|
|
group.long 0x218c++0x3
|
|
line.long 0x00 "MPIN3,GPIO masked port 3 pin register"
|
|
bitfld.long 0x00 15. " MPORTP3[15] ,Masked P3_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " MPORTP3[14] ,Masked P3_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MPORTP3[13] ,Masked P3_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " MPORTP3[12] ,Masked P3_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP3[11] ,Masked P3_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " MPORTP3[10] ,Masked P3_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPORTP3[9] ,Masked P3_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " MPORTP3[8] ,Masked P3_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP3[7] ,Masked P3_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " MPORTP3[6] ,Masked P3_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPORTP3[5] ,Masked P3_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " MPORTP3[4] ,Masked P3_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP3[3] ,Masked P3_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " MPORTP3[2] ,Masked P3_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MPORTP3[1] ,Masked P3_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " MPORTP3[0] ,Masked P3_0 pin state" "Low,High"
|
|
group.long 0x220c++0x3
|
|
line.long 0x00 "SET3,GPIO set port 3 register"
|
|
bitfld.long 0x00 15. " SETP3[15] ,State/Set P3_15" "Low,High"
|
|
bitfld.long 0x00 14. " SETP3[14] ,State/Set P3_14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SETP3[13] ,State/Set P3_13" "Low,High"
|
|
bitfld.long 0x00 12. " SETP3[12] ,State/Set P3_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETP3[11] ,State/Set P3_11" "Low,High"
|
|
bitfld.long 0x00 10. " SETP3[10] ,State/Set P3_10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SETP3[9] ,State/Set P3_9" "Low,High"
|
|
bitfld.long 0x00 8. " SETP3[8] ,State/Set P3_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SETP3[7] ,State/Set P3_7" "Low,High"
|
|
bitfld.long 0x00 6. " SETP3[6] ,State/Set P3_6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETP3[5] ,State/Set P3_5" "Low,High"
|
|
bitfld.long 0x00 4. " SETP3[4] ,State/Set P3_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SETP3[3] ,State/Set P3_3" "Low,High"
|
|
bitfld.long 0x00 2. " SETP3[2] ,State/Set P3_2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SETP3[1] ,State/Set P3_1" "Low,High"
|
|
bitfld.long 0x00 0. " SETP3[0] ,State/Set P3_0" "Low,High"
|
|
wgroup.long 0x228c++0x3
|
|
line.long 0x00 "CLR3,GPIO clear port 3 register"
|
|
bitfld.long 0x00 15. " CLRP3[15] ,Clear P3_15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLRP3[14] ,Clear P3_14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLRP3[13] ,Clear P3_13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLRP3[12] ,Clear P3_12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLRP3[11] ,Clear P3_11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLRP3[10] ,Clear P3_10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLRP3[9] ,Clear P3_9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLRP3[8] ,Clear P3_8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLRP3[7] ,Clear P3_7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLRP3[6] ,Clear P3_6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLRP3[5] ,Clear P3_5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLRP3[4] ,Clear P3_4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLRP3[3] ,Clear P3_3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLRP3[2] ,Clear P3_2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLRP3[1] ,Clear P3_1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLRP3[0] ,Clear P3_0" "No effect,Clear"
|
|
wgroup.long 0x230c++0x3
|
|
line.long 0x00 "NOT3,GPIO toggle port 3 register"
|
|
bitfld.long 0x00 15. " NOTP3[15] ,Toggle P3_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP3[14] ,Toggle P3_14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTP3[13] ,Toggle P3_13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " NOTP3[12] ,Toggle P3_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP3[11] ,Toggle P3_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP3[10] ,Toggle P3_10" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTP3[9] ,Toggle P3_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP3[8] ,Toggle P3_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP3[7] ,Toggle P3_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP3[6] ,Toggle P3_6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTP3[5] ,Toggle P3_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP3[4] ,Toggle P3_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP3[3] ,Toggle P3_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP3[2] ,Toggle P3_2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTP3[1] ,Toggle P3_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP3[0] ,Toggle P3_0" "No effect,Toggle"
|
|
tree.end
|
|
tree "Port 4"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
group.byte 0x8b++0x1
|
|
line.byte 0x00 "B139,GPIO port 4 byte pin 11 register"
|
|
bitfld.byte 0x0 0. " PBYTE_11 ,State of the pin P4_11" "0,1"
|
|
else
|
|
group.byte 0x80++0x16
|
|
line.byte 0x0 "B128,GPIO port 4 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P4_0 " "0,1"
|
|
line.byte 0x1 "B129,GPIO port 4 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P4_1 " "0,1"
|
|
line.byte 0x2 "B130,GPIO port 4 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P4_2 " "0,1"
|
|
line.byte 0x3 "B131,GPIO port 4 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P4_3 " "0,1"
|
|
line.byte 0x4 "B132,GPIO port 4 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P4_4 " "0,1"
|
|
line.byte 0x5 "B133,GPIO port 4 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P4_5 " "0,1"
|
|
line.byte 0x6 "B134,GPIO port 4 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P4_6 " "0,1"
|
|
line.byte 0x7 "B135,GPIO port 4 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P4_7 " "0,1"
|
|
line.byte 0x8 "B136,GPIO port 4 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P4_8 " "0,1"
|
|
line.byte 0x9 "B137,GPIO port 4 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P4_9 " "0,1"
|
|
line.byte 0xA "B138,GPIO port 4 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P4_10" "0,1"
|
|
line.byte 0xB "B139,GPIO port 4 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P4_11" "0,1"
|
|
line.byte 0xC "B140,GPIO port 4 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P4_12" "0,1"
|
|
line.byte 0xD "B141,GPIO port 4 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P4_13" "0,1"
|
|
line.byte 0xE "B142,GPIO port 4 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P4_14" "0,1"
|
|
line.byte 0xF "B143,GPIO port 4 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P4_15" "0,1"
|
|
endif
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
group.byte 0x120B++0x3
|
|
line.long 0x00 "W139,GPIO port 4 word pin 11 register"
|
|
hexmask.long 0x00 0.--31. 1. " PWORD_11 ,State of the pin P4_11"
|
|
else
|
|
group.byte 0x1200++0x43
|
|
line.long 0x0 "W128,GPIO port 4 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P4_0 "
|
|
line.long 0x4 "W129,GPIO port 4 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P4_1 "
|
|
line.long 0x8 "W130,GPIO port 4 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P4_2 "
|
|
line.long 0xC "W131,GPIO port 4 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P4_3 "
|
|
line.long 0x10 "W132,GPIO port 4 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P4_4 "
|
|
line.long 0x14 "W133,GPIO port 4 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P4_5 "
|
|
line.long 0x18 "W134,GPIO port 4 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P4_6 "
|
|
line.long 0x1C "W135,GPIO port 4 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P4_7 "
|
|
line.long 0x20 "W136,GPIO port 4 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P4_8 "
|
|
line.long 0x24 "W137,GPIO port 4 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P4_9 "
|
|
line.long 0x28 "W138,GPIO port 4 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P4_10"
|
|
line.long 0x2C "W139,GPIO port 4 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P4_11"
|
|
line.long 0x30 "W140,GPIO port 4 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P4_12"
|
|
line.long 0x34 "W141,GPIO port 4 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P4_13"
|
|
line.long 0x38 "W142,GPIO port 4 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P4_14"
|
|
line.long 0x3C "W143,GPIO port 4 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P4_15"
|
|
endif
|
|
group.long 0x2010++0x3
|
|
line.long 0x00 "DIR4,GPIO direction port 4 register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " DIRP4[11] ,Pin direction for pin P4_11" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 15. " DIRP4[15] ,Pin direction for pin P4_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP4[14] ,Pin direction for pin P4_14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRP4[13] ,Pin direction for pin P4_13" "Input,Output"
|
|
bitfld.long 0x00 12. " DIRP4[12] ,Pin direction for pin P4_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP4[11] ,Pin direction for pin P4_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP4[10] ,Pin direction for pin P4_10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIRP4[9] ,Pin direction for pin P4_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP4[8] ,Pin direction for pin P4_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP4[7] ,Pin direction for pin P4_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP4[6] ,Pin direction for pin P4_6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DIRP4[5] ,Pin direction for pin P4_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP4[4] ,Pin direction for pin P4_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP4[3] ,Pin direction for pin P4_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP4[2] ,Pin direction for pin P4_2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIRP4[1] ,Pin direction for pin P4_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP4[0] ,Pin direction for pin P4_0" "Input,Output"
|
|
endif
|
|
group.long 0x2090++0x3
|
|
line.long 0x00 "MASK4,GPIO mask port 4 register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " MASKP4[11] ,Mask for pin P4_11" "Not masked,Masked"
|
|
else
|
|
bitfld.long 0x00 15. " MASKP4[15] ,Mask for pin P4_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP4[14] ,Mask for pin P4_14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASKP4[13] ,Mask for pin P4_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASKP4[12] ,Mask for pin P4_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP4[11] ,Mask for pin P4_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP4[10] ,Mask for pin P4_10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MASKP4[9] ,Mask for pin P4_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP4[8] ,Mask for pin P4_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP4[7] ,Mask for pin P4_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP4[6] ,Mask for pin P4_6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MASKP4[5] ,Mask for pin P4_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP4[4] ,Mask for pin P4_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP4[3] ,Mask for pin P4_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP4[2] ,Mask for pin P4_2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASKP4[1] ,Mask for pin P4_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP4[0] ,Mask for pin P4_0" "Not masked,Masked"
|
|
endif
|
|
group.long 0x2110++0x3
|
|
line.long 0x00 "PIN4,GPIO port 4 pin register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " PORT4[11] ,P4_11 pin state" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " PORT4[15] ,P4_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " PORT4[14] ,P4_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PORT4[13] ,P4_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " PORT4[12] ,P4_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT4[11] ,P4_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " PORT4[10] ,P4_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PORT4[9] ,P4_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " PORT4[8] ,P4_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT4[7] ,P4_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " PORT4[6] ,P4_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PORT4[5] ,P4_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " PORT4[4] ,P4_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT4[3] ,P4_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " PORT4[2] ,P4_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PORT4[1] ,P4_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " PORT4[0] ,P4_0 pin state" "Low,High"
|
|
endif
|
|
group.long 0x2190++0x3
|
|
line.long 0x00 "MPIN4,GPIO masked port 4 pin register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")
|
|
bitfld.long 0x00 11. " MPORTP4[11] ,Masked P4_11 pin state" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " MPORTP4[15] ,Masked P4_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " MPORTP4[14] ,Masked P4_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MPORTP4[13] ,Masked P4_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " MPORTP4[12] ,Masked P4_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP4[11] ,Masked P4_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " MPORTP4[10] ,Masked P4_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPORTP4[9] ,Masked P4_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " MPORTP4[8] ,Masked P4_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP4[7] ,Masked P4_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " MPORTP4[6] ,Masked P4_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPORTP4[5] ,Masked P4_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " MPORTP4[4] ,Masked P4_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP4[3] ,Masked P4_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " MPORTP4[2] ,Masked P4_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MPORTP4[1] ,Masked P4_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " MPORTP4[0] ,Masked P4_0 pin state" "Low,High"
|
|
endif
|
|
group.long 0x2210++0x3
|
|
line.long 0x00 "SET4,GPIO set port 4 register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " SETP4[11] ,State/Set P4_11" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " SETP4[15] ,State/Set P4_15" "Low,High"
|
|
bitfld.long 0x00 14. " SETP4[14] ,State/Set P4_14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SETP4[13] ,State/Set P4_13" "Low,High"
|
|
bitfld.long 0x00 12. " SETP4[12] ,State/Set P4_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETP4[11] ,State/Set P4_11" "Low,High"
|
|
bitfld.long 0x00 10. " SETP4[10] ,State/Set P4_10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SETP4[9] ,State/Set P4_9" "Low,High"
|
|
bitfld.long 0x00 8. " SETP4[8] ,State/Set P4_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SETP4[7] ,State/Set P4_7" "Low,High"
|
|
bitfld.long 0x00 6. " SETP4[6] ,State/Set P4_6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETP4[5] ,State/Set P4_5" "Low,High"
|
|
bitfld.long 0x00 4. " SETP4[4] ,State/Set P4_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SETP4[3] ,State/Set P4_3" "Low,High"
|
|
bitfld.long 0x00 2. " SETP4[2] ,State/Set P4_2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SETP4[1] ,State/Set P4_1" "Low,High"
|
|
bitfld.long 0x00 0. " SETP4[0] ,State/Set P4_0" "Low,High"
|
|
endif
|
|
wgroup.long 0x2290++0x3
|
|
line.long 0x00 "CLR4,GPIO clear port 4 register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " CLRP4[11] ,Clear P4_11" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 15. " CLRP4[15] ,Clear P4_15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLRP4[14] ,Clear P4_14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLRP4[13] ,Clear P4_13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLRP4[12] ,Clear P4_12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLRP4[11] ,Clear P4_11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLRP4[10] ,Clear P4_10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLRP4[9] ,Clear P4_9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLRP4[8] ,Clear P4_8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLRP4[7] ,Clear P4_7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLRP4[6] ,Clear P4_6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLRP4[5] ,Clear P4_5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLRP4[4] ,Clear P4_4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLRP4[3] ,Clear P4_3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLRP4[2] ,Clear P4_2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLRP4[1] ,Clear P4_1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLRP4[0] ,Clear P4_0" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x2310++0x3
|
|
line.long 0x00 "NOT4,GPIO toggle port 4 register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 11. " NOTP4[11] ,Toggle P4_11" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 15. " NOTP4[15] ,Toggle P4_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP4[14] ,Toggle P4_14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTP4[13] ,Toggle P4_13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " NOTP4[12] ,Toggle P4_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP4[11] ,Toggle P4_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP4[10] ,Toggle P4_10" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTP4[9] ,Toggle P4_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP4[8] ,Toggle P4_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP4[7] ,Toggle P4_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP4[6] ,Toggle P4_6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTP4[5] ,Toggle P4_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP4[4] ,Toggle P4_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP4[3] ,Toggle P4_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP4[2] ,Toggle P4_2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTP4[1] ,Toggle P4_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP4[0] ,Toggle P4_0" "No effect,Toggle"
|
|
endif
|
|
tree.end
|
|
tree "Port 5"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
group.byte 0xa0++0x16
|
|
line.byte 0x00 "B160,GPIO port 5 byte pin 0 register"
|
|
bitfld.byte 0x00 0. " PBYTE_0 ,State of the pin P5_0" "0,1"
|
|
line.byte 0x01 "B161,GPIO port 5 byte pin 1 register"
|
|
bitfld.byte 0x01 0. " PBYTE_1 ,State of the pin P5_1" "0,1"
|
|
line.byte 0x02 "B162,GPIO port 5 byte pin 2 register"
|
|
bitfld.byte 0x02 0. " PBYTE_2 ,State of the pin P5_2" "0,1"
|
|
line.byte 0x03 "B163,GPIO port 5 byte pin 3 register"
|
|
bitfld.byte 0x03 0. " PBYTE_3 ,State of the pin P5_3" "0,1"
|
|
line.byte 0x04 "B164,GPIO port 5 byte pin 4 register"
|
|
bitfld.byte 0x04 0. " PBYTE_4 ,State of the pin P5_4" "0,1"
|
|
line.byte 0x05 "B165,GPIO port 5 byte pin 5 register"
|
|
bitfld.byte 0x05 0. " PBYTE_5 ,State of the pin P5_5" "0,1"
|
|
line.byte 0x06 "B166,GPIO port 5 byte pin 6 register"
|
|
bitfld.byte 0x06 0. " PBYTE_6 ,State of the pin P5_6" "0,1"
|
|
line.byte 0x07 "B167,GPIO port 5 byte pin 7 register"
|
|
bitfld.byte 0x07 0. " PBYTE_7 ,State of the pin P5_7" "0,1"
|
|
line.byte 0x08 "B168,GPIO port 5 byte pin 8 register"
|
|
bitfld.byte 0x08 0. " PBYTE_8 ,State of the pin P5_8" "0,1"
|
|
line.byte 0x09 "B169,GPIO port 5 byte pin 9 register"
|
|
bitfld.byte 0x09 0. " PBYTE_9 ,State of the pin P5_9" "0,1"
|
|
line.byte 0x10 "B170,GPIO port 5 byte pin 10 register"
|
|
bitfld.byte 0x10 0. " PBYTE_10 ,State of the pin P5_10" "0,1"
|
|
line.byte 0x11 "B171,GPIO port 5 byte pin 11 register"
|
|
bitfld.byte 0x11 0. " PBYTE_11 ,State of the pin P5_11" "0,1"
|
|
line.byte 0x12 "B172,GPIO port 5 byte pin 12 register"
|
|
bitfld.byte 0x12 0. " PBYTE_12 ,State of the pin P5_12" "0,1"
|
|
line.byte 0x13 "B173,GPIO port 5 byte pin 13 register"
|
|
bitfld.byte 0x13 0. " PBYTE_13 ,State of the pin P5_13" "0,1"
|
|
line.byte 0x14 "B174,GPIO port 5 byte pin 14 register"
|
|
bitfld.byte 0x14 0. " PBYTE_14 ,State of the pin P5_14" "0,1"
|
|
line.byte 0x15 "B175,GPIO port 5 byte pin 15 register"
|
|
bitfld.byte 0x15 0. " PBYTE_15 ,State of the pin P5_15" "0,1"
|
|
line.byte 0x16 "B176,GPIO port 5 byte pin 16 register"
|
|
bitfld.byte 0x16 0. " PBYTE_16 ,State of the pin P5_16" "0,1"
|
|
group.byte 0xb8++0x1
|
|
line.byte 0x00 "B178,GPIO port 5 byte pin 18 register"
|
|
bitfld.byte 0x00 0. " PBYTE_18 ,State of the pin P5_18" "0,1"
|
|
else
|
|
group.byte 0xa0++0x1C
|
|
line.byte 0x00 "B160,GPIO port 5 byte pin 0 register"
|
|
bitfld.byte 0x00 0. " PBYTE_0 ,State of the pin P5_0" "0,1"
|
|
line.byte 0x01 "B161,GPIO port 5 byte pin 1 register"
|
|
bitfld.byte 0x01 0. " PBYTE_1 ,State of the pin P5_1" "0,1"
|
|
line.byte 0x02 "B162,GPIO port 5 byte pin 2 register"
|
|
bitfld.byte 0x02 0. " PBYTE_2 ,State of the pin P5_2" "0,1"
|
|
line.byte 0x03 "B163,GPIO port 5 byte pin 3 register"
|
|
bitfld.byte 0x03 0. " PBYTE_3 ,State of the pin P5_3" "0,1"
|
|
line.byte 0x04 "B164,GPIO port 5 byte pin 4 register"
|
|
bitfld.byte 0x04 0. " PBYTE_4 ,State of the pin P5_4" "0,1"
|
|
line.byte 0x05 "B165,GPIO port 5 byte pin 5 register"
|
|
bitfld.byte 0x05 0. " PBYTE_5 ,State of the pin P5_5" "0,1"
|
|
line.byte 0x06 "B166,GPIO port 5 byte pin 6 register"
|
|
bitfld.byte 0x06 0. " PBYTE_6 ,State of the pin P5_6" "0,1"
|
|
line.byte 0x07 "B167,GPIO port 5 byte pin 7 register"
|
|
bitfld.byte 0x07 0. " PBYTE_7 ,State of the pin P5_7" "0,1"
|
|
line.byte 0x08 "B168,GPIO port 5 byte pin 8 register"
|
|
bitfld.byte 0x08 0. " PBYTE_8 ,State of the pin P5_8" "0,1"
|
|
line.byte 0x0a "B169,GPIO port 5 byte pin 9 register"
|
|
bitfld.byte 0x0a 0. " PBYTE_9 ,State of the pin P5_9" "0,1"
|
|
line.byte 0xb "B170,GPIO port 5 byte pin 10 register"
|
|
bitfld.byte 0xb 0. " PBYTE_10 ,State of the pin P5_10" "0,1"
|
|
line.byte 0xc "B171,GPIO port 5 byte pin 11 register"
|
|
bitfld.byte 0xc 0. " PBYTE_11 ,State of the pin P5_11" "0,1"
|
|
line.byte 0xd "B172,GPIO port 5 byte pin 12 register"
|
|
bitfld.byte 0xd 0. " PBYTE_12 ,State of the pin P5_12" "0,1"
|
|
line.byte 0xe "B173,GPIO port 5 byte pin 13 register"
|
|
bitfld.byte 0xe 0. " PBYTE_13 ,State of the pin P5_13" "0,1"
|
|
line.byte 0xf "B174,GPIO port 5 byte pin 14 register"
|
|
bitfld.byte 0xf 0. " PBYTE_14 ,State of the pin P5_14" "0,1"
|
|
line.byte 0x10 "B175,GPIO port 5 byte pin 15 register"
|
|
bitfld.byte 0x10 0. " PBYTE_15 ,State of the pin P5_15" "0,1"
|
|
line.byte 0x11 "B176,GPIO port 5 byte pin 16 register"
|
|
bitfld.byte 0x11 0. " PBYTE_16 ,State of the pin P5_16" "0,1"
|
|
line.byte 0x12 "B177,GPIO port 5 byte pin 17 register"
|
|
bitfld.byte 0x12 0. " PBYTE_17 ,State of the pin P5_17" "0,1"
|
|
line.byte 0x13 "B178,GPIO port 5 byte pin 18 register"
|
|
bitfld.byte 0x13 0. " PBYTE_18 ,State of the pin P5_18" "0,1"
|
|
line.byte 0x14 "B179,GPIO port 5 byte pin 19 register"
|
|
bitfld.byte 0x14 0. " PBYTE_19 ,State of the pin P5_19" "0,1"
|
|
line.byte 0x15 "B180,GPIO port 5 byte pin 20 register"
|
|
bitfld.byte 0x15 0. " PBYTE_20 ,State of the pin P5_20" "0,1"
|
|
line.byte 0x16 "B181,GPIO port 5 byte pin 21 register"
|
|
bitfld.byte 0x16 0. " PBYTE_21 ,State of the pin P5_21" "0,1"
|
|
line.byte 0x17 "B182,GPIO port 5 byte pin 22 register"
|
|
bitfld.byte 0x17 0. " PBYTE_22 ,State of the pin P5_22" "0,1"
|
|
line.byte 0x18 "B183,GPIO port 5 byte pin 23 register"
|
|
bitfld.byte 0x18 0. " PBYTE_23 ,State of the pin P5_23" "0,1"
|
|
line.byte 0x19 "B184,GPIO port 5 byte pin 24 register"
|
|
bitfld.byte 0x19 0. " PBYTE_24 ,State of the pin P5_24" "0,1"
|
|
line.byte 0x1a "B185,GPIO port 5 byte pin 25 register"
|
|
bitfld.byte 0x1a 0. " PBYTE_25 ,State of the pin P5_25" "0,1"
|
|
line.byte 0x1b "B185,GPIO port 5 byte pin 25 register"
|
|
bitfld.byte 0x1b 0. " PBYTE_25 ,State of the pin P5_25" "0,1"
|
|
line.byte 0x1c "B186,GPIO port 5 byte pin 26 register"
|
|
bitfld.byte 0x1c 0. " PBYTE_26 ,State of the pin P5_26" "0,1"
|
|
endif
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
group.byte 0x1280++0x43
|
|
line.byte 0x00 "W160,GPIO port 5 word pin 0 register"
|
|
bitfld.byte 0x00 0. " PWORD_0 ,State of the pin P5_0" "0,1"
|
|
line.byte 0x04 "W161,GPIO port 5 word pin 1 register"
|
|
bitfld.byte 0x04 0. " PWORD_1 ,State of the pin P5_1" "0,1"
|
|
line.byte 0x08 "W162,GPIO port 5 word pin 2 register"
|
|
bitfld.byte 0x08 0. " PWORD_2 ,State of the pin P5_2" "0,1"
|
|
line.byte 0x0c "W163,GPIO port 5 word pin 3 register"
|
|
bitfld.byte 0x0c 0. " PWORD_3 ,State of the pin P5_3" "0,1"
|
|
line.byte 0x10 "W164,GPIO port 5 word pin 4 register"
|
|
bitfld.byte 0x10 0. " PWORD_4 ,State of the pin P5_4" "0,1"
|
|
line.byte 0x14 "W165,GPIO port 5 word pin 5 register"
|
|
bitfld.byte 0x14 0. " PWORD_5 ,State of the pin P5_5" "0,1"
|
|
line.byte 0x18 "W166,GPIO port 5 word pin 6 register"
|
|
bitfld.byte 0x18 0. " PWORD_6 ,State of the pin P5_6" "0,1"
|
|
line.byte 0x1c "W167,GPIO port 5 word pin 7 register"
|
|
bitfld.byte 0x1c 0. " PWORD_7 ,State of the pin P5_7" "0,1"
|
|
line.byte 0x20 "W168,GPIO port 5 word pin 8 register"
|
|
bitfld.byte 0x20 0. " PWORD_8 ,State of the pin P5_8" "0,1"
|
|
line.byte 0x24 "W169,GPIO port 5 word pin 9 register"
|
|
bitfld.byte 0x24 0. " PWORD_9 ,State of the pin P5_9" "0,1"
|
|
line.byte 0x28 "W170,GPIO port 5 word pin 10 register"
|
|
bitfld.byte 0x28 0. " PWORD_10 ,State of the pin P5_10" "0,1"
|
|
line.byte 0x2c "W171,GPIO port 5 word pin 11 register"
|
|
bitfld.byte 0x2c 0. " PWORD_11 ,State of the pin P5_11" "0,1"
|
|
line.byte 0x30 "W172,GPIO port 5 word pin 12 register"
|
|
bitfld.byte 0x30 0. " PWORD_12 ,State of the pin P5_12" "0,1"
|
|
line.byte 0x34 "W173,GPIO port 5 word pin 13 register"
|
|
bitfld.byte 0x34 0. " PWORD_13 ,State of the pin P5_13" "0,1"
|
|
line.byte 0x38 "W174,GPIO port 5 word pin 14 register"
|
|
bitfld.byte 0x38 0. " PWORD_14 ,State of the pin P5_14" "0,1"
|
|
line.byte 0x3c "W175,GPIO port 5 word pin 15 register"
|
|
bitfld.byte 0x3c 0. " PWORD_15 ,State of the pin P5_15" "0,1"
|
|
line.byte 0x40 "W176,GPIO port 5 word pin 16 register"
|
|
bitfld.byte 0x40 0. " PWORD_16 ,State of the pin P5_16" "0,1"
|
|
group.byte 0x12a8++0x3
|
|
line.byte 0x00 "W178,GPIO port 5 word pin 18 register"
|
|
bitfld.byte 0x00 0. " PWORD_18 ,State of the pin P5_18" "0,1"
|
|
else
|
|
group.byte 0x1280++0x6f
|
|
line.byte 0x00 "W160,GPIO port 5 word pin 0 register"
|
|
bitfld.byte 0x00 0. " PWORD_0 ,State of the pin P5_0" "0,1"
|
|
line.byte 0x04 "W161,GPIO port 5 word pin 1 register"
|
|
bitfld.byte 0x04 0. " PWORD_1 ,State of the pin P5_1" "0,1"
|
|
line.byte 0x08 "W162,GPIO port 5 word pin 2 register"
|
|
bitfld.byte 0x08 0. " PWORD_2 ,State of the pin P5_2" "0,1"
|
|
line.byte 0x0c "W163,GPIO port 5 word pin 3 register"
|
|
bitfld.byte 0x0c 0. " PWORD_3 ,State of the pin P5_3" "0,1"
|
|
line.byte 0x10 "W164,GPIO port 5 word pin 4 register"
|
|
bitfld.byte 0x10 0. " PWORD_4 ,State of the pin P5_4" "0,1"
|
|
line.byte 0x14 "W165,GPIO port 5 word pin 5 register"
|
|
bitfld.byte 0x14 0. " PWORD_5 ,State of the pin P5_5" "0,1"
|
|
line.byte 0x18 "W166,GPIO port 5 word pin 6 register"
|
|
bitfld.byte 0x18 0. " PWORD_6 ,State of the pin P5_6" "0,1"
|
|
line.byte 0x1c "W167,GPIO port 5 word pin 7 register"
|
|
bitfld.byte 0x1c 0. " PWORD_7 ,State of the pin P5_7" "0,1"
|
|
line.byte 0x20 "W168,GPIO port 5 word pin 8 register"
|
|
bitfld.byte 0x20 0. " PWORD_8 ,State of the pin P5_8" "0,1"
|
|
line.byte 0x24 "W169,GPIO port 5 word pin 9 register"
|
|
bitfld.byte 0x24 0. " PWORD_9 ,State of the pin P5_9" "0,1"
|
|
line.byte 0x28 "W170,GPIO port 5 word pin 10 register"
|
|
bitfld.byte 0x28 0. " PWORD_10 ,State of the pin P5_10" "0,1"
|
|
line.byte 0x2c "W171,GPIO port 5 word pin 11 register"
|
|
bitfld.byte 0x2c 0. " PWORD_11 ,State of the pin P5_11" "0,1"
|
|
line.byte 0x30 "W172,GPIO port 5 word pin 12 register"
|
|
bitfld.byte 0x30 0. " PWORD_12 ,State of the pin P5_12" "0,1"
|
|
line.byte 0x34 "W173,GPIO port 5 word pin 13 register"
|
|
bitfld.byte 0x34 0. " PWORD_13 ,State of the pin P5_13" "0,1"
|
|
line.byte 0x38 "W174,GPIO port 5 word pin 14 register"
|
|
bitfld.byte 0x38 0. " PWORD_14 ,State of the pin P5_14" "0,1"
|
|
line.byte 0x3c "W175,GPIO port 5 word pin 15 register"
|
|
bitfld.byte 0x3c 0. " PWORD_15 ,State of the pin P5_15" "0,1"
|
|
line.byte 0x40 "W176,GPIO port 5 word pin 16 register"
|
|
bitfld.byte 0x40 0. " PWORD_16 ,State of the pin P5_16" "0,1"
|
|
line.byte 0x44 "W177,GPIO port 5 word pin 17 register"
|
|
bitfld.byte 0x44 0. " PWORD_17 ,State of the pin P5_17" "0,1"
|
|
line.byte 0x48 "W178,GPIO port 5 word pin 18 register"
|
|
bitfld.byte 0x48 0. " PWORD_18 ,State of the pin P5_18" "0,1"
|
|
line.byte 0x4c "W179,GPIO port 5 word pin 19 register"
|
|
bitfld.byte 0x4c 0. " PWORD_19 ,State of the pin P5_19" "0,1"
|
|
line.byte 0x50 "W180,GPIO port 5 word pin 20 register"
|
|
bitfld.byte 0x50 0. " PWORD_20 ,State of the pin P5_20" "0,1"
|
|
line.byte 0x54 "W181,GPIO port 5 word pin 21 register"
|
|
bitfld.byte 0x54 0. " PWORD_21 ,State of the pin P5_21" "0,1"
|
|
line.byte 0x58 "W182,GPIO port 5 word pin 22 register"
|
|
bitfld.byte 0x58 0. " PWORD_22 ,State of the pin P5_22" "0,1"
|
|
line.byte 0x5c "W183,GPIO port 5 word pin 23 register"
|
|
bitfld.byte 0x5c 0. " PWORD_23 ,State of the pin P5_23" "0,1"
|
|
line.byte 0x60 "W184,GPIO port 5 word pin 24 register"
|
|
bitfld.byte 0x60 0. " PWORD_24 ,State of the pin P5_24" "0,1"
|
|
line.byte 0x64 "W185,GPIO port 5 word pin 25 register"
|
|
bitfld.byte 0x64 0. " PWORD_25 ,State of the pin P5_25" "0,1"
|
|
line.byte 0x68 "W185,GPIO port 5 word pin 25 register"
|
|
bitfld.byte 0x68 0. " PWORD_25 ,State of the pin P5_25" "0,1"
|
|
line.byte 0x6c "W186,GPIO port 5 word pin 26 register"
|
|
bitfld.byte 0x6c 0. " PWORD_26 ,State of the pin P5_26" "0,1"
|
|
endif
|
|
group.long 0x2014++0x3
|
|
line.long 0x00 "DIR5,GPIO direction port 5 register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*"))
|
|
bitfld.long 0x00 18. " DIRP5[18] ,Pin direction for pin P5_18" "Input,Output"
|
|
bitfld.long 0x00 16. " DIRP5[16] ,Pin direction for pin P5_16" "Input,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " DIRP5[26] ,Pin direction for pin P5_26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DIRP5[25] ,Pin direction for pin P5_25" "Input,Output"
|
|
bitfld.long 0x00 24. " DIRP5[24] ,Pin direction for pin P5_24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DIRP5[23] ,Pin direction for pin P5_23" "Input,Output"
|
|
bitfld.long 0x00 22. " DIRP5[22] ,Pin direction for pin P5_22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DIRP5[21] ,Pin direction for pin P5_21" "Input,Output"
|
|
bitfld.long 0x00 20. " DIRP5[20] ,Pin direction for pin P5_20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIRP5[19] ,Pin direction for pin P5_19" "Input,Output"
|
|
bitfld.long 0x00 18. " DIRP5[18] ,Pin direction for pin P5_18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DIRP5[17] ,Pin direction for pin P5_17" "Input,Output"
|
|
bitfld.long 0x00 16. " DIRP5[16] ,Pin direction for pin P5_16" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " DIRP5[15] ,Pin direction for pin P5_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP5[14] ,Pin direction for pin P5_14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRP5[13] ,Pin direction for pin P5_13" "Input,Output"
|
|
bitfld.long 0x00 12. " DIRP5[12] ,Pin direction for pin P5_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP5[11] ,Pin direction for pin P5_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP5[10] ,Pin direction for pin P5_10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIRP5[9] ,Pin direction for pin P5_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP5[8] ,Pin direction for pin P5_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP5[7] ,Pin direction for pin P5_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP5[6] ,Pin direction for pin P5_6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DIRP5[5] ,Pin direction for pin P5_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP5[4] ,Pin direction for pin P5_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP5[3] ,Pin direction for pin P5_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP5[2] ,Pin direction for pin P5_2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIRP5[1] ,Pin direction for pin P5_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP5[0] ,Pin direction for pin P5_0" "Input,Output"
|
|
group.long 0x2094++0x3
|
|
line.long 0x00 "MASK5,GPIO mask port 5 register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")
|
|
bitfld.long 0x00 18. " MASKP5[18] ,Mask for pin P5_18" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " MASKP5[16] ,Mask for pin P5_16" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " MASKP5[26] ,Mask for pin P5_26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MASKP5[25] ,Mask for pin P5_25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " MASKP5[24] ,Mask for pin P5_24" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MASKP5[23] ,Mask for pin P5_23" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " MASKP5[22] ,Mask for pin P5_22" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MASKP5[21] ,Mask for pin P5_21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " MASKP5[20] ,Mask for pin P5_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MASKP5[19] ,Mask for pin P5_19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " MASKP5[18] ,Mask for pin P5_18" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MASKP5[17] ,Mask for pin P5_17" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " MASKP5[16] ,Mask for pin P5_16" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " MASKP5[15] ,Mask for pin P5_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP5[14] ,Mask for pin P5_14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASKP5[13] ,Mask for pin P5_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASKP5[12] ,Mask for pin P5_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP5[11] ,Mask for pin P5_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP5[10] ,Mask for pin P5_10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MASKP5[9] ,Mask for pin P5_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP5[8] ,Mask for pin P5_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP5[7] ,Mask for pin P5_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP5[6] ,Mask for pin P5_6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MASKP5[5] ,Mask for pin P5_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP5[4] ,Mask for pin P5_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP5[3] ,Mask for pin P5_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP5[2] ,Mask for pin P5_2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASKP5[1] ,Mask for pin P5_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP5[0] ,Mask for pin P5_0" "Not masked,Masked"
|
|
group.long 0x2114++0x3
|
|
line.long 0x00 "PIN5,GPIO port 5 pin register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")
|
|
bitfld.long 0x00 18. " PORT5[18] ,P5_18 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " PORT5[16] ,P5_16 pin state" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " PORT5[26] ,P5_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PORT5[25] ,P5_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " PORT5[24] ,P5_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PORT5[23] ,P5_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " PORT5[22] ,P5_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PORT5[21] ,P5_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " PORT5[20] ,P5_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PORT5[19] ,P5_19 pin state" "Low,High"
|
|
bitfld.long 0x00 18. " PORT5[18] ,P5_18 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PORT5[17] ,P5_17 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " PORT5[16] ,P5_16 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PORT5[15] ,P5_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " PORT5[14] ,P5_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PORT5[13] ,P5_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " PORT5[12] ,P5_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT5[11] ,P5_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " PORT5[10] ,P5_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PORT5[9] ,P5_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " PORT5[8] ,P5_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT5[7] ,P5_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " PORT5[6] ,P5_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PORT5[5] ,P5_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " PORT5[4] ,P5_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT5[3] ,P5_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " PORT5[2] ,P5_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PORT5[1] ,P5_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " PORT5[0] ,P5_0 pin state" "Low,High"
|
|
group.long 0x2194++0x3
|
|
line.long 0x00 "MPIN5,GPIO masked port 5 pin register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")
|
|
bitfld.long 0x00 18. " MPORTP5[18] ,Masked P5_18 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " MPORTP5[16] ,Masked P5_16 pin state" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " MPORTP5[26] ,Masked P5_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MPORTP5[25] ,Masked P5_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " MPORTP5[24] ,Masked P5_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MPORTP5[23] ,Masked P5_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " MPORTP5[22] ,Masked P5_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MPORTP5[21] ,Masked P5_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " MPORTP5[20] ,Masked P5_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MPORTP5[19] ,Masked P5_19 pin state" "Low,High"
|
|
bitfld.long 0x00 18. " MPORTP5[18] ,Masked P5_18 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MPORTP5[17] ,Masked P5_17 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " MPORTP5[16] ,Masked P5_16 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MPORTP5[15] ,Masked P5_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " MPORTP5[14] ,Masked P5_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MPORTP5[13] ,Masked P5_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " MPORTP5[12] ,Masked P5_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP5[11] ,Masked P5_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " MPORTP5[10] ,Masked P5_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPORTP5[9] ,Masked P5_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " MPORTP5[8] ,Masked P5_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP5[7] ,Masked P5_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " MPORTP5[6] ,Masked P5_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPORTP5[5] ,Masked P5_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " MPORTP5[4] ,Masked P5_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP5[3] ,Masked P5_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " MPORTP5[2] ,Masked P5_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MPORTP5[1] ,Masked P5_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " MPORTP5[0] ,Masked P5_0 pin state" "Low,High"
|
|
group.long 0x2214++0x3
|
|
line.long 0x00 "SET5,GPIO set port 5 register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")
|
|
bitfld.long 0x00 18. " SETP5[18] ,State/Set P5_18" "Low,High"
|
|
bitfld.long 0x00 16. " SETP5[16] ,State/Set P5_16" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " SETP5[26] ,State/Set P5_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SETP5[25] ,State/Set P5_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " SETP5[24] ,State/Set P5_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SETP5[23] ,State/Set P5_23" "Low,High"
|
|
bitfld.long 0x00 22. " SETP5[22] ,State/Set P5_22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SETP5[21] ,State/Set P5_21" "Low,High"
|
|
bitfld.long 0x00 20. " SETP5[20] ,State/Set P5_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SETP5[19] ,State/Set P5_19" "Low,High"
|
|
bitfld.long 0x00 18. " SETP5[18] ,State/Set P5_18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SETP5[17] ,State/Set P5_17" "Low,High"
|
|
bitfld.long 0x00 16. " SETP5[16] ,State/Set P5_16" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " SETP5[15] ,State/Set P5_15" "Low,High"
|
|
bitfld.long 0x00 14. " SETP5[14] ,State/Set P5_14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SETP5[13] ,State/Set P5_13" "Low,High"
|
|
bitfld.long 0x00 12. " SETP5[12] ,State/Set P5_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETP5[11] ,State/Set P5_11" "Low,High"
|
|
bitfld.long 0x00 10. " SETP5[10] ,State/Set P5_10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SETP5[9] ,State/Set P5_9" "Low,High"
|
|
bitfld.long 0x00 8. " SETP5[8] ,State/Set P5_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SETP5[7] ,State/Set P5_7" "Low,High"
|
|
bitfld.long 0x00 6. " SETP5[6] ,State/Set P5_6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETP5[5] ,State/Set P5_5" "Low,High"
|
|
bitfld.long 0x00 4. " SETP5[4] ,State/Set P5_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SETP5[3] ,State/Set P5_3" "Low,High"
|
|
bitfld.long 0x00 2. " SETP5[2] ,State/Set P5_2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SETP5[1] ,State/Set P5_1" "Low,High"
|
|
bitfld.long 0x00 0. " SETP5[0] ,State/Set P5_0" "Low,High"
|
|
wgroup.long 0x2294++0x3
|
|
line.long 0x00 "CLR5,GPIO clear port 5 register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")
|
|
bitfld.long 0x00 18. " CLRP5[18] ,Clear P5_18" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CLRP5[16] ,Clear P5_16" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " CLRP5[26] ,Clear P5_26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CLRP5[25] ,Clear P5_25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CLRP5[24] ,Clear P5_24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLRP5[23] ,Clear P5_23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CLRP5[22] ,Clear P5_22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CLRP5[21] ,Clear P5_21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CLRP5[20] ,Clear P5_20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLRP5[19] ,Clear P5_19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CLRP5[18] ,Clear P5_18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CLRP5[17] ,Clear P5_17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CLRP5[16] ,Clear P5_16" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " CLRP5[15] ,Clear P5_15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLRP5[14] ,Clear P5_14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLRP5[13] ,Clear P5_13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLRP5[12] ,Clear P5_12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLRP5[11] ,Clear P5_11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLRP5[10] ,Clear P5_10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLRP5[9] ,Clear P5_9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLRP5[8] ,Clear P5_8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLRP5[7] ,Clear P5_7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLRP5[6] ,Clear P5_6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLRP5[5] ,Clear P5_5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLRP5[4] ,Clear P5_4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLRP5[3] ,Clear P5_3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLRP5[2] ,Clear P5_2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLRP5[1] ,Clear P5_1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLRP5[0] ,Clear P5_0" "No effect,Clear"
|
|
wgroup.long 0x2314++0x3
|
|
line.long 0x00 "NOT5,GPIO toggle port 5 register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")
|
|
bitfld.long 0x00 18. " NOTP5[18] ,Toggle P5_18" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " NOTP5[16] ,Toggle P5_16" "No effect,Toggle"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " NOTP5[26] ,Toggle P5_26" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOTP5[25] ,Toggle P5_25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " NOTP5[24] ,Toggle P5_24" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NOTP5[23] ,Toggle P5_23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " NOTP5[22] ,Toggle P5_22" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTP5[21] ,Toggle P5_21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " NOTP5[20] ,Toggle P5_20" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTP5[19] ,Toggle P5_19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " NOTP5[18] ,Toggle P5_18" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTP5[17] ,Toggle P5_17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " NOTP5[16] ,Toggle P5_16" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " NOTP5[15] ,Toggle P5_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP5[14] ,Toggle P5_14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTP5[13] ,Toggle P5_13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " NOTP5[12] ,Toggle P5_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP5[11] ,Toggle P5_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP5[10] ,Toggle P5_10" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTP5[9] ,Toggle P5_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP5[8] ,Toggle P5_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP5[7] ,Toggle P5_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP5[6] ,Toggle P5_6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTP5[5] ,Toggle P5_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP5[4] ,Toggle P5_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP5[3] ,Toggle P5_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP5[2] ,Toggle P5_2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTP5[1] ,Toggle P5_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP5[0] ,Toggle P5_0" "No effect,Toggle"
|
|
tree.end
|
|
sif !cpuis("LPC181*")&&!cpuis("LPC182*")
|
|
tree "Port 6"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
group.byte 0xc0++0x31
|
|
line.byte 0x0 "B192,GPIO port 6 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P6_0 " "0,1"
|
|
line.byte 0x1 "B193,GPIO port 6 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P6_1 " "0,1"
|
|
line.byte 0x2 "B194,GPIO port 6 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P6_2 " "0,1"
|
|
line.byte 0x3 "B195,GPIO port 6 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P6_3 " "0,1"
|
|
line.byte 0x4 "B196,GPIO port 6 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P6_4 " "0,1"
|
|
line.byte 0x5 "B197,GPIO port 6 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P6_5 " "0,1"
|
|
line.byte 0x6 "B198,GPIO port 6 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P6_6 " "0,1"
|
|
line.byte 0x7 "B199,GPIO port 6 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P6_7 " "0,1"
|
|
line.byte 0x8 "B200,GPIO port 6 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P6_8 " "0,1"
|
|
line.byte 0x9 "B201,GPIO port 6 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P6_9 " "0,1"
|
|
line.byte 0xA "B202,GPIO port 6 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P6_10" "0,1"
|
|
line.byte 0xB "B203,GPIO port 6 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P6_11" "0,1"
|
|
line.byte 0xC "B204,GPIO port 6 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P6_12" "0,1"
|
|
line.byte 0xD "B205,GPIO port 6 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P6_13" "0,1"
|
|
line.byte 0xE "B206,GPIO port 6 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P6_14" "0,1"
|
|
line.byte 0xF "B207,GPIO port 6 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P6_15" "0,1"
|
|
line.byte 0x10 "B208,GPIO port 6 byte pin 16 register"
|
|
bitfld.byte 0x10 0. " PBYTE_16 ,State of the pin P6_16" "0,1"
|
|
line.byte 0x11 "B209,GPIO port 6 byte pin 17 register"
|
|
bitfld.byte 0x11 0. " PBYTE_17 ,State of the pin P6_17" "0,1"
|
|
line.byte 0x12 "B210,GPIO port 6 byte pin 18 register"
|
|
bitfld.byte 0x12 0. " PBYTE_18 ,State of the pin P6_18" "0,1"
|
|
line.byte 0x13 "B211,GPIO port 6 byte pin 19 register"
|
|
bitfld.byte 0x13 0. " PBYTE_19 ,State of the pin P6_19" "0,1"
|
|
line.byte 0x14 "B212,GPIO port 6 byte pin 20 register"
|
|
bitfld.byte 0x14 0. " PBYTE_20 ,State of the pin P6_20" "0,1"
|
|
line.byte 0x15 "B213,GPIO port 6 byte pin 21 register"
|
|
bitfld.byte 0x15 0. " PBYTE_21 ,State of the pin P6_21" "0,1"
|
|
line.byte 0x16 "B214,GPIO port 6 byte pin 22 register"
|
|
bitfld.byte 0x16 0. " PBYTE_22 ,State of the pin P6_22" "0,1"
|
|
line.byte 0x17 "B215,GPIO port 6 byte pin 23 register"
|
|
bitfld.byte 0x17 0. " PBYTE_23 ,State of the pin P6_23" "0,1"
|
|
line.byte 0x18 "B216,GPIO port 6 byte pin 24 register"
|
|
bitfld.byte 0x18 0. " PBYTE_24 ,State of the pin P6_24" "0,1"
|
|
line.byte 0x19 "B217,GPIO port 6 byte pin 25 register"
|
|
bitfld.byte 0x19 0. " PBYTE_25 ,State of the pin P6_25" "0,1"
|
|
line.byte 0x1A "B218,GPIO port 6 byte pin 26 register"
|
|
bitfld.byte 0x1A 0. " PBYTE_26 ,State of the pin P6_26" "0,1"
|
|
line.byte 0x1B "B219,GPIO port 6 byte pin 27 register"
|
|
bitfld.byte 0x1B 0. " PBYTE_27 ,State of the pin P6_27" "0,1"
|
|
line.byte 0x1C "B220,GPIO port 6 byte pin 28 register"
|
|
bitfld.byte 0x1C 0. " PBYTE_28 ,State of the pin P6_28" "0,1"
|
|
line.byte 0x1D "B221,GPIO port 6 byte pin 29 register"
|
|
bitfld.byte 0x1D 0. " PBYTE_29 ,State of the pin P6_29" "0,1"
|
|
line.byte 0x1E "B222,GPIO port 6 byte pin 30 register"
|
|
bitfld.byte 0x1E 0. " PBYTE_30 ,State of the pin P6_30" "0,1"
|
|
group.long 0x1300++0x7F
|
|
line.long 0x0 "W192,GPIO port 6 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P6_0 "
|
|
line.long 0x4 "W193,GPIO port 6 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P6_1 "
|
|
line.long 0x8 "W194,GPIO port 6 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P6_2 "
|
|
line.long 0xC "W195,GPIO port 6 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P6_3 "
|
|
line.long 0x10 "W196,GPIO port 6 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P6_4 "
|
|
line.long 0x14 "W197,GPIO port 6 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P6_5 "
|
|
line.long 0x18 "W198,GPIO port 6 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P6_6 "
|
|
line.long 0x1C "W199,GPIO port 6 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P6_7 "
|
|
line.long 0x20 "W200,GPIO port 6 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P6_8 "
|
|
line.long 0x24 "W201,GPIO port 6 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P6_9 "
|
|
line.long 0x28 "W202,GPIO port 6 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P6_10"
|
|
line.long 0x2C "W203,GPIO port 6 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P6_11"
|
|
line.long 0x30 "W204,GPIO port 6 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P6_12"
|
|
line.long 0x34 "W205,GPIO port 6 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P6_13"
|
|
line.long 0x38 "W206,GPIO port 6 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P6_14"
|
|
line.long 0x3C "W207,GPIO port 6 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P6_15"
|
|
line.long 0x40 "W208,GPIO port 6 word pin 16 register"
|
|
hexmask.long 0x40 0.--31. 1. " PWORD_16 ,State of the pin P6_16"
|
|
line.long 0x44 "W209,GPIO port 6 word pin 17 register"
|
|
hexmask.long 0x44 0.--31. 1. " PWORD_17 ,State of the pin P6_17"
|
|
line.long 0x48 "W210,GPIO port 6 word pin 18 register"
|
|
hexmask.long 0x48 0.--31. 1. " PWORD_18 ,State of the pin P6_18"
|
|
line.long 0x4C "W211,GPIO port 6 word pin 19 register"
|
|
hexmask.long 0x4C 0.--31. 1. " PWORD_19 ,State of the pin P6_19"
|
|
line.long 0x50 "W212,GPIO port 6 word pin 20 register"
|
|
hexmask.long 0x50 0.--31. 1. " PWORD_20 ,State of the pin P6_20"
|
|
line.long 0x54 "W213,GPIO port 6 word pin 21 register"
|
|
hexmask.long 0x54 0.--31. 1. " PWORD_21 ,State of the pin P6_21"
|
|
line.long 0x58 "W214,GPIO port 6 word pin 22 register"
|
|
hexmask.long 0x58 0.--31. 1. " PWORD_22 ,State of the pin P6_22"
|
|
line.long 0x5C "W215,GPIO port 6 word pin 23 register"
|
|
hexmask.long 0x5C 0.--31. 1. " PWORD_23 ,State of the pin P6_23"
|
|
line.long 0x60 "W216,GPIO port 6 word pin 24 register"
|
|
hexmask.long 0x60 0.--31. 1. " PWORD_24 ,State of the pin P6_24"
|
|
line.long 0x64 "W217,GPIO port 6 word pin 25 register"
|
|
hexmask.long 0x64 0.--31. 1. " PWORD_25 ,State of the pin P6_25"
|
|
line.long 0x68 "W218,GPIO port 6 word pin 26 register"
|
|
hexmask.long 0x68 0.--31. 1. " PWORD_26 ,State of the pin P6_26"
|
|
line.long 0x6C "W219,GPIO port 6 word pin 27 register"
|
|
hexmask.long 0x6C 0.--31. 1. " PWORD_27 ,State of the pin P6_27"
|
|
line.long 0x70 "W220,GPIO port 6 word pin 28 register"
|
|
hexmask.long 0x70 0.--31. 1. " PWORD_28 ,State of the pin P6_28"
|
|
line.long 0x74 "W221,GPIO port 6 word pin 29 register"
|
|
hexmask.long 0x74 0.--31. 1. " PWORD_29 ,State of the pin P6_29"
|
|
line.long 0x78 "W222,GPIO port 6 word pin 30 register"
|
|
hexmask.long 0x78 0.--31. 1. " PWORD_30 ,State of the pin P6_30"
|
|
else
|
|
group.byte 0xc0++32
|
|
line.byte 0x0 "B192,GPIO port 6 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P6_0 " "0,1"
|
|
line.byte 0x1 "B193,GPIO port 6 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P6_1 " "0,1"
|
|
line.byte 0x2 "B194,GPIO port 6 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P6_2 " "0,1"
|
|
line.byte 0x3 "B195,GPIO port 6 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P6_3 " "0,1"
|
|
line.byte 0x4 "B196,GPIO port 6 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P6_4 " "0,1"
|
|
line.byte 0x5 "B197,GPIO port 6 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P6_5 " "0,1"
|
|
line.byte 0x6 "B198,GPIO port 6 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P6_6 " "0,1"
|
|
line.byte 0x7 "B199,GPIO port 6 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P6_7 " "0,1"
|
|
line.byte 0x8 "B200,GPIO port 6 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P6_8 " "0,1"
|
|
line.byte 0x9 "B201,GPIO port 6 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P6_9 " "0,1"
|
|
line.byte 0xA "B202,GPIO port 6 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P6_10" "0,1"
|
|
line.byte 0xB "B203,GPIO port 6 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P6_11" "0,1"
|
|
line.byte 0xC "B204,GPIO port 6 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P6_12" "0,1"
|
|
line.byte 0xD "B205,GPIO port 6 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P6_13" "0,1"
|
|
line.byte 0xE "B206,GPIO port 6 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P6_14" "0,1"
|
|
line.byte 0xF "B207,GPIO port 6 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P6_15" "0,1"
|
|
line.byte 0x10 "B208,GPIO port 6 byte pin 16 register"
|
|
bitfld.byte 0x10 0. " PBYTE_16 ,State of the pin P6_16" "0,1"
|
|
line.byte 0x11 "B209,GPIO port 6 byte pin 17 register"
|
|
bitfld.byte 0x11 0. " PBYTE_17 ,State of the pin P6_17" "0,1"
|
|
line.byte 0x12 "B210,GPIO port 6 byte pin 18 register"
|
|
bitfld.byte 0x12 0. " PBYTE_18 ,State of the pin P6_18" "0,1"
|
|
line.byte 0x13 "B211,GPIO port 6 byte pin 19 register"
|
|
bitfld.byte 0x13 0. " PBYTE_19 ,State of the pin P6_19" "0,1"
|
|
line.byte 0x14 "B212,GPIO port 6 byte pin 20 register"
|
|
bitfld.byte 0x14 0. " PBYTE_20 ,State of the pin P6_20" "0,1"
|
|
line.byte 0x15 "B213,GPIO port 6 byte pin 21 register"
|
|
bitfld.byte 0x15 0. " PBYTE_21 ,State of the pin P6_21" "0,1"
|
|
line.byte 0x16 "B214,GPIO port 6 byte pin 22 register"
|
|
bitfld.byte 0x16 0. " PBYTE_22 ,State of the pin P6_22" "0,1"
|
|
line.byte 0x17 "B215,GPIO port 6 byte pin 23 register"
|
|
bitfld.byte 0x17 0. " PBYTE_23 ,State of the pin P6_23" "0,1"
|
|
line.byte 0x18 "B216,GPIO port 6 byte pin 24 register"
|
|
bitfld.byte 0x18 0. " PBYTE_24 ,State of the pin P6_24" "0,1"
|
|
line.byte 0x19 "B217,GPIO port 6 byte pin 25 register"
|
|
bitfld.byte 0x19 0. " PBYTE_25 ,State of the pin P6_25" "0,1"
|
|
line.byte 0x1A "B218,GPIO port 6 byte pin 26 register"
|
|
bitfld.byte 0x1A 0. " PBYTE_26 ,State of the pin P6_26" "0,1"
|
|
line.byte 0x1B "B219,GPIO port 6 byte pin 27 register"
|
|
bitfld.byte 0x1B 0. " PBYTE_27 ,State of the pin P6_27" "0,1"
|
|
line.byte 0x1C "B220,GPIO port 6 byte pin 28 register"
|
|
bitfld.byte 0x1C 0. " PBYTE_28 ,State of the pin P6_28" "0,1"
|
|
line.byte 0x1D "B221,GPIO port 6 byte pin 29 register"
|
|
bitfld.byte 0x1D 0. " PBYTE_29 ,State of the pin P6_29" "0,1"
|
|
line.byte 0x1E "B222,GPIO port 6 byte pin 30 register"
|
|
bitfld.byte 0x1E 0. " PBYTE_30 ,State of the pin P6_30" "0,1"
|
|
line.byte 0x1F "B223,GPIO port 6 byte pin 31 register"
|
|
bitfld.byte 0x1F 0. " PBYTE_31 ,State of the pin P6_31" "0,1"
|
|
group.long 0x1300++0x83
|
|
line.long 0x0 "W192,GPIO port 6 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P6_0 "
|
|
line.long 0x4 "W193,GPIO port 6 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P6_1 "
|
|
line.long 0x8 "W194,GPIO port 6 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P6_2 "
|
|
line.long 0xC "W195,GPIO port 6 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P6_3 "
|
|
line.long 0x10 "W196,GPIO port 6 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P6_4 "
|
|
line.long 0x14 "W197,GPIO port 6 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P6_5 "
|
|
line.long 0x18 "W198,GPIO port 6 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P6_6 "
|
|
line.long 0x1C "W199,GPIO port 6 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P6_7 "
|
|
line.long 0x20 "W200,GPIO port 6 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P6_8 "
|
|
line.long 0x24 "W201,GPIO port 6 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P6_9 "
|
|
line.long 0x28 "W202,GPIO port 6 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P6_10"
|
|
line.long 0x2C "W203,GPIO port 6 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P6_11"
|
|
line.long 0x30 "W204,GPIO port 6 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P6_12"
|
|
line.long 0x34 "W205,GPIO port 6 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P6_13"
|
|
line.long 0x38 "W206,GPIO port 6 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P6_14"
|
|
line.long 0x3C "W207,GPIO port 6 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P6_15"
|
|
line.long 0x40 "W208,GPIO port 6 word pin 16 register"
|
|
hexmask.long 0x40 0.--31. 1. " PWORD_16 ,State of the pin P6_16"
|
|
line.long 0x44 "W209,GPIO port 6 word pin 17 register"
|
|
hexmask.long 0x44 0.--31. 1. " PWORD_17 ,State of the pin P6_17"
|
|
line.long 0x48 "W210,GPIO port 6 word pin 18 register"
|
|
hexmask.long 0x48 0.--31. 1. " PWORD_18 ,State of the pin P6_18"
|
|
line.long 0x4C "W211,GPIO port 6 word pin 19 register"
|
|
hexmask.long 0x4C 0.--31. 1. " PWORD_19 ,State of the pin P6_19"
|
|
line.long 0x50 "W212,GPIO port 6 word pin 20 register"
|
|
hexmask.long 0x50 0.--31. 1. " PWORD_20 ,State of the pin P6_20"
|
|
line.long 0x54 "W213,GPIO port 6 word pin 21 register"
|
|
hexmask.long 0x54 0.--31. 1. " PWORD_21 ,State of the pin P6_21"
|
|
line.long 0x58 "W214,GPIO port 6 word pin 22 register"
|
|
hexmask.long 0x58 0.--31. 1. " PWORD_22 ,State of the pin P6_22"
|
|
line.long 0x5C "W215,GPIO port 6 word pin 23 register"
|
|
hexmask.long 0x5C 0.--31. 1. " PWORD_23 ,State of the pin P6_23"
|
|
line.long 0x60 "W216,GPIO port 6 word pin 24 register"
|
|
hexmask.long 0x60 0.--31. 1. " PWORD_24 ,State of the pin P6_24"
|
|
line.long 0x64 "W217,GPIO port 6 word pin 25 register"
|
|
hexmask.long 0x64 0.--31. 1. " PWORD_25 ,State of the pin P6_25"
|
|
line.long 0x68 "W218,GPIO port 6 word pin 26 register"
|
|
hexmask.long 0x68 0.--31. 1. " PWORD_26 ,State of the pin P6_26"
|
|
line.long 0x6C "W219,GPIO port 6 word pin 27 register"
|
|
hexmask.long 0x6C 0.--31. 1. " PWORD_27 ,State of the pin P6_27"
|
|
line.long 0x70 "W220,GPIO port 6 word pin 28 register"
|
|
hexmask.long 0x70 0.--31. 1. " PWORD_28 ,State of the pin P6_28"
|
|
line.long 0x74 "W221,GPIO port 6 word pin 29 register"
|
|
hexmask.long 0x74 0.--31. 1. " PWORD_29 ,State of the pin P6_29"
|
|
line.long 0x78 "W222,GPIO port 6 word pin 30 register"
|
|
hexmask.long 0x78 0.--31. 1. " PWORD_30 ,State of the pin P6_30"
|
|
line.long 0x7C "W223,GPIO port 6 word pin 31 register"
|
|
hexmask.long 0x7C 0.--31. 1. " PWORD_31 ,State of the pin P6_31"
|
|
endif
|
|
group.long 0x2018++0x3
|
|
line.long 0x00 "DIR6,GPIO direction port 6 register"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30. " DIRP6[30] ,Pin direction for pin P6_30" "Input,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " DIRP6[31] ,Pin direction for pin P6_31" "Input,Output"
|
|
bitfld.long 0x00 30. " DIRP6[30] ,Pin direction for pin P6_30" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " DIRP6[29] ,Pin direction for pin P6_29" "Input,Output"
|
|
bitfld.long 0x00 28. " DIRP6[28] ,Pin direction for pin P6_28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DIRP6[27] ,Pin direction for pin P6_27" "Input,Output"
|
|
bitfld.long 0x00 26. " DIRP6[26] ,Pin direction for pin P6_26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DIRP6[25] ,Pin direction for pin P6_25" "Input,Output"
|
|
bitfld.long 0x00 24. " DIRP6[24] ,Pin direction for pin P6_24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DIRP6[23] ,Pin direction for pin P6_23" "Input,Output"
|
|
bitfld.long 0x00 22. " DIRP6[22] ,Pin direction for pin P6_22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DIRP6[21] ,Pin direction for pin P6_21" "Input,Output"
|
|
bitfld.long 0x00 20. " DIRP6[20] ,Pin direction for pin P6_20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIRP6[19] ,Pin direction for pin P6_19" "Input,Output"
|
|
bitfld.long 0x00 18. " DIRP6[18] ,Pin direction for pin P6_18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DIRP6[17] ,Pin direction for pin P6_17" "Input,Output"
|
|
bitfld.long 0x00 16. " DIRP6[16] ,Pin direction for pin P6_16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIRP6[15] ,Pin direction for pin P6_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP6[14] ,Pin direction for pin P6_14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRP6[13] ,Pin direction for pin P6_13" "Input,Output"
|
|
bitfld.long 0x00 12. " DIRP6[12] ,Pin direction for pin P6_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP6[11] ,Pin direction for pin P6_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP6[10] ,Pin direction for pin P6_10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIRP6[9] ,Pin direction for pin P6_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP6[8] ,Pin direction for pin P6_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP6[7] ,Pin direction for pin P6_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP6[6] ,Pin direction for pin P6_6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DIRP6[5] ,Pin direction for pin P6_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP6[4] ,Pin direction for pin P6_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP6[3] ,Pin direction for pin P6_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP6[2] ,Pin direction for pin P6_2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIRP6[1] ,Pin direction for pin P6_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP6[0] ,Pin direction for pin P6_0" "Input,Output"
|
|
group.long 0x2098++0x3
|
|
line.long 0x00 "MASK6,GPIO mask port 6 register"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30. " MASKP6[30] ,Mask for pin P6_30" "Not masked,Masked"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " MASKP6[31] ,Mask for pin P6_31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " MASKP6[30] ,Mask for pin P6_30" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " MASKP6[29] ,Mask for pin P6_29" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " MASKP6[28] ,Mask for pin P6_28" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MASKP6[27] ,Mask for pin P6_27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " MASKP6[26] ,Mask for pin P6_26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MASKP6[25] ,Mask for pin P6_25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " MASKP6[24] ,Mask for pin P6_24" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MASKP6[23] ,Mask for pin P6_23" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " MASKP6[22] ,Mask for pin P6_22" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MASKP6[21] ,Mask for pin P6_21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " MASKP6[20] ,Mask for pin P6_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MASKP6[19] ,Mask for pin P6_19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " MASKP6[18] ,Mask for pin P6_18" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MASKP6[17] ,Mask for pin P6_17" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " MASKP6[16] ,Mask for pin P6_16" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MASKP6[15] ,Mask for pin P6_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP6[14] ,Mask for pin P6_14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASKP6[13] ,Mask for pin P6_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASKP6[12] ,Mask for pin P6_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP6[11] ,Mask for pin P6_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP6[10] ,Mask for pin P6_10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MASKP6[9] ,Mask for pin P6_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP6[8] ,Mask for pin P6_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP6[7] ,Mask for pin P6_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP6[6] ,Mask for pin P6_6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MASKP6[5] ,Mask for pin P6_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP6[4] ,Mask for pin P6_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP6[3] ,Mask for pin P6_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP6[2] ,Mask for pin P6_2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASKP6[1] ,Mask for pin P6_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP6[0] ,Mask for pin P6_0" "Not masked,Masked"
|
|
group.long 0x2118++0x3
|
|
line.long 0x00 "PIN6,GPIO port 6 pin register"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30. " PORT6[30] ,P6_30 pin state" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " PORT6[31] ,P6_31 pin state" "Low,High"
|
|
bitfld.long 0x00 30. " PORT6[30] ,P6_30 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " PORT6[29] ,P6_29 pin state" "Low,High"
|
|
bitfld.long 0x00 28. " PORT6[28] ,P6_28 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PORT6[27] ,P6_27 pin state" "Low,High"
|
|
bitfld.long 0x00 26. " PORT6[26] ,P6_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PORT6[25] ,P6_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " PORT6[23] ,P6_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PORT6[23] ,P6_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " PORT6[22] ,P6_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PORT6[21] ,P6_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " PORT6[20] ,P6_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PORT6[19] ,P6_19 pin state" "Low,High"
|
|
bitfld.long 0x00 18. " PORT6[18] ,P6_18 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PORT6[17] ,P6_17 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " PORT6[16] ,P6_16 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PORT6[15] ,P6_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " PORT6[14] ,P6_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PORT6[13] ,P6_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " PORT6[12] ,P6_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT6[11] ,P6_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " PORT6[10] ,P6_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PORT6[9] ,P6_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " PORT6[8] ,P6_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT6[7] ,P6_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " PORT6[6] ,P6_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PORT6[5] ,P6_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " PORT6[4] ,P6_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT6[3] ,P6_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " PORT6[2] ,P6_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PORT6[1] ,P6_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " PORT6[0] ,P6_0 pin state" "Low,High"
|
|
group.long 0x2198++0x3
|
|
line.long 0x00 "MPIN6,GPIO masked port 6 pin register"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30. " MPORTP6[30] ,Masked P6_30 pin state" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " MPORTP6[31] ,Masked P6_31 pin state" "Low,High"
|
|
bitfld.long 0x00 30. " MPORTP6[30] ,Masked P6_30 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " MPORTP6[29] ,Masked P6_29 pin state" "Low,High"
|
|
bitfld.long 0x00 28. " MPORTP6[28] ,Masked P6_28 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MPORTP6[27] ,Masked P6_27 pin state" "Low,High"
|
|
bitfld.long 0x00 26. " MPORTP6[26] ,Masked P6_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MPORTP6[25] ,Masked P6_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " MPORTP6[24] ,Masked P6_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MPORTP6[23] ,Masked P6_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " MPORTP6[22] ,Masked P6_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MPORTP6[21] ,Masked P6_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " MPORTP6[20] ,Masked P6_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MPORTP6[19] ,Masked P6_19 pin state" "Low,High"
|
|
bitfld.long 0x00 18. " MPORTP6[18] ,Masked P6_18 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MPORTP6[17] ,Masked P6_17 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " MPORTP6[16] ,Masked P6_16 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MPORTP6[15] ,Masked P6_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " MPORTP6[14] ,Masked P6_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MPORTP6[13] ,Masked P6_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " MPORTP6[12] ,Masked P6_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP6[11] ,Masked P6_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " MPORTP6[10] ,Masked P6_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPORTP6[9] ,Masked P6_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " MPORTP6[8] ,Masked P6_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP6[7] ,Masked P6_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " MPORTP6[6] ,Masked P6_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPORTP6[5] ,Masked P6_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " MPORTP6[4] ,Masked P6_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP6[3] ,Masked P6_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " MPORTP6[2] ,Masked P6_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MPORTP6[1] ,Masked P6_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " MPORTP7[0] ,Masked P7_0 pin state" "Low,High"
|
|
group.long 0x2218++0x3
|
|
line.long 0x00 "SET6,GPIO set port 6 register"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30. " SETP6[30] ,State/Set P6_30 pin state" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " SETP6[31] ,State/Set P6_31 pin state" "Low,High"
|
|
bitfld.long 0x00 30. " SETP6[30] ,State/Set P6_30 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " SETP6[29] ,State/Set P6_29 pin state" "Low,High"
|
|
bitfld.long 0x00 28. " SETP6[28] ,State/Set P6_28 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SETP6[27] ,State/Set P6_27 pin state" "Low,High"
|
|
bitfld.long 0x00 26. " SETP6[26] ,State/Set P6_26 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SETP6[25] ,State/Set P6_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " SETP6[24] ,State/Set P6_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SETP6[23] ,State/Set P6_23" "Low,High"
|
|
bitfld.long 0x00 22. " SETP6[22] ,State/Set P6_22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SETP6[21] ,State/Set P6_21" "Low,High"
|
|
bitfld.long 0x00 20. " SETP6[20] ,State/Set P6_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SETP6[19] ,State/Set P6_19" "Low,High"
|
|
bitfld.long 0x00 18. " SETP6[18] ,State/Set P6_18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SETP6[17] ,State/Set P6_17" "Low,High"
|
|
bitfld.long 0x00 16. " SETP6[16] ,State/Set P6_16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SETP6[15] ,State/Set P6_15" "Low,High"
|
|
bitfld.long 0x00 14. " SETP6[14] ,State/Set P6_14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SETP6[13] ,State/Set P6_13" "Low,High"
|
|
bitfld.long 0x00 12. " SETP6[12] ,State/Set P6_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETP6[11] ,State/Set P6_11" "Low,High"
|
|
bitfld.long 0x00 10. " SETP6[10] ,State/Set P6_10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SETP6[9] ,State/Set P6_9" "Low,High"
|
|
bitfld.long 0x00 8. " SETP6[8] ,State/Set P6_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SETP6[7] ,State/Set P6_7" "Low,High"
|
|
bitfld.long 0x00 6. " SETP6[6] ,State/Set P6_6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETP6[5] ,State/Set P6_5" "Low,High"
|
|
bitfld.long 0x00 4. " SETP6[4] ,State/Set P6_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SETP6[3] ,State/Set P6_3" "Low,High"
|
|
bitfld.long 0x00 2. " SETP6[2] ,State/Set P6_2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SETP6[1] ,State/Set P6_1" "Low,High"
|
|
bitfld.long 0x00 0. " SETP6[0] ,State/Set P6_0" "Low,High"
|
|
wgroup.long 0x2298++0x3
|
|
line.long 0x00 "CLR6,GPIO clear port 6 register"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30. " CLRP6[30] ,Clear P6_30" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " CLRP6[31] ,Clear P6_31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " CLRP6[30] ,Clear P6_30" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " CLRP6[29] ,Clear P6_29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " CLRP6[28] ,Clear P6_28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CLRP6[27] ,Clear P6_27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CLRP6[26] ,Clear P6_26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CLRP6[25] ,Clear P6_25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CLRP6[24] ,Clear P6_24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLRP6[23] ,Clear P6_23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CLRP6[22] ,Clear P6_22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CLRP6[21] ,Clear P6_21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CLRP6[20] ,Clear P6_20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLRP6[19] ,Clear P6_19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CLRP6[18] ,Clear P6_18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CLRP6[17] ,Clear P6_17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CLRP6[16] ,Clear P6_16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLRP6[15] ,Clear P6_15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLRP6[14] ,Clear P6_14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLRP6[13] ,Clear P6_13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLRP6[12] ,Clear P6_12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLRP6[11] ,Clear P6_11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLRP6[10] ,Clear P6_10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLRP6[9] ,Clear P6_9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLRP6[8] ,Clear P6_8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLRP6[7] ,Clear P6_7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLRP6[6] ,Clear P6_6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLRP6[5] ,Clear P6_5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLRP6[4] ,Clear P6_4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLRP6[3] ,Clear P6_3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLRP6[2] ,Clear P6_2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLRP6[1] ,Clear P6_1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLRP6[0] ,Clear P6_0" "No effect,Clear"
|
|
wgroup.long 0x2318++0x3
|
|
line.long 0x00 "NOT6,GPIO toggle port 6 register"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30. " NOTP6[30] ,Toggle P6_30" "No effect,Toggle"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " NOTP6[31] ,Toggle P6_31" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " NOTP6[30] ,Toggle P6_30" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " NOTP6[29] ,Toggle P6_29" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " NOTP6[28] ,Toggle P6_28" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NOTP6[27] ,Toggle P6_27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " NOTP6[26] ,Toggle P6_26" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOTP6[25] ,Toggle P6_25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " NOTP6[24] ,Toggle P6_24" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NOTP6[23] ,Toggle P6_23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " NOTP6[22] ,Toggle P6_22" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTP6[21] ,Toggle P6_21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " NOTP6[20] ,Toggle P6_20" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTP6[19] ,Toggle P6_19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " NOTP6[18] ,Toggle P6_18" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTP6[17] ,Toggle P6_17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " NOTP6[16] ,Toggle P6_16" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTP6[15] ,Toggle P6_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP6[14] ,Toggle P6_14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTP6[13] ,Toggle P6_13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " NOTP6[12] ,Toggle P6_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP6[11] ,Toggle P6_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP6[10] ,Toggle P6_10" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTP6[9] ,Toggle P6_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP6[8] ,Toggle P6_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP6[7] ,Toggle P6_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP6[6] ,Toggle P6_6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTP6[5] ,Toggle P6_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP6[4] ,Toggle P6_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP6[3] ,Toggle P6_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP6[2] ,Toggle P6_2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTP6[1] ,Toggle P6_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP6[0] ,Toggle P6_0" "No effect,Toggle"
|
|
tree.end
|
|
tree "Port 7"
|
|
group.byte 0xe0++0x26
|
|
line.byte 0x0 "B224,GPIO port 7 byte pin 0 register"
|
|
bitfld.byte 0x0 0. " PBYTE_0 ,State of the pin P7_0 " "0,1"
|
|
line.byte 0x1 "B225,GPIO port 7 byte pin 1 register"
|
|
bitfld.byte 0x1 0. " PBYTE_1 ,State of the pin P7_1 " "0,1"
|
|
line.byte 0x2 "B226,GPIO port 7 byte pin 2 register"
|
|
bitfld.byte 0x2 0. " PBYTE_2 ,State of the pin P7_2 " "0,1"
|
|
line.byte 0x3 "B227,GPIO port 7 byte pin 3 register"
|
|
bitfld.byte 0x3 0. " PBYTE_3 ,State of the pin P7_3 " "0,1"
|
|
line.byte 0x4 "B228,GPIO port 7 byte pin 4 register"
|
|
bitfld.byte 0x4 0. " PBYTE_4 ,State of the pin P7_4 " "0,1"
|
|
line.byte 0x5 "B229,GPIO port 7 byte pin 5 register"
|
|
bitfld.byte 0x5 0. " PBYTE_5 ,State of the pin P7_5 " "0,1"
|
|
line.byte 0x6 "B230,GPIO port 7 byte pin 6 register"
|
|
bitfld.byte 0x6 0. " PBYTE_6 ,State of the pin P7_6 " "0,1"
|
|
line.byte 0x7 "B231,GPIO port 7 byte pin 7 register"
|
|
bitfld.byte 0x7 0. " PBYTE_7 ,State of the pin P7_7 " "0,1"
|
|
line.byte 0x8 "B232,GPIO port 7 byte pin 8 register"
|
|
bitfld.byte 0x8 0. " PBYTE_8 ,State of the pin P7_8 " "0,1"
|
|
line.byte 0x9 "B233,GPIO port 7 byte pin 9 register"
|
|
bitfld.byte 0x9 0. " PBYTE_9 ,State of the pin P7_9 " "0,1"
|
|
line.byte 0xA "B234,GPIO port 7 byte pin 10 register"
|
|
bitfld.byte 0xA 0. " PBYTE_10 ,State of the pin P7_10" "0,1"
|
|
line.byte 0xB "B235,GPIO port 7 byte pin 11 register"
|
|
bitfld.byte 0xB 0. " PBYTE_11 ,State of the pin P7_11" "0,1"
|
|
line.byte 0xC "B236,GPIO port 7 byte pin 12 register"
|
|
bitfld.byte 0xC 0. " PBYTE_12 ,State of the pin P7_12" "0,1"
|
|
line.byte 0xD "B237,GPIO port 7 byte pin 13 register"
|
|
bitfld.byte 0xD 0. " PBYTE_13 ,State of the pin P7_13" "0,1"
|
|
line.byte 0xE "B238,GPIO port 7 byte pin 14 register"
|
|
bitfld.byte 0xE 0. " PBYTE_14 ,State of the pin P7_14" "0,1"
|
|
line.byte 0xF "B239,GPIO port 7 byte pin 15 register"
|
|
bitfld.byte 0xF 0. " PBYTE_15 ,State of the pin P7_15" "0,1"
|
|
line.byte 0x10 "B240,GPIO port 7 byte pin 16 register"
|
|
bitfld.byte 0x10 0. " PBYTE_16 ,State of the pin P7_16" "0,1"
|
|
line.byte 0x11 "B241,GPIO port 7 byte pin 17 register"
|
|
bitfld.byte 0x11 0. " PBYTE_17 ,State of the pin P7_17" "0,1"
|
|
line.byte 0x12 "B242,GPIO port 7 byte pin 18 register"
|
|
bitfld.byte 0x12 0. " PBYTE_18 ,State of the pin P7_18" "0,1"
|
|
line.byte 0x13 "B243,GPIO port 7 byte pin 19 register"
|
|
bitfld.byte 0x13 0. " PBYTE_19 ,State of the pin P7_19" "0,1"
|
|
line.byte 0x14 "B244,GPIO port 7 byte pin 20 register"
|
|
bitfld.byte 0x14 0. " PBYTE_20 ,State of the pin P7_20" "0,1"
|
|
line.byte 0x15 "B245,GPIO port 7 byte pin 21 register"
|
|
bitfld.byte 0x15 0. " PBYTE_21 ,State of the pin P7_21" "0,1"
|
|
line.byte 0x16 "B246,GPIO port 7 byte pin 22 register"
|
|
bitfld.byte 0x16 0. " PBYTE_22 ,State of the pin P7_22" "0,1"
|
|
line.byte 0x17 "B247,GPIO port 7 byte pin 23 register"
|
|
bitfld.byte 0x17 0. " PBYTE_23 ,State of the pin P7_23" "0,1"
|
|
line.byte 0x18 "B248,GPIO port 7 byte pin 24 register"
|
|
bitfld.byte 0x18 0. " PBYTE_24 ,State of the pin P7_24" "0,1"
|
|
line.byte 0x19 "B249,GPIO port 7 byte pin 25 register"
|
|
bitfld.byte 0x19 0. " PBYTE_25 ,State of the pin P7_25" "0,1"
|
|
group.long 0x1380++0x67
|
|
line.long 0x0 "W224,GPIO port 7 word pin 0 register"
|
|
hexmask.long 0x0 0.--31. 1. " PWORD_0 ,State of the pin P7_0 "
|
|
line.long 0x4 "W225,GPIO port 7 word pin 1 register"
|
|
hexmask.long 0x4 0.--31. 1. " PWORD_1 ,State of the pin P7_1 "
|
|
line.long 0x8 "W226,GPIO port 7 word pin 2 register"
|
|
hexmask.long 0x8 0.--31. 1. " PWORD_2 ,State of the pin P7_2 "
|
|
line.long 0xC "W227,GPIO port 7 word pin 3 register"
|
|
hexmask.long 0xC 0.--31. 1. " PWORD_3 ,State of the pin P7_3 "
|
|
line.long 0x10 "W228,GPIO port 7 word pin 4 register"
|
|
hexmask.long 0x10 0.--31. 1. " PWORD_4 ,State of the pin P7_4 "
|
|
line.long 0x14 "W229,GPIO port 7 word pin 5 register"
|
|
hexmask.long 0x14 0.--31. 1. " PWORD_5 ,State of the pin P7_5 "
|
|
line.long 0x18 "W230,GPIO port 7 word pin 6 register"
|
|
hexmask.long 0x18 0.--31. 1. " PWORD_6 ,State of the pin P7_6 "
|
|
line.long 0x1C "W231,GPIO port 7 word pin 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. " PWORD_7 ,State of the pin P7_7 "
|
|
line.long 0x20 "W232,GPIO port 7 word pin 8 register"
|
|
hexmask.long 0x20 0.--31. 1. " PWORD_8 ,State of the pin P7_8 "
|
|
line.long 0x24 "W233,GPIO port 7 word pin 9 register"
|
|
hexmask.long 0x24 0.--31. 1. " PWORD_9 ,State of the pin P7_9 "
|
|
line.long 0x28 "W234,GPIO port 7 word pin 10 register"
|
|
hexmask.long 0x28 0.--31. 1. " PWORD_10 ,State of the pin P7_10"
|
|
line.long 0x2C "W235,GPIO port 7 word pin 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. " PWORD_11 ,State of the pin P7_11"
|
|
line.long 0x30 "W236,GPIO port 7 word pin 12 register"
|
|
hexmask.long 0x30 0.--31. 1. " PWORD_12 ,State of the pin P7_12"
|
|
line.long 0x34 "W237,GPIO port 7 word pin 13 register"
|
|
hexmask.long 0x34 0.--31. 1. " PWORD_13 ,State of the pin P7_13"
|
|
line.long 0x38 "W238,GPIO port 7 word pin 14 register"
|
|
hexmask.long 0x38 0.--31. 1. " PWORD_14 ,State of the pin P7_14"
|
|
line.long 0x3C "W239,GPIO port 7 word pin 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. " PWORD_15 ,State of the pin P7_15"
|
|
line.long 0x40 "W240,GPIO port 7 word pin 16 register"
|
|
hexmask.long 0x40 0.--31. 1. " PWORD_16 ,State of the pin P7_16"
|
|
line.long 0x44 "W241,GPIO port 7 word pin 17 register"
|
|
hexmask.long 0x44 0.--31. 1. " PWORD_17 ,State of the pin P7_17"
|
|
line.long 0x48 "W242,GPIO port 7 word pin 18 register"
|
|
hexmask.long 0x48 0.--31. 1. " PWORD_18 ,State of the pin P7_18"
|
|
line.long 0x4C "W243,GPIO port 7 word pin 19 register"
|
|
hexmask.long 0x4C 0.--31. 1. " PWORD_19 ,State of the pin P7_19"
|
|
line.long 0x50 "W244,GPIO port 7 word pin 20 register"
|
|
hexmask.long 0x50 0.--31. 1. " PWORD_20 ,State of the pin P7_20"
|
|
line.long 0x54 "W245,GPIO port 7 word pin 21 register"
|
|
hexmask.long 0x54 0.--31. 1. " PWORD_21 ,State of the pin P7_21"
|
|
line.long 0x58 "W246,GPIO port 7 word pin 22 register"
|
|
hexmask.long 0x58 0.--31. 1. " PWORD_22 ,State of the pin P7_22"
|
|
line.long 0x5C "W247,GPIO port 7 word pin 23 register"
|
|
hexmask.long 0x5C 0.--31. 1. " PWORD_23 ,State of the pin P7_23"
|
|
line.long 0x60 "W248,GPIO port 7 word pin 24 register"
|
|
hexmask.long 0x60 0.--31. 1. " PWORD_24 ,State of the pin P7_24"
|
|
line.long 0x64 "W249,GPIO port 7 word pin 25 register"
|
|
hexmask.long 0x64 0.--31. 1. " PWORD_25 ,State of the pin P7_25"
|
|
group.long 0x201c++0x3
|
|
line.long 0x00 "DIR7,GPIO direction port 7 register"
|
|
bitfld.long 0x00 25. " DIRP7[25] ,Pin direction for pin P7_25" "Input,Output"
|
|
bitfld.long 0x00 24. " DIRP7[24] ,Pin direction for pin P7_24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DIRP7[23] ,Pin direction for pin P7_23" "Input,Output"
|
|
bitfld.long 0x00 22. " DIRP7[22] ,Pin direction for pin P7_22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DIRP7[21] ,Pin direction for pin P7_21" "Input,Output"
|
|
bitfld.long 0x00 20. " DIRP7[20] ,Pin direction for pin P7_20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIRP7[19] ,Pin direction for pin P7_19" "Input,Output"
|
|
bitfld.long 0x00 18. " DIRP7[18] ,Pin direction for pin P7_18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DIRP7[17] ,Pin direction for pin P7_17" "Input,Output"
|
|
bitfld.long 0x00 16. " DIRP7[16] ,Pin direction for pin P7_16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIRP7[15] ,Pin direction for pin P7_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP7[14] ,Pin direction for pin P7_14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRP7[13] ,Pin direction for pin P7_13" "Input,Output"
|
|
bitfld.long 0x00 12. " DIRP7[12] ,Pin direction for pin P7_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP7[11] ,Pin direction for pin P7_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP7[10] ,Pin direction for pin P7_10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIRP7[9] ,Pin direction for pin P7_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP7[8] ,Pin direction for pin P7_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP7[7] ,Pin direction for pin P7_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP7[6] ,Pin direction for pin P7_6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DIRP7[5] ,Pin direction for pin P7_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP7[4] ,Pin direction for pin P7_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP7[3] ,Pin direction for pin P7_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP7[2] ,Pin direction for pin P7_2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIRP7[1] ,Pin direction for pin P7_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP7[0] ,Pin direction for pin P7_0" "Input,Output"
|
|
group.long 0x209c++0x3
|
|
line.long 0x00 "MASK7,GPIO mask port 7 register"
|
|
bitfld.long 0x00 25. " MASKP7[25] ,Mask for pin P7_25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " MASKP7[24] ,Mask for pin P7_24" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MASKP7[23] ,Mask for pin P7_23" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " MASKP7[22] ,Mask for pin P7_22" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MASKP7[21] ,Mask for pin P7_21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " MASKP7[20] ,Mask for pin P7_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MASKP7[19] ,Mask for pin P7_19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " MASKP7[18] ,Mask for pin P7_18" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MASKP7[17] ,Mask for pin P7_17" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " MASKP7[16] ,Mask for pin P7_16" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MASKP7[15] ,Mask for pin P7_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP7[14] ,Mask for pin P7_14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASKP7[13] ,Mask for pin P7_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASKP7[12] ,Mask for pin P7_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP7[11] ,Mask for pin P7_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP7[10] ,Mask for pin P7_10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MASKP7[9] ,Mask for pin P7_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP7[8] ,Mask for pin P7_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP7[7] ,Mask for pin P7_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP7[6] ,Mask for pin P7_6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MASKP7[5] ,Mask for pin P7_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP7[4] ,Mask for pin P7_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP7[3] ,Mask for pin P7_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP7[2] ,Mask for pin P7_2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASKP7[1] ,Mask for pin P7_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP7[0] ,Mask for pin P7_0" "Not masked,Masked"
|
|
group.long 0x211c++0x3
|
|
line.long 0x00 "PIN7,GPIO port 7 pin register"
|
|
bitfld.long 0x00 25. " PORT7[25] ,P7_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " PORT7[23] ,P7_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PORT7[23] ,P7_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " PORT7[22] ,P7_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PORT7[21] ,P7_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " PORT7[20] ,P7_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PORT7[19] ,P7_19 pin state" "Low,High"
|
|
bitfld.long 0x00 18. " PORT7[18] ,P7_18 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PORT7[17] ,P7_17 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " PORT7[16] ,P7_16 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PORT7[15] ,P7_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " PORT7[14] ,P7_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PORT7[13] ,P7_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " PORT7[12] ,P7_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT7[11] ,P7_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " PORT7[10] ,P7_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PORT7[9] ,P7_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " PORT7[8] ,P7_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT7[7] ,P7_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " PORT7[6] ,P7_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PORT7[5] ,P7_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " PORT7[4] ,P7_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT7[3] ,P7_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " PORT7[2] ,P7_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PORT7[1] ,P7_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " PORT7[0] ,P7_0 pin state" "Low,High"
|
|
group.long 0x219c++0x3
|
|
line.long 0x00 "MPIN7,GPIO masked port 7 pin register"
|
|
bitfld.long 0x00 25. " MPORTP7[25] ,Masked P7_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " MPORTP7[24] ,Masked P7_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MPORTP7[23] ,Masked P7_23 pin state" "Low,High"
|
|
bitfld.long 0x00 22. " MPORTP7[22] ,Masked P7_22 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MPORTP7[21] ,Masked P7_21 pin state" "Low,High"
|
|
bitfld.long 0x00 20. " MPORTP7[20] ,Masked P7_20 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MPORTP7[19] ,Masked P7_19 pin state" "Low,High"
|
|
bitfld.long 0x00 18. " MPORTP7[18] ,Masked P7_18 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MPORTP7[17] ,Masked P7_17 pin state" "Low,High"
|
|
bitfld.long 0x00 16. " MPORTP7[16] ,Masked P7_16 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MPORTP7[15] ,Masked P7_15 pin state" "Low,High"
|
|
bitfld.long 0x00 14. " MPORTP7[14] ,Masked P7_14 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MPORTP7[13] ,Masked P7_13 pin state" "Low,High"
|
|
bitfld.long 0x00 12. " MPORTP7[12] ,Masked P7_12 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP7[11] ,Masked P7_11 pin state" "Low,High"
|
|
bitfld.long 0x00 10. " MPORTP7[10] ,Masked P7_10 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPORTP7[9] ,Masked P7_9 pin state" "Low,High"
|
|
bitfld.long 0x00 8. " MPORTP7[8] ,Masked P7_8 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP7[7] ,Masked P7_7 pin state" "Low,High"
|
|
bitfld.long 0x00 6. " MPORTP7[6] ,Masked P7_6 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MPORTP7[5] ,Masked P7_5 pin state" "Low,High"
|
|
bitfld.long 0x00 4. " MPORTP7[4] ,Masked P7_4 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP7[3] ,Masked P7_3 pin state" "Low,High"
|
|
bitfld.long 0x00 2. " MPORTP7[2] ,Masked P7_2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MPORTP7[1] ,Masked P7_1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " MPORTP7[0] ,Masked P7_0 pin state" "Low,High"
|
|
group.long 0x221c++0x3
|
|
line.long 0x00 "SET7,GPIO set port 7 register"
|
|
bitfld.long 0x00 25. " SETP7[25] ,State/Set P7_25 pin state" "Low,High"
|
|
bitfld.long 0x00 24. " SETP7[24] ,State/Set P7_24 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SETP7[23] ,State/Set P7_23" "Low,High"
|
|
bitfld.long 0x00 22. " SETP7[22] ,State/Set P7_22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SETP7[21] ,State/Set P7_21" "Low,High"
|
|
bitfld.long 0x00 20. " SETP7[20] ,State/Set P7_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SETP7[19] ,State/Set P7_19" "Low,High"
|
|
bitfld.long 0x00 18. " SETP7[18] ,State/Set P7_18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SETP7[17] ,State/Set P7_17" "Low,High"
|
|
bitfld.long 0x00 16. " SETP7[16] ,State/Set P7_16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SETP7[15] ,State/Set P7_15" "Low,High"
|
|
bitfld.long 0x00 14. " SETP7[14] ,State/Set P7_14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SETP7[13] ,State/Set P7_13" "Low,High"
|
|
bitfld.long 0x00 12. " SETP7[12] ,State/Set P7_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETP7[11] ,State/Set P7_11" "Low,High"
|
|
bitfld.long 0x00 10. " SETP7[10] ,State/Set P7_10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SETP7[9] ,State/Set P7_9" "Low,High"
|
|
bitfld.long 0x00 8. " SETP7[8] ,State/Set P7_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SETP7[7] ,State/Set P7_7" "Low,High"
|
|
bitfld.long 0x00 6. " SETP7[6] ,State/Set P7_6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETP7[5] ,State/Set P7_5" "Low,High"
|
|
bitfld.long 0x00 4. " SETP7[4] ,State/Set P7_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SETP7[3] ,State/Set P7_3" "Low,High"
|
|
bitfld.long 0x00 2. " SETP7[2] ,State/Set P7_2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SETP7[1] ,State/Set P7_1" "Low,High"
|
|
bitfld.long 0x00 0. " SETP7[0] ,State/Set P7_0" "Low,High"
|
|
wgroup.long 0x229c++0x3
|
|
line.long 0x00 "CLR7,GPIO clear port 7 register"
|
|
bitfld.long 0x00 25. " CLRP7[25] ,Clear P7_25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CLRP7[24] ,Clear P7_24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLRP7[23] ,Clear P7_23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CLRP7[22] ,Clear P7_22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CLRP7[21] ,Clear P7_21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CLRP7[20] ,Clear P7_20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLRP7[19] ,Clear P7_19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CLRP7[18] ,Clear P7_18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CLRP7[17] ,Clear P7_17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CLRP7[16] ,Clear P7_16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLRP7[15] ,Clear P7_15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLRP7[14] ,Clear P7_14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLRP7[13] ,Clear P7_13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLRP7[12] ,Clear P7_12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLRP7[11] ,Clear P7_11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLRP7[10] ,Clear P7_10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLRP7[9] ,Clear P7_9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLRP7[8] ,Clear P7_8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLRP7[7] ,Clear P7_7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLRP7[6] ,Clear P7_6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLRP7[5] ,Clear P7_5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CLRP7[4] ,Clear P7_4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLRP7[3] ,Clear P7_3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLRP7[2] ,Clear P7_2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLRP7[1] ,Clear P7_1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLRP7[0] ,Clear P7_0" "No effect,Clear"
|
|
wgroup.long 0x231c++0x3
|
|
line.long 0x00 "NOT7,GPIO toggle port 7 register"
|
|
bitfld.long 0x00 25. " NOTP7[25] ,Toggle P7_25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " NOTP7[24] ,Toggle P7_24" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NOTP7[23] ,Toggle P7_23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " NOTP7[22] ,Toggle P7_22" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NOTP7[21] ,Toggle P7_21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " NOTP7[20] ,Toggle P7_20" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTP7[19] ,Toggle P7_19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " NOTP7[18] ,Toggle P7_18" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NOTP7[17] ,Toggle P7_17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " NOTP7[16] ,Toggle P7_16" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTP7[15] ,Toggle P7_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP7[14] ,Toggle P7_14" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOTP7[13] ,Toggle P7_13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " NOTP7[12] ,Toggle P7_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP7[11] ,Toggle P7_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP7[10] ,Toggle P7_10" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOTP7[9] ,Toggle P7_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP7[8] ,Toggle P7_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP7[7] ,Toggle P7_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP7[6] ,Toggle P7_6" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOTP7[5] ,Toggle P7_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP7[4] ,Toggle P7_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP7[3] ,Toggle P7_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP7[2] ,Toggle P7_2" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTP7[1] ,Toggle P7_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP7[0] ,Toggle P7_0" "No effect,Toggle"
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "GPDMA (General Purpose DMA)"
|
|
base ad:0x40002000
|
|
width 15.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "INTSTAT,DMA Interrupt Status register"
|
|
bitfld.long 0x00 7. " INTSTAT7 ,DMA channel 7 interrupt after masking" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTSTAT6 ,DMA channel 6 interrupt after masking" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTSTAT5 ,DMA channel 5 interrupt after masking" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTSTAT4 ,DMA channel 4 interrupt after masking" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INTSTAT3 ,DMA channel 3 interrupt after masking" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTSTAT2 ,DMA channel 2 interrupt after masking" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTSTAT1 ,DMA channel 1 interrupt after masking" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTSTAT0 ,DMA channel 0 interrupt after masking" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTTCSTAT,DMA Interrupt Terminal Count Request Status Register"
|
|
bitfld.long 0x04 7. " INTTCSTAT7 ,DMA channel 7 terminal count interrupt request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTTCSTAT6 ,DMA channel 6 terminal count interrupt request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTTCSTAT5 ,DMA channel 5 terminal count interrupt request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTTCSTAT4 ,DMA channel 4 terminal count interrupt request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " INTTCSTAT3 ,DMA channel 3 terminal count interrupt request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTTCSTAT2 ,DMA channel 2 terminal count interrupt request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTTCSTAT1 ,TDMA channel 1 terminal count interrupt request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTTCSTAT0 ,DMA channel 0 terminal count interrupt request status" "No interrupt,Interrupt"
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "INTTCCLEAR,DMA Interrupt Terminal Count Request Clear Register"
|
|
bitfld.long 0x00 7. " INTTCCLEAR7 ,DMA channel 7 terminal count interrupt request clear" "No action,Clear"
|
|
bitfld.long 0x00 6. " INTTCCLEAR6 ,DMA channel 6 terminal count interrupt request clear" "No action,Clear"
|
|
bitfld.long 0x00 5. " INTTCCLEAR5 ,DMA channel 5 terminal count interrupt request clear" "No action,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTTCCLEAR4 ,DMA channel 4 terminal count interrupt request clear" "No action,Clear"
|
|
bitfld.long 0x00 3. " INTTCCLEAR3 ,DMA channel 3 terminal count interrupt request clear" "No action,Clear"
|
|
bitfld.long 0x00 2. " INTTCCLEAR2 ,DMA channel 2 terminal count interrupt request clear" "No action,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTTCCLEAR1 ,DMA channel 1 terminal count interrupt request clear" "No action,Clear"
|
|
bitfld.long 0x00 0. " INTTCCLEAR0 ,DMA channel 0 terminal count interrupt request clear" "No action,Clear"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 "INTERRSTAT,DMA Interrupt Error Status Register"
|
|
bitfld.long 0x00 7. " INTERRSTAT7 ,DMA channel 7 interrupt error status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTERRSTAT6 ,DMA channel 6 interrupt error status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTERRSTAT5 ,DMA channel 5 interrupt error status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTERRSTAT4 ,DMA channel 4 interrupt error status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " INTERRSTAT3 ,DMA channel 3 interrupt error status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTERRSTAT2 ,DMA channel 2 interrupt error status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTERRSTAT1 ,DMA channel 1 interrupt error status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTERRSTAT0 ,DMA channel 0 interrupt error status" "No interrupt,Interrupt"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x00 "INTERRCLR,DMA Interrupt Error Clear Register"
|
|
bitfld.long 0x00 7. " INTERRCLR7 ,DMA channel 7 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " INTERRCLR6 ,DMA channel 6 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " INTERRCLR5 ,DMA channel 5 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTERRCLR4 ,DMA channel 4 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " INTERRCLR3 ,DMA channel 3 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " INTERRCLR2 ,DMA channel 2 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTERRCLR1 ,DMA channel 1 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " INTERRCLR0 ,DMA channel 0 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
rgroup.long 0x14++0xB
|
|
line.long 0x00 "RAWINTTCSTAT,DMA Raw Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 7. " RAWINTTCSTAT7 ,DMA channel 7 raw interrupt terminal count status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RAWINTTCSTAT6 ,DMA channel 6 raw interrupt terminal count status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RAWINTTCSTAT5 ,DMA channel 5 raw interrupt terminal count status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RAWINTTCSTAT4 ,DMA channel 4 raw interrupt terminal count status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RAWINTTCSTAT3 ,DMA channel 3 raw interrupt terminal count status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWINTTCSTAT2 ,DMA channel 2 raw interrupt terminal count status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWINTTCSTAT1 ,DMA channel 1 raw interrupt terminal count status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWINTTCSTAT0 ,DMA channel 0 raw interrupt terminal count status" "No interrupt,Interrupt"
|
|
line.long 0x04 "RAWINTERRSTAT,DMA Raw Error Interrupt Status Register"
|
|
bitfld.long 0x04 7. " RAWINTERRSTAT7 ,DMA Channel 7 Raw Error Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RAWINTERRSTAT6 ,DMA Channel 6 Raw Error Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " RAWINTERRSTAT5 ,DMA Channel 5 Raw Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RAWINTERRSTAT4 ,DMA Channel 4 Raw Error Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " RAWINTERRSTAT3 ,DMA Channel 3 Raw Error Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RAWINTERRSTAT2 ,DMA Channel 2 Raw Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RAWINTERRSTAT1 ,DMA Channel 1 Raw Error Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RAWINTERRSTAT0 ,DMA Channel 0 Raw Error Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "ENABLEDCHNS,DMA Enabled Channel Register"
|
|
bitfld.long 0x08 7. " ENABLEDCHANNELS7 ,DMA Channel 7 Enabled " "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " ENABLEDCHANNELS6 ,DMA Channel 6 Enabled " "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " ENABLEDCHANNELS5 ,DMA Channel 5 Enabled " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " ENABLEDCHANNELS4 ,DMA Channel 4 Enabled " "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " ENABLEDCHANNELS3 ,DMA Channel 3 Enabled " "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " ENABLEDCHANNELS2 ,DMA Channel 2 Enabled " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ENABLEDCHANNELS1 ,DMA Channel 1 Enabled " "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLEDCHANNELS0 ,DMA Channel 0 Enabled " "Disabled,Enabled"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "SOFTBREQ,DMA Software Burst Request Register"
|
|
bitfld.long 0x00 15. " SOFTBREQ15 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 14. " SOFTBREQ14 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 13. " SOFTBREQ13 ,Software burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SOFTBREQ12 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 11. " SOFTBREQ11 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 10. " SOFTBREQ10 ,Software burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SOFTBREQ9 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 8. " SOFTBREQ8 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 7. " SOFTBREQ7 ,Software burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SOFTBREQ6 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 5. " SOFTBREQ5 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 4. " SOFTBREQ4 ,Software burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOFTBREQ3 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 2. " SOFTBREQ2 ,Software burst request flag" "No effect,Requested"
|
|
bitfld.long 0x00 1. " SOFTBREQ1 ,Software burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTBREQ0 ,Software burst request flag" "No effect,Requested"
|
|
line.long 0x04 "SOFTSREQ,DMA Software Single Request Register"
|
|
bitfld.long 0x04 15. " SOFTSREQ15 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 14. " SOFTSREQ14 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 13. " SOFTSREQ13 ,Software single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SOFTSREQ12 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 11. " SOFTSREQ11 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 10. " SOFTSREQ10 ,Software single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SOFTSREQ9 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 8. " SOFTSREQ8 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 7. " SOFTSREQ7 ,Software single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 6. " SOFTSREQ6 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 5. " SOFTSREQ5 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 4. " SOFTSREQ4 ,Software single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SOFTSREQ3 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 2. " SOFTSREQ2 ,Software single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x04 1. " SOFTSREQ1 ,Software single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SOFTSREQ0 ,Software single transfer request flag" "No effect,Requested"
|
|
line.long 0x08 "SOFTLBREQ,Software Last Burst Request Register"
|
|
bitfld.long 0x08 15. " SOFTLBREQ15 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 14. " SOFTLBREQ14 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 13. " SOFTLBREQ13 ,Software last burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 12. " SOFTLBREQ12 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 11. " SOFTLBREQ11 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 10. " SOFTLBREQ10 ,Software last burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SOFTLBREQ9 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 8. " SOFTLBREQ8 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 7. " SOFTLBREQ7 ,Software last burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SOFTLBREQ6 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 5. " SOFTLBREQ5 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 4. " SOFTLBREQ4 ,Software last burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SOFTLBREQ3 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 2. " SOFTLBREQ2 ,Software last burst request flag" "No effect,Requested"
|
|
bitfld.long 0x08 1. " SOFTLBREQ1 ,Software last burst request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SOFTLBREQ0 ,Software last burst request flag" "No effect,Requested"
|
|
line.long 0x0C "SOFTLSREQ,DMA Software Last Single Request Register"
|
|
bitfld.long 0x0C 15. " SOFTLSREQ15 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 14. " SOFTLSREQ14 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 13. " SOFTLSREQ13 ,Software last single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " SOFTLSREQ12 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 11. " SOFTLSREQ11 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 10. " SOFTLSREQ10 ,Software last single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SOFTLSREQ9 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 8. " SOFTLSREQ8 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 7. " SOFTLSREQ7 ,Software last single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SOFTLSREQ6 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 5. " SOFTLSREQ5 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 4. " SOFTLSREQ4 ,Software last single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SOFTLSREQ3 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 2. " SOFTLSREQ2 ,Software last single transfer request flag" "No effect,Requested"
|
|
bitfld.long 0x0C 1. " SOFTLSREQ1 ,Software last single transfer request flag" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " SOFTLSREQ0 ,Software last single transfer request flag" "No effect,Requested"
|
|
line.long 0x10 "CONFIG,DMA Configuration Register"
|
|
bitfld.long 0x10 2. " M1 ,AHB Master 1 endianness configuration" "Little-endian,Big-endian"
|
|
bitfld.long 0x10 1. " M0 ,AHB Master 0 endianness configuration" "Little-endian,Big-endian"
|
|
bitfld.long 0x10 0. " E ,DMA Controller enable" "Disabled,Enabled"
|
|
line.long 0x14 "SYNC,DMA Synchronization Register"
|
|
bitfld.long 0x14 15. " DMACSYNC15 ,Synchronization logic group 15 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 14. " DMACSYNC14 ,Synchronization logic group 14 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 13. " DMACSYNC13 ,Synchronization logic group 13 of DMA requests" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " DMACSYNC12 ,Synchronization logic group 12 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 11. " DMACSYNC11 ,Synchronization logic group 11 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 10. " DMACSYNC10 ,Synchronization logic group 10 of DMA requests" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DMACSYNC9 ,Synchronization logic group 9 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 8. " DMACSYNC8 ,Synchronization logic group 8 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 7. " DMACSYNC7 ,Synchronization logic group 7 of DMA requests" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DMACSYNC6 ,Synchronization logic group 6 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 5. " DMACSYNC5 ,Synchronization logic group 5 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 4. " DMACSYNC4 ,Synchronization logic group 4 of DMA requests" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DMACSYNC3 ,Synchronization logic group 3 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 2. " DMACSYNC2 ,Synchronization logic group 2 of DMA requests" "Enabled,Disabled"
|
|
bitfld.long 0x14 1. " DMACSYNC1 ,Synchronization logic group 1 of DMA requests" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " DMACSYNC0 ,Synchronization logic group 0 of DMA requests" "Enabled,Disabled"
|
|
tree "DMA Channel 0 registers"
|
|
width 11.
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "SRCADDR0,DMA Channel 0 Source Address Registers"
|
|
line.long 0x04 "DESTADDR0,DMA Channel 0 Destination Address register"
|
|
line.long 0x08 "LLI0,DMA Channel 0 Linked List Item register"
|
|
hexmask.long 0x08 2.--31. 4. " LLI ,Linked list item"
|
|
bitfld.long 0x08 0. " LM ,AHB master select for loading the next LLI" "0,1"
|
|
line.long 0x0C "CONTROL0,DMA Channel 0 Control register"
|
|
bitfld.long 0x0C 31. " I ,Terminal count interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PROT3 , Access cacheable" "Not cacheable,Cacheable"
|
|
bitfld.long 0x0C 29. " PROT2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0x0C 28. " PROT1 ,Access mode" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DI ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 26. " SI ,Source increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 25. " D ,Destination AHB master select" "0,1"
|
|
bitfld.long 0x0C 24. " S ,Source AHB master select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " DWIDTH ,Destination transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 18.--20. " SWIDTH ,Source transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 15.--17. " DBSIZE ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0C 12.--14. " SBSIZE ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TRANSFERSIZE ,Transfer size in number of transfers"
|
|
textline " "
|
|
line.long 0x10 "CONFIG0,DMA Channel 0 Configuration register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Not halted,Halted"
|
|
bitfld.long 0x10 17. " A ,Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "0,1"
|
|
bitfld.long 0x10 11.--13. " FLOWCNTRL ,Flow control and transfer type" "Memory to memory(DMA control),Memory to peripheral(DMA control),Peripheral to memory(DMA control),Source peripheral to destination peripheral,Source peripheral to destination peripheral,Memory to peripheral (peripheral control),Peripheral to memory (peripheral control),Source peripheral to destination peripheral"
|
|
textline " "
|
|
textline " "
|
|
sif (cpuis("LPC43*")&&!cpuis("LPC4370*")&&!cpuis("LPC43S70*"))
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")||cpuis("LPC43S70FET256*")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1t/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DMA Channel 1 registers"
|
|
width 11.
|
|
group.long 0x120++0x13
|
|
line.long 0x00 "SRCADDR1,DMA Channel 1 Source Address Registers"
|
|
line.long 0x04 "DESTADDR1,DMA Channel 1 Destination Address register"
|
|
line.long 0x08 "LLI1,DMA Channel 1 Linked List Item register"
|
|
hexmask.long 0x08 2.--31. 4. " LLI ,Linked list item"
|
|
bitfld.long 0x08 0. " LM ,AHB master select for loading the next LLI" "0,1"
|
|
line.long 0x0C "CONTROL1,DMA Channel 1 Control register"
|
|
bitfld.long 0x0C 31. " I ,Terminal count interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PROT3 , Access cacheable" "Not cacheable,Cacheable"
|
|
bitfld.long 0x0C 29. " PROT2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0x0C 28. " PROT1 ,Access mode" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DI ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 26. " SI ,Source increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 25. " D ,Destination AHB master select" "0,1"
|
|
bitfld.long 0x0C 24. " S ,Source AHB master select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " DWIDTH ,Destination transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 18.--20. " SWIDTH ,Source transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 15.--17. " DBSIZE ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0C 12.--14. " SBSIZE ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TRANSFERSIZE ,Transfer size in number of transfers"
|
|
textline " "
|
|
line.long 0x10 "CONFIG1,DMA Channel 1 Configuration register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Not halted,Halted"
|
|
bitfld.long 0x10 17. " A ,Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "0,1"
|
|
bitfld.long 0x10 11.--13. " FLOWCNTRL ,Flow control and transfer type" "Memory to memory(DMA control),Memory to peripheral(DMA control),Peripheral to memory(DMA control),Source peripheral to destination peripheral,Source peripheral to destination peripheral,Memory to peripheral (peripheral control),Peripheral to memory (peripheral control),Source peripheral to destination peripheral"
|
|
textline " "
|
|
textline " "
|
|
sif (cpuis("LPC43*")&&!cpuis("LPC4370*")&&!cpuis("LPC43S70*"))
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")||cpuis("LPC43S70FET256*")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1t/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DMA Channel 2 registers"
|
|
width 11.
|
|
group.long 0x140++0x13
|
|
line.long 0x00 "SRCADDR2,DMA Channel 2 Source Address Registers"
|
|
line.long 0x04 "DESTADDR2,DMA Channel 2 Destination Address register"
|
|
line.long 0x08 "LLI2,DMA Channel 2 Linked List Item register"
|
|
hexmask.long 0x08 2.--31. 4. " LLI ,Linked list item"
|
|
bitfld.long 0x08 0. " LM ,AHB master select for loading the next LLI" "0,1"
|
|
line.long 0x0C "CONTROL2,DMA Channel 2 Control register"
|
|
bitfld.long 0x0C 31. " I ,Terminal count interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PROT3 , Access cacheable" "Not cacheable,Cacheable"
|
|
bitfld.long 0x0C 29. " PROT2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0x0C 28. " PROT1 ,Access mode" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DI ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 26. " SI ,Source increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 25. " D ,Destination AHB master select" "0,1"
|
|
bitfld.long 0x0C 24. " S ,Source AHB master select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " DWIDTH ,Destination transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 18.--20. " SWIDTH ,Source transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 15.--17. " DBSIZE ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0C 12.--14. " SBSIZE ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TRANSFERSIZE ,Transfer size in number of transfers"
|
|
textline " "
|
|
line.long 0x10 "CONFIG2,DMA Channel 2 Configuration register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Not halted,Halted"
|
|
bitfld.long 0x10 17. " A ,Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "0,1"
|
|
bitfld.long 0x10 11.--13. " FLOWCNTRL ,Flow control and transfer type" "Memory to memory(DMA control),Memory to peripheral(DMA control),Peripheral to memory(DMA control),Source peripheral to destination peripheral,Source peripheral to destination peripheral,Memory to peripheral (peripheral control),Peripheral to memory (peripheral control),Source peripheral to destination peripheral"
|
|
textline " "
|
|
textline " "
|
|
sif (cpuis("LPC43*")&&!cpuis("LPC4370*")&&!cpuis("LPC43S70*"))
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")||cpuis("LPC43S70FET256*")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1t/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DMA Channel 3 registers"
|
|
width 11.
|
|
group.long 0x160++0x13
|
|
line.long 0x00 "SRCADDR3,DMA Channel 3 Source Address Registers"
|
|
line.long 0x04 "DESTADDR3,DMA Channel 3 Destination Address register"
|
|
line.long 0x08 "LLI3,DMA Channel 3 Linked List Item register"
|
|
hexmask.long 0x08 2.--31. 4. " LLI ,Linked list item"
|
|
bitfld.long 0x08 0. " LM ,AHB master select for loading the next LLI" "0,1"
|
|
line.long 0x0C "CONTROL3,DMA Channel 3 Control register"
|
|
bitfld.long 0x0C 31. " I ,Terminal count interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PROT3 , Access cacheable" "Not cacheable,Cacheable"
|
|
bitfld.long 0x0C 29. " PROT2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0x0C 28. " PROT1 ,Access mode" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DI ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 26. " SI ,Source increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 25. " D ,Destination AHB master select" "0,1"
|
|
bitfld.long 0x0C 24. " S ,Source AHB master select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " DWIDTH ,Destination transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 18.--20. " SWIDTH ,Source transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 15.--17. " DBSIZE ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0C 12.--14. " SBSIZE ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TRANSFERSIZE ,Transfer size in number of transfers"
|
|
textline " "
|
|
line.long 0x10 "CONFIG3,DMA Channel 3 Configuration register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Not halted,Halted"
|
|
bitfld.long 0x10 17. " A ,Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "0,1"
|
|
bitfld.long 0x10 11.--13. " FLOWCNTRL ,Flow control and transfer type" "Memory to memory(DMA control),Memory to peripheral(DMA control),Peripheral to memory(DMA control),Source peripheral to destination peripheral,Source peripheral to destination peripheral,Memory to peripheral (peripheral control),Peripheral to memory (peripheral control),Source peripheral to destination peripheral"
|
|
textline " "
|
|
textline " "
|
|
sif (cpuis("LPC43*")&&!cpuis("LPC4370*")&&!cpuis("LPC43S70*"))
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")||cpuis("LPC43S70FET256*")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1t/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DMA Channel 4 registers"
|
|
width 11.
|
|
group.long 0x180++0x13
|
|
line.long 0x00 "SRCADDR4,DMA Channel 4 Source Address Registers"
|
|
line.long 0x04 "DESTADDR4,DMA Channel 4 Destination Address register"
|
|
line.long 0x08 "LLI4,DMA Channel 4 Linked List Item register"
|
|
hexmask.long 0x08 2.--31. 4. " LLI ,Linked list item"
|
|
bitfld.long 0x08 0. " LM ,AHB master select for loading the next LLI" "0,1"
|
|
line.long 0x0C "CONTROL4,DMA Channel 4 Control register"
|
|
bitfld.long 0x0C 31. " I ,Terminal count interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PROT3 , Access cacheable" "Not cacheable,Cacheable"
|
|
bitfld.long 0x0C 29. " PROT2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0x0C 28. " PROT1 ,Access mode" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DI ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 26. " SI ,Source increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 25. " D ,Destination AHB master select" "0,1"
|
|
bitfld.long 0x0C 24. " S ,Source AHB master select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " DWIDTH ,Destination transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 18.--20. " SWIDTH ,Source transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 15.--17. " DBSIZE ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0C 12.--14. " SBSIZE ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TRANSFERSIZE ,Transfer size in number of transfers"
|
|
textline " "
|
|
line.long 0x10 "CONFIG4,DMA Channel 4 Configuration register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Not halted,Halted"
|
|
bitfld.long 0x10 17. " A ,Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "0,1"
|
|
bitfld.long 0x10 11.--13. " FLOWCNTRL ,Flow control and transfer type" "Memory to memory(DMA control),Memory to peripheral(DMA control),Peripheral to memory(DMA control),Source peripheral to destination peripheral,Source peripheral to destination peripheral,Memory to peripheral (peripheral control),Peripheral to memory (peripheral control),Source peripheral to destination peripheral"
|
|
textline " "
|
|
textline " "
|
|
sif (cpuis("LPC43*")&&!cpuis("LPC4370*")&&!cpuis("LPC43S70*"))
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")||cpuis("LPC43S70FET256*")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1t/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DMA Channel 5 registers"
|
|
width 11.
|
|
group.long 0x1A0++0x13
|
|
line.long 0x00 "SRCADDR5,DMA Channel 5 Source Address Registers"
|
|
line.long 0x04 "DESTADDR5,DMA Channel 5 Destination Address register"
|
|
line.long 0x08 "LLI5,DMA Channel 5 Linked List Item register"
|
|
hexmask.long 0x08 2.--31. 4. " LLI ,Linked list item"
|
|
bitfld.long 0x08 0. " LM ,AHB master select for loading the next LLI" "0,1"
|
|
line.long 0x0C "CONTROL5,DMA Channel 5 Control register"
|
|
bitfld.long 0x0C 31. " I ,Terminal count interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PROT3 , Access cacheable" "Not cacheable,Cacheable"
|
|
bitfld.long 0x0C 29. " PROT2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0x0C 28. " PROT1 ,Access mode" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DI ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 26. " SI ,Source increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 25. " D ,Destination AHB master select" "0,1"
|
|
bitfld.long 0x0C 24. " S ,Source AHB master select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " DWIDTH ,Destination transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 18.--20. " SWIDTH ,Source transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 15.--17. " DBSIZE ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0C 12.--14. " SBSIZE ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TRANSFERSIZE ,Transfer size in number of transfers"
|
|
textline " "
|
|
line.long 0x10 "CONFIG5,DMA Channel 5 Configuration register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Not halted,Halted"
|
|
bitfld.long 0x10 17. " A ,Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "0,1"
|
|
bitfld.long 0x10 11.--13. " FLOWCNTRL ,Flow control and transfer type" "Memory to memory(DMA control),Memory to peripheral(DMA control),Peripheral to memory(DMA control),Source peripheral to destination peripheral,Source peripheral to destination peripheral,Memory to peripheral (peripheral control),Peripheral to memory (peripheral control),Source peripheral to destination peripheral"
|
|
textline " "
|
|
textline " "
|
|
sif (cpuis("LPC43*")&&!cpuis("LPC4370*")&&!cpuis("LPC43S70*"))
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")||cpuis("LPC43S70FET256*")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1t/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DMA Channel 6 registers"
|
|
width 11.
|
|
group.long 0x1C0++0x13
|
|
line.long 0x00 "SRCADDR6,DMA Channel 6 Source Address Registers"
|
|
line.long 0x04 "DESTADDR6,DMA Channel 6 Destination Address register"
|
|
line.long 0x08 "LLI6,DMA Channel 6 Linked List Item register"
|
|
hexmask.long 0x08 2.--31. 4. " LLI ,Linked list item"
|
|
bitfld.long 0x08 0. " LM ,AHB master select for loading the next LLI" "0,1"
|
|
line.long 0x0C "CONTROL6,DMA Channel 6 Control register"
|
|
bitfld.long 0x0C 31. " I ,Terminal count interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PROT3 , Access cacheable" "Not cacheable,Cacheable"
|
|
bitfld.long 0x0C 29. " PROT2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0x0C 28. " PROT1 ,Access mode" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DI ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 26. " SI ,Source increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 25. " D ,Destination AHB master select" "0,1"
|
|
bitfld.long 0x0C 24. " S ,Source AHB master select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " DWIDTH ,Destination transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 18.--20. " SWIDTH ,Source transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 15.--17. " DBSIZE ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0C 12.--14. " SBSIZE ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TRANSFERSIZE ,Transfer size in number of transfers"
|
|
textline " "
|
|
line.long 0x10 "CONFIG6,DMA Channel 6 Configuration register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Not halted,Halted"
|
|
bitfld.long 0x10 17. " A ,Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "0,1"
|
|
bitfld.long 0x10 11.--13. " FLOWCNTRL ,Flow control and transfer type" "Memory to memory(DMA control),Memory to peripheral(DMA control),Peripheral to memory(DMA control),Source peripheral to destination peripheral,Source peripheral to destination peripheral,Memory to peripheral (peripheral control),Peripheral to memory (peripheral control),Source peripheral to destination peripheral"
|
|
textline " "
|
|
textline " "
|
|
sif (cpuis("LPC43*")&&!cpuis("LPC4370*")&&!cpuis("LPC43S70*"))
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")||cpuis("LPC43S70FET256*")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1t/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DMA Channel 7 registers"
|
|
width 11.
|
|
group.long 0x1E0++0x13
|
|
line.long 0x00 "SRCADDR7,DMA Channel 7 Source Address Registers"
|
|
line.long 0x04 "DESTADDR7,DMA Channel 7 Destination Address register"
|
|
line.long 0x08 "LLI7,DMA Channel 7 Linked List Item register"
|
|
hexmask.long 0x08 2.--31. 4. " LLI ,Linked list item"
|
|
bitfld.long 0x08 0. " LM ,AHB master select for loading the next LLI" "0,1"
|
|
line.long 0x0C "CONTROL7,DMA Channel 7 Control register"
|
|
bitfld.long 0x0C 31. " I ,Terminal count interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PROT3 , Access cacheable" "Not cacheable,Cacheable"
|
|
bitfld.long 0x0C 29. " PROT2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0x0C 28. " PROT1 ,Access mode" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DI ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 26. " SI ,Source increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 25. " D ,Destination AHB master select" "0,1"
|
|
bitfld.long 0x0C 24. " S ,Source AHB master select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " DWIDTH ,Destination transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 18.--20. " SWIDTH ,Source transfer width" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x0C 15.--17. " DBSIZE ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0C 12.--14. " SBSIZE ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TRANSFERSIZE ,Transfer size in number of transfers"
|
|
textline " "
|
|
line.long 0x10 "CONFIG7,DMA Channel 7 Configuration register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Not halted,Halted"
|
|
bitfld.long 0x10 17. " A ,Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "0,1"
|
|
bitfld.long 0x10 11.--13. " FLOWCNTRL ,Flow control and transfer type" "Memory to memory(DMA control),Memory to peripheral(DMA control),Peripheral to memory(DMA control),Source peripheral to destination peripheral,Source peripheral to destination peripheral,Memory to peripheral (peripheral control),Peripheral to memory (peripheral control),Source peripheral to destination peripheral"
|
|
textline " "
|
|
textline " "
|
|
sif (cpuis("LPC43*")&&!cpuis("LPC4370*")&&!cpuis("LPC43S70*"))
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0,Timer3 match 1/UART3 receive/SCT DMA request 1,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4370FET100")||(cpu()=="LPC4370FET256")||(cpu()=="LPC4370FET100-M0")||(cpu()=="LPC4370FET256-M0")||cpuis("LPC43S70FET256*")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match 2/SGPIO14/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15,Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14,Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS write,Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/SGPIO14/USART0 transmit,SSP1 transmit/SGPIO15/USART0 receive,ADC0/SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/SGPIO15/Timer3 match 0,?..."
|
|
textline " "
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "(unused)/T0_MAT[0],SD card/T0_MAT[1],SSP0 Tx/T1_MAT[0],SSP0 Rx/T1_MAT[1],SSP1 Tx/T2_MAT[0],SSP1 Rx/T2_MAT[1],SSP2 TX/I2S channel 0,SSP2 Rx/I2S channel 1,ADC,DAC,UART0 Tx/UART3 Tx,UART0 Rx/UART3 Rx,UART1 Tx/UART4 Tx,UART1 Rx/UART4 Rx,UART2 Tx/T3_MAT[0],UART2 Rx/T3_MAT[1],?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 6.--10. " DESTPERIPHERAL ,Destination peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SRCPERIPHERAL ,Source peripheral" "SPIFI/SCT match3/Timer3 match 1,Timer0 match 0/USART0 transmit,Timer0 match 1/USART0 receive,Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1 transmit,Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1 receive,Timer2 match 0/USART2 transmit/SSP1 transmit,Timer2 match 1/USART2 receive/SSP1 receive,Timer3 match 0/UART3 transmit/SCT DMA request 0/VADC write,Timer3 match 1/UART3 receive/SCT DMA request 1/VADC read,SSP0 receive/I2S0 DMA request 1/SCT DMA request 1,SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0,SSP1 receive/USART0 transmit,SSP1 transmit/USART0 receive,ADC0//SSP1 receive/USART3 receive,ADC1t/SSP1 transmit/USART3 transmit,DAC/SCT match 3/Timer3 match 0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "SD (SD/MMC interface)"
|
|
base ad:0x40004000
|
|
width 9.
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 25. " USE_INTERNAL_DMAC ,SD/MMC DMA use" "Slave interface,Internal DMA"
|
|
bitfld.long 0x00 18. " CARD_VOLTAGE_A2 ,Controls the state of the SD_VOLT2 pin" "0,1"
|
|
bitfld.long 0x00 17. " CARD_VOLTAGE_A1 ,Controls the state of the SD_VOLT1 pin" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CARD_VOLTAGE_A0 ,Controls the state of the SD_VOLT0 pin" "0,1"
|
|
bitfld.long 0x00 11. " CEATA_DEV_INT_STATUS ,CEATA device interrupt status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SEND_AUTO_STOP_CCSD ,Send auto stop ccsd" "Clear,Send"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SEND_CCSD ,Send ccsd" "Clear,Send"
|
|
bitfld.long 0x00 8. " ABORT_READ_DATA ,Abort read data" "No change,Suspended"
|
|
bitfld.long 0x00 7. " SEND_IRQ_RESPONSE ,Send irq response" "No change,Send"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_WAIT ,Read/wait" "Clear,Assert"
|
|
bitfld.long 0x00 4. " INT_ENABLE ,Global interrupt enable/disable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMA_RESET ,Dma_reset" "No change,Reset"
|
|
bitfld.long 0x00 1. " FIFO_RESET ,Fifo reset" "No change,Reset"
|
|
bitfld.long 0x00 0. " CONTROLLER_RESET ,Controller reset" "No change,Reset"
|
|
line.long 0x04 "PWREN,Power Enable Register"
|
|
bitfld.long 0x04 0. " POWER_ENABLE ,Power on/off switch for card" "Power off,Power on"
|
|
line.long 0x08 "CLKDIV,Clock Divider Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CLK_DIVIDER3 ,Clock divider-3 value"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CLK_DIVIDER2 ,Clock divider-2 value"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CLK_DIVIDER1 ,Clock divider-1 value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " CLK_DIVIDER0 ,Clock divider-0 value"
|
|
line.long 0x0C "CLKSRC,SD Clock Source Register"
|
|
bitfld.long 0x0C 0.--1. " CLK_SOURCE ,Clock divider source for SD card" "/0,/1,/2,/3"
|
|
line.long 0x10 "CLKENA,Clock Enable Register"
|
|
bitfld.long 0x10 16. " CCLK_LOW_POWER ,Low-power control for SD card clock" "Non-low-power,Low-power"
|
|
bitfld.long 0x10 0. " CCLK_ENABLE ,Clock-enable control for SD card clock" "Disabled,Enabled"
|
|
line.long 0x14 "TMOUT,Time-out Register"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. " DATA_TIMEOUT ,Value for card Data Read time-out"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RESPONSE_TIMEOUT ,Response time-out value"
|
|
line.long 0x18 "CTYPE,Card Type Register"
|
|
bitfld.long 0x18 16. " CARD_WIDTH1 ,Indicates if card is 8-bit" "Non 8-bit,8-bit"
|
|
bitfld.long 0x18 0. " CARD_WIDTH0 ,Indicates if card is 1-bit or 4-bit" "1-bit,4-bit"
|
|
line.long 0x1C "BLKSIZ,Block Size Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " BLOCK_SIZE ,Block size"
|
|
line.long 0x20 "BYTCNT,Byte Count Register"
|
|
line.long 0x24 "INTMASK,Interrupt Mask Register"
|
|
bitfld.long 0x24 16. " SDIO_INT_MASK ,Mask SDIO interrupt" "Masked,Not masked"
|
|
bitfld.long 0x24 15. " EBE ,End-bit error (read)/Write no CRC" "Masked,Not masked"
|
|
bitfld.long 0x24 14. " ACD ,Auto command done" "Masked,Not masked"
|
|
bitfld.long 0x24 13. " SBE ,Start-bit error" "Masked,Not masked"
|
|
bitfld.long 0x24 12. " HLE ,Hardware locked write error" "Masked,Not masked"
|
|
bitfld.long 0x24 11. " FRUN ,FIFO underrun/overrun error" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x24 10. " HTO ,Data starvation-by-host time-out (HTO) /Volt_switch_int" "Masked,Not masked"
|
|
bitfld.long 0x24 9. " DRTO ,Data read time-out" "Masked,Not masked"
|
|
bitfld.long 0x24 8. " RTO ,Response time-out" "Masked,Not masked"
|
|
bitfld.long 0x24 7. " DCRC ,Data CRC error" "Masked,Not masked"
|
|
bitfld.long 0x24 6. " RCRC ,Response CRC error" "Masked,Not masked"
|
|
bitfld.long 0x24 5. " RXDR ,Receive FIFO data request" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x24 4. " TXDR ,Transmit FIFO data request" "Masked,Not masked"
|
|
bitfld.long 0x24 3. " DTO ,Data transfer over" "Masked,Not masked"
|
|
bitfld.long 0x24 2. " CDONE ,Command done" "Masked,Not masked"
|
|
bitfld.long 0x24 1. " RE ,Response error" "Masked,Not masked"
|
|
bitfld.long 0x24 0. " CDET ,Card detect" "Masked,Not masked"
|
|
line.long 0x28 "CMDARG,Command Argument Register"
|
|
line.long 0x2C "CMD,Command Register"
|
|
bitfld.long 0x2C 31. " START_CMD ,Start command" "Disabled,Enabled"
|
|
bitfld.long 0x2C 28. " VOLT_SWITCH ,Voltage switch bit" "Disabled,Enabled"
|
|
bitfld.long 0x2C 27. " BOOT_MODE ,Boot Mode" "Mandatory,Alternate"
|
|
bitfld.long 0x2C 26. " DISABLE_BOOT ,Disable Boot" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 25. " EXPECT_BOOT_ACK ,Expect Boot Acknowledge" "Not expected,Expected"
|
|
bitfld.long 0x2C 24. " ENABLE_BOOT ,Enable Boot" "Disabled,Enabled"
|
|
bitfld.long 0x2C 23. " CCS_EXPECTED ,CCS expected" "Disabled,Enabled"
|
|
bitfld.long 0x2C 22. " READ_CEATA_DEV ,Read ceata device" "Not performing,Performing"
|
|
textline " "
|
|
bitfld.long 0x2C 21. " UPD_CLK_REG_ONLY ,Update clock registers only" "Normal,Update"
|
|
bitfld.long 0x2C 15. " SEND_INIT ,Send initialization" "Not send,Send"
|
|
bitfld.long 0x2C 14. " STOP_ABORT_CMD ,Stop abort cmd" "Neither stop,Stop"
|
|
bitfld.long 0x2C 13. " WAIT_PRVDATA_COMPL ,Wait prvdata complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " SEND_AUTO_STOP ,Send auto stop" "Not send,Send"
|
|
bitfld.long 0x2C 11. " TRANSFER_MODE ,Transfer mode" "Block,Stream"
|
|
bitfld.long 0x2C 10. " READ_WRITE ,Read/write" "Read,Write"
|
|
bitfld.long 0x2C 9. " DATA_EXPECTED ,Data expected" "Not expected,Expected"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " CHECK_RESP_CRC ,Check response CRC" "Not checked,Checked"
|
|
bitfld.long 0x2C 7. " RESP_LENGTH ,Response length" "Short,Long"
|
|
bitfld.long 0x2C 6. " RESP_EXPECT ,Response expect" "Not expected,Expected"
|
|
bitfld.long 0x2C 0.--5. " CMD_INDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x30++0xF
|
|
line.long 0x0 "RESP0,Response Register 0"
|
|
line.long 0x4 "RESP1,Response Register 1"
|
|
line.long 0x8 "RESP2,Response Register 2"
|
|
line.long 0xC "RESP3,Response Register 3"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "MINTSTS,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 16. " SDIO_INT ,Interrupt from SDIO card" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " EBE ,End-bit error" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " ACD ,Auto command done" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " SBE ,Start-bit error" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " HLE ,Hardware locked write error" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " FRUN ,FIFO underrun/overrun error" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HTO ,Data starvation-by-host time-out" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " DRTO ,Data read time-out" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RTO ,Response time-out" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " DCRC ,Data CRC error" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RCRC ,Response CRC error" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RXDR ,Receive FIFO data request" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXDR ,Transmit FIFO data request" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " DTO ,Data transfer over" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " CDONE ,Command done" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " RE ,Response error" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CDET ,Card detect" "Masked,Not masked"
|
|
textline ""
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "RINTSTS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 16. " SDIO_INT ,Interrupt from SDIO card" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " EBE ,End-bit error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " ACD ,Auto command done" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " SBE ,Start-bit error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " HLE ,Hardware locked write error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " FRUN ,FIFO underrun/overrun error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HTO ,Data starvation-by-host time-out" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " DRTO_BDS ,Data read time-out" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RTO_BAR ,Response time-out" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " DCRC ,Data CRC error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RCRC ,Response CRC error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RXDR ,Receive FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXDR ,Transmit FIFO data request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " DTO ,Data transfer over" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " CDONE ,Command done" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RE ,Response error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CDET ,Card detect" "No interrupt,Interrupt"
|
|
textline ""
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 31. " DMA_REQ ,DMA request signal state" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " DMA_ACK ,DMA acknowledge signal state" "Not acknowledged,Acknowledged"
|
|
hexmask.long.word 0x00 17.--29. 1. " FIFO_COUNT ,FIFO count - Number of filled locations in FIFO"
|
|
bitfld.long 0x00 11.--16. " RESP_INDEX ,Index of previous response, including any auto-stop sent by core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DATA_STATE_MC_BUSY ,Data transmit or receive state-machine is busy" "Not busy,Busy"
|
|
bitfld.long 0x00 9. " DATA_BUSY ,Inverted version of raw selected card_data" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " DATA_3_STATUS ,Raw selected card_data" "Not presented,Presented"
|
|
bitfld.long 0x00 4.--7. " CMDFSMSTATES ,Command FSM states" "Idle,Send init sequence,Tx cmd start bit,Tx cmd tx bit,Tx cmd index + arg,Tx cmd crc7,Tx cmd end bit,Rx resp start bit,Rx resp IRQ response,Rx resp tx bit,Rx resp cmd idx,Rx resp data,Rx resp crc7,Rx resp end bit,Cmd path wait NCC,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIFO_FULL ,FIFO is full status" "Not full,Full"
|
|
bitfld.long 0x00 2. " FIFO_EMPTY ,FIFO is empty status" "Not empty,Empty"
|
|
bitfld.long 0x00 1. " FIFO_TX_WATERMARK ,FIFO reached Transmit watermark level" "Not reached,Reached"
|
|
bitfld.long 0x00 0. " FIFO_RX_WATERMARK ,FIFO reached Receive watermark level" "Not reached,Reached"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FIFOTH,FIFO Threshold Watermark Register"
|
|
bitfld.long 0x00 28.--30. " DMA_MTS ,Burst size of multiple transaction" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_WMARK ,FIFO threshold watermark level when receiving data to card"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_WMARK ,FIFO threshold watermark level when transmitting data to card"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x00 "CDETECT,Card Detect Register"
|
|
bitfld.long 0x00 0. " CARD_DETECT ,Card detect" "Detected,Not detected"
|
|
line.long 0x04 "WRTPRT,Write Protect Register"
|
|
bitfld.long 0x04 0. " WRITE_PROTECT ,Write protect" "Not protected,Protected"
|
|
rgroup.long 0x5C++0x7
|
|
line.long 0x00 "TCBCNT,Transferred CIU Card Byte Count Register"
|
|
line.long 0x04 "TBBCNT,Transferred Host to BIU-FIFO Byte Count Register"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "DEBNCE,Debounce Count Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " DEBOUNCE_COUNT ,Number of host clocks (clk) used by debounce filter logic for card detect"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RST_N,Hardware Reset"
|
|
bitfld.long 0x00 0. " CARD_RESET ,Hardware reset" "Reset,No Reset"
|
|
textline ""
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "BMOD,Bus Mode Register"
|
|
bitfld.long 0x00 8.--10. " PBL ,Programmable Burst Length" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x00 7. " DE ,SD/MMC DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " FB ,Fixed Burst" "Not performed,Performed"
|
|
bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x00 "PLDMND,Poll Demand Register"
|
|
group.long 0x88++0xB
|
|
line.long 0x00 "DBADDR,Descriptor List Base Address Register"
|
|
line.long 0x04 "IDSTS,Internal DMAC Status Register"
|
|
bitfld.long 0x04 13.--16. " FSM ,DMAC state machine present state" "DMA_IDLE,DMA_SUSPEND,DESC_RD,DESC_CHK,DMA_RD_REQ_WAIT,DMA_WR_REQ_WAIT,DMA_RD,DMA_WR,DESC_CLOSE,?..."
|
|
bitfld.long 0x04 10.--12. " EB ,Error Bits (host abort)" "Reserved,During transmission,During reception,?..."
|
|
eventfld.long 0x04 9. " AIS ,Abnormal Interrupt Summary" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " NIS ,Normal Interrupt Summary" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " CES ,Card Error Summary" "No error,Error"
|
|
eventfld.long 0x04 4. " DU ,Descriptor Unavailable Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 2. " FBE ,Fatal Bus Error Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " RI ,Receive Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " TI ,Transmit Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "IDINTEN,Internal DMAC Interrupt Enable Register"
|
|
bitfld.long 0x08 9. " AIS ,Abnormal Interrupt Summary Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NIS ,Normal Interrupt Summary Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CES ,Card Error summary Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " DU ,Descriptor Unavailable Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " FBE ,Fatal Bus Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RI ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TI ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x94++0x7
|
|
line.long 0x00 "DSCADDR,Current Host Descriptor Address Register"
|
|
line.long 0x04 "BUFADDR,Current Buffer Descriptor Address Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "SPIFI (SPI Flash Interface)"
|
|
base ad:0x40003000
|
|
width 8.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CTRL,SPIFI Control Register"
|
|
bitfld.long 0x00 31. " DMAEN ,DMA Request Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FBCLK ,Feedback clock select" "Internal,Feedback"
|
|
bitfld.long 0x00 29. " RFCLK ,Input data active edge" "Rising,Falling"
|
|
newline
|
|
bitfld.long 0x00 28. " DUAL ,Dual protocol" "Quad protocol,Dual protocol"
|
|
bitfld.long 0x00 27. " PRFTCH_DIS ,Cache prefetching disable" "No,Yes"
|
|
bitfld.long 0x00 23. " MODE3 ,SPI Mode 3 select" "SCK LOW,SCK HIGH"
|
|
newline
|
|
bitfld.long 0x00 22. " INTEN ,SPIFI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " D_PRFTCH_DIS ,Data prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 16.--19. " CSHIGH ,CS high time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMEOUT ,Timeout value"
|
|
line.long 0x04 "CMD,SPIFI Command Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " OPCODE ,Command opcode"
|
|
bitfld.long 0x04 21.--23. " FRAMEFORM ,Opcode and address fields control" ",Opcode / no address,Opcode / 1 LSB,Opcode / 2 LSBs,Opcode / 3 LSBs,Opcode / 4 LSBs,No opcode / 3 LSBs,No opcode / 4 bytes"
|
|
bitfld.long 0x04 19.--20. " FIELDFORM ,Command fields send control" "All serial,Data quad/dual,Serial opcode,All quad/dual"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " INTLEN ,Intermediate bytes preceding data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 15. " DOUT ,Data direction" "Input,Output"
|
|
bitfld.long 0x04 14. " POLL ,Polling enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x04 0.--13. 1. " DATALEN ,Data length"
|
|
line.long 0x08 "ADDR,SPIFI Address Register"
|
|
line.long 0x0C "IDATA,SPIFI Intermediate Data Register"
|
|
line.long 0x10 "CLIMIT,SPIFI Cache Limit Register"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "DATA,SPIFI Data Register"
|
|
in
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "MCMD,SPIFI Memory Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " OPCODE ,Command opcode"
|
|
bitfld.long 0x00 21.--23. " FRAMEFORM ,Opcode and address fields control" ",Opcode / no address,Opcode / 1 LSB,Opcode / 2 LSBs,Opcode / 3 LSBs,Opcode / 4 LSBs,No opcode / 3 LSBs,No opcode / 4 bytes"
|
|
bitfld.long 0x00 19.--20. " FIELDFORM ,Command fields send control" "All serial,Data quad/dual,Serial opcode,All quad/dual"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " INTLEN ,Intermediate bytes preceding data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DOUT ,Data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " POLL ,Polling enable" "Disabled,Enabled"
|
|
line.long 0x04 "STAT,SPIFI Status Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " VERSION ,SPIFI version"
|
|
eventfld.long 0x04 5. " INTRQ ,Interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RESET ,Current command or memory mode abort" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x04 1. " CMD ,Command register written" "Not written,Written"
|
|
bitfld.long 0x04 0. " MCINIT ,Memory Command register write successful" "Not written,Written"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMC (External Memory Controller)"
|
|
base ad:0x40005000
|
|
width 16.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CONTROL,EMC Control register"
|
|
bitfld.long 0x0 2. " L ,Low-power mode" "Normal,Low-power"
|
|
bitfld.long 0x0 1. " M ,Address mirror" "Normal memory map,Reset memory map"
|
|
textline " "
|
|
bitfld.long 0x0 0. " E ,EMC Enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "STATUS,EMC Status register"
|
|
bitfld.long 0x00 2. " SA ,Self-refresh acknowledge" "Normal,Self-refresh"
|
|
bitfld.long 0x00 1. " S ,Write buffer status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B ,Busy" "Not busy,Busy"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "CONFIG,EMC Configuration register"
|
|
sif cpuis("LPC407?*")||cpuis("LPC408?*")
|
|
bitfld.long 0x00 8. " CR ,CLKOUT[1:0] ratio" "1:1,1:2"
|
|
bitfld.long 0x00 0. " EM ,Endian mode" "Little,Big"
|
|
elif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43*")
|
|
bitfld.long 0x00 0. " EM ,Endian mode" "Little,Big"
|
|
else
|
|
bitfld.long 0x00 8. " CCLK ,CLKOUT[1:0] ratio" "1:1,1:2"
|
|
bitfld.long 0x00 0. " Endian ,Endian mode" "Little,Big"
|
|
endif
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "DC,Dynamic Memory Control register"
|
|
sif (!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))&&!cpuis("LPC407?*")&&!cpuis("LPC408?*")&&!cpuis("LPC43*")&&!cpuis("LPC546*")
|
|
bitfld.long 0x00 13. " DP ,Low-power SDRAM deep-sleep mode" "Normal,Deep-sleep"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " I ,SDRAM initialization" "SDRAM NORMAL,SDRAM MODE,SDRAM PALL,SDRAM NOP"
|
|
bitfld.long 0x00 5. " MMC ,Memory clock control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SR ,Self-refresh request" "Normal,Self-refresh"
|
|
bitfld.long 0x00 1. " CS ,Dynamic memory clock control" "Stopped,Runned"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CE ,Dynamic memory clock enable" "Power-save enabled,All clock enabled"
|
|
line.long 0x04 "DR,Dynamic Memory Refresh Timer register"
|
|
hexmask.long.word 0x04 0.--10. 1. " REFRESH ,Indicates the multiple of 16 CCLKs between SDRAM refresh cycles"
|
|
line.long 0x08 "DRC,Dynamic Memory Read Configuration register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43*")||cpuis("LPC546*")
|
|
bitfld.long 0x08 0.--1. " RD ,Read data strategy" ",Command delayed,Command delayed +1 clock cycle,Command delayed +2 clock cycles"
|
|
else
|
|
bitfld.long 0x08 0.--1. " RD ,Read data strategy" "Clock out delayed,Command delayed,Command delayed +1 clock cycle,Command delayed +2 clock cycles"
|
|
endif
|
|
group.long 0x30++0x2B
|
|
line.long 0x00 "DTRP,Dynamic Memory Precharge Command Period register"
|
|
bitfld.long 0x00 0.--3. " TRP ,Precharge command period" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "DTRAS,Dynamic Memory Active to Precharge Command Period register"
|
|
bitfld.long 0x04 0.--3. " TRAS ,Active to precharge command period" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x08 "DTSREX,Dynamic Memory Self-refresh Exit Time register"
|
|
bitfld.long 0x08 0.--3. " TSREX ,Self-refresh exit time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x0C "DTAPR,Dynamic Memory Last Data Out to Active Time register"
|
|
bitfld.long 0x0C 0.--3. " TAPR ,Last-data-out to active command time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x10 "DTDAL,Dynamic Memory Data-in to Active Command Time register"
|
|
bitfld.long 0x10 0.--3. " TDAL ,Data-in to active command" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x14 "DTWR,Dynamic Memory Write Recovery Time register"
|
|
bitfld.long 0x14 0.--3. " TWR ,Write recovery time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x18 "DTRC,Dynamic Memory Active to Active Command Period register"
|
|
bitfld.long 0x18 0.--4. " TRC ,Active to active command period" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x1C "DTRFC,Dynamic Memory Auto-refresh Period register"
|
|
bitfld.long 0x1C 0.--4. " TRFC ,Auto-refresh period and auto-refresh to active command period" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x20 "DTXSR,Dynamic Memory Exit Self-refresh register"
|
|
bitfld.long 0x20 0.--4. " TXSR ,Exit self-refresh to active command time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x24 "DTRRD,Dynamic Memory Active Bank A to Active Bank B Time register"
|
|
bitfld.long 0x24 0.--3. " TRRD ,Active bank A to active bank B latency" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x28 "DTMRD,Dynamic Memory Load Mode register to Active Command Time"
|
|
bitfld.long 0x28 0.--3. " TMRD ,Load mode register to active command time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SEW,Static Memory Extended Wait register"
|
|
hexmask.long.word 0x00 0.--9. 1. " EXTENDEDWAIT ,Extended wait time out"
|
|
sif !cpuis("LPC407?FBD144")&&!cpuis("LPC408?FBD144")
|
|
group.long 0x100++0x07 "Dynamic Memory EMC 0"
|
|
line.long 0x00 "DCONFIG0,Dynamic Memory Configuration register"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AM[14] ,Address mapping(bus length)" "16 bit,32 bit"
|
|
bitfld.long 0x00 7.--12. " AM[12-7] ,Address mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3.--4. " MD ,Memory device" "SDRAM,Low-power SDRAM,?..."
|
|
line.long 0x04 "DRASCAS0,Dynamic Memory RAS & CAS Delay register"
|
|
bitfld.long 0x04 8.--9. " CAS ,CAS latency" ",1,2,3"
|
|
bitfld.long 0x04 0.--1. " RAS ,RAS latency" ",1,2,3"
|
|
group.long 0x120++0x07 "Dynamic Memory EMC 1"
|
|
line.long 0x00 "DCONFIG1,Dynamic Memory Configuration register"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AM[14] ,Address mapping(bus length)" "16 bit,32 bit"
|
|
bitfld.long 0x00 7.--12. " AM[12-7] ,Address mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3.--4. " MD ,Memory device" "SDRAM,Low-power SDRAM,?..."
|
|
line.long 0x04 "DRASCAS1,Dynamic Memory RAS & CAS Delay register"
|
|
bitfld.long 0x04 8.--9. " CAS ,CAS latency" ",1,2,3"
|
|
bitfld.long 0x04 0.--1. " RAS ,RAS latency" ",1,2,3"
|
|
group.long 0x140++0x07 "Dynamic Memory EMC 2"
|
|
line.long 0x00 "DCONFIG2,Dynamic Memory Configuration register"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AM[14] ,Address mapping(bus length)" "16 bit,32 bit"
|
|
bitfld.long 0x00 7.--12. " AM[12-7] ,Address mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3.--4. " MD ,Memory device" "SDRAM,Low-power SDRAM,?..."
|
|
line.long 0x04 "DRASCAS2,Dynamic Memory RAS & CAS Delay register"
|
|
bitfld.long 0x04 8.--9. " CAS ,CAS latency" ",1,2,3"
|
|
bitfld.long 0x04 0.--1. " RAS ,RAS latency" ",1,2,3"
|
|
group.long 0x160++0x07 "Dynamic Memory EMC 3"
|
|
line.long 0x00 "DCONFIG3,Dynamic Memory Configuration register"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AM[14] ,Address mapping(bus length)" "16 bit,32 bit"
|
|
bitfld.long 0x00 7.--12. " AM[12-7] ,Address mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3.--4. " MD ,Memory device" "SDRAM,Low-power SDRAM,?..."
|
|
line.long 0x04 "DRASCAS3,Dynamic Memory RAS & CAS Delay register"
|
|
bitfld.long 0x04 8.--9. " CAS ,CAS latency" ",1,2,3"
|
|
bitfld.long 0x04 0.--1. " RAS ,RAS latency" ",1,2,3"
|
|
endif
|
|
group.long 0x200++0x0B "Static Memory EMC 0"
|
|
line.long 0x00 "EMCSCONFIG0,Static Memory Configuration registers"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EW ,Extended wait" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PB ,Byte lane state" "High/Low,Low/Low"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PC ,Chip select polarity" "Low,High"
|
|
bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Asynchronous"
|
|
bitfld.long 0x00 0.--1. " MW ,Memory width" "8 bit,16 bit,32 bit,?..."
|
|
line.long 0x04 "EMCSWAITWEN0, Static Memory Write Enable Delay registers"
|
|
bitfld.long 0x04 0.--3. " WAITWEN ,Wait write enable" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x08 "EMCSWAITOEN0,Static Memory Output Enable Delay registers"
|
|
bitfld.long 0x08 0.--3. " WAITOEN ,Wait output enable" "No delay,1,2,3,5,5,6,8,8,9,10,11,12,13,14,15"
|
|
sif cpuis("LPC407?*")||cpuis("LPC408?*")||cpuis("LPC43*")||cpuis("LPC546*")
|
|
group.long (0x200+0x0C)++0x0F
|
|
line.long 0x00 "EMCSWAITRD0,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read wait states/Read first access wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x04 "EMCSWAITPAGE0,Static Memory Page Mode Read Delay registers"
|
|
bitfld.long 0x04 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x08 "EMCSWAITWR0,Static Memory Write Delay registers"
|
|
bitfld.long 0x08 0.--4. " WAITWR ,Write wait states" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33"
|
|
line.long 0x0C "EMCSWAITTURN0,Static Memory Turn Round Delay registers"
|
|
bitfld.long 0x0C 0.--3. " WAITTURN ,Bus turnaround cycles" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
if (((per.l((ad:0x40005000+0x200)))&0x8)==0x00)
|
|
group.long (0x200+0xC)++0x03
|
|
line.long 0x00 "EMCSWAITRD0,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
group.long (0x200+0xC)++0x03
|
|
line.long 0x00 "EMCSWAITRD0,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read first access wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
if (((per.l((ad:0x40005000+0x200)))&0x8)==0x00)
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "EMCSWAITPAGE0,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
hgroup.long (0x200+0x10)++0x03
|
|
hide.long 0x00 "EMCSWAITPAGE0,Static Memory Read Delay registers"
|
|
endif
|
|
group.long (0x200+0x14)++0x07
|
|
line.long 0x00 "EMCSWAITWR0,Static Memory Write Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITWR ,Write wait states" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33"
|
|
line.long 0x04 "EMCSWAITTURN0,Static Memory Turn Round Delay registers"
|
|
bitfld.long 0x04 0.--3. " WAITTURN ,Bus turnaround cycles" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
endif
|
|
group.long 0x220++0x0B "Static Memory EMC 1"
|
|
line.long 0x00 "EMCSCONFIG1,Static Memory Configuration registers"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EW ,Extended wait" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PB ,Byte lane state" "High/Low,Low/Low"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PC ,Chip select polarity" "Low,High"
|
|
bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Asynchronous"
|
|
bitfld.long 0x00 0.--1. " MW ,Memory width" "8 bit,16 bit,32 bit,?..."
|
|
line.long 0x04 "EMCSWAITWEN1, Static Memory Write Enable Delay registers"
|
|
bitfld.long 0x04 0.--3. " WAITWEN ,Wait write enable" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x08 "EMCSWAITOEN1,Static Memory Output Enable Delay registers"
|
|
bitfld.long 0x08 0.--3. " WAITOEN ,Wait output enable" "No delay,1,2,3,5,5,6,8,8,9,10,11,12,13,14,15"
|
|
sif cpuis("LPC407?*")||cpuis("LPC408?*")||cpuis("LPC43*")||cpuis("LPC546*")
|
|
group.long (0x220+0x0C)++0x0F
|
|
line.long 0x00 "EMCSWAITRD1,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read wait states/Read first access wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x04 "EMCSWAITPAGE1,Static Memory Page Mode Read Delay registers"
|
|
bitfld.long 0x04 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x08 "EMCSWAITWR1,Static Memory Write Delay registers"
|
|
bitfld.long 0x08 0.--4. " WAITWR ,Write wait states" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33"
|
|
line.long 0x0C "EMCSWAITTURN1,Static Memory Turn Round Delay registers"
|
|
bitfld.long 0x0C 0.--3. " WAITTURN ,Bus turnaround cycles" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
if (((per.l((ad:0x40005000+0x220)))&0x8)==0x00)
|
|
group.long (0x220+0xC)++0x03
|
|
line.long 0x00 "EMCSWAITRD1,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
group.long (0x220+0xC)++0x03
|
|
line.long 0x00 "EMCSWAITRD1,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read first access wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
if (((per.l((ad:0x40005000+0x220)))&0x8)==0x00)
|
|
group.long (0x220+0x10)++0x03
|
|
line.long 0x00 "EMCSWAITPAGE1,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
hgroup.long (0x220+0x10)++0x03
|
|
hide.long 0x00 "EMCSWAITPAGE1,Static Memory Read Delay registers"
|
|
endif
|
|
group.long (0x220+0x14)++0x07
|
|
line.long 0x00 "EMCSWAITWR1,Static Memory Write Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITWR ,Write wait states" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33"
|
|
line.long 0x04 "EMCSWAITTURN1,Static Memory Turn Round Delay registers"
|
|
bitfld.long 0x04 0.--3. " WAITTURN ,Bus turnaround cycles" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
endif
|
|
group.long 0x240++0x0B "Static Memory EMC 2"
|
|
line.long 0x00 "EMCSCONFIG2,Static Memory Configuration registers"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EW ,Extended wait" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PB ,Byte lane state" "High/Low,Low/Low"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PC ,Chip select polarity" "Low,High"
|
|
bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Asynchronous"
|
|
bitfld.long 0x00 0.--1. " MW ,Memory width" "8 bit,16 bit,32 bit,?..."
|
|
line.long 0x04 "EMCSWAITWEN2, Static Memory Write Enable Delay registers"
|
|
bitfld.long 0x04 0.--3. " WAITWEN ,Wait write enable" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x08 "EMCSWAITOEN2,Static Memory Output Enable Delay registers"
|
|
bitfld.long 0x08 0.--3. " WAITOEN ,Wait output enable" "No delay,1,2,3,5,5,6,8,8,9,10,11,12,13,14,15"
|
|
sif cpuis("LPC407?*")||cpuis("LPC408?*")||cpuis("LPC43*")||cpuis("LPC546*")
|
|
group.long (0x240+0x0C)++0x0F
|
|
line.long 0x00 "EMCSWAITRD2,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read wait states/Read first access wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x04 "EMCSWAITPAGE2,Static Memory Page Mode Read Delay registers"
|
|
bitfld.long 0x04 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x08 "EMCSWAITWR2,Static Memory Write Delay registers"
|
|
bitfld.long 0x08 0.--4. " WAITWR ,Write wait states" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33"
|
|
line.long 0x0C "EMCSWAITTURN2,Static Memory Turn Round Delay registers"
|
|
bitfld.long 0x0C 0.--3. " WAITTURN ,Bus turnaround cycles" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
if (((per.l((ad:0x40005000+0x240)))&0x8)==0x00)
|
|
group.long (0x240+0xC)++0x03
|
|
line.long 0x00 "EMCSWAITRD2,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
group.long (0x240+0xC)++0x03
|
|
line.long 0x00 "EMCSWAITRD2,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read first access wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
if (((per.l((ad:0x40005000+0x240)))&0x8)==0x00)
|
|
group.long (0x240+0x10)++0x03
|
|
line.long 0x00 "EMCSWAITPAGE2,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
hgroup.long (0x240+0x10)++0x03
|
|
hide.long 0x00 "EMCSWAITPAGE2,Static Memory Read Delay registers"
|
|
endif
|
|
group.long (0x240+0x14)++0x07
|
|
line.long 0x00 "EMCSWAITWR2,Static Memory Write Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITWR ,Write wait states" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33"
|
|
line.long 0x04 "EMCSWAITTURN2,Static Memory Turn Round Delay registers"
|
|
bitfld.long 0x04 0.--3. " WAITTURN ,Bus turnaround cycles" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
endif
|
|
group.long 0x260++0x0B "Static Memory EMC 3"
|
|
line.long 0x00 "EMCSCONFIG3,Static Memory Configuration registers"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EW ,Extended wait" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PB ,Byte lane state" "High/Low,Low/Low"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PC ,Chip select polarity" "Low,High"
|
|
bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Asynchronous"
|
|
bitfld.long 0x00 0.--1. " MW ,Memory width" "8 bit,16 bit,32 bit,?..."
|
|
line.long 0x04 "EMCSWAITWEN3, Static Memory Write Enable Delay registers"
|
|
bitfld.long 0x04 0.--3. " WAITWEN ,Wait write enable" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x08 "EMCSWAITOEN3,Static Memory Output Enable Delay registers"
|
|
bitfld.long 0x08 0.--3. " WAITOEN ,Wait output enable" "No delay,1,2,3,5,5,6,8,8,9,10,11,12,13,14,15"
|
|
sif cpuis("LPC407?*")||cpuis("LPC408?*")||cpuis("LPC43*")||cpuis("LPC546*")
|
|
group.long (0x260+0x0C)++0x0F
|
|
line.long 0x00 "EMCSWAITRD3,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read wait states/Read first access wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x04 "EMCSWAITPAGE3,Static Memory Page Mode Read Delay registers"
|
|
bitfld.long 0x04 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x08 "EMCSWAITWR3,Static Memory Write Delay registers"
|
|
bitfld.long 0x08 0.--4. " WAITWR ,Write wait states" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33"
|
|
line.long 0x0C "EMCSWAITTURN3,Static Memory Turn Round Delay registers"
|
|
bitfld.long 0x0C 0.--3. " WAITTURN ,Bus turnaround cycles" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
if (((per.l((ad:0x40005000+0x260)))&0x8)==0x00)
|
|
group.long (0x260+0xC)++0x03
|
|
line.long 0x00 "EMCSWAITRD3,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
group.long (0x260+0xC)++0x03
|
|
line.long 0x00 "EMCSWAITRD3,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Read first access wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
if (((per.l((ad:0x40005000+0x260)))&0x8)==0x00)
|
|
group.long (0x260+0x10)++0x03
|
|
line.long 0x00 "EMCSWAITPAGE3,Static Memory Read Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
hgroup.long (0x260+0x10)++0x03
|
|
hide.long 0x00 "EMCSWAITPAGE3,Static Memory Read Delay registers"
|
|
endif
|
|
group.long (0x260+0x14)++0x07
|
|
line.long 0x00 "EMCSWAITWR3,Static Memory Write Delay registers"
|
|
bitfld.long 0x00 0.--4. " WAITWR ,Write wait states" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33"
|
|
line.long 0x04 "EMCSWAITTURN3,Static Memory Turn Round Delay registers"
|
|
bitfld.long 0x04 0.--3. " WAITTURN ,Bus turnaround cycles" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
endif
|
|
sif !cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")&&!cpuis("LPC407?*")&&!cpuis("LPC408?*")&&!cpuis("LPC43*")
|
|
textline " "
|
|
group.long 0x200601DC++0x07
|
|
line.long 0x00 "EMCDLYCTL,Delay Control register"
|
|
bitfld.long 0x00 24.--28. " CLKOUT1DLY ,Programmable delay value for the CLKOUT[1] output" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 16.--20. " CLKOUT0DLY ,Programmable delay value for the CLKOUT[0] output" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 8.--12. " FBCLKDLY ,Programmable delay value for the feedback clock" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CMDDLY ,Programmable delay value for EMC outputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x04 "EMCCAL,EMC Calibration register"
|
|
bitfld.long 0x04 15. " DONE ,Measurement completion flag" "Not completed,Completed"
|
|
bitfld.long 0x04 14. " START ,Start control bit for the EMC calibration counter" "No effect,Started"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CALVALUE ,Returns the count of the approximately 50 MHz ring oscillator"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "USB (USB Host/Device/OTG controller)"
|
|
sif cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
tree "USB0 Host/Device/OTG controller"
|
|
base ad:0x40006000
|
|
width 12.
|
|
tree "Device/host capability registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SBUSCFG,System bus interface configuration register"
|
|
bitfld.long 0x00 0.--2. " AHB_BRST ,Burst length" "Unspecified,INCR4/singles,INCR8/INCR4 or singles,INCR16/INCR4-8 or singles,,INCR4/unspecified,INCR8/unspecified,INCR16/unspecified"
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x00 "CAPLENGTH,CAPLENGTH register"
|
|
hexmask.long.word 0x00 8.--23. 1. " HCIVERSION ,BCD encoding of the EHCI revision number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Indicates offset to add to the register base address"
|
|
line.long 0x04 "HCSPARAMS,HCSPARAMS register"
|
|
bitfld.long 0x04 24.--27. " N_TT ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " N_PTT ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16. " PI ,Port indicators" "Not supported,Supported"
|
|
bitfld.long 0x04 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4. " PPC ,Port Power Control" "Not included,Included"
|
|
bitfld.long 0x04 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "HCCPARAMS,HCCPARAMS register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x08 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported"
|
|
bitfld.long 0x08 1. " PFL ,Programmable Frame List Flag" "Not used,Used"
|
|
bitfld.long 0x08 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported"
|
|
rgroup.long 0x120++0x7
|
|
line.long 0x00 "DCIVERSION,DCIVERSION register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register"
|
|
line.long 0x4 "DCCPARAMS,DCCPARAMS"
|
|
bitfld.long 0x4 8. " HC ,Host Capable" "No,Yes"
|
|
bitfld.long 0x4 7. " DC ,Device Capable" "No,Yes"
|
|
bitfld.long 0x4 0.--4. " DEN ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 18.
|
|
tree "Device/host operational registers"
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "USBCMD_D,USB Command register in device mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,Add dTD trip wire" "Not ensured,Ensured"
|
|
bitfld.long 0x00 13. " SUTW ,Setup trip wire" "Not ensured,Ensured"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "USBCMD_H,USB Command register in host mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FS2 ,Bit 2 of the Frame List Size bits" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASP1_0 ,Asynchronous schedule park mode" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,This bit is used as a doorbell by software" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASE ,This bit controls whether the host controller skips processing the asynchronous schedule" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,This bit controls whether the host controller skips processing the periodic schedule" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FS1 ,Bit 1 of the Frame List Size bits" "0,1"
|
|
bitfld.long 0x00 2. " FS0 ,Bit 0 of the Frame List Size bits" "0,1"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
endif
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "USBSTS_D,USB Status register in device mode"
|
|
rbitfld.long 0x00 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " SLI ,DCSuspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
eventfld.long 0x00 6. " URI ,USB reset received" "Not received,Received"
|
|
eventfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PCI ,Port change detect" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " UEI ,USB error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "USBSTS_H,USB Status register in host mode"
|
|
eventfld.long 0x00 19. " UPI ,USB host periodic interrupt" "Not interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " UAI ,USB host asynchronous interrupt" "Not interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " AS ,Asynchronous schedule status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " PS ,Periodic schedule status" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " RCL ,Reclamation" "No empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " HCH ,HCHalted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " AAI ,Interrupt on async advance" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRI ,Frame list roll-over" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PCI ,Port change detect" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " UEI ,USB error interrupt" "Not interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UI ,USB interrupt" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "USBINTR_D,USB Interrupt register"
|
|
bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF received enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " URE ,USB reset enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "USBINTR_H,USB Interrupt register"
|
|
bitfld.long 0x00 19. " UPIA ,USB host periodic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF received enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on asynchronous advance enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("LPC43*"))
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
rgroup.long 0x14C++0x3
|
|
line.long 0x00 "FRINDEX_D,USB frame index register in device mode"
|
|
hexmask.long.word 0x00 3.--13. 1. " FRINDEX13_3 ,Current frame number of the last frame transmitted"
|
|
bitfld.long 0x00 0.--2. " FRINDEX2_0 ,Current micro frame number" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "FRINDEX_H,USB frame index register in host mode"
|
|
hexmask.long.word 0x00 3.--12. 1. " FRINDEX12_3 ,Frame list current index"
|
|
bitfld.long 0x00 0.--2. " FRINDEX2_0 ,Current micro frame number" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "FRINDEX_D,USB frame index register in device mode"
|
|
hexmask.long.word 0x00 3.--13. 1. " FRINDEX13_3 ,Current frame number of the last frame transmitted"
|
|
bitfld.long 0x00 0.--2. " FRINDEX2_0 ,Current micro frame number" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "FRINDEX_H,USB frame index register in host mode"
|
|
hexmask.long.word 0x00 3.--12. 1. " FRINDEX12_3 ,Frame list current index"
|
|
bitfld.long 0x00 0.--2. " FRINDEX2_0 ,Current micro frame number" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x154++0xF
|
|
line.long 0x00 "DEVICEADDR,USB Device Address register in device mode"
|
|
hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,USB device address"
|
|
textline " "
|
|
bitfld.long 0x00 24. " USBADRA ,Device address advance" "0,1"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x154++0x13
|
|
line.long 0x00 "PERIODICLISTBASE,USB Periodic List Base register in host mode"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " PERBASE31_12 ,Base Address (Low)"
|
|
textline " "
|
|
endif
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x158++0x3
|
|
line.long 0x00 "ENDPOINTLISTADDR,USB Endpoint List Address register in device mode"
|
|
hexmask.long 0x00 11.--31. 1. " EPBASE31_11 ,Endpoint list pointer (low)"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x158++0x7
|
|
line.long 0x00 "ASYNCLISTADDR,USB Asynchronous List Address register in host mode"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE31_5 ,Link pointer (Low) LPL"
|
|
line.long 0x04 "TTCTRL,USB TT Control register in host mode"
|
|
hexmask.long.byte 0x04 24.--30. 1. " TTHA ,Hub address when FS or LS device are connected directly"
|
|
endif
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "BURSTSIZE,USB burst size register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programmable TX burst length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX burst length"
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x164++0x3
|
|
line.long 0x00 "TXFILLTUNING,USB Transfer buffer Fill Tuning register in host mode"
|
|
hexmask.long.byte 0x00 16.--21. 1. " TXFIFOTHRES ,Scheduler overhead"
|
|
bitfld.long 0x00 8.--12. " TXSCHEATLTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXSCHOH ,FIFO burst threshold"
|
|
endif
|
|
sif (!cpuis("LPC43?????10*")&&!cpuis("LPC43?????14*"))
|
|
else
|
|
endif
|
|
group.long 0x174++0x3
|
|
line.long 0x00 "BINTERVAL,USB BINTERVAL register"
|
|
bitfld.long 0x00 0.--3. " BINT ,bInterval value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x178++0x7
|
|
line.long 0x00 "ENDPTNAK,USB endpoint NAK register"
|
|
eventfld.long 0x00 21. " EPTN5 ,Tx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 20. " EPTN4 ,Tx endpoint NAK" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " EPTN3 ,Tx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 18. " EPTN2 ,Tx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " EPTN1 ,Tx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 16. " EPTN0 ,Tx endpoint NAK" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 5. " EPRN5 ,Rx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " EPRN4 ,Rx endpoint NAK" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 3. " EPRN3 ,Rx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 2. " EPRN2 ,Rx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPRN1 ,Rx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " EPRN0 ,Rx endpoint NAK" "Not detected,Detected"
|
|
line.long 0x04 "ENDPTNAKEN,USB endpoint NAK enable register"
|
|
bitfld.long 0x04 21. " EPTNE5 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " EPTNE4 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EPTNE3 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " EPTNE2 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " EPTNE1 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " EPTNE0 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EPRNE5 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " EPRNE4 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EPRNE3 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " EPRNE2 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EPRNE1 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EPRNE0 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("LPC432*")||cpuis("LPC433*")||cpuis("LPC435*")||cpuis("LPC437*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*")||cpuis("LPC43S7*"))
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_D,Port Status and Control register in device mode"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset"
|
|
rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "No resume,Resume"
|
|
rbitfld.long 0x00 3. " PEC ,Port enable/disable change" "Enabled,?..."
|
|
rbitfld.long 0x00 2. " PE ,Port enable" ",Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)&&(((per.l(ad:0x40006000+0x184))&0x1000)==0)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_H,Port Status and Control register in host mode"
|
|
rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low-speed,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,?..."
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,?..."
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port power control" "Power off,Power on"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,Undefined"
|
|
rbitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "No reset,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,?..."
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "No resume,?..."
|
|
eventfld.long 0x00 5. " OCC ,Over-current change" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current active" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port enable/disable change" "No changed,?..."
|
|
bitfld.long 0x00 2. " PE ,Port enable" "Disabled,?..."
|
|
eventfld.long 0x00 1. " CSC ,Connect status change" "No changed,?..."
|
|
eventfld.long 0x00 0. " CCS ,Current connect status" "Not attached,?..."
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)&&(((per.l(ad:0x40006000+0x184))&0x1000)==0x1000)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_H,Port Status and Control register in host mode"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low-speed,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port power control" "Power off,Power on"
|
|
bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,Undefined"
|
|
bitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "No resume,Resume"
|
|
eventfld.long 0x00 5. " OCC ,Over-current change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " OCA ,Over-current active" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port enable/disable change" "No changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " CSC ,Connect status change" "No changed,Changed"
|
|
eventfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_D,Port Status and Control register in device mode"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset"
|
|
rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FPR ,Force port resume" "No resume,Resume"
|
|
rbitfld.long 0x00 3. " PEC ,Port enable/disable change" "Enabled,?..."
|
|
rbitfld.long 0x00 2. " PE ,Port enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached"
|
|
elif (((per.l(ad:0x40006000+0x1A8))&0x3)==0x3)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_H,Port Status and Control register in host mode"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_FS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port power control" "Power off,Power on"
|
|
bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,Undefined"
|
|
bitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "No resume,Resume"
|
|
bitfld.long 0x00 5. " OCC ,Over-current change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " OCA ,Over-current active" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "Enabled,?..."
|
|
bitfld.long 0x00 2. " PE ,Port enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " CSC ,Connect status change" "No change,Change"
|
|
eventfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached"
|
|
endif
|
|
endif
|
|
group.long 0x1A4++0x3
|
|
line.long 0x00 "OTGSC,OTG Status and Control register"
|
|
bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MS1E ,1 millisecond timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BSEIE ,B-session end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BSVIE ,B-session valid interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ASVIE ,A-session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AVVIE ,A-VBUS valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 21. " MS1S ,1 millisecond timer interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " BSEIS ,B-Session end interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " BSVIS ,B-Session valid interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ASVIS ,A-Session valid interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " AVVIS ,A-VBUS valid interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IDIS ,USB ID interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 14. " DPS ,Data bus pulsing status" "Not detected,Detected"
|
|
rbitfld.long 0x00 13. " MS1T ,1 millisecond timer toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " BSE ,B-session end" "Not end,End"
|
|
rbitfld.long 0x00 11. " BSV ,B-session valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 10. " ASV ,A-session valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 9. " AVV ,A-VBUS valid" "Not valid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " ID ,USB ID" "A,B"
|
|
bitfld.long 0x00 7. " HABA ,Hardware assist B-disconnect to A-connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HADP ,Hardware assist data pulse" "Idle,Start"
|
|
bitfld.long 0x00 5. " IDPU ,ID pull-up" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DP ,Data pulsing" "Not asserted,Asserted"
|
|
bitfld.long 0x00 3. " OT ,OTG termination" ",Device mode"
|
|
bitfld.long 0x00 2. " HAAR ,Hardware assist auto_reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VC ,VBUS_Charge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VD ,VBUS_Discharge" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40006000+0x1A8))&0x3)==0x2)
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "USBMODE_D,USB Mode register in device mode"
|
|
bitfld.long 0x00 4. " SDIS ,Stream disable mode" "No,Yes"
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout mode" "On,Off"
|
|
bitfld.long 0x00 2. " ES ,Endian select" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CM1_0 ,Controller mode" "Idle,,Device,Host"
|
|
else
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "USBMODE_H,USB Mode register in host mode"
|
|
bitfld.long 0x00 5. " VBPS ,VBUS power select" "Low,High"
|
|
bitfld.long 0x00 4. " SDIS ,Stream disable mode" "No,Yes"
|
|
bitfld.long 0x00 2. " ES ,Endian select" "Little endian,Big endian"
|
|
textline " "
|
|
sif (cpuis("LPC432*")||cpuis("LPC433*")||cpuis("LPC435*")||cpuis("LPC437*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*")||cpuis("LPC43S7*"))
|
|
bitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device,Host"
|
|
else
|
|
bitfld.long 0x00 0.--1. " CM1_0 ,Controller mode" "Idle,,Device,Host"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 16.
|
|
tree "Device endpoint registers"
|
|
group.long 0x1AC++0xB
|
|
line.long 0x00 "ENDPTSETUPSTAT,USB Endpoint Setup Status register"
|
|
eventfld.long 0x00 5. " ENDPTSET_UPSTAT5 ,Setup endpoint status for logical endpoint 5" "Low,High"
|
|
eventfld.long 0x00 4. " ENDPTSET_UPSTAT4 ,Setup endpoint status for logical endpoint 4" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ENDPTSET_UPSTAT3 ,Setup endpoint status for logical endpoint 3" "Low,High"
|
|
eventfld.long 0x00 2. " ENDPTSET_UPSTAT2 ,Setup endpoint status for logical endpoint 2" "Low,High"
|
|
eventfld.long 0x00 1. " ENDPTSET_UPSTAT1 ,Setup endpoint status for logical endpoint 1" "Low,High"
|
|
eventfld.long 0x00 0. " ENDPTSET_UPSTAT0 ,Setup endpoint status for logical endpoint 0" "Low,High"
|
|
textline ""
|
|
line.long 0x04 "ENDPTPRIME,USB Endpoint Prime register"
|
|
bitfld.long 0x04 21. " PETB5 ,Prime endpoint transmit buffer for physical IN endpoint 5" "Low,High"
|
|
bitfld.long 0x04 20. " PETB4 ,Prime endpoint transmit buffer for physical IN endpoint 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PETB3 ,Prime endpoint transmit buffer for physical IN endpoint 3" "Low,High"
|
|
bitfld.long 0x04 18. " PETB2 ,Prime endpoint transmit buffer for physical IN endpoint 2" "Low,High"
|
|
bitfld.long 0x04 17. " PETB1 ,Prime endpoint transmit buffer for physical IN endpoint 1" "Low,High"
|
|
bitfld.long 0x04 16. " PETB0 ,Prime endpoint transmit buffer for physical IN endpoint 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PERB5 ,Prime endpoint receive buffer for physical OUT endpoint 5" "Low,High"
|
|
bitfld.long 0x04 4. " PERB4 ,Prime endpoint receive buffer for physical OUT endpoint 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PERB3 ,Prime endpoint receive buffer for physical OUT endpoint 3" "Low,High"
|
|
bitfld.long 0x04 2. " PERB2 ,Prime endpoint receive buffer for physical OUT endpoint 2" "Low,High"
|
|
bitfld.long 0x04 1. " PERB1 ,Prime endpoint receive buffer for physical OUT endpoint 1" "Low,High"
|
|
bitfld.long 0x04 0. " PERB0 ,Prime endpoint receive buffer for physical OUT endpoint 0" "Low,High"
|
|
line.long 0x08 "ENDPTFLUSH,USB Endpoint Flush register"
|
|
eventfld.long 0x08 21. " FETB5 ,Flush endpoint transmit buffer for physical IN endpoint 5" "Low,High"
|
|
eventfld.long 0x08 20. " FETB4 ,Flush endpoint transmit buffer for physical IN endpoint 4" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x08 19. " FETB3 ,Flush endpoint transmit buffer for physical IN endpoint 3" "Low,High"
|
|
eventfld.long 0x08 18. " FETB2 ,Flush endpoint transmit buffer for physical IN endpoint 2" "Low,High"
|
|
eventfld.long 0x08 17. " FETB1 ,Flush endpoint transmit buffer for physical IN endpoint 1" "Low,High"
|
|
eventfld.long 0x08 16. " FETB0 ,Flush endpoint transmit buffer for physical IN endpoint 0" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x08 5. " FERB5 ,Flush endpoint receive buffer for physical OUT endpoint 5" "Low,High"
|
|
eventfld.long 0x08 4. " FERB4 ,Flush endpoint receive buffer for physical OUT endpoint 4" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x08 3. " FERB3 ,Flush endpoint receive buffer for physical OUT endpoint 3" "Low,High"
|
|
eventfld.long 0x08 2. " FERB2 ,Flush endpoint receive buffer for physical OUT endpoint 2" "Low,High"
|
|
eventfld.long 0x08 1. " FERB1 ,Flush endpoint receive buffer for physical OUT endpoint 1" "Low,High"
|
|
eventfld.long 0x08 0. " FERB0 ,Flush endpoint receive buffer for physical OUT endpoint 0" "Low,High"
|
|
rgroup.long 0x1B8++0x3
|
|
line.long 0x00 "ENDPTSTAT,USB Endpoint Status register"
|
|
bitfld.long 0x00 21. " ETBR5 ,Endpoint transmit buffer ready for physical IN endpoint 5" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " ETBR4 ,Endpoint transmit buffer ready for physical IN endpoint 4" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETBR3 ,Endpoint transmit buffer ready for physical IN endpoint 3" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " ETBR2 ,Endpoint transmit buffer ready for physical IN endpoint 2" "Not ready,Ready"
|
|
bitfld.long 0x00 17. " ETBR1 ,Endpoint transmit buffer ready for physical IN endpoint 1" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " ETBR0 ,Endpoint transmit buffer ready for physical IN endpoint 0" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERBR5 ,Endpoint receive buffer ready for physical OUT endpoint 5" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " ERBR4 ,Endpoint receive buffer ready for physical OUT endpoint 4" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERBR3 ,Endpoint receive buffer ready for physical OUT endpoint 3" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ERBR2 ,Endpoint receive buffer ready for physical OUT endpoint 2" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " ERBR1 ,Endpoint receive buffer ready for physical OUT endpoint 1" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ERBR0 ,Endpoint receive buffer ready for physical OUT endpoint 0" "Not ready,Ready"
|
|
group.long 0x1BC++0x1B
|
|
line.long 0x00 "ENDPTCOMPLETE,USB Endpoint Complete register"
|
|
eventfld.long 0x00 21. " ETCE5 ,Endpoint transmit complete event for physical IN endpoint 5" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " ETCE4 ,Endpoint transmit complete event for physical IN endpoint 4" "Not occurred,Occurred"
|
|
eventfld.long 0x00 19. " ETCE3 ,Endpoint transmit complete event for physical IN endpoint 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " ETCE2 ,Endpoint transmit complete event for physical IN endpoint 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ETCE1 ,Endpoint transmit complete event for physical IN endpoint 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " ETCE0 ,Endpoint transmit complete event for physical IN endpoint 0" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " ERCE5 ,Endpoint receive complete event for physical OUT endpoint 5" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " ERCE4 ,Endpoint receive complete event for physical OUT endpoint 4" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERCE3 ,Endpoint receive complete event for physical OUT endpoint 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " ERCE2 ,Endpoint receive complete event for physical OUT endpoint 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " ERCE1 ,Endpoint receive complete event for physical OUT endpoint 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " ERCE0 ,Endpoint receive complete event for physical OUT endpoint 0" "Not occurred,Occurred"
|
|
textline ""
|
|
line.long 0x04 "ENDPTCTRL0,USB Endpoint 0 Control register"
|
|
rbitfld.long 0x04 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 18.--19. " TXT1_0 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x04 16. " TXS ,Tx endpoint stall" "Not stalled,Stalled"
|
|
textline " "
|
|
rbitfld.long 0x04 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2.--3. " RXT1_0 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x04 0. " RXS ,Rx endpoint stall" "Not stalled,Stalled"
|
|
line.long 0x8 "ENDPTCTRL1,USB Endpoint 1 Control register"
|
|
bitfld.long 0x8 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 22. " TXR ,Tx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x8 21. " TXI ,Tx data toggle inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x8 18.--19. " TXT1 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x8 16. " TXS ,Tx endpoint stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x8 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " RXR ,Rx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x8 5. " RXI ,Rx data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 2.--3. " RXT1 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x8 0. " RXS ,Rx endpoint stall" "Not stalled,Stalled"
|
|
line.long 0xC "ENDPTCTRL2,USB Endpoint 2 Control register"
|
|
bitfld.long 0xC 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 22. " TXR ,Tx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0xC 21. " TXI ,Tx data toggle inhibit" "Enabled,Disabled"
|
|
bitfld.long 0xC 18.--19. " TXT2 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0xC 16. " TXS ,Tx endpoint stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0xC 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " RXR ,Rx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0xC 5. " RXI ,Rx data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 2.--3. " RXT2 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0xC 0. " RXS ,Rx endpoint stall" "Not stalled,Stalled"
|
|
line.long 0x10 "ENDPTCTRL3,USB Endpoint 3 Control register"
|
|
bitfld.long 0x10 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " TXR ,Tx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x10 21. " TXI ,Tx data toggle inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x10 18.--19. " TXT3 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x10 16. " TXS ,Tx endpoint stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " RXR ,Rx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x10 5. " RXI ,Rx data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 2.--3. " RXT3 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x10 0. " RXS ,Rx endpoint stall" "Not stalled,Stalled"
|
|
line.long 0x14 "ENDPTCTRL4,USB Endpoint 4 Control register"
|
|
bitfld.long 0x14 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " TXR ,Tx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x14 21. " TXI ,Tx data toggle inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x14 18.--19. " TXT4 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x14 16. " TXS ,Tx endpoint stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " RXR ,Rx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x14 5. " RXI ,Rx data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " RXT4 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x14 0. " RXS ,Rx endpoint stall" "Not stalled,Stalled"
|
|
line.long 0x18 "ENDPTCTRL5,USB Endpoint 5 Control register"
|
|
bitfld.long 0x18 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " TXR ,Tx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x18 21. " TXI ,Tx data toggle inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x18 18.--19. " TXT5 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x18 16. " TXS ,Tx endpoint stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " RXR ,Rx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x18 5. " RXI ,Rx data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 2.--3. " RXT5 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x18 0. " RXS ,Rx endpoint stall" "Not stalled,Stalled"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
tree "USB1 Host/Device controller"
|
|
base ad:0x40007000
|
|
width 12.
|
|
tree "Device/host capability registers"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SBUSCFG,System bus interface configuration register"
|
|
bitfld.long 0x00 0.--2. " AHB_BRST ,Burst length" "Unspecified,INCR4/singles,INCR8/INCR4 or singles,INCR16/INCR4-8 or singles,,INCR4/unspecified,INCR8/unspecified,INCR16/unspecified"
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x00 "CAPLENGTH,CAPLENGTH register"
|
|
hexmask.long.word 0x00 8.--23. 1. " HCIVERSION ,BCD encoding of the EHCI revision number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Indicates offset to add to the register base address"
|
|
line.long 0x04 "HCSPARAMS,HCSPARAMS register"
|
|
bitfld.long 0x04 24.--27. " N_TT ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " N_PTT ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16. " PI ,Port indicators" "Not supported,Supported"
|
|
bitfld.long 0x04 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4. " PPC ,Port Power Control" "Not included,Included"
|
|
bitfld.long 0x04 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "HCCPARAMS,HCCPARAMS register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x08 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported"
|
|
bitfld.long 0x08 1. " PFL ,Programmable Frame List Flag" "Not used,Used"
|
|
bitfld.long 0x08 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported"
|
|
rgroup.long 0x120++0x7
|
|
line.long 0x00 "DCIVERSION,DCIVERSION register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register"
|
|
line.long 0x4 "DCCPARAMS,DCCPARAMS"
|
|
bitfld.long 0x4 8. " HC ,Host Capable" "No,Yes"
|
|
bitfld.long 0x4 7. " DC ,Device Capable" "No,Yes"
|
|
bitfld.long 0x4 0.--4. " DEN ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 18.
|
|
tree "Device/host operational registers"
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "USBCMD_D,USB Command register in device mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,Add dTD trip wire" "Not ensured,Ensured"
|
|
bitfld.long 0x00 13. " SUTW ,Setup trip wire" "Not ensured,Ensured"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "USBCMD_H,USB Command register in host mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FS2 ,Bit 2 of the Frame List Size bits" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASP1_0 ,Asynchronous schedule park mode" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,This bit is used as a doorbell by software" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASE ,This bit controls whether the host controller skips processing the asynchronous schedule" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,This bit controls whether the host controller skips processing the periodic schedule" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FS1 ,Bit 1 of the Frame List Size bits" "0,1"
|
|
bitfld.long 0x00 2. " FS0 ,Bit 0 of the Frame List Size bits" "0,1"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
endif
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "USBSTS_D,USB Status register in device mode"
|
|
rbitfld.long 0x00 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " SLI ,DCSuspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
eventfld.long 0x00 6. " URI ,USB reset received" "Not received,Received"
|
|
eventfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PCI ,Port change detect" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " UEI ,USB error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "USBSTS_H,USB Status register in host mode"
|
|
eventfld.long 0x00 19. " UPI ,USB host periodic interrupt" "Not interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " UAI ,USB host asynchronous interrupt" "Not interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " AS ,Asynchronous schedule status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " PS ,Periodic schedule status" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " RCL ,Reclamation" "No empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " HCH ,HCHalted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " AAI ,Interrupt on async advance" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRI ,Frame list roll-over" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PCI ,Port change detect" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " UEI ,USB error interrupt" "Not interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UI ,USB interrupt" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "USBINTR_D,USB Interrupt register"
|
|
bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF received enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " URE ,USB reset enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "USBINTR_H,USB Interrupt register"
|
|
bitfld.long 0x00 19. " UPIA ,USB host periodic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF received enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on asynchronous advance enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("LPC43*"))
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
rgroup.long 0x14C++0x3
|
|
line.long 0x00 "FRINDEX_D,USB frame index register in device mode"
|
|
hexmask.long.word 0x00 3.--13. 1. " FRINDEX13_3 ,Current frame number of the last frame transmitted"
|
|
bitfld.long 0x00 0.--2. " FRINDEX2_0 ,Current micro frame number" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "FRINDEX_H,USB frame index register in host mode"
|
|
hexmask.long.word 0x00 3.--12. 1. " FRINDEX12_3 ,Frame list current index"
|
|
bitfld.long 0x00 0.--2. " FRINDEX2_0 ,Current micro frame number" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "FRINDEX_D,USB frame index register in device mode"
|
|
hexmask.long.word 0x00 3.--13. 1. " FRINDEX13_3 ,Current frame number of the last frame transmitted"
|
|
bitfld.long 0x00 0.--2. " FRINDEX2_0 ,Current micro frame number" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "FRINDEX_H,USB frame index register in host mode"
|
|
hexmask.long.word 0x00 3.--12. 1. " FRINDEX12_3 ,Frame list current index"
|
|
bitfld.long 0x00 0.--2. " FRINDEX2_0 ,Current micro frame number" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x154++0xF
|
|
line.long 0x00 "DEVICEADDR,USB Device Address register in device mode"
|
|
hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,USB device address"
|
|
textline " "
|
|
bitfld.long 0x00 24. " USBADRA ,Device address advance" "0,1"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x154++0x13
|
|
line.long 0x00 "PERIODICLISTBASE,USB Periodic List Base register in host mode"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " PERBASE31_12 ,Base Address (Low)"
|
|
textline " "
|
|
endif
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x158++0x3
|
|
line.long 0x00 "ENDPOINTLISTADDR,USB Endpoint List Address register in device mode"
|
|
hexmask.long 0x00 11.--31. 1. " EPBASE31_11 ,Endpoint list pointer (low)"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x158++0x7
|
|
line.long 0x00 "ASYNCLISTADDR,USB Asynchronous List Address register in host mode"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE31_5 ,Link pointer (Low) LPL"
|
|
line.long 0x04 "TTCTRL,USB TT Control register in host mode"
|
|
hexmask.long.byte 0x04 24.--30. 1. " TTHA ,Hub address when FS or LS device are connected directly"
|
|
endif
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "BURSTSIZE,USB burst size register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programmable TX burst length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX burst length"
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x164++0x3
|
|
line.long 0x00 "TXFILLTUNING,USB Transfer buffer Fill Tuning register in host mode"
|
|
hexmask.long.byte 0x00 16.--21. 1. " TXFIFOTHRES ,Scheduler overhead"
|
|
bitfld.long 0x00 8.--12. " TXSCHEATLTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXSCHOH ,FIFO burst threshold"
|
|
endif
|
|
sif (!cpuis("LPC43?????10*")&&!cpuis("LPC43?????14*"))
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "ULPIVIEWPORT,USB ULPI viewport register"
|
|
bitfld.long 0x00 31. " ULPIWU ,ULPI Wake-up" "No efect,Wake-up"
|
|
bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "Idle,Run"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write control" "Read,Write"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " ULPISS ,ULPI sync state" "Another,Sync."
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,Wake up or read/write operation executed" "Executed,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,Address of the operation (read or write)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,Result of completion read operation"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,Data to be sent"
|
|
else
|
|
group.long 0x170++0x3
|
|
line.long 0x00 "ULPIVIEWPORT,USB ULPI viewport register"
|
|
bitfld.long 0x00 31. " ULPIWU ,ULPI Wake-up" "Complete,Wake-up"
|
|
bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "Complete,Read/Write"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write control" "Read,Write"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI sync state" "Another state,Normal Sync."
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,For the wakeup or read/write operation to be executed" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,When a read or write operation is commanded, the address of the operation is written to this field"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,After a read operation completes, the result is placed in this field"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,When a write operation is commanded, the data to be sent is written to this field"
|
|
endif
|
|
group.long 0x174++0x3
|
|
line.long 0x00 "BINTERVAL,USB BINTERVAL register"
|
|
bitfld.long 0x00 0.--3. " BINT ,bInterval value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x178++0x7
|
|
line.long 0x00 "ENDPTNAK,USB endpoint NAK register"
|
|
eventfld.long 0x00 19. " EPTN3 ,Tx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 18. " EPTN2 ,Tx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " EPTN1 ,Tx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 16. " EPTN0 ,Tx endpoint NAK" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 3. " EPRN3 ,Rx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 2. " EPRN2 ,Rx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPRN1 ,Rx endpoint NAK" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " EPRN0 ,Rx endpoint NAK" "Not detected,Detected"
|
|
line.long 0x04 "ENDPTNAKEN,USB endpoint NAK enable register"
|
|
bitfld.long 0x04 19. " EPTNE3 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " EPTNE2 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " EPTNE1 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " EPTNE0 ,Tx endpoint NAK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EPRNE3 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " EPRNE2 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EPRNE1 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EPRNE0 ,Rx endpoint NAK enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("LPC432*")||cpuis("LPC433*")||cpuis("LPC435*")||cpuis("LPC437*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*")||cpuis("LPC43S7*"))
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_D,Port Status and Control register in device mode"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,Serial/1.1 PHY"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset"
|
|
rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "No resume,Resume"
|
|
rbitfld.long 0x00 3. " PEC ,Port enable/disable change" "Enabled,?..."
|
|
rbitfld.long 0x00 2. " PE ,Port enable" ",Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)&&(((per.l(ad:0x40007000+0x184))&0x1000)==0)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_H,Port Status and Control register in host mode"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,Serial/1.1 PHY"
|
|
textline " "
|
|
rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low-speed,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,?..."
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,?..."
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port power control" "Power off,Power on"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,Undefined"
|
|
rbitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "No reset,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,?..."
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "No resume,?..."
|
|
eventfld.long 0x00 5. " OCC ,Over-current change" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current active" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port enable/disable change" "No changed,?..."
|
|
bitfld.long 0x00 2. " PE ,Port enable" "Disabled,?..."
|
|
eventfld.long 0x00 1. " CSC ,Connect status change" "No changed,?..."
|
|
eventfld.long 0x00 0. " CCS ,Current connect status" "Not attached,?..."
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)&&(((per.l(ad:0x40007000+0x184))&0x1000)==0x1000)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_H,Port Status and Control register in host mode"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,Serial/1.1 PHY"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low-speed,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port power control" "Power off,Power on"
|
|
bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,Undefined"
|
|
bitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "No resume,Resume"
|
|
eventfld.long 0x00 5. " OCC ,Over-current change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " OCA ,Over-current active" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port enable/disable change" "No changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " CSC ,Connect status change" "No changed,Changed"
|
|
eventfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_D,Port Status and Control register in device mode"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,Serial/1.1 PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset"
|
|
rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FPR ,Force port resume" "No resume,Resume"
|
|
rbitfld.long 0x00 3. " PEC ,Port enable/disable change" "Enabled,?..."
|
|
rbitfld.long 0x00 2. " PE ,Port enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached"
|
|
elif (((per.l(ad:0x40007000+0x1A8))&0x3)==0x3)
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PORTSC1_H,Port Status and Control register in host mode"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,Serial/1.1 PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full speed,Low speed,High speed,?..."
|
|
bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Any speed,Full speed"
|
|
bitfld.long 0x00 23. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC3_0 ,Port test control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_FS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC1_0 ,Port indicator control" "Off,Amber,Green,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port power control" "Power off,Power on"
|
|
bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,Undefined"
|
|
bitfld.long 0x00 9. " HSP ,High-speed status" "No,Yes"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "No resume,Resume"
|
|
bitfld.long 0x00 5. " OCC ,Over-current change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " OCA ,Over-current active" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "Enabled,?..."
|
|
bitfld.long 0x00 2. " PE ,Port enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " CSC ,Connect status change" "No change,Change"
|
|
eventfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40007000+0x1A8))&0x3)==0x2)
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "USBMODE_D,USB Mode register in device mode"
|
|
bitfld.long 0x00 4. " SDIS ,Stream disable mode" "No,Yes"
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout mode" "On,Off"
|
|
bitfld.long 0x00 2. " ES ,Endian select" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CM1_0 ,Controller mode" "Idle,,Device,Host"
|
|
else
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "USBMODE_H,USB Mode register in host mode"
|
|
bitfld.long 0x00 5. " VBPS ,VBUS power select" "Low,High"
|
|
bitfld.long 0x00 4. " SDIS ,Stream disable mode" "No,Yes"
|
|
bitfld.long 0x00 2. " ES ,Endian select" "Little endian,Big endian"
|
|
textline " "
|
|
sif (cpuis("LPC432*")||cpuis("LPC433*")||cpuis("LPC435*")||cpuis("LPC437*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*")||cpuis("LPC43S7*"))
|
|
bitfld.long 0x00 0.--1. " CM1_0 ,Controller mode" "Idle,,Device,Host"
|
|
textfld ""
|
|
else
|
|
bitfld.long 0x00 0.--1. " CM1_0 ,Controller mode" "Idle,,Device,Host"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 16.
|
|
tree "Device endpoint registers"
|
|
group.long 0x1AC++0xB
|
|
line.long 0x00 "ENDPTSETUPSTAT,USB Endpoint Setup Status register"
|
|
eventfld.long 0x00 3. " ENDPTSET_UPSTAT3 ,Setup endpoint status for logical endpoint 3" "Low,High"
|
|
eventfld.long 0x00 2. " ENDPTSET_UPSTAT2 ,Setup endpoint status for logical endpoint 2" "Low,High"
|
|
eventfld.long 0x00 1. " ENDPTSET_UPSTAT1 ,Setup endpoint status for logical endpoint 1" "Low,High"
|
|
eventfld.long 0x00 0. " ENDPTSET_UPSTAT0 ,Setup endpoint status for logical endpoint 0" "Low,High"
|
|
textline ""
|
|
line.long 0x04 "ENDPTPRIME,USB Endpoint Prime register"
|
|
bitfld.long 0x04 19. " PETB3 ,Prime endpoint transmit buffer for physical IN endpoint 3" "Low,High"
|
|
bitfld.long 0x04 18. " PETB2 ,Prime endpoint transmit buffer for physical IN endpoint 2" "Low,High"
|
|
bitfld.long 0x04 17. " PETB1 ,Prime endpoint transmit buffer for physical IN endpoint 1" "Low,High"
|
|
bitfld.long 0x04 16. " PETB0 ,Prime endpoint transmit buffer for physical IN endpoint 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PERB3 ,Prime endpoint receive buffer for physical OUT endpoint 3" "Low,High"
|
|
bitfld.long 0x04 2. " PERB2 ,Prime endpoint receive buffer for physical OUT endpoint 2" "Low,High"
|
|
bitfld.long 0x04 1. " PERB1 ,Prime endpoint receive buffer for physical OUT endpoint 1" "Low,High"
|
|
bitfld.long 0x04 0. " PERB0 ,Prime endpoint receive buffer for physical OUT endpoint 0" "Low,High"
|
|
line.long 0x08 "ENDPTFLUSH,USB Endpoint Flush register"
|
|
eventfld.long 0x08 19. " FETB3 ,Flush endpoint transmit buffer for physical IN endpoint 3" "Low,High"
|
|
eventfld.long 0x08 18. " FETB2 ,Flush endpoint transmit buffer for physical IN endpoint 2" "Low,High"
|
|
eventfld.long 0x08 17. " FETB1 ,Flush endpoint transmit buffer for physical IN endpoint 1" "Low,High"
|
|
eventfld.long 0x08 16. " FETB0 ,Flush endpoint transmit buffer for physical IN endpoint 0" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x08 3. " FERB3 ,Flush endpoint receive buffer for physical OUT endpoint 3" "Low,High"
|
|
eventfld.long 0x08 2. " FERB2 ,Flush endpoint receive buffer for physical OUT endpoint 2" "Low,High"
|
|
eventfld.long 0x08 1. " FERB1 ,Flush endpoint receive buffer for physical OUT endpoint 1" "Low,High"
|
|
eventfld.long 0x08 0. " FERB0 ,Flush endpoint receive buffer for physical OUT endpoint 0" "Low,High"
|
|
rgroup.long 0x1B8++0x3
|
|
line.long 0x00 "ENDPTSTAT,USB Endpoint Status register"
|
|
bitfld.long 0x00 19. " ETBR3 ,Endpoint transmit buffer ready for physical IN endpoint 3" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " ETBR2 ,Endpoint transmit buffer ready for physical IN endpoint 2" "Not ready,Ready"
|
|
bitfld.long 0x00 17. " ETBR1 ,Endpoint transmit buffer ready for physical IN endpoint 1" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " ETBR0 ,Endpoint transmit buffer ready for physical IN endpoint 0" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERBR3 ,Endpoint receive buffer ready for physical OUT endpoint 3" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ERBR2 ,Endpoint receive buffer ready for physical OUT endpoint 2" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " ERBR1 ,Endpoint receive buffer ready for physical OUT endpoint 1" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ERBR0 ,Endpoint receive buffer ready for physical OUT endpoint 0" "Not ready,Ready"
|
|
group.long 0x1BC++0x13
|
|
line.long 0x00 "ENDPTCOMPLETE,USB Endpoint Complete register"
|
|
eventfld.long 0x00 21. " ETCE5 ,Endpoint transmit complete event for physical IN endpoint 5" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " ETCE4 ,Endpoint transmit complete event for physical IN endpoint 4" "Not occurred,Occurred"
|
|
eventfld.long 0x00 19. " ETCE3 ,Endpoint transmit complete event for physical IN endpoint 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " ETCE2 ,Endpoint transmit complete event for physical IN endpoint 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ETCE1 ,Endpoint transmit complete event for physical IN endpoint 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " ETCE0 ,Endpoint transmit complete event for physical IN endpoint 0" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " ERCE5 ,Endpoint receive complete event for physical OUT endpoint 5" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " ERCE4 ,Endpoint receive complete event for physical OUT endpoint 4" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERCE3 ,Endpoint receive complete event for physical OUT endpoint 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " ERCE2 ,Endpoint receive complete event for physical OUT endpoint 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " ERCE1 ,Endpoint receive complete event for physical OUT endpoint 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " ERCE0 ,Endpoint receive complete event for physical OUT endpoint 0" "Not occurred,Occurred"
|
|
textline ""
|
|
line.long 0x04 "ENDPTCTRL0,USB Endpoint 0 Control register"
|
|
bitfld.long 0x04 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18.--19. " TXT1_0 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x04 16. " TXS ,Tx endpoint stall" "OK,Stalled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2.--3. " RXT1_0 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x04 0. " RXS ,Rx endpoint stall" "OK,Stalled"
|
|
line.long 0x8 "ENDPTCTRL1,USB Endpoint 1 Control register"
|
|
bitfld.long 0x8 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 22. " TXR ,Tx data toggle reset" ",Reset"
|
|
bitfld.long 0x8 21. " TXI ,Tx data toggle inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x8 18.--19. " TXT1 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x8 16. " TXS ,Tx endpoint stall" "OK,Stalled"
|
|
bitfld.long 0x8 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 6. " RXR ,Rx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x8 5. " RXI ,Rx data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 2.--3. " RXT1 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x8 0. " RXS ,Rx endpoint stall" "OK,Stalled"
|
|
line.long 0xC "ENDPTCTRL2,USB Endpoint 2 Control register"
|
|
bitfld.long 0xC 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 22. " TXR ,Tx data toggle reset" ",Reset"
|
|
bitfld.long 0xC 21. " TXI ,Tx data toggle inhibit" "Enabled,Disabled"
|
|
bitfld.long 0xC 18.--19. " TXT2 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0xC 16. " TXS ,Tx endpoint stall" "OK,Stalled"
|
|
bitfld.long 0xC 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 6. " RXR ,Rx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0xC 5. " RXI ,Rx data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 2.--3. " RXT2 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0xC 0. " RXS ,Rx endpoint stall" "OK,Stalled"
|
|
line.long 0x10 "ENDPTCTRL3,USB Endpoint 3 Control register"
|
|
bitfld.long 0x10 23. " TXE ,Tx endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " TXR ,Tx data toggle reset" ",Reset"
|
|
bitfld.long 0x10 21. " TXI ,Tx data toggle inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x10 18.--19. " TXT3 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x10 16. " TXS ,Tx endpoint stall" "OK,Stalled"
|
|
bitfld.long 0x10 7. " RXE ,Rx endpoint enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " RXR ,Rx data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x10 5. " RXI ,Rx data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 2.--3. " RXT3 ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x10 0. " RXS ,Rx endpoint stall" "OK,Stalled"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
tree "ETH (Ethernet)"
|
|
base ad:0x40010000
|
|
width 23.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "MAC_CONFIG,MAC Configuration register"
|
|
bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes"
|
|
bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--19. " IFG ,Inter-frame gap" "96,88,80,72,64,56,48,40"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DCRS ,Disable carrier sense during transmission" "No,Yes"
|
|
bitfld.long 0x00 15. " PS ,Port select" "Reserved,MII"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FES ,Speed" "10Mbps,100Mbps"
|
|
bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LM ,Loopback Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DM ,Duplex Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR ,Disable Retry" "No,Yes"
|
|
bitfld.long 0x00 8. " LN ,Link Up/Down" "Down,Up"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " BL ,Back-Off Limit" "min(n;10),min(n;8),min(n;4),min(n;1)"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DF ,Deferral Check" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
line.long 0x04 "MAC_FRAME_FILTER,MAC Frame filter register"
|
|
bitfld.long 0x04 31. " RA ,Receive all" "No,Yes"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
textline " "
|
|
bitfld.long 0x04 10. " HPF ,Hash or perfect filter" "Hash,Perfect"
|
|
bitfld.long 0x04 6.--7. " PCF ,Pass Control Frames" "None,All except PAUSE (even address filtered),All (even address filtered),All (address passed)"
|
|
else
|
|
bitfld.long 0x04 9. " SAF ,Source Address Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SAIF ,SA Inverse Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x04 6.--7. " PCF ,Pass Control Frames" "From reaching the application,To appl. even if they fail the Address filter,Even if they fail the Address Filter,Pass the Address Filter"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 5. " DBF ,Disable Broadcast Frames" "No,Yes"
|
|
bitfld.long 0x04 4. " PM ,Pass All Multicast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAIF ,DA Inverse Filtering" "Disabled,Enabled"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x04 2. " HMC ,Hash Multicast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HUC ,Hash Unicast" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x04 0. " PR ,Promiscuous Mode" "Disabled,Enabled"
|
|
line.long 0x08 "MAC_HASHTABLE_HIGH,MAC Hash table high register"
|
|
line.long 0x0C "MAC_HASHTABLE_LOW,MAC Hash table low register"
|
|
line.long 0x10 "MAC_MII_ADDR,MAC MII Address register"
|
|
bitfld.long 0x10 11.--15. " PA ,Physical layer address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 6.--10. " GR ,MII register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 2.--5. " CR ,CSR clock range" "/42,/62,/16,/26,/102,/124,Reserved,Reserved,/42,/62,/16,/26,/102,/124,/42,/62"
|
|
bitfld.long 0x10 1. " W ,MII write" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x10 0. " GB ,MII busy" "Idle,Busy"
|
|
line.long 0x14 "MAC_MII_DATA,MII Data register"
|
|
hexmask.long.word 0x14 0.--15. 1. " GD ,MII data"
|
|
line.long 0x18 "MAC_FLOW_CTRL,MAC Flow control register"
|
|
hexmask.long.word 0x18 16.--31. 1. " PT ,Pause time"
|
|
bitfld.long 0x18 7. " DZPQ ,Disable Zero-Quanta Pause" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 4.--5. " PLT ,Pause Low Threshold" "0,1,2,3"
|
|
bitfld.long 0x18 3. " UP ,Unicast Pause Frame Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " RFE ,Receive Flow Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " TFE ,Transmit Flow Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " FCB ,Flow Control Busy/Backpressure Activate" "Not activated,Activated"
|
|
line.long 0x1C "MAC_VLAN_TAG,MAC VLAN tag register"
|
|
bitfld.long 0x1C 16. " ETV ,Enable 12-Bit VLAN Tag Comparison" "Disabled,Enabled"
|
|
hexmask.long.word 0x1C 0.--15. 1. " VL ,VLAN Tag Identifier for Receive Frames"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "MAC_DEBUG,MAC Debug register"
|
|
bitfld.long 0x00 25. " TXFIFOFULL ,TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission" "Not full,Full"
|
|
bitfld.long 0x00 24. " TXFIFOLVL ,TxFIFO is not empty and has some data left for transmission" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TXFIFOSTAT1 ,TxFIFO Write Controller" "Not activated,Activated"
|
|
bitfld.long 0x00 20.--21. " TXFIFOSTAT ,State of the TxFIFO read Controller" "Idle,Read,Waiting for TxStatus from MAC transmitter,Writing the received TxStatus or flushing the TxFIFO"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PAUSE ,MAC transmitter PAUSE condition" "Not paused,Paused"
|
|
bitfld.long 0x00 17.--18. " TXSTAT ,State of the MAC Transmit Frame Controller module" "Idle,Waiting for Status of previous frame or IFG/backoff period to be over,Generating and transmitting a PAUSE control frame,Transferring input frame for transmission"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXIDLESTAT ,MAC MII transmit protocol engine " "Not transmitting,Transmitting"
|
|
bitfld.long 0x00 8.--9. " RXFIFOLVL ,Status of the RxFIFO Fill-level" "Empty,de-activate,activate,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RXFIFOSTAT ,State of the RxFIFO read Controller" "Idle,Reading frame data,reading frame status,Flushing the frame data and status"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXFIFOSTAT1 ,MTL RxFIFO Write Controller State" "Not activated,Activated"
|
|
bitfld.long 0x00 1.--2. " FIFOSTAT0 ,State of the small FIFO Read and Write controllers" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXIDLESTAT ,MAC MII receive protocol engine" "Not receiving,Receiving"
|
|
group.long 0x28++0x7
|
|
line.long 0x00 "MAC_RWAKE_FRFLT,MAC Remote wake-up frame filter register"
|
|
line.long 0x04 "MAC_PMT_CTRL_STAT,MAC PMT control and status register"
|
|
bitfld.long 0x04 31. " WFFRPR ,Wake-up Frame Filter Register Pointer Reset" "No reset,Reset"
|
|
bitfld.long 0x04 9. " GU ,Global Unicast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WFR ,Wake-up Frame Received" "Not received,Received"
|
|
bitfld.long 0x04 5. " MPR ,Magic Packet Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WFE ,Wake-up frame enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " MPE ,Magic packet enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PD ,Power-down" "Up,Down"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "MAC_INTR,MAC Interrupt status register"
|
|
bitfld.long 0x00 9. " TS ,Timestamp interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PMT ,PMT Interrupt Status" "Not received,Received"
|
|
group.long 0x3C++0xB
|
|
line.long 0x00 "MAC_INTR_MASK,MAC Interrupt mask register"
|
|
bitfld.long 0x00 9. " TSIM ,Timestamp interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " PMTIM ,PMT Interrupt Mask" "Not masked,Masked"
|
|
line.long 0x04 "MAC_ADDR0_HIGH,MAC Address 0 high register"
|
|
bitfld.long 0x04 31. " MO ,Always 1" "0,1"
|
|
hexmask.long.word 0x04 0.--15. 1. " A47_32 ,MAC Address0"
|
|
line.long 0x08 "MAC_ADDR0_LOW,MAC Address 0 low register"
|
|
group.long 0x700++0xB
|
|
line.long 0x00 "MAC_TIMESTP_CTRL,MAC IEEE1588 time stamp control register"
|
|
bitfld.long 0x00 18. " TSENMACADDR ,Enable MAC address for PTP frame filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TSCLKTYPE ,Select the type of clock node" "Ordinary,Boundary,End-to-end,peer-to-peer"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TSMSTRENA ,Enable Snapshot for Messages Relevant to Master" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TSEVNTENA ,Enable Time Stamp Snapshot for Event Messages" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TSIPV4ENA ,Enable Time Stamp Snapshot for IPv4 frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TSIPV6ENA ,Enable Time Stamp Snapshot for IPv6 frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TSIPENA ,Enable Time Stamp Snapshot for PTP over Ethernet frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TSVER2ENA ,Enable PTP packet snooping for version 2 format" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TSCTRLSSR ,Time Stamp Digital or Binary rollover control" "Binary,Digital"
|
|
bitfld.long 0x00 8. " TSENALL ,Enable Time Stamp for All Frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TSADDREG ,Addend Reg Update" "Not updated,Updated"
|
|
bitfld.long 0x00 4. " TSTRIG ,Time Stamp Interrupt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TSUPDT ,Time Stamp Update" "Not updated,Updated"
|
|
bitfld.long 0x00 2. " TSINIT ,Time Stamp Initialize" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TSCFUPDT ,Time Stamp Fine or Coarse Update" "Not updated,Updated"
|
|
bitfld.long 0x00 0. " TSENA ,Time Stamp Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SUBSECOND_INCR,Sub-second increment register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SSINC ,Sub-second increment value"
|
|
line.long 0x08 "SECONDS,System time seconds register"
|
|
rgroup.long 0x70C++0x3
|
|
line.long 0x00 "NANOSECONDS,System time nanoseconds register"
|
|
bitfld.long 0x00 31. " PSNT ,Positive or negative time" "Positive,Negative"
|
|
hexmask.long 0x00 0.--30. 1. " TSSS ,Time stamp sub seconds"
|
|
group.long 0x710++0xF
|
|
line.long 0x00 "SECONDSUPDATE,System time seconds update register"
|
|
line.long 0x04 "NANOSECONDSUPDATE,System time nanoseconds update register"
|
|
bitfld.long 0x04 31. " ADDSUB ,Add or subtract time" "Not substracted,Substracted"
|
|
hexmask.long 0x04 0.--31. 1. " TSSS ,Time stamp sub seconds"
|
|
line.long 0x08 "ADDEND,Time stamp addend register"
|
|
line.long 0x0C "TARGETSECONDS,Target time seconds register"
|
|
rgroup.long 0x720++0x3
|
|
line.long 0x00 "TARGETNANOSECONDS,Target time nanoseconds register"
|
|
group.long 0x724++0x7
|
|
line.long 0x00 "HIGHWORD,System time higher words seconds register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSHWR ,Time stamp higher word"
|
|
line.long 0x04 "TIMESTAMPSTAT,Time stamp status register"
|
|
bitfld.long 0x04 1. " TSTARGT ,Time stamp target reached" "Lower,Greater or equal"
|
|
bitfld.long 0x04 0. " TSSOVF ,Time stamp seconds overflow" "Not overflowed,Overflowed"
|
|
group.long 0x1000++0x1F
|
|
line.long 0x00 "DMA_BUS_MODE,DMA Bus mode register"
|
|
bitfld.long 0x00 27. " TXPR ,When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus" "Lower,Higher"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AAL ,Address-aligned beats" "Not set,Set"
|
|
bitfld.long 0x00 24. " PBL8X ,8 x PBL mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Not used,Used"
|
|
bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "-,1,2,Reserved,4,Reserved,Reserved,Reserved,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PR ,Rx-to-Tx priority ratio" "1-to-1,2-to-1,3-to-1,4-to-1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " PBL ,Programmable burst length" "Reserved,1,2,Reserved,4,Reserved,Reserved,Reserved,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,?..."
|
|
bitfld.long 0x00 7. " ATDS ,Alternate descriptor size" "16 bytes,32 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration scheme" "Round-robin with Rx,Rx has priority over Tx"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "DMA_TRANS_POLL_DEMAND,DMA Transmit poll demand register"
|
|
line.long 0x08 "DMA_REC_POLL_DEMAND,DMA Receive poll demand register"
|
|
line.long 0x0C "DMA_REC_DES_ADDR,DMA Receive descriptor list address register"
|
|
line.long 0x10 "DMA_TRANS_DES_ADDR,DMA Transmit descriptor list address register"
|
|
line.long 0x14 "DMA_STAT,DMA Status register"
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
rbitfld.long 0x14 25. " EB3 ,Bus Error error access type" "Data buffer,Descriptor"
|
|
rbitfld.long 0x14 24. " EB2 ,Bus error transfer direction" "Write,Read"
|
|
textline " "
|
|
rbitfld.long 0x14 23. " EB1 ,Bus Error error source" "RxDMA,TxDMA"
|
|
rbitfld.long 0x14 20.--22. " TS ,Transmit process state" "Stopped,Running (Fetch),Running (Wait),Running (Read),TIME_STAMP write,Reserved,Suspended,Running (Close)"
|
|
textline " "
|
|
rbitfld.long 0x14 17.--19. " RS ,Receive process state" "Stopped,Running (Fetch),Reserved,Running (Wait),Suspended,Running (Close),TIME_STAMP write,Running (Transfer)"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 16. " NIS ,Normal interrupt summary" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 15. " AIE ,Abnormal interrupt summary" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 14. " ERI ,Early receive interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 13. " FBI ,Fatal bus error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 10. " ETI ,Early transmit interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 9. " RWT ,Receive watchdog timeout" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x14 8. " RPS ,Received process stopped" "Running,Stopped"
|
|
bitfld.long 0x14 7. " RU ,Receive buffer unavailable" "Available,Unavailable"
|
|
textline " "
|
|
bitfld.long 0x14 6. " RI ,Receive interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 5. " UNF ,Transmit underflow" "Not overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x14 4. " OVF ,Receive overflow" "Not overflow,Overflow"
|
|
bitfld.long 0x14 3. " TJT ,Transmit jabber timeout" "Not expired,Expired"
|
|
textline " "
|
|
bitfld.long 0x14 2. " TU ,Transmit buffer unavailable" "Available,Unavailable"
|
|
bitfld.long 0x14 1. " TPS ,Transmit process stopped" "Running,Stopped"
|
|
textline " "
|
|
bitfld.long 0x14 0. " TI ,Transmit interrupt" "No interrupt,Interrupt"
|
|
line.long 0x18 "DMA_OP_MODE,DMA operation mode register"
|
|
bitfld.long 0x18 24. " DFF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x18 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
bitfld.long 0x18 13. " ST ,Start/Stop Transmission Command" "Stop,Start"
|
|
textline " "
|
|
bitfld.long 0x18 7. " FEF ,Forward error frames" "No error,Error"
|
|
bitfld.long 0x18 6. " FUF ,Forward undersized good frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x18 2. " OSF ,Operate on second frame" "Not on second frame,On second frame"
|
|
textline " "
|
|
bitfld.long 0x18 1. " SR ,Start/stop receive" "Stop,Start"
|
|
line.long 0x1C "DMA_INT_EN,DMA Interrupt enable register"
|
|
bitfld.long 0x1C 16. " NIE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 15. " AIE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " ERE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 13. " FBE ,Fatal bus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " ETE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " RWE ,Receive watchdog timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " RSE ,Received stopped stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 7. " RUE ,Receive buffer unavailable enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " UNE ,Transmit underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " OVE ,Receive overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 3. " TJE ,Transmit jabber timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " TUE ,Transmit buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " TSE ,Transmit stopped enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x00 "DMA_MFRM_BUFOF,DMA Missed frame and buffer overflow counter register"
|
|
bitfld.long 0x00 28. " OF ,Overflow bit for FIFO overflow counter" "No overflow,Overflow"
|
|
hexmask.long.word 0x00 17.--27. 1. " FMA ,Number of frames missed by the application"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OC ,Overflow bit for missed frame counter" "No overflow,Overflow"
|
|
hexmask.long.word 0x00 0.--15. 1. " FMC ,Number of frames missed"
|
|
group.long 0x1024++0x3
|
|
line.long 0x00 "DMA_REC_INT_WDT,DMA Receive interrupt watchdog timer register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI watchdog timeout"
|
|
rgroup.long 0x1048++0xF
|
|
line.long 0x00 "DMA_CURHOST_TRANS_DES,DMA Current host transmit descriptor register"
|
|
line.long 0x04 "DMA_CURHOST_REC_DES,DMA Current host receive descriptor register"
|
|
line.long 0x08 "DMA_CURHOST_TRANS_BUF,DMA Current host transmit buffer address register"
|
|
line.long 0x0C "DMA_CURHOST_REC_BUF,DMA Current host receive buffer address register"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("LPC185*")
|
|
tree "LCD"
|
|
base ad:0x40008000
|
|
width 14.
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850"&&cpu()!="LPC1853"&&cpu()!="LPC1857")&&(cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
group.long 0x200841B8++0x3
|
|
line.long 0x00 "LCD_CFG,LCD Configuration register"
|
|
bitfld.long 0x00 0.--4. " CLKDIV ,LCD panel clock prescaler selection" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "LCD_TIMH,Horizontal Timing register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " HBP ,Horizontal back porch"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HFP ,Horizontal front porch"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSW ,Horizontal synchronization pulse width"
|
|
textline " "
|
|
bitfld.long 0x00 2.--7. " PPL ,Pixels-per-line" "16,32,48,64,80,96,112,128,144,160,176,192,208,224,240,256,272,288,304,320,336,352,368,384,400,416,432,448,464,480,496,512,528,544,560,576,592,608,624,640,656,672,688,704,720,736,752,768,784,800,816,832,848,864,880,896,912,928,944,960,976,992,1008,1024"
|
|
line.long 0x04 "LCD_TIMV,Vertical Timing register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " VBP ,Vertical back porch"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VFP ,Vertical front porch"
|
|
bitfld.long 0x04 10.--15. " VSW ,Vertical synchronization pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " LPP ,Lines per panel"
|
|
line.long 0x08 "LCD_POL,Clock and Signal Polarity register"
|
|
bitfld.long 0x08 27.--31. " PCD_HI ,Panel clock divisor High" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 26. " BCD ,Bypass pixel clock divider" "Not bypassed,Bypassed"
|
|
hexmask.long.word 0x08 16.--25. 1. " CPL ,Clocks per line"
|
|
textline " "
|
|
bitfld.long 0x08 14. " IOE ,Invert output enable" "Active HIGH,Active LOW"
|
|
bitfld.long 0x08 13. " IPC ,Invert panel clock" "Rising,Falling"
|
|
bitfld.long 0x08 12. " IHS ,Invert horizontal synchronization" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 11. " IVS ,Invert vertical synchronization" "Not inverted,Inverted"
|
|
bitfld.long 0x08 6.--10. " ACB ,AC bias pin frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 5. " CLKSEL ,Selection of the source for LCDCLK" "CCLK,LCD_CLKIN"
|
|
textline " "
|
|
bitfld.long 0x08 0.--4. " PCD_LO ,Panel clock divisor Low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "LCD_LE,Line End Control register"
|
|
bitfld.long 0x0C 16. " LEE ,LCD Line end enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " LED ,Line-end delay"
|
|
line.long 0x10 "LCD_UPBASE,Upper Panel Frame Base Address register"
|
|
hexmask.long 0x10 3.--31. 0x8 " LCDUPBASE ,LCD upper panel base address"
|
|
line.long 0x14 "LCD_LPBASE,Lower Panel Frame Base Address register"
|
|
hexmask.long 0x14 3.--31. 0x8 " LCDLPBASE ,LCD lower panel base address"
|
|
if (((per.l(ad:0x40008018))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "LCD_CTRL,LCD Control register"
|
|
bitfld.long 0x00 16. " WATERMARK ,LCD DMA FIFO watermark level" ">=4,>=8"
|
|
bitfld.long 0x00 12.--13. " LCDVCOMP ,LCD Vertical Compare Interrupt" "Vsync,Back porch,Active video,Front porch"
|
|
bitfld.long 0x00 11. " LCDPWR ,LCD power enable" "Not gated,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BEPO ,Big-Endian Pixel Ordering" "Little,Big"
|
|
bitfld.long 0x00 9. " BEBO ,Big-endian Byte Order" "Little,Big"
|
|
bitfld.long 0x00 8. " BGR ,Color format selection" "RGB,BGR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCDDUAL ,Single or Dual LCD panel selection" "Single,Dual"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LCDTFT ,LCD panel TFT type selection" "STN,TFT"
|
|
bitfld.long 0x00 1.--3. " LCDBPP ,LCD bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp,16 bpp(5:6:5),12 bpp(4:4:4)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCDEN ,LCD enable control bit" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40008018))&0x30)==0x10)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "LCD_CTRL,LCD Control register"
|
|
bitfld.long 0x00 16. " WATERMARK ,LCD DMA FIFO watermark level" ">=4,>=8"
|
|
bitfld.long 0x00 12.--13. " LCDVCOMP ,LCD Vertical Compare Interrupt" "Vsync,Back porch,Active video,Front porch"
|
|
bitfld.long 0x00 11. " LCDPWR ,LCD power enable" "Not gated,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BEPO ,Big-Endian Pixel Ordering" "Little,Big"
|
|
bitfld.long 0x00 9. " BEBO ,Big-endian Byte Order" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BGR ,Color format selection" "RGB,BGR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCDDUAL ,Single or Dual LCD panel selection" "Single,Dual"
|
|
bitfld.long 0x00 6. " LCDMONO8 ,Monochrome LCD interface width" "4-bit,8-bit"
|
|
bitfld.long 0x00 5. " LCDTFT ,LCD panel TFT type selection" "STN,TFT"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCDBW ,STN LCD monochrome/color selection" "Color,Monochrome"
|
|
bitfld.long 0x00 1.--3. " LCDBPP ,LCD bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,Reserved,16 bpp(5:6:5),12 bpp(4:4:4)"
|
|
bitfld.long 0x00 0. " LCDEN ,LCD enable control bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "LCD_CTRL,LCD Control register"
|
|
bitfld.long 0x00 16. " WATERMARK ,LCD DMA FIFO watermark level" ">=4,>=8"
|
|
bitfld.long 0x00 12.--13. " LCDVCOMP ,LCD Vertical Compare Interrupt" "Vsync,Back porch,Active video,Front porch"
|
|
bitfld.long 0x00 11. " LCDPWR ,LCD power enable" "Not gated,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BEPO ,Big-Endian Pixel Ordering" "Little,Big"
|
|
bitfld.long 0x00 9. " BEBO ,Big-endian Byte Order" "Little,Big"
|
|
bitfld.long 0x00 8. " BGR ,Color format selection" "RGB,BGR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCDDUAL ,Single or Dual LCD panel selection" "Single,Dual"
|
|
bitfld.long 0x00 5. " LCDTFT ,LCD panel TFT type selection" "STN,TFT"
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|
textline " "
|
|
bitfld.long 0x00 4. " LCDBW ,STN LCD monochrome/color selection" "Color,Monochrome"
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|
bitfld.long 0x00 1.--3. " LCDBPP ,LCD bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,Reserved,16 bpp(5:6:5),12 bpp(4:4:4)"
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|
bitfld.long 0x00 0. " LCDEN ,LCD enable control bit" "Disabled,Enabled"
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|
endif
|
|
group.long 0x1C++0x3
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|
line.long 0x00 "LCD_INTMSK,Interrupt Mask register"
|
|
bitfld.long 0x00 4. " BERIM ,AHB master error interrupt enable" "Disabled,Enabled"
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|
bitfld.long 0x00 3. " VCOMPIM ,Vertical compare interrupt enable" "Disabled,Enabled"
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|
bitfld.long 0x00 2. " LNBUIM ,LCD next base address update interrupt enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x00 1. " FUFIM ,FIFO underflow interrupt enable" "Disabled,Enabled"
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|
rgroup.long 0x20++0x3
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|
line.long 0x00 "LCD_INTRAW,Raw interrupt status register"
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|
bitfld.long 0x00 4. " BERRAW ,AHB master bus error raw interrupt status" "No interrupt,Interrupt"
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|
bitfld.long 0x00 3. " VCOMPRIS ,Vertical compare raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " LNBURIS ,LCD next address base update raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FUFRIS ,FIFO underflow raw interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "LCD_INTSTAT,Masked Interrupt Status register"
|
|
bitfld.long 0x00 4. " BERMIS ,AHB master bus error masked interrupt status" "Not masked,Masked"
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|
bitfld.long 0x00 3. " VCOMPMIS ,Vertical compare masked interrupt status" "Not masked,Masked"
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|
bitfld.long 0x00 2. " LNBUMIS ,LCD next address base update masked interrupt status" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FUFMIS ,FIFO underflow masked interrupt status" "Not masked,Masked"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "LCD_INTCLR,Interrupt Clear register"
|
|
bitfld.long 0x00 4. " BERIC ,AHB master error interrupt clear" "Not clear,Clear"
|
|
bitfld.long 0x00 3. " VCOMPIC ,Vertical compare interrupt clear" "Not clear,Clear"
|
|
bitfld.long 0x00 2. " LNBUIC ,LCD next address base update interrupt clear" "Not clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FUFIC ,FIFO underflow interrupt clear" "Not clear,Clear"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x00 "LCD_UPCURR,Upper panel current address register"
|
|
line.long 0x04 "LCD_LPCURR,Lower panel current address register"
|
|
tree "Color Palette registers"
|
|
textline ""
|
|
if (((per.l(ad:0x40008018))&0x20)==0x20)
|
|
group.long 0x200++0x1FF
|
|
line.long 0x0 "LCD_PAL0 ,Color Palette register"
|
|
bitfld.long 0x0 31. " IH ,Higher Intensity" "Low,High"
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|
bitfld.long 0x0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x0 15. " IL ,Lower Intensity" "Low,High"
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|
bitfld.long 0x0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x4 "LCD_PAL1 ,Color Palette register"
|
|
bitfld.long 0x4 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x4 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x8 "LCD_PAL2 ,Color Palette register"
|
|
bitfld.long 0x8 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x8 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0xC "LCD_PAL3 ,Color Palette register"
|
|
bitfld.long 0xC 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0xC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0xC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0xC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0xC 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0xC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0xC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0xC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x10 "LCD_PAL4 ,Color Palette register"
|
|
bitfld.long 0x10 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x10 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x10 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x10 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x10 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x10 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x10 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x10 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x14 "LCD_PAL5 ,Color Palette register"
|
|
bitfld.long 0x14 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x14 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x14 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x14 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x14 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x14 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x14 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x14 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x18 "LCD_PAL6 ,Color Palette register"
|
|
bitfld.long 0x18 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x18 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x18 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x18 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x18 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x18 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x18 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x18 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x1C "LCD_PAL7 ,Color Palette register"
|
|
bitfld.long 0x1C 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x1C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1C 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x1C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x20 "LCD_PAL8 ,Color Palette register"
|
|
bitfld.long 0x20 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x20 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x20 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x20 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x20 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x20 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x20 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x24 "LCD_PAL9 ,Color Palette register"
|
|
bitfld.long 0x24 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x24 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x24 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x24 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x24 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x24 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x24 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x28 "LCD_PAL10 ,Color Palette register"
|
|
bitfld.long 0x28 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x28 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x28 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x28 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x28 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x28 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x28 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x28 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x2C "LCD_PAL11 ,Color Palette register"
|
|
bitfld.long 0x2C 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x2C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x2C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x2C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x2C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x2C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x2C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x2C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x30 "LCD_PAL12 ,Color Palette register"
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bitfld.long 0x30 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x30 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x30 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x30 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x30 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x30 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x30 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x30 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x34 "LCD_PAL13 ,Color Palette register"
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bitfld.long 0x34 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x34 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x34 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x34 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x34 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x34 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x34 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x34 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x38 "LCD_PAL14 ,Color Palette register"
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bitfld.long 0x38 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x38 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x38 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x38 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x38 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x38 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x38 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x38 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x3C "LCD_PAL15 ,Color Palette register"
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bitfld.long 0x3C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x3C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x3C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x3C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x3C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x3C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x3C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x3C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x40 "LCD_PAL16 ,Color Palette register"
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bitfld.long 0x40 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x40 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x40 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x40 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x40 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x40 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x40 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x40 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x44 "LCD_PAL17 ,Color Palette register"
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bitfld.long 0x44 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x44 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x44 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x44 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x44 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x44 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x44 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x44 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x48 "LCD_PAL18 ,Color Palette register"
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bitfld.long 0x48 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x48 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x48 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x48 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x48 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x48 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x48 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x48 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x4C "LCD_PAL19 ,Color Palette register"
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bitfld.long 0x4C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x4C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x4C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x4C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x4C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x4C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x4C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x4C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x50 "LCD_PAL20 ,Color Palette register"
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bitfld.long 0x50 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x50 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x50 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x50 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x50 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x50 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x50 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x50 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x54 "LCD_PAL21 ,Color Palette register"
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bitfld.long 0x54 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x54 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x54 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x54 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x54 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x54 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
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bitfld.long 0x54 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x54 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x58 "LCD_PAL22 ,Color Palette register"
|
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bitfld.long 0x58 31. " IH ,Higher Intensity" "Low,High"
|
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bitfld.long 0x58 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x58 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
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bitfld.long 0x58 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
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bitfld.long 0x58 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x58 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x58 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x58 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
line.long 0x5C "LCD_PAL23 ,Color Palette register"
|
|
bitfld.long 0x5C 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x5C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x5C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x5C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x5C 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x5C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x5C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x5C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
line.long 0x60 "LCD_PAL24 ,Color Palette register"
|
|
bitfld.long 0x60 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x60 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x60 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
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bitfld.long 0x60 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x60 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x60 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x60 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x60 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x64 "LCD_PAL25 ,Color Palette register"
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bitfld.long 0x64 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x64 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x64 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x64 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x64 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x64 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x64 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x64 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x68 "LCD_PAL26 ,Color Palette register"
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bitfld.long 0x68 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x68 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x68 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x68 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x68 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x68 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x68 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x68 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x6C "LCD_PAL27 ,Color Palette register"
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bitfld.long 0x6C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x6C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x6C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x6C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x6C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x6C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x6C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x6C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x70 "LCD_PAL28 ,Color Palette register"
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bitfld.long 0x70 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x70 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x70 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x70 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x70 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x70 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x70 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x70 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x74 "LCD_PAL29 ,Color Palette register"
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bitfld.long 0x74 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x74 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x74 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x74 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x74 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x74 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x74 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x74 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x78 "LCD_PAL30 ,Color Palette register"
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bitfld.long 0x78 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x78 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x78 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x78 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x78 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x78 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x78 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x78 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x7C "LCD_PAL31 ,Color Palette register"
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bitfld.long 0x7C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x7C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x7C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x7C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x7C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x7C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x7C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x7C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x80 "LCD_PAL32 ,Color Palette register"
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bitfld.long 0x80 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x80 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x80 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x80 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x80 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x80 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x80 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x80 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x84 "LCD_PAL33 ,Color Palette register"
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bitfld.long 0x84 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x84 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x84 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x84 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x84 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x84 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x84 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x84 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x88 "LCD_PAL34 ,Color Palette register"
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bitfld.long 0x88 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x88 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x88 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x88 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x88 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x88 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x88 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x88 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x8C "LCD_PAL35 ,Color Palette register"
|
|
bitfld.long 0x8C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x8C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x8C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x8C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x8C 15. " IL ,Lower Intensity" "Low,High"
|
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bitfld.long 0x8C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x8C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x8C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x90 "LCD_PAL36 ,Color Palette register"
|
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bitfld.long 0x90 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x90 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x90 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x90 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x90 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x90 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x90 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x90 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
line.long 0x94 "LCD_PAL37 ,Color Palette register"
|
|
bitfld.long 0x94 31. " IH ,Higher Intensity" "Low,High"
|
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bitfld.long 0x94 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x94 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x94 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x94 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x94 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x94 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x94 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x98 "LCD_PAL38 ,Color Palette register"
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bitfld.long 0x98 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x98 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x98 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x98 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x98 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x98 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x98 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x98 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x9C "LCD_PAL39 ,Color Palette register"
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bitfld.long 0x9C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x9C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x9C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x9C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x9C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x9C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x9C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x9C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xA0 "LCD_PAL40 ,Color Palette register"
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bitfld.long 0xA0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xA0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xA0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xA0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xA0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xA4 "LCD_PAL41 ,Color Palette register"
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bitfld.long 0xA4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xA4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0xA4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xA4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xA4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xA8 "LCD_PAL42 ,Color Palette register"
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bitfld.long 0xA8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xA8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xA8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xA8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0xA8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xA8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xAC "LCD_PAL43 ,Color Palette register"
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bitfld.long 0xAC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xAC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xAC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0xAC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xAC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xAC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xAC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xAC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xB0 "LCD_PAL44 ,Color Palette register"
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bitfld.long 0xB0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xB0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xB0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xB0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xB0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xB4 "LCD_PAL45 ,Color Palette register"
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bitfld.long 0xB4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xB4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xB4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xB4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0xB4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xB8 "LCD_PAL46 ,Color Palette register"
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bitfld.long 0xB8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xB8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0xB8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xB8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0xB8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xB8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xBC "LCD_PAL47 ,Color Palette register"
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bitfld.long 0xBC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xBC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xBC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0xBC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xBC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xBC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0xBC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xBC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xC0 "LCD_PAL48 ,Color Palette register"
|
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bitfld.long 0xC0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xC0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xC0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0xC0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xC0 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0xC0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0xC0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0xC0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xC4 "LCD_PAL49 ,Color Palette register"
|
|
bitfld.long 0xC4 31. " IH ,Higher Intensity" "Low,High"
|
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bitfld.long 0xC4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xC4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0xC4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
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bitfld.long 0xC4 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0xC4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0xC4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0xC4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
line.long 0xC8 "LCD_PAL50 ,Color Palette register"
|
|
bitfld.long 0xC8 31. " IH ,Higher Intensity" "Low,High"
|
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bitfld.long 0xC8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
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bitfld.long 0xC8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0xC8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0xC8 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0xC8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xC8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xC8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xCC "LCD_PAL51 ,Color Palette register"
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bitfld.long 0xCC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xCC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xCC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xCC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xCC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xCC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xCC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xCC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xD0 "LCD_PAL52 ,Color Palette register"
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bitfld.long 0xD0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xD0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xD0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xD0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xD0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xD4 "LCD_PAL53 ,Color Palette register"
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bitfld.long 0xD4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xD4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xD4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xD4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xD4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xD8 "LCD_PAL54 ,Color Palette register"
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bitfld.long 0xD8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xD8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xD8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xD8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xD8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xD8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xDC "LCD_PAL55 ,Color Palette register"
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bitfld.long 0xDC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xDC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xDC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xDC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xDC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xDC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xDC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xDC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xE0 "LCD_PAL56 ,Color Palette register"
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bitfld.long 0xE0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xE0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xE0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xE0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xE0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xE4 "LCD_PAL57 ,Color Palette register"
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bitfld.long 0xE4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xE4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xE4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xE4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xE4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xE8 "LCD_PAL58 ,Color Palette register"
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bitfld.long 0xE8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xE8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xE8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xE8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xE8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xE8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xEC "LCD_PAL59 ,Color Palette register"
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bitfld.long 0xEC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xEC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xEC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xEC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xEC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xEC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xEC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xEC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xF0 "LCD_PAL60 ,Color Palette register"
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bitfld.long 0xF0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xF0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xF0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xF0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0xF0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xF4 "LCD_PAL61 ,Color Palette register"
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bitfld.long 0xF4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xF4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0xF4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0xF4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0xF4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xF8 "LCD_PAL62 ,Color Palette register"
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bitfld.long 0xF8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xF8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0xF8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF8 15. " IL ,Lower Intensity" "Low,High"
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|
bitfld.long 0xF8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
|
bitfld.long 0xF8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xF8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0xFC "LCD_PAL63 ,Color Palette register"
|
|
bitfld.long 0xFC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0xFC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xFC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0xFC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xFC 15. " IL ,Lower Intensity" "Low,High"
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|
bitfld.long 0xFC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
|
bitfld.long 0xFC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0xFC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x100 "LCD_PAL64 ,Color Palette register"
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bitfld.long 0x100 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x100 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x100 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x100 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x100 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x100 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x100 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x100 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x104 "LCD_PAL65 ,Color Palette register"
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bitfld.long 0x104 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x104 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x104 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x104 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x104 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x104 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x104 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x104 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x108 "LCD_PAL66 ,Color Palette register"
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bitfld.long 0x108 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x108 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x108 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x108 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x108 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x108 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x108 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x108 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x10C "LCD_PAL67 ,Color Palette register"
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bitfld.long 0x10C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x10C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x10C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x10C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x10C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x10C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x10C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x10C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x110 "LCD_PAL68 ,Color Palette register"
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bitfld.long 0x110 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x110 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x110 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x110 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x110 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x110 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x110 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x110 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x114 "LCD_PAL69 ,Color Palette register"
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bitfld.long 0x114 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x114 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x114 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x114 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x114 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x114 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x114 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x114 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x118 "LCD_PAL70 ,Color Palette register"
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bitfld.long 0x118 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x118 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x118 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x118 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x118 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x118 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x118 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x118 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x11C "LCD_PAL71 ,Color Palette register"
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bitfld.long 0x11C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x11C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x11C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x11C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x11C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x11C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x11C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x11C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x120 "LCD_PAL72 ,Color Palette register"
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bitfld.long 0x120 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x120 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x120 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x120 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x120 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x120 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x120 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x120 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x124 "LCD_PAL73 ,Color Palette register"
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bitfld.long 0x124 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x124 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x124 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x124 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x124 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x124 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x124 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x124 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x128 "LCD_PAL74 ,Color Palette register"
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bitfld.long 0x128 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x128 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x128 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x128 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x128 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x128 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x128 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x128 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x12C "LCD_PAL75 ,Color Palette register"
|
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bitfld.long 0x12C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x12C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x12C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x12C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x12C 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x12C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x12C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x12C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x130 "LCD_PAL76 ,Color Palette register"
|
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bitfld.long 0x130 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x130 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x130 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
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bitfld.long 0x130 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x130 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x130 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x130 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x130 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x134 "LCD_PAL77 ,Color Palette register"
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bitfld.long 0x134 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x134 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x134 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x134 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x134 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x134 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x134 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x134 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x138 "LCD_PAL78 ,Color Palette register"
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bitfld.long 0x138 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x138 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x138 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x138 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x138 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x138 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x138 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x138 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x13C "LCD_PAL79 ,Color Palette register"
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bitfld.long 0x13C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x13C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x13C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x13C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x13C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x13C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x13C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x13C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x140 "LCD_PAL80 ,Color Palette register"
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bitfld.long 0x140 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x140 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x140 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x140 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x140 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x140 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x140 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x140 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x144 "LCD_PAL81 ,Color Palette register"
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bitfld.long 0x144 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x144 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x144 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x144 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x144 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x144 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x144 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x144 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x148 "LCD_PAL82 ,Color Palette register"
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bitfld.long 0x148 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x148 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x148 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x148 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x148 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x148 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x148 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x148 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x14C "LCD_PAL83 ,Color Palette register"
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bitfld.long 0x14C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x14C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x14C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x14C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x14C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x14C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x14C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x14C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x150 "LCD_PAL84 ,Color Palette register"
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bitfld.long 0x150 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x150 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x150 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x150 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x150 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x150 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x150 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x150 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x154 "LCD_PAL85 ,Color Palette register"
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bitfld.long 0x154 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x154 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x154 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x154 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x154 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x154 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x154 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x154 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x158 "LCD_PAL86 ,Color Palette register"
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bitfld.long 0x158 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x158 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x158 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x158 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x158 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x158 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x158 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x158 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x15C "LCD_PAL87 ,Color Palette register"
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bitfld.long 0x15C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x15C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x15C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x15C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x15C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x15C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x15C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x15C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x160 "LCD_PAL88 ,Color Palette register"
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bitfld.long 0x160 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x160 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x160 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x160 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x160 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x160 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x160 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x160 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x164 "LCD_PAL89 ,Color Palette register"
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bitfld.long 0x164 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x164 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x164 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x164 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x164 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x164 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x164 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x164 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x168 "LCD_PAL90 ,Color Palette register"
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bitfld.long 0x168 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x168 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x168 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x168 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x168 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x168 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x168 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x168 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x16C "LCD_PAL91 ,Color Palette register"
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bitfld.long 0x16C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x16C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x16C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x16C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x16C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x16C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x16C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x16C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x170 "LCD_PAL92 ,Color Palette register"
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bitfld.long 0x170 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x170 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x170 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x170 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x170 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x170 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x170 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x170 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x174 "LCD_PAL93 ,Color Palette register"
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bitfld.long 0x174 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x174 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x174 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x174 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x174 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x174 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x174 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x174 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x178 "LCD_PAL94 ,Color Palette register"
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bitfld.long 0x178 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x178 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x178 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x178 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x178 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x178 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x178 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x178 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x17C "LCD_PAL95 ,Color Palette register"
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bitfld.long 0x17C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x17C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x17C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x17C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x17C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x17C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x17C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x17C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x180 "LCD_PAL96 ,Color Palette register"
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bitfld.long 0x180 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x180 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x180 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x180 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x180 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x180 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x180 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x180 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x184 "LCD_PAL97 ,Color Palette register"
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bitfld.long 0x184 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x184 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x184 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x184 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x184 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x184 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x184 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x184 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x188 "LCD_PAL98 ,Color Palette register"
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bitfld.long 0x188 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x188 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x188 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x188 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x188 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x188 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x188 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x188 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x18C "LCD_PAL99 ,Color Palette register"
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bitfld.long 0x18C 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x18C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x18C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x18C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x18C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x18C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x18C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x18C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x190 "LCD_PAL100,Color Palette register"
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bitfld.long 0x190 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x190 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x190 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x190 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x190 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x190 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
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bitfld.long 0x190 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x190 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x194 "LCD_PAL101,Color Palette register"
|
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bitfld.long 0x194 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x194 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x194 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x194 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
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bitfld.long 0x194 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x194 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x194 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x194 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
line.long 0x198 "LCD_PAL102,Color Palette register"
|
|
bitfld.long 0x198 31. " IH ,Higher Intensity" "Low,High"
|
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bitfld.long 0x198 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x198 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x198 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x198 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x198 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x198 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x198 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
line.long 0x19C "LCD_PAL103,Color Palette register"
|
|
bitfld.long 0x19C 31. " IH ,Higher Intensity" "Low,High"
|
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bitfld.long 0x19C 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x19C 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x19C 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x19C 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x19C 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x19C 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x19C 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1A0 "LCD_PAL104,Color Palette register"
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bitfld.long 0x1A0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1A0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1A0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1A0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1A0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1A4 "LCD_PAL105,Color Palette register"
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bitfld.long 0x1A4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1A4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1A4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1A4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1A4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1A8 "LCD_PAL106,Color Palette register"
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bitfld.long 0x1A8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1A8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1A8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1A8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1A8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1A8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1AC "LCD_PAL107,Color Palette register"
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bitfld.long 0x1AC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1AC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1AC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1AC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1AC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1AC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1AC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1AC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1B0 "LCD_PAL108,Color Palette register"
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bitfld.long 0x1B0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1B0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1B0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1B0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1B0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1B4 "LCD_PAL109,Color Palette register"
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bitfld.long 0x1B4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1B4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1B4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1B4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1B4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1B8 "LCD_PAL110,Color Palette register"
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bitfld.long 0x1B8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1B8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1B8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1B8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1B8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1B8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1BC "LCD_PAL111,Color Palette register"
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bitfld.long 0x1BC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1BC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1BC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1BC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1BC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1BC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1BC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1BC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1C0 "LCD_PAL112,Color Palette register"
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bitfld.long 0x1C0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1C0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1C0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1C0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1C0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1C4 "LCD_PAL113,Color Palette register"
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bitfld.long 0x1C4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1C4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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textline " "
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bitfld.long 0x1C4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1C4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x1C4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1C8 "LCD_PAL114,Color Palette register"
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bitfld.long 0x1C8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1C8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x1C8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1C8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x1C8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1C8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1CC "LCD_PAL115,Color Palette register"
|
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bitfld.long 0x1CC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1CC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1CC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x1CC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1CC 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x1CC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
|
bitfld.long 0x1CC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1CC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1D0 "LCD_PAL116,Color Palette register"
|
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bitfld.long 0x1D0 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x1D0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1D0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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|
bitfld.long 0x1D0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x1D0 15. " IL ,Lower Intensity" "Low,High"
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|
bitfld.long 0x1D0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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|
bitfld.long 0x1D0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1D0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1D4 "LCD_PAL117,Color Palette register"
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bitfld.long 0x1D4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1D4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1D4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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|
bitfld.long 0x1D4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1D4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1D4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x1D4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1D4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1D8 "LCD_PAL118,Color Palette register"
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bitfld.long 0x1D8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1D8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1D8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x1D8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1D8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1D8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x1D8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1D8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1DC "LCD_PAL119,Color Palette register"
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bitfld.long 0x1DC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1DC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1DC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x1DC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1DC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1DC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x1DC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1DC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1E0 "LCD_PAL120,Color Palette register"
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bitfld.long 0x1E0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1E0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x1E0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E0 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1E0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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|
bitfld.long 0x1E0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1E4 "LCD_PAL121,Color Palette register"
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bitfld.long 0x1E4 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1E4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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|
bitfld.long 0x1E4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E4 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1E4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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|
bitfld.long 0x1E4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1E8 "LCD_PAL122,Color Palette register"
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bitfld.long 0x1E8 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1E8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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bitfld.long 0x1E8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E8 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1E8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
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|
bitfld.long 0x1E8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1E8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1EC "LCD_PAL123,Color Palette register"
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bitfld.long 0x1EC 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1EC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1EC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x1EC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1EC 15. " IL ,Lower Intensity" "Low,High"
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bitfld.long 0x1EC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
textline " "
|
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bitfld.long 0x1EC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1EC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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line.long 0x1F0 "LCD_PAL124,Color Palette register"
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bitfld.long 0x1F0 31. " IH ,Higher Intensity" "Low,High"
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bitfld.long 0x1F0 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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bitfld.long 0x1F0 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1F0 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x1F0 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x1F0 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1F0 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
bitfld.long 0x1F0 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
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|
line.long 0x1F4 "LCD_PAL125,Color Palette register"
|
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bitfld.long 0x1F4 31. " IH ,Higher Intensity" "Low,High"
|
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bitfld.long 0x1F4 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1F4 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1F4 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1F4 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x1F4 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1F4 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1F4 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x1F8 "LCD_PAL126,Color Palette register"
|
|
bitfld.long 0x1F8 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x1F8 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1F8 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1F8 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1F8 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x1F8 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1F8 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1F8 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x1FC "LCD_PAL127,Color Palette register"
|
|
bitfld.long 0x1FC 31. " IH ,Higher Intensity" "Low,High"
|
|
bitfld.long 0x1FC 26.--30. " BH[4:0] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1FC 21.--25. " GH[4:0] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1FC 16.--20. " RH[4:0] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1FC 15. " IL ,Lower Intensity" "Low,High"
|
|
bitfld.long 0x1FC 10.--14. " BL[4:0] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x1FC 5.--9. " GL[4:0] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x1FC 0.--4. " RL[4:0] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
elif (((per.l(ad:0x40008018))&0x30)==0x10)
|
|
group.long 0x200++0x1FF
|
|
line.long 0x0 "LCD_PAL0 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "LCD_PAL1 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "LCD_PAL2 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "LCD_PAL3 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "LCD_PAL4 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x10 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x10 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "LCD_PAL5 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x14 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x14 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "LCD_PAL6 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x18 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x18 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "LCD_PAL7 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "LCD_PAL8 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x20 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x20 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x20 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "LCD_PAL9 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x24 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x24 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x24 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "LCD_PAL10 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x28 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x28 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x28 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "LCD_PAL11 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x2C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x2C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x2C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "LCD_PAL12 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x30 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x30 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x30 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x34 "LCD_PAL13 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x34 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x34 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x34 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x38 "LCD_PAL14 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x38 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x38 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x38 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x38 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "LCD_PAL15 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x3C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x3C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x3C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x3C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "LCD_PAL16 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x40 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x40 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x40 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x40 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "LCD_PAL17 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x44 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x44 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x44 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x44 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "LCD_PAL18 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x48 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x48 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x48 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x48 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "LCD_PAL19 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x4C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x4C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x4C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x50 "LCD_PAL20 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x50 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x50 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x50 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x50 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x54 "LCD_PAL21 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x54 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x54 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x54 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x54 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x58 "LCD_PAL22 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x58 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x58 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x58 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x58 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x5C "LCD_PAL23 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x5C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x5C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x5C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x5C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x60 "LCD_PAL24 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x60 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x60 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x60 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x60 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x64 "LCD_PAL25 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x64 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x64 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x64 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x64 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x68 "LCD_PAL26 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x68 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x68 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x68 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x68 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x6C "LCD_PAL27 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x6C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x6C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x6C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x6C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x70 "LCD_PAL28 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x70 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x70 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x70 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x70 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x74 "LCD_PAL29 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x74 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x74 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x74 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x74 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x78 "LCD_PAL30 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x78 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x78 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x78 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x78 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x7C "LCD_PAL31 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x7C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x7C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x7C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x7C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x80 "LCD_PAL32 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x80 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x80 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x80 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x80 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x84 "LCD_PAL33 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x84 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x84 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x84 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x84 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x88 "LCD_PAL34 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x88 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x88 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x88 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x88 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8C "LCD_PAL35 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x8C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x8C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x8C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x90 "LCD_PAL36 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x90 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x90 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x90 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x90 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x94 "LCD_PAL37 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x94 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x94 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x94 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x94 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x98 "LCD_PAL38 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x98 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x98 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x98 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x98 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x9C "LCD_PAL39 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x9C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x9C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x9C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x9C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA0 "LCD_PAL40 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xA0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA4 "LCD_PAL41 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xA4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA8 "LCD_PAL42 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xA8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xAC "LCD_PAL43 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xAC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xAC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xAC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xAC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB0 "LCD_PAL44 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xB0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB4 "LCD_PAL45 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xB4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB8 "LCD_PAL46 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xB8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xBC "LCD_PAL47 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xBC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xBC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xBC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xBC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC0 "LCD_PAL48 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xC0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC4 "LCD_PAL49 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xC4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC8 "LCD_PAL50 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xC8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xCC "LCD_PAL51 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xCC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xCC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xCC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xCC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD0 "LCD_PAL52 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xD0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD4 "LCD_PAL53 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xD4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD8 "LCD_PAL54 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xD8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xDC "LCD_PAL55 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xDC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xDC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xDC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xDC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE0 "LCD_PAL56 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xE0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE4 "LCD_PAL57 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xE4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE8 "LCD_PAL58 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xE8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xEC "LCD_PAL59 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xEC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xEC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xEC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xEC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF0 "LCD_PAL60 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xF0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF4 "LCD_PAL61 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xF4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF8 "LCD_PAL62 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xF8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xFC "LCD_PAL63 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xFC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0xFC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xFC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xFC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x100 "LCD_PAL64 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x100 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x100 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x100 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x100 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x104 "LCD_PAL65 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x104 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x104 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x104 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x104 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x108 "LCD_PAL66 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x108 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x108 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x108 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x108 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10C "LCD_PAL67 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x10C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x10C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x110 "LCD_PAL68 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x110 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x110 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x110 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x110 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x114 "LCD_PAL69 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x114 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x114 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x114 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x114 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x118 "LCD_PAL70 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x118 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x118 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x118 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x118 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x11C "LCD_PAL71 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x11C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x11C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x11C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x11C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x120 "LCD_PAL72 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x120 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x120 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x120 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x120 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x124 "LCD_PAL73 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x124 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x124 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x124 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x124 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x128 "LCD_PAL74 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x128 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x128 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x128 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x128 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x12C "LCD_PAL75 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x12C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x12C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x12C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x12C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x130 "LCD_PAL76 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x130 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x130 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x130 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x130 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x134 "LCD_PAL77 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x134 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x134 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x134 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x134 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x138 "LCD_PAL78 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x138 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x138 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x138 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x138 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x13C "LCD_PAL79 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x13C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x13C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x13C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x13C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x140 "LCD_PAL80 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x140 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x140 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x140 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x140 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x144 "LCD_PAL81 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x144 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x144 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x144 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x144 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x148 "LCD_PAL82 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x148 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x148 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x148 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x148 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14C "LCD_PAL83 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x14C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x14C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x150 "LCD_PAL84 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x150 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x150 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x150 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x150 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x154 "LCD_PAL85 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x154 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x154 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x154 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x154 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x158 "LCD_PAL86 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x158 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x158 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x158 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x158 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x15C "LCD_PAL87 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x15C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x15C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x15C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x15C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x160 "LCD_PAL88 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x160 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x160 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x160 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x160 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x164 "LCD_PAL89 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x164 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x164 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x164 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x164 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x168 "LCD_PAL90 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x168 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x168 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x168 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x168 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x16C "LCD_PAL91 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x16C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x16C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x16C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x16C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x170 "LCD_PAL92 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x170 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x170 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x170 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x170 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x174 "LCD_PAL93 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x174 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x174 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x174 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x174 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x178 "LCD_PAL94 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x178 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x178 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x178 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x178 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x17C "LCD_PAL95 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x17C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x17C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x17C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x17C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x180 "LCD_PAL96 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x180 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x180 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x180 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x180 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x184 "LCD_PAL97 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x184 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x184 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x184 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x184 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x188 "LCD_PAL98 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x188 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x188 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x188 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x188 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18C "LCD_PAL99 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x18C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x18C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x190 "LCD_PAL100,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x190 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x190 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x190 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x190 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x194 "LCD_PAL101,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x194 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x194 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x194 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x194 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x198 "LCD_PAL102,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x198 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x198 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x198 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x198 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x19C "LCD_PAL103,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x19C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x19C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x19C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x19C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1A0 "LCD_PAL104,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1A0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1A4 "LCD_PAL105,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1A4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1A8 "LCD_PAL106,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1A8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1AC "LCD_PAL107,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1AC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1AC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1AC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1AC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1B0 "LCD_PAL108,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1B0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1B4 "LCD_PAL109,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1B4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1B8 "LCD_PAL110,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1B8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1BC "LCD_PAL111,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1BC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1BC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1BC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1BC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C0 "LCD_PAL112,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C4 "LCD_PAL113,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C8 "LCD_PAL114,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1CC "LCD_PAL115,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1CC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1CC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1CC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1CC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1D0 "LCD_PAL116,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1D0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1D4 "LCD_PAL117,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1D4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1D8 "LCD_PAL118,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1D8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1DC "LCD_PAL119,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1DC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1DC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1DC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1DC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1E0 "LCD_PAL120,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1E0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1E4 "LCD_PAL121,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1E4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1E8 "LCD_PAL122,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1E8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1EC "LCD_PAL123,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1EC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1EC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1EC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1EC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1F0 "LCD_PAL124,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1F0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1F4 "LCD_PAL125,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1F4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1F8 "LCD_PAL126,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1F8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1FC "LCD_PAL127,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1FC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1FC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1FC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1FC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x200++0x1FF
|
|
line.long 0x0 "LCD_PAL0 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "LCD_PAL1 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "LCD_PAL2 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "LCD_PAL3 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "LCD_PAL4 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x10 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x10 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "LCD_PAL5 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x14 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x14 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "LCD_PAL6 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x18 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x18 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "LCD_PAL7 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "LCD_PAL8 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x20 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x20 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "LCD_PAL9 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x24 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x24 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "LCD_PAL10 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x28 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x28 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "LCD_PAL11 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x2C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x2C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x2C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x2C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "LCD_PAL12 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x30 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x30 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x30 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x30 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x34 "LCD_PAL13 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x34 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x34 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x38 "LCD_PAL14 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x38 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x38 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x38 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x38 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x38 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x38 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x38 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x38 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "LCD_PAL15 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x3C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x3C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x3C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x3C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x3C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x3C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x3C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x3C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "LCD_PAL16 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x40 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x40 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x40 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x40 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x40 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x40 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x40 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x40 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "LCD_PAL17 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x44 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x44 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x44 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x44 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x44 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x44 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x44 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x44 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "LCD_PAL18 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x48 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x48 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x48 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x48 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x48 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x48 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x48 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x48 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "LCD_PAL19 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x4C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x4C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x50 "LCD_PAL20 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x50 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x50 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x50 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x50 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x50 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x50 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x50 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x50 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x54 "LCD_PAL21 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x54 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x54 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x54 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x54 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x54 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x54 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x54 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x54 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x58 "LCD_PAL22 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x58 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x58 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x58 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x58 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x58 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x58 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x58 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x58 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x5C "LCD_PAL23 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x5C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x5C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x5C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x5C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x5C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x5C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x5C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x5C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x60 "LCD_PAL24 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x60 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x60 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x60 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x60 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x60 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x60 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x60 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x60 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x64 "LCD_PAL25 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x64 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x64 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x64 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x64 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x64 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x64 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x64 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x64 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x68 "LCD_PAL26 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x68 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x68 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x68 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x68 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x68 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x68 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x68 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x68 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x6C "LCD_PAL27 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x6C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x6C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x6C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x6C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x6C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x6C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x6C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x6C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x70 "LCD_PAL28 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x70 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x70 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x70 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x70 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x70 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x70 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x70 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x70 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x74 "LCD_PAL29 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x74 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x74 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x74 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x74 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x74 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x74 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x74 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x74 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x78 "LCD_PAL30 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x78 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x78 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x78 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x78 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x78 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x78 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x78 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x78 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x7C "LCD_PAL31 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x7C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x7C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x7C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x7C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x7C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x7C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x7C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x7C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x80 "LCD_PAL32 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x80 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x80 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x80 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x80 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x80 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x80 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x80 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x80 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x84 "LCD_PAL33 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x84 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x84 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x84 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x84 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x84 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x84 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x84 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x84 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x88 "LCD_PAL34 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x88 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x88 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x88 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x88 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x88 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x88 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x88 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x88 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8C "LCD_PAL35 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x8C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x8C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x8C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x90 "LCD_PAL36 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x90 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x90 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x90 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x90 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x90 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x90 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x90 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x90 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x94 "LCD_PAL37 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x94 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x94 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x94 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x94 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x94 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x94 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x94 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x94 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x98 "LCD_PAL38 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x98 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x98 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x98 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x98 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x98 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x98 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x98 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x98 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x9C "LCD_PAL39 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x9C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x9C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x9C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x9C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x9C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x9C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x9C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x9C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA0 "LCD_PAL40 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xA0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xA0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA4 "LCD_PAL41 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xA4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xA4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA8 "LCD_PAL42 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xA8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xA8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xA8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xA8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xAC "LCD_PAL43 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xAC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xAC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xAC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xAC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xAC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xAC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xAC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xAC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB0 "LCD_PAL44 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xB0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xB0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB4 "LCD_PAL45 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xB4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xB4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB8 "LCD_PAL46 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xB8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xB8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xB8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xB8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xBC "LCD_PAL47 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xBC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xBC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xBC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xBC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xBC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xBC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xBC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xBC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC0 "LCD_PAL48 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC4 "LCD_PAL49 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC8 "LCD_PAL50 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xC8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xC8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xCC "LCD_PAL51 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xCC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xCC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xCC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xCC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xCC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xCC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xCC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xCC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD0 "LCD_PAL52 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xD0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xD0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD4 "LCD_PAL53 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xD4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xD4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD8 "LCD_PAL54 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xD8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xD8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xD8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xD8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xDC "LCD_PAL55 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xDC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xDC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xDC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xDC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xDC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xDC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xDC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xDC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE0 "LCD_PAL56 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xE0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xE0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE4 "LCD_PAL57 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xE4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xE4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE8 "LCD_PAL58 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xE8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xE8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xE8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xE8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xEC "LCD_PAL59 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xEC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xEC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xEC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xEC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xEC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xEC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xEC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xEC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF0 "LCD_PAL60 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xF0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xF0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF4 "LCD_PAL61 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xF4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xF4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF8 "LCD_PAL62 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xF8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xF8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xF8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xF8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xFC "LCD_PAL63 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xFC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xFC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xFC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xFC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0xFC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0xFC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xFC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xFC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x100 "LCD_PAL64 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x100 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x100 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x100 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x100 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x100 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x100 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x100 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x100 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x104 "LCD_PAL65 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x104 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x104 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x104 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x104 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x104 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x104 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x104 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x104 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x108 "LCD_PAL66 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x108 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x108 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x108 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x108 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x108 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x108 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x108 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x108 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10C "LCD_PAL67 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x10C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x10C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x110 "LCD_PAL68 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x110 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x110 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x110 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x110 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x110 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x110 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x110 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x110 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x114 "LCD_PAL69 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x114 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x114 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x114 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x114 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x114 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x114 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x114 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x114 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x118 "LCD_PAL70 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x118 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x118 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x118 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x118 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x118 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x118 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x118 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x118 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x11C "LCD_PAL71 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x11C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x11C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x11C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x11C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x11C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x11C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x11C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x11C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x120 "LCD_PAL72 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x120 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x120 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x120 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x120 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x120 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x120 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x120 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x120 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x124 "LCD_PAL73 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x124 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x124 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x124 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x124 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x124 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x124 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x124 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x124 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x128 "LCD_PAL74 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x128 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x128 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x128 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x128 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x128 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x128 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x128 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x128 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x12C "LCD_PAL75 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x12C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x12C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x12C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x12C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x12C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x12C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x12C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x12C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x130 "LCD_PAL76 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x130 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x130 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x130 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x130 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x130 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x130 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x130 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x130 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x134 "LCD_PAL77 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x134 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x134 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x134 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x134 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x134 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x134 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x134 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x134 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x138 "LCD_PAL78 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x138 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x138 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x138 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x138 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x138 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x138 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x138 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x138 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x13C "LCD_PAL79 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x13C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x13C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x13C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x13C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x13C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x13C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x13C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x13C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x140 "LCD_PAL80 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x140 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x140 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x140 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x140 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x140 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x140 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x140 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x140 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x144 "LCD_PAL81 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x144 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x144 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x144 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x144 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x144 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x144 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x144 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x144 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x148 "LCD_PAL82 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x148 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x148 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x148 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x148 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x148 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x148 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x148 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x148 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14C "LCD_PAL83 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x14C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x14C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x150 "LCD_PAL84 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x150 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x150 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x150 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x150 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x150 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x150 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x150 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x150 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x154 "LCD_PAL85 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x154 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x154 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x154 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x154 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x154 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x154 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x154 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x154 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x158 "LCD_PAL86 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x158 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x158 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x158 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x158 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x158 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x158 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x158 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x158 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x15C "LCD_PAL87 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x15C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x15C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x15C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x15C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x15C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x15C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x15C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x15C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x160 "LCD_PAL88 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x160 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x160 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x160 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x160 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x160 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x160 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x160 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x160 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x164 "LCD_PAL89 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x164 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x164 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x164 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x164 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x164 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x164 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x164 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x164 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x168 "LCD_PAL90 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x168 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x168 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x168 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x168 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x168 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x168 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x168 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x168 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x16C "LCD_PAL91 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x16C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x16C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x16C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x16C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x16C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x16C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x16C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x16C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x170 "LCD_PAL92 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x170 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x170 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x170 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x170 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x170 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x170 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x170 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x170 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x174 "LCD_PAL93 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x174 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x174 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x174 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x174 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x174 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x174 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x174 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x174 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x178 "LCD_PAL94 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x178 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x178 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x178 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x178 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x178 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x178 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x178 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x178 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x17C "LCD_PAL95 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x17C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x17C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x17C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x17C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x17C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x17C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x17C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x17C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x180 "LCD_PAL96 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x180 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x180 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x180 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x180 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x180 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x180 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x180 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x180 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x184 "LCD_PAL97 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x184 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x184 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x184 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x184 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x184 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x184 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x184 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x184 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x188 "LCD_PAL98 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x188 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x188 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x188 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x188 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x188 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x188 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x188 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x188 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18C "LCD_PAL99 ,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x18C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x18C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x190 "LCD_PAL100,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x190 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x190 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x190 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x190 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x190 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x190 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x190 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x190 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x194 "LCD_PAL101,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x194 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x194 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x194 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x194 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x194 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x194 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x194 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x194 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x198 "LCD_PAL102,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x198 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x198 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x198 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x198 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x198 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x198 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x198 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x198 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x19C "LCD_PAL103,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x19C 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x19C 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x19C 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x19C 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x19C 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x19C 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x19C 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x19C 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1A0 "LCD_PAL104,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1A0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1A0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1A0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1A0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1A4 "LCD_PAL105,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1A4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1A4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1A4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1A4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1A8 "LCD_PAL106,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1A8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1A8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1A8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1A8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1A8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1A8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1AC "LCD_PAL107,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1AC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1AC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1AC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1AC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1AC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1AC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1AC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1AC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1B0 "LCD_PAL108,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1B0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1B0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1B0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1B0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1B4 "LCD_PAL109,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1B4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1B4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1B4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1B4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1B8 "LCD_PAL110,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1B8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1B8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1B8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1B8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1B8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1B8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1BC "LCD_PAL111,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1BC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1BC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1BC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1BC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1BC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1BC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1BC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1BC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C0 "LCD_PAL112,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C4 "LCD_PAL113,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C8 "LCD_PAL114,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1C8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1CC "LCD_PAL115,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1CC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1CC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1CC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1CC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1CC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1CC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1CC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1CC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1D0 "LCD_PAL116,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1D0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1D0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1D0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1D0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1D4 "LCD_PAL117,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1D4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1D4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1D4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1D4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1D8 "LCD_PAL118,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1D8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1D8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1D8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1D8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1D8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1D8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1DC "LCD_PAL119,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1DC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1DC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1DC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1DC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1DC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1DC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1DC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1DC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1E0 "LCD_PAL120,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1E0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1E0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1E0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1E0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1E4 "LCD_PAL121,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1E4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1E4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1E4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1E4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1E8 "LCD_PAL122,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1E8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1E8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1E8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1E8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1E8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1E8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1EC "LCD_PAL123,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1EC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1EC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1EC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1EC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1EC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1EC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1EC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1EC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1F0 "LCD_PAL124,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F0 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F0 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1F0 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1F0 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F0 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F0 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1F0 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1F0 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1F4 "LCD_PAL125,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F4 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F4 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1F4 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1F4 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F4 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F4 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1F4 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1F4 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1F8 "LCD_PAL126,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F8 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F8 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1F8 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1F8 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1F8 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1F8 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1F8 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1F8 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1FC "LCD_PAL127,Color Palette register"
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1FC 31. " IH ,Higher Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1FC 27.--30. " BH[4:1] ,Higher Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1FC 22.--25. " GH[4:1] ,Higher Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1FC 17.--20. " RH[4:1] ,Higher Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()!="LPC4350FET256")&&(cpu()!="LPC4350FET180")&&(cpu()!="LPC4350FBD208")&&(cpu()!="LPC4350FET256-M0")&&(cpu()!="LPC4350FET180-M0")&&(cpu()!="LPC4350FBD208-M0")
|
|
bitfld.long 0x1FC 15. " IL ,Lower Intensity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1FC 11.--14. " BL[4:1] ,Lower Blue palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1FC 6.--9. " GL[4:1] ,Lower Green palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1FC 1.--4. " RL[4:1] ,Lower Red palette data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
tree "Cursor Image registers"
|
|
textline ""
|
|
group.long 0x800++0x3FF
|
|
line.long 0x0 "CRSR_IMG0 ,Cursor Image register"
|
|
line.long 0x4 "CRSR_IMG1 ,Cursor Image register"
|
|
line.long 0x8 "CRSR_IMG2 ,Cursor Image register"
|
|
line.long 0xC "CRSR_IMG3 ,Cursor Image register"
|
|
line.long 0x10 "CRSR_IMG4 ,Cursor Image register"
|
|
line.long 0x14 "CRSR_IMG5 ,Cursor Image register"
|
|
line.long 0x18 "CRSR_IMG6 ,Cursor Image register"
|
|
line.long 0x1C "CRSR_IMG7 ,Cursor Image register"
|
|
line.long 0x20 "CRSR_IMG8 ,Cursor Image register"
|
|
line.long 0x24 "CRSR_IMG9 ,Cursor Image register"
|
|
line.long 0x28 "CRSR_IMG10 ,Cursor Image register"
|
|
line.long 0x2C "CRSR_IMG11 ,Cursor Image register"
|
|
line.long 0x30 "CRSR_IMG12 ,Cursor Image register"
|
|
line.long 0x34 "CRSR_IMG13 ,Cursor Image register"
|
|
line.long 0x38 "CRSR_IMG14 ,Cursor Image register"
|
|
line.long 0x3C "CRSR_IMG15 ,Cursor Image register"
|
|
line.long 0x40 "CRSR_IMG16 ,Cursor Image register"
|
|
line.long 0x44 "CRSR_IMG17 ,Cursor Image register"
|
|
line.long 0x48 "CRSR_IMG18 ,Cursor Image register"
|
|
line.long 0x4C "CRSR_IMG19 ,Cursor Image register"
|
|
line.long 0x50 "CRSR_IMG20 ,Cursor Image register"
|
|
line.long 0x54 "CRSR_IMG21 ,Cursor Image register"
|
|
line.long 0x58 "CRSR_IMG22 ,Cursor Image register"
|
|
line.long 0x5C "CRSR_IMG23 ,Cursor Image register"
|
|
line.long 0x60 "CRSR_IMG24 ,Cursor Image register"
|
|
line.long 0x64 "CRSR_IMG25 ,Cursor Image register"
|
|
line.long 0x68 "CRSR_IMG26 ,Cursor Image register"
|
|
line.long 0x6C "CRSR_IMG27 ,Cursor Image register"
|
|
line.long 0x70 "CRSR_IMG28 ,Cursor Image register"
|
|
line.long 0x74 "CRSR_IMG29 ,Cursor Image register"
|
|
line.long 0x78 "CRSR_IMG30 ,Cursor Image register"
|
|
line.long 0x7C "CRSR_IMG31 ,Cursor Image register"
|
|
line.long 0x80 "CRSR_IMG32 ,Cursor Image register"
|
|
line.long 0x84 "CRSR_IMG33 ,Cursor Image register"
|
|
line.long 0x88 "CRSR_IMG34 ,Cursor Image register"
|
|
line.long 0x8C "CRSR_IMG35 ,Cursor Image register"
|
|
line.long 0x90 "CRSR_IMG36 ,Cursor Image register"
|
|
line.long 0x94 "CRSR_IMG37 ,Cursor Image register"
|
|
line.long 0x98 "CRSR_IMG38 ,Cursor Image register"
|
|
line.long 0x9C "CRSR_IMG39 ,Cursor Image register"
|
|
line.long 0xA0 "CRSR_IMG40 ,Cursor Image register"
|
|
line.long 0xA4 "CRSR_IMG41 ,Cursor Image register"
|
|
line.long 0xA8 "CRSR_IMG42 ,Cursor Image register"
|
|
line.long 0xAC "CRSR_IMG43 ,Cursor Image register"
|
|
line.long 0xB0 "CRSR_IMG44 ,Cursor Image register"
|
|
line.long 0xB4 "CRSR_IMG45 ,Cursor Image register"
|
|
line.long 0xB8 "CRSR_IMG46 ,Cursor Image register"
|
|
line.long 0xBC "CRSR_IMG47 ,Cursor Image register"
|
|
line.long 0xC0 "CRSR_IMG48 ,Cursor Image register"
|
|
line.long 0xC4 "CRSR_IMG49 ,Cursor Image register"
|
|
line.long 0xC8 "CRSR_IMG50 ,Cursor Image register"
|
|
line.long 0xCC "CRSR_IMG51 ,Cursor Image register"
|
|
line.long 0xD0 "CRSR_IMG52 ,Cursor Image register"
|
|
line.long 0xD4 "CRSR_IMG53 ,Cursor Image register"
|
|
line.long 0xD8 "CRSR_IMG54 ,Cursor Image register"
|
|
line.long 0xDC "CRSR_IMG55 ,Cursor Image register"
|
|
line.long 0xE0 "CRSR_IMG56 ,Cursor Image register"
|
|
line.long 0xE4 "CRSR_IMG57 ,Cursor Image register"
|
|
line.long 0xE8 "CRSR_IMG58 ,Cursor Image register"
|
|
line.long 0xEC "CRSR_IMG59 ,Cursor Image register"
|
|
line.long 0xF0 "CRSR_IMG60 ,Cursor Image register"
|
|
line.long 0xF4 "CRSR_IMG61 ,Cursor Image register"
|
|
line.long 0xF8 "CRSR_IMG62 ,Cursor Image register"
|
|
line.long 0xFC "CRSR_IMG63 ,Cursor Image register"
|
|
line.long 0x100 "CRSR_IMG64 ,Cursor Image register"
|
|
line.long 0x104 "CRSR_IMG65 ,Cursor Image register"
|
|
line.long 0x108 "CRSR_IMG66 ,Cursor Image register"
|
|
line.long 0x10C "CRSR_IMG67 ,Cursor Image register"
|
|
line.long 0x110 "CRSR_IMG68 ,Cursor Image register"
|
|
line.long 0x114 "CRSR_IMG69 ,Cursor Image register"
|
|
line.long 0x118 "CRSR_IMG70 ,Cursor Image register"
|
|
line.long 0x11C "CRSR_IMG71 ,Cursor Image register"
|
|
line.long 0x120 "CRSR_IMG72 ,Cursor Image register"
|
|
line.long 0x124 "CRSR_IMG73 ,Cursor Image register"
|
|
line.long 0x128 "CRSR_IMG74 ,Cursor Image register"
|
|
line.long 0x12C "CRSR_IMG75 ,Cursor Image register"
|
|
line.long 0x130 "CRSR_IMG76 ,Cursor Image register"
|
|
line.long 0x134 "CRSR_IMG77 ,Cursor Image register"
|
|
line.long 0x138 "CRSR_IMG78 ,Cursor Image register"
|
|
line.long 0x13C "CRSR_IMG79 ,Cursor Image register"
|
|
line.long 0x140 "CRSR_IMG80 ,Cursor Image register"
|
|
line.long 0x144 "CRSR_IMG81 ,Cursor Image register"
|
|
line.long 0x148 "CRSR_IMG82 ,Cursor Image register"
|
|
line.long 0x14C "CRSR_IMG83 ,Cursor Image register"
|
|
line.long 0x150 "CRSR_IMG84 ,Cursor Image register"
|
|
line.long 0x154 "CRSR_IMG85 ,Cursor Image register"
|
|
line.long 0x158 "CRSR_IMG86 ,Cursor Image register"
|
|
line.long 0x15C "CRSR_IMG87 ,Cursor Image register"
|
|
line.long 0x160 "CRSR_IMG88 ,Cursor Image register"
|
|
line.long 0x164 "CRSR_IMG89 ,Cursor Image register"
|
|
line.long 0x168 "CRSR_IMG90 ,Cursor Image register"
|
|
line.long 0x16C "CRSR_IMG91 ,Cursor Image register"
|
|
line.long 0x170 "CRSR_IMG92 ,Cursor Image register"
|
|
line.long 0x174 "CRSR_IMG93 ,Cursor Image register"
|
|
line.long 0x178 "CRSR_IMG94 ,Cursor Image register"
|
|
line.long 0x17C "CRSR_IMG95 ,Cursor Image register"
|
|
line.long 0x180 "CRSR_IMG96 ,Cursor Image register"
|
|
line.long 0x184 "CRSR_IMG97 ,Cursor Image register"
|
|
line.long 0x188 "CRSR_IMG98 ,Cursor Image register"
|
|
line.long 0x18C "CRSR_IMG99 ,Cursor Image register"
|
|
line.long 0x190 "CRSR_IMG100,Cursor Image register"
|
|
line.long 0x194 "CRSR_IMG101,Cursor Image register"
|
|
line.long 0x198 "CRSR_IMG102,Cursor Image register"
|
|
line.long 0x19C "CRSR_IMG103,Cursor Image register"
|
|
line.long 0x1A0 "CRSR_IMG104,Cursor Image register"
|
|
line.long 0x1A4 "CRSR_IMG105,Cursor Image register"
|
|
line.long 0x1A8 "CRSR_IMG106,Cursor Image register"
|
|
line.long 0x1AC "CRSR_IMG107,Cursor Image register"
|
|
line.long 0x1B0 "CRSR_IMG108,Cursor Image register"
|
|
line.long 0x1B4 "CRSR_IMG109,Cursor Image register"
|
|
line.long 0x1B8 "CRSR_IMG110,Cursor Image register"
|
|
line.long 0x1BC "CRSR_IMG111,Cursor Image register"
|
|
line.long 0x1C0 "CRSR_IMG112,Cursor Image register"
|
|
line.long 0x1C4 "CRSR_IMG113,Cursor Image register"
|
|
line.long 0x1C8 "CRSR_IMG114,Cursor Image register"
|
|
line.long 0x1CC "CRSR_IMG115,Cursor Image register"
|
|
line.long 0x1D0 "CRSR_IMG116,Cursor Image register"
|
|
line.long 0x1D4 "CRSR_IMG117,Cursor Image register"
|
|
line.long 0x1D8 "CRSR_IMG118,Cursor Image register"
|
|
line.long 0x1DC "CRSR_IMG119,Cursor Image register"
|
|
line.long 0x1E0 "CRSR_IMG120,Cursor Image register"
|
|
line.long 0x1E4 "CRSR_IMG121,Cursor Image register"
|
|
line.long 0x1E8 "CRSR_IMG122,Cursor Image register"
|
|
line.long 0x1EC "CRSR_IMG123,Cursor Image register"
|
|
line.long 0x1F0 "CRSR_IMG124,Cursor Image register"
|
|
line.long 0x1F4 "CRSR_IMG125,Cursor Image register"
|
|
line.long 0x1F8 "CRSR_IMG126,Cursor Image register"
|
|
line.long 0x1FC "CRSR_IMG127,Cursor Image register"
|
|
line.long 0x200 "CRSR_IMG128,Cursor Image register"
|
|
line.long 0x204 "CRSR_IMG129,Cursor Image register"
|
|
line.long 0x208 "CRSR_IMG130,Cursor Image register"
|
|
line.long 0x20C "CRSR_IMG131,Cursor Image register"
|
|
line.long 0x210 "CRSR_IMG132,Cursor Image register"
|
|
line.long 0x214 "CRSR_IMG133,Cursor Image register"
|
|
line.long 0x218 "CRSR_IMG134,Cursor Image register"
|
|
line.long 0x21C "CRSR_IMG135,Cursor Image register"
|
|
line.long 0x220 "CRSR_IMG136,Cursor Image register"
|
|
line.long 0x224 "CRSR_IMG137,Cursor Image register"
|
|
line.long 0x228 "CRSR_IMG138,Cursor Image register"
|
|
line.long 0x22C "CRSR_IMG139,Cursor Image register"
|
|
line.long 0x230 "CRSR_IMG140,Cursor Image register"
|
|
line.long 0x234 "CRSR_IMG141,Cursor Image register"
|
|
line.long 0x238 "CRSR_IMG142,Cursor Image register"
|
|
line.long 0x23C "CRSR_IMG143,Cursor Image register"
|
|
line.long 0x240 "CRSR_IMG144,Cursor Image register"
|
|
line.long 0x244 "CRSR_IMG145,Cursor Image register"
|
|
line.long 0x248 "CRSR_IMG146,Cursor Image register"
|
|
line.long 0x24C "CRSR_IMG147,Cursor Image register"
|
|
line.long 0x250 "CRSR_IMG148,Cursor Image register"
|
|
line.long 0x254 "CRSR_IMG149,Cursor Image register"
|
|
line.long 0x258 "CRSR_IMG150,Cursor Image register"
|
|
line.long 0x25C "CRSR_IMG151,Cursor Image register"
|
|
line.long 0x260 "CRSR_IMG152,Cursor Image register"
|
|
line.long 0x264 "CRSR_IMG153,Cursor Image register"
|
|
line.long 0x268 "CRSR_IMG154,Cursor Image register"
|
|
line.long 0x26C "CRSR_IMG155,Cursor Image register"
|
|
line.long 0x270 "CRSR_IMG156,Cursor Image register"
|
|
line.long 0x274 "CRSR_IMG157,Cursor Image register"
|
|
line.long 0x278 "CRSR_IMG158,Cursor Image register"
|
|
line.long 0x27C "CRSR_IMG159,Cursor Image register"
|
|
line.long 0x280 "CRSR_IMG160,Cursor Image register"
|
|
line.long 0x284 "CRSR_IMG161,Cursor Image register"
|
|
line.long 0x288 "CRSR_IMG162,Cursor Image register"
|
|
line.long 0x28C "CRSR_IMG163,Cursor Image register"
|
|
line.long 0x290 "CRSR_IMG164,Cursor Image register"
|
|
line.long 0x294 "CRSR_IMG165,Cursor Image register"
|
|
line.long 0x298 "CRSR_IMG166,Cursor Image register"
|
|
line.long 0x29C "CRSR_IMG167,Cursor Image register"
|
|
line.long 0x2A0 "CRSR_IMG168,Cursor Image register"
|
|
line.long 0x2A4 "CRSR_IMG169,Cursor Image register"
|
|
line.long 0x2A8 "CRSR_IMG170,Cursor Image register"
|
|
line.long 0x2AC "CRSR_IMG171,Cursor Image register"
|
|
line.long 0x2B0 "CRSR_IMG172,Cursor Image register"
|
|
line.long 0x2B4 "CRSR_IMG173,Cursor Image register"
|
|
line.long 0x2B8 "CRSR_IMG174,Cursor Image register"
|
|
line.long 0x2BC "CRSR_IMG175,Cursor Image register"
|
|
line.long 0x2C0 "CRSR_IMG176,Cursor Image register"
|
|
line.long 0x2C4 "CRSR_IMG177,Cursor Image register"
|
|
line.long 0x2C8 "CRSR_IMG178,Cursor Image register"
|
|
line.long 0x2CC "CRSR_IMG179,Cursor Image register"
|
|
line.long 0x2D0 "CRSR_IMG180,Cursor Image register"
|
|
line.long 0x2D4 "CRSR_IMG181,Cursor Image register"
|
|
line.long 0x2D8 "CRSR_IMG182,Cursor Image register"
|
|
line.long 0x2DC "CRSR_IMG183,Cursor Image register"
|
|
line.long 0x2E0 "CRSR_IMG184,Cursor Image register"
|
|
line.long 0x2E4 "CRSR_IMG185,Cursor Image register"
|
|
line.long 0x2E8 "CRSR_IMG186,Cursor Image register"
|
|
line.long 0x2EC "CRSR_IMG187,Cursor Image register"
|
|
line.long 0x2F0 "CRSR_IMG188,Cursor Image register"
|
|
line.long 0x2F4 "CRSR_IMG189,Cursor Image register"
|
|
line.long 0x2F8 "CRSR_IMG190,Cursor Image register"
|
|
line.long 0x2FC "CRSR_IMG191,Cursor Image register"
|
|
line.long 0x300 "CRSR_IMG192,Cursor Image register"
|
|
line.long 0x304 "CRSR_IMG193,Cursor Image register"
|
|
line.long 0x308 "CRSR_IMG194,Cursor Image register"
|
|
line.long 0x30C "CRSR_IMG195,Cursor Image register"
|
|
line.long 0x310 "CRSR_IMG196,Cursor Image register"
|
|
line.long 0x314 "CRSR_IMG197,Cursor Image register"
|
|
line.long 0x318 "CRSR_IMG198,Cursor Image register"
|
|
line.long 0x31C "CRSR_IMG199,Cursor Image register"
|
|
line.long 0x320 "CRSR_IMG200,Cursor Image register"
|
|
line.long 0x324 "CRSR_IMG201,Cursor Image register"
|
|
line.long 0x328 "CRSR_IMG202,Cursor Image register"
|
|
line.long 0x32C "CRSR_IMG203,Cursor Image register"
|
|
line.long 0x330 "CRSR_IMG204,Cursor Image register"
|
|
line.long 0x334 "CRSR_IMG205,Cursor Image register"
|
|
line.long 0x338 "CRSR_IMG206,Cursor Image register"
|
|
line.long 0x33C "CRSR_IMG207,Cursor Image register"
|
|
line.long 0x340 "CRSR_IMG208,Cursor Image register"
|
|
line.long 0x344 "CRSR_IMG209,Cursor Image register"
|
|
line.long 0x348 "CRSR_IMG210,Cursor Image register"
|
|
line.long 0x34C "CRSR_IMG211,Cursor Image register"
|
|
line.long 0x350 "CRSR_IMG212,Cursor Image register"
|
|
line.long 0x354 "CRSR_IMG213,Cursor Image register"
|
|
line.long 0x358 "CRSR_IMG214,Cursor Image register"
|
|
line.long 0x35C "CRSR_IMG215,Cursor Image register"
|
|
line.long 0x360 "CRSR_IMG216,Cursor Image register"
|
|
line.long 0x364 "CRSR_IMG217,Cursor Image register"
|
|
line.long 0x368 "CRSR_IMG218,Cursor Image register"
|
|
line.long 0x36C "CRSR_IMG219,Cursor Image register"
|
|
line.long 0x370 "CRSR_IMG220,Cursor Image register"
|
|
line.long 0x374 "CRSR_IMG221,Cursor Image register"
|
|
line.long 0x378 "CRSR_IMG222,Cursor Image register"
|
|
line.long 0x37C "CRSR_IMG223,Cursor Image register"
|
|
line.long 0x380 "CRSR_IMG224,Cursor Image register"
|
|
line.long 0x384 "CRSR_IMG225,Cursor Image register"
|
|
line.long 0x388 "CRSR_IMG226,Cursor Image register"
|
|
line.long 0x38C "CRSR_IMG227,Cursor Image register"
|
|
line.long 0x390 "CRSR_IMG228,Cursor Image register"
|
|
line.long 0x394 "CRSR_IMG229,Cursor Image register"
|
|
line.long 0x398 "CRSR_IMG230,Cursor Image register"
|
|
line.long 0x39C "CRSR_IMG231,Cursor Image register"
|
|
line.long 0x3A0 "CRSR_IMG232,Cursor Image register"
|
|
line.long 0x3A4 "CRSR_IMG233,Cursor Image register"
|
|
line.long 0x3A8 "CRSR_IMG234,Cursor Image register"
|
|
line.long 0x3AC "CRSR_IMG235,Cursor Image register"
|
|
line.long 0x3B0 "CRSR_IMG236,Cursor Image register"
|
|
line.long 0x3B4 "CRSR_IMG237,Cursor Image register"
|
|
line.long 0x3B8 "CRSR_IMG238,Cursor Image register"
|
|
line.long 0x3BC "CRSR_IMG239,Cursor Image register"
|
|
line.long 0x3C0 "CRSR_IMG240,Cursor Image register"
|
|
line.long 0x3C4 "CRSR_IMG241,Cursor Image register"
|
|
line.long 0x3C8 "CRSR_IMG242,Cursor Image register"
|
|
line.long 0x3CC "CRSR_IMG243,Cursor Image register"
|
|
line.long 0x3D0 "CRSR_IMG244,Cursor Image register"
|
|
line.long 0x3D4 "CRSR_IMG245,Cursor Image register"
|
|
line.long 0x3D8 "CRSR_IMG246,Cursor Image register"
|
|
line.long 0x3DC "CRSR_IMG247,Cursor Image register"
|
|
line.long 0x3E0 "CRSR_IMG248,Cursor Image register"
|
|
line.long 0x3E4 "CRSR_IMG249,Cursor Image register"
|
|
line.long 0x3E8 "CRSR_IMG250,Cursor Image register"
|
|
line.long 0x3EC "CRSR_IMG251,Cursor Image register"
|
|
line.long 0x3F0 "CRSR_IMG252,Cursor Image register"
|
|
line.long 0x3F4 "CRSR_IMG253,Cursor Image register"
|
|
line.long 0x3F8 "CRSR_IMG254,Cursor Image register"
|
|
line.long 0x3FC "CRSR_IMG255,Cursor Image register"
|
|
tree.end
|
|
textline " "
|
|
if (((per.l(ad:0x040008C04))&0x1)==0x0)
|
|
group.long 0xC00++0x3
|
|
line.long 0x00 "CRSR_CTRL,Cursor Control register"
|
|
bitfld.long 0x00 4.--5. " CRSRNUM[1:0] ,Cursor image number" "Cursor0,Cursor1,Cursor2,Cursor3"
|
|
bitfld.long 0x00 0. " CRSRON ,Cursor enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC00++0x3
|
|
line.long 0x00 "CRSR_CTRL,Cursor Control register"
|
|
bitfld.long 0x00 0. " CRSRON ,Cursor enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "CRSR_CFG,Cursor configuration register"
|
|
bitfld.long 0x00 1. " FRAMESYNC ,Cursor frame synchronization type" "Async,Sync"
|
|
bitfld.long 0x00 0. " CRSRSIZE ,Cursor size selection" "32x32,64x64"
|
|
if (((per.l(ad:0x40008018))&0x20)==0x20)
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "CRSR_PAL0,Cursor Palette register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BLUE ,Blue color component"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green color component"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RED ,Red color component"
|
|
elif (((per.l(ad:0x40008018))&0x30)==0x10)
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "CRSR_PAL0,Cursor Palette register 0"
|
|
bitfld.long 0x00 4.--7. " RED ,Red color component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "CRSR_PAL0,Cursor Palette register 0"
|
|
bitfld.long 0x00 20.--23. " BLUE ,Blue color component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " GREEN ,Green color component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " RED ,Red color component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40008018))&0x20)==0x20)
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "CRSR_PAL1,Cursor Palette register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BLUE ,Blue color component"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green color component"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RED ,Red color component"
|
|
elif (((per.l(ad:0x40008018))&0x30)==0x10)
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "CRSR_PAL1,Cursor Palette register 1"
|
|
bitfld.long 0x00 4.--7. " RED ,Red color component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "CRSR_PAL1,Cursor Palette register 1"
|
|
bitfld.long 0x00 20.--23. " BLUE ,Blue color component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " GREEN ,Green color component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " RED ,Red color component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0xC10++0x7
|
|
line.long 0x00 "CRSR_XY,Cursor XY position register"
|
|
hexmask.long.word 0x00 16.--25. 1. " CRSRY ,Y ordinate of the cursor origin measured in pixels"
|
|
hexmask.long.word 0x00 0.--9. 1. " CRSRX ,X ordinate of the cursor origin measured in pixels"
|
|
line.long 0x04 "CRSR_CLIP,Cursor Clip Position register"
|
|
bitfld.long 0x04 8.--13. " CRSRCLIPY ,Cursor clip position for Y direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " CRSRCLIPX ,Cursor clip position for X direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "CRSR_INTMSK,Cursor Interrupt Mask register"
|
|
bitfld.long 0x00 0. " CRSRIM ,Cursor interrupt mask" "Masked,Not masked"
|
|
wgroup.long 0xC24++0x03
|
|
line.long 0x00 "CRSR_INTCLR,Cursor Interrupt Clear register"
|
|
bitfld.long 0x00 0. " CRSRIC ,Cursor interrupt clear" "Not clear,Clear"
|
|
rgroup.long 0xC28++0x07
|
|
line.long 0x00 "CRSR_INTRAW,Cursor Raw Interrupt Status register"
|
|
bitfld.long 0x00 0. " CRSRRIS ,Cursor raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "CRSR_INTSTAT,Cursor Masked Interrupt Status register"
|
|
bitfld.long 0x04 0. " CRSRMIS ,Cursor masked interrupt status" "Not masked,Masked"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "SCT (State Configurable Timer)"
|
|
base ad:0x40000000
|
|
width 15.
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,SCT Configuration Register"
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("LPC811M001JDH16")&&!cpuis("LPC832M101FDH20")&&!cpuis("LPC834M101FHI33")&&!cpuis("LPC84*")&&!cpuis("LPC11E*")
|
|
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " NORELAOD ,Prevents the lower and higher match registers from being reloaded" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("LPC11E*")
|
|
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..."
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT"
|
|
else
|
|
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),Rising edges(input 4),Falling edges(input 4),Rising edges(input 5),Falling edges(input 5),Rising edges(input 6),Falling edges(input 6),Rising edges(input 7),Falling edges(input 7)"
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,SCT Configuration Register"
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 18. " AUTOLIMIT_H ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on match register 0 as a limit condition" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("LPC811M001JDH16")&&!cpuis("LPC832M101FDH20")&&!cpuis("LPC834M101FHI33")&&!cpuis("LPC84*")&&!cpuis("LPC11E*")
|
|
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " NORELOADH ,Prevents the higher match registers from being reloaded" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " NORELAODL ,Prevents the lower match registers from being reloaded" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("LPC11E*")
|
|
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..."
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT"
|
|
else
|
|
bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),Rising edges(input 4),Falling edges(input 4),Rising edges(input 5),Falling edges(input 5),Rising edges(input 6),Falling edges(input 6),Rising edges(input 7),Falling edges(input 7)"
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit"
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL,SCT Control Register"
|
|
hexmask.long.byte 0x00 5.--12. 1. " PRE ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
|
|
bitfld.long 0x00 4. " BIDIR ,L or unified counter direction select" "Limit then zero,Limit then down"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRCTR ,Unified clear counter" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " HALT ,Unified halt counter" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 1. " STOP ,Unified stop counter" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " DOWN ,Unified counting down counter" "No action,Counting down"
|
|
else
|
|
group.word 0x04++0x03
|
|
line.word 0x00 "CTRL_L,SCT Control Register Low Counter 16-bit"
|
|
hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
|
|
bitfld.word 0x00 4. " BIDIR_L ,L or unified counter direction select" "Limit then zero,Limit then down"
|
|
newline
|
|
bitfld.word 0x00 3. " CLRCTR_L ,Unified clear counter" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " HALT_L ,Unified halt counter" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x00 1. " STOP_L ,Unified stop counter" "Not stopped,Stopped"
|
|
bitfld.word 0x00 0. " DOWN_L ,Unified counting down counter" "No action,Counting down"
|
|
line.word 0x02 "CTRL_H,SCT Control Register High Counter 16-bit"
|
|
hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Specifies the factor by which the SCT clock is prescaled to produce the H counter lock"
|
|
bitfld.word 0x02 4. " BIDIR_H ,Direction select" "Limit then zero,Limit then down"
|
|
newline
|
|
bitfld.word 0x02 3. " CLRCTR_H ,Unified clear counter" "Not cleared,Cleared"
|
|
bitfld.word 0x02 2. " HALT_H ,Unified halt counter" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x02 1. " STOP_H ,Unified stop counter" "Not stopped,Stopped"
|
|
bitfld.word 0x02 0. " DOWN_H ,Unified counting down counter" "No action,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LIMIT,SCT Limit Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 15. " LIMMSK_L15 ,Event 15 used as counter limit" "Not used,Used"
|
|
bitfld.long 0x00 14. " LIMMSK_L14 ,Event 14 used as counter limit" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 13. " LIMMSK_L13 ,Event 13 used as counter limit" "Not used,Used"
|
|
bitfld.long 0x00 12. " LIMMSK_L12 ,Event 12 used as counter limit" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " LIMMSK_L11 ,Event 11 used as counter limit" "Not used,Used"
|
|
bitfld.long 0x00 10. " LIMMSK_L10 ,Event 10 used as counter limit" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 9. " LIMMSK_L9 ,Event 9 used as counter limit" "Not used,Used"
|
|
bitfld.long 0x00 8. " LIMMSK_L8 ,Event 8 used as counter limit" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 7. " LIMMSK_L7 ,Event 7 used as counter limit" "Not used,Used"
|
|
bitfld.long 0x00 6. " LIMMSK_L6 ,Event 6 used as counter limit" "Not used,Used"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit" "Not used,Used"
|
|
bitfld.long 0x00 4. " LIMMSK_L4 ,Event 4 used as counter limit" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 3. " LIMMSK_L3 ,Event 3 used as counter limit" "Not used,Used"
|
|
bitfld.long 0x00 2. " LIMMSK_L2 ,Event 2 used as counter limit" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 1. " LIMMSK_L1 ,Event 1 used as counter limit" "Not used,Used"
|
|
bitfld.long 0x00 0. " LIMMSK_L0 ,Event 0 used as counter limit" "Not used,Used"
|
|
else
|
|
group.word 0x08++0x03
|
|
line.word 0x00 "LIMIT_L,SCT Limit Register Low Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit L" "Not used,Used"
|
|
else
|
|
newline
|
|
bitfld.word 0x00 15. " LIMMSK_L15 ,Event 15 used as counter limit L" "Not used,Used"
|
|
bitfld.word 0x00 14. " LIMMSK_L14 ,Event 14 used as counter limit L" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x00 13. " LIMMSK_L13 ,Event 13 used as counter limit L" "Not used,Used"
|
|
bitfld.word 0x00 12. " LIMMSK_L12 ,Event 12 used as counter limit L" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x00 11. " LIMMSK_L11 ,Event 11 used as counter limit L" "Not used,Used"
|
|
bitfld.word 0x00 10. " LIMMSK_L10 ,Event 10 used as counter limit L" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x00 9. " LIMMSK_L9 ,Event 9 used as counter limit L" "Not used,Used"
|
|
bitfld.word 0x00 8. " LIMMSK_L8 ,Event 8 used as counter limit L" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x00 7. " LIMMSK_L7 ,Event 7 used as counter limit L" "Not used,Used"
|
|
bitfld.word 0x00 6. " LIMMSK_L6 ,Event 6 used as counter limit L" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit L" "Not used,Used"
|
|
endif
|
|
bitfld.word 0x00 4. " LIMMSK_L4 ,Event 4 used as counter limit L" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x00 3. " LIMMSK_L3 ,Event 3 used as counter limit L" "Not used,Used"
|
|
bitfld.word 0x00 2. " LIMMSK_L2 ,Event 2 used as counter limit L" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x00 1. " LIMMSK_L1 ,Event 1 used as counter limit L" "Not used,Used"
|
|
bitfld.word 0x00 0. " LIMMSK_L0 ,Event 0 used as counter limit L" "Not used,Used"
|
|
line.word 0x02 "LIMIT_H,SCT Limit Register High Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x02 5. " LIMMSK_H21 ,Event 21 used as counter limit H" "Not used,Used"
|
|
else
|
|
newline
|
|
bitfld.word 0x02 15. " LIMMSK_H31 ,Event 31 used as counter limit H" "Not used,Used"
|
|
bitfld.word 0x02 14. " LIMMSK_H30 ,Event 30 used as counter limit H" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x02 13. " LIMMSK_H29 ,Event 29 used as counter limit H" "Not used,Used"
|
|
bitfld.word 0x02 12. " LIMMSK_H28 ,Event 28 used as counter limit H" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x02 11. " LIMMSK_H27 ,Event 27 used as counter limit H" "Not used,Used"
|
|
bitfld.word 0x02 10. " LIMMSK_H26 ,Event 26 used as counter limit H" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x02 9. " LIMMSK_H25 ,Event 25 used as counter limit H" "Not used,Used"
|
|
bitfld.word 0x02 8. " LIMMSK_H24 ,Event 24 used as counter limit H" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x02 7. " LIMMSK_H23 ,Event 23 used as counter limit H" "Not used,Used"
|
|
bitfld.word 0x02 6. " LIMMSK_H22 ,Event 22 used as counter limit H" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x02 5. " LIMMSK_H21 ,Event 21 used as counter limit H" "Not used,Used"
|
|
endif
|
|
bitfld.word 0x02 4. " LIMMSK_H20 ,Event 20 used as counter limit H" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x02 3. " LIMMSK_H19 ,Event 19 used as counter limit H" "Not used,Used"
|
|
bitfld.word 0x02 2. " LIMMSK_H18 ,Event 18 used as counter limit H" "Not used,Used"
|
|
newline
|
|
bitfld.word 0x02 1. " LIMMSK_H17 ,Event 17 used as counter limit H" "Not used,Used"
|
|
bitfld.word 0x02 0. " LIMMSK_H16 ,Event 16 used as counter limit H" "Not used,Used"
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HALT,SCT Halt Condition Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 15. " HALTMSK_L15 ,Counter halted L event 15" "Not halted,Halted"
|
|
bitfld.long 0x00 14. " HALTMSK_L14 ,Counter halted L event 14" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 13. " HALTMSK_L13 ,Counter halted L event 13" "Not halted,Halted"
|
|
bitfld.long 0x00 12. " HALTMSK_L12 ,Counter halted L event 12" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 11. " HALTMSK_L11 ,Counter halted L event 11" "Not halted,Halted"
|
|
bitfld.long 0x00 10. " HALTMSK_L10 ,Counter halted L event 10" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 9. " HALTMSK_L9 ,Counter halted L event 9" "Not halted,Halted"
|
|
bitfld.long 0x00 8. " HALTMSK_L8 ,Counter halted L event 8" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted"
|
|
bitfld.long 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
|
|
bitfld.long 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted"
|
|
bitfld.long 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted"
|
|
else
|
|
group.word 0x0C++0x03
|
|
line.word 0x00 "HALT_L,SCT Halt Condition Register Low Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
|
|
else
|
|
newline
|
|
bitfld.word 0x00 15. " HALTMSK_L15 ,Counter halted L event 15" "Not halted,Halted"
|
|
bitfld.word 0x00 14. " HALTMSK_L14 ,Counter halted L event 14" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x00 13. " HALTMSK_L13 ,Counter halted L event 13" "Not halted,Halted"
|
|
bitfld.word 0x00 12. " HALTMSK_L12 ,Counter halted L event 12" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x00 11. " HALTMSK_L11 ,Counter halted L event 11" "Not halted,Halted"
|
|
bitfld.word 0x00 10. " HALTMSK_L10 ,Counter halted L event 10" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x00 9. " HALTMSK_L9 ,Counter halted L event 9" "Not halted,Halted"
|
|
bitfld.word 0x00 8. " HALTMSK_L8 ,Counter halted L event 8" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted"
|
|
bitfld.word 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted"
|
|
endif
|
|
bitfld.word 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted"
|
|
bitfld.word 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted"
|
|
bitfld.word 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted"
|
|
line.word 0x02 "HALT_H,SCT Halt Condition Register High Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted"
|
|
else
|
|
newline
|
|
bitfld.word 0x02 15. " HALTMSK_H31 ,Counter halted H event 31" "Not halted,Halted"
|
|
bitfld.word 0x02 14. " HALTMSK_H30 ,Counter halted H event 30" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x02 13. " HALTMSK_H29 ,Counter halted H event 29" "Not halted,Halted"
|
|
bitfld.word 0x02 12. " HALTMSK_H28 ,Counter halted H event 28" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x02 11. " HALTMSK_H27 ,Counter halted H event 27" "Not halted,Halted"
|
|
bitfld.word 0x02 10. " HALTMSK_H26 ,Counter halted H event 26" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x02 9. " HALTMSK_H25 ,Counter halted H event 25" "Not halted,Halted"
|
|
bitfld.word 0x02 8. " HALTMSK_H24 ,Counter halted H event 24" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x02 7. " HALTMSK_H23 ,Counter halted H event 23" "Not halted,Halted"
|
|
bitfld.word 0x02 6. " HALTMSK_H22 ,Counter halted H event 22" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted"
|
|
bitfld.word 0x02 4. " HALTMSK_H20 ,Counter halted H event 20" "Not halted,Halted"
|
|
endif
|
|
newline
|
|
bitfld.word 0x02 3. " HALTMSK_H19 ,Counter halted H event 19" "Not halted,Halted"
|
|
bitfld.word 0x02 2. " HALTMSK_H18 ,Counter halted H event 18" "Not halted,Halted"
|
|
newline
|
|
bitfld.word 0x02 1. " HALTMSK_H17 ,Counter halted H event 17" "Not halted,Halted"
|
|
bitfld.word 0x02 0. " HALTMSK_H16 ,Counter halted H event 16" "Not halted,Halted"
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STOP,SCT Stop Condition Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 15. " STOPMSK_L15 ,Event 15 counter stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " STOPMSK_L14 ,Event 14 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 13. " STOPMSK_L13 ,Event 13 counter stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " STOPMSK_L12 ,Event 12 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 11. " STOPMSK_L11 ,Event 11 counter stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 10. " STOPMSK_L10 ,Event 10 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 9. " STOPMSK_L9 ,Event 9 counter stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " STOPMSK_L8 ,Event 8 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " STOPMSK_L7 ,Event 7 counter stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 6. " STOPMSK_L6 ,Event 6 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " STOPMSK_L5 ,Event 6 counter stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4. " STOPMSK_L4 ,Event 4 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 3. " STOPMSK_L3 ,Event 3 counter stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " STOPMSK_L2 ,Event 2 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 1. " STOPMSK_L1 ,Event 1 counter stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " STOPMSK_L0 ,Event 0 counter stopped" "Not stopped,Stopped"
|
|
else
|
|
group.word 0x10++0x03
|
|
line.word 0x00 "STOP_L,SCT Stop Condition Register Low Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter stopped" "Not stopped,Stopped"
|
|
else
|
|
newline
|
|
bitfld.word 0x00 15. " STOPMSK_L15 ,Event 15 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x00 14. " STOPMSK_L14 ,Event 14 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 13. " STOPMSK_L13 ,Event 13 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x00 12. " STOPMSK_L12 ,Event 12 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 11. " STOPMSK_L11 ,Event 11 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x00 10. " STOPMSK_L10 ,Event 10 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 9. " STOPMSK_L9 ,Event 9 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x00 8. " STOPMSK_L8 ,Event 8 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 7. " STOPMSK_L7 ,Event 7 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x00 6. " STOPMSK_L6 ,Event 6 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter stopped" "Not stopped,Stopped"
|
|
endif
|
|
bitfld.word 0x00 4. " STOPMSK_L4 ,Event 4 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 3. " STOPMSK_L3 ,Event 3 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " STOPMSK_L2 ,Event 2 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 1. " STOPMSK_L1 ,Event 1 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x00 0. " STOPMSK_L0 ,Event 0 counter stopped" "Not stopped,Stopped"
|
|
line.word 0x02 "STOP_H,SCT Stop Condition Register High Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter stopped" "Not stopped,Stopped"
|
|
else
|
|
newline
|
|
bitfld.word 0x02 15. " STOPMSK_H31 ,Event 31 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x02 14. " STOPMSK_H30 ,Event 30 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x02 13. " STOPMSK_H29 ,Event 29 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x02 12. " STOPMSK_H28 ,Event 28 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x02 11. " STOPMSK_H27 ,Event 27 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x02 10. " STOPMSK_H26 ,Event 26 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x02 9. " STOPMSK_H25 ,Event 25 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x02 8. " STOPMSK_H24 ,Event 24 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x02 7. " STOPMSK_H23 ,Event 23 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x02 6. " STOPMSK_H22 ,Event 22 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter stopped" "Not stopped,Stopped"
|
|
endif
|
|
bitfld.word 0x02 4. " STOPMSK_H20 ,Event 20 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x02 3. " STOPMSK_H19 ,Event 19 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x02 2. " STOPMSK_H18 ,Event 18 counter stopped" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x02 1. " STOPMSK_H17 ,Event 17 counter stopped" "Not stopped,Stopped"
|
|
bitfld.word 0x02 0. " STOPMSK_H16 ,Event 16 counter stopped" "Not stopped,Stopped"
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "START,SCT Start Condition Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 15. " STARTMSK_L15 ,Event 15 counter started" "Not started,Started"
|
|
bitfld.long 0x00 14. " STARTMSK_L14 ,Event 14 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 13. " STARTMSK_L13 ,Event 13 counter started" "Not started,Started"
|
|
bitfld.long 0x00 12. " STARTMSK_L12 ,Event 12 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 11. " STARTMSK_L11 ,Event 11 counter started" "Not started,Started"
|
|
bitfld.long 0x00 10. " STARTMSK_L10 ,Event 10 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " STARTMSK_L9 ,Event 9 counter started" "Not started,Started"
|
|
bitfld.long 0x00 8. " STARTMSK_L8 ,Event 8 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 7. " STARTMSK_L7 ,Event 7 counter started" "Not started,Started"
|
|
bitfld.long 0x00 6. " STARTMSK_L6 ,Event 6 counter started" "Not started,Started"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
|
|
bitfld.long 0x00 4. " STARTMSK_L4 ,Event 4 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 3. " STARTMSK_L3 ,Event 3 counter started" "Not started,Started"
|
|
bitfld.long 0x00 2. " STARTMSK_L2 ,Event 2 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 1. " STARTMSK_L1 ,Event 1 counter started" "Not started,Started"
|
|
bitfld.long 0x00 0. " STARTMSK_L0 ,Event 0 counter started" "Not started,Started"
|
|
else
|
|
group.word 0x14++0x03
|
|
line.word 0x00 "START_L,SCT Start Condition Register Low Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
|
|
else
|
|
newline
|
|
bitfld.word 0x00 15. " STARTMSK_L15 ,Event 15 counter started" "Not started,Started"
|
|
bitfld.word 0x00 14. " STARTMSK_L14 ,Event 14 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x00 13. " STARTMSK_L13 ,Event 13 counter started" "Not started,Started"
|
|
bitfld.word 0x00 12. " STARTMSK_L12 ,Event 12 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x00 11. " STARTMSK_L11 ,Event 11 counter started" "Not started,Started"
|
|
bitfld.word 0x00 10. " STARTMSK_L10 ,Event 10 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x00 9. " STARTMSK_L9 ,Event 9 counter started" "Not started,Started"
|
|
bitfld.word 0x00 8. " STARTMSK_L8 ,Event 8 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x00 7. " STARTMSK_L7 ,Event 7 counter started" "Not started,Started"
|
|
bitfld.word 0x00 6. " STARTMSK_L6 ,Event 6 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started"
|
|
endif
|
|
bitfld.word 0x00 4. " STARTMSK_L4 ,Event 4 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x00 3. " STARTMSK_L3 ,Event 3 counter started" "Not started,Started"
|
|
bitfld.word 0x00 2. " STARTMSK_L2 ,Event 2 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x00 1. " STARTMSK_L1 ,Event 1 counter started" "Not started,Started"
|
|
bitfld.word 0x00 0. " STARTMSK_L0 ,Event 0 counter started" "Not started,Started"
|
|
line.word 0x02 "START_H,SCT Start Condition Register High Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter started" "Not started,Started"
|
|
else
|
|
newline
|
|
bitfld.word 0x02 15. " STARTMSK_H31 ,Event 31 counter started" "Not started,Started"
|
|
bitfld.word 0x02 14. " STARTMSK_H30 ,Event 30 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x02 13. " STARTMSK_H29 ,Event 29 counter started" "Not started,Started"
|
|
bitfld.word 0x02 12. " STARTMSK_H28 ,Event 28 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x02 11. " STARTMSK_H27 ,Event 27 counter started" "Not started,Started"
|
|
bitfld.word 0x02 10. " STARTMSK_H26 ,Event 26 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x02 9. " STARTMSK_H25 ,Event 25 counter started" "Not started,Started"
|
|
bitfld.word 0x02 8. " STARTMSK_H24 ,Event 24 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x02 7. " STARTMSK_H23 ,Event 23 counter started" "Not started,Started"
|
|
bitfld.word 0x02 6. " STARTMSK_H22 ,Event 22 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter started" "Not started,Started"
|
|
endif
|
|
bitfld.word 0x02 4. " STARTMSK_H20 ,Event 20 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x02 3. " STARTMSK_H19 ,Event 19 counter started" "Not started,Started"
|
|
bitfld.word 0x02 2. " STARTMSK_H18 ,Event 18 counter started" "Not started,Started"
|
|
newline
|
|
bitfld.word 0x02 1. " STARTMSK_H17 ,Event 17 counter started" "Not started,Started"
|
|
bitfld.word 0x02 0. " STARTMSK_H16 ,Event 16 counter started" "Not started,Started"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DITHER_L,SCT Dither Condition Register"
|
|
bitfld.long 0x00 15. " DITHMSK_L15 ,Event 15 dither mask" "Not dithered,Dithered"
|
|
bitfld.long 0x00 14. " DITHMSK_L14 ,Event 14 dither mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.long 0x00 13. " DITHMSK_L13 ,Event 13 dither mask" "Not dithered,Dithered"
|
|
bitfld.long 0x00 12. " DITHMSK_L12 ,Event 12 dither mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.long 0x00 11. " DITHMSK_L11 ,Event 11 dither mask" "Not dithered,Dithered"
|
|
bitfld.long 0x00 10. " DITHMSK_L10 ,Event 10 dither mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.long 0x00 9. " DITHMSK_L9 ,Event 9 dither mask" "Not dithered,Dithered"
|
|
bitfld.long 0x00 8. " DITHMSK_L8 ,Event 8 dither mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.long 0x00 7. " DITHMSK_L7 ,Event 7 dither mask" "Not dithered,Dithered"
|
|
bitfld.long 0x00 6. " DITHMSK_L6 ,Event 6 dither mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.long 0x00 5. " DITHMSK_L5 ,Event 5 dither mask" "Not dithered,Dithered"
|
|
bitfld.long 0x00 4. " DITHMSK_L4 ,Event 4 dither mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.long 0x00 3. " DITHMSK_L3 ,Event 3 dither mask" "Not dithered,Dithered"
|
|
bitfld.long 0x00 2. " DITHMSK_L2 ,Event 2 dither mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.long 0x00 1. " DITHMSK_L1 ,Event 1 dither mask" "Not dithered,Dithered"
|
|
bitfld.long 0x00 0. " DITHMSK_L0 ,Event 0 dither mask" "Not dithered,Dithered"
|
|
else
|
|
group.word 0x18++0x03
|
|
line.word 0x00 "DITHER_L,SCT Dither Condition Register"
|
|
bitfld.word 0x00 15. " DITHMSK_L15 ,Event 15 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x00 14. " DITHMSK_L14 ,Event 14 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x00 13. " DITHMSK_L13 ,Event 13 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x00 12. " DITHMSK_L12 ,Event 12 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x00 11. " DITHMSK_L11 ,Event 11 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x00 10. " DITHMSK_L10 ,Event 10 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x00 9. " DITHMSK_L9 ,Event 9 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x00 8. " DITHMSK_L8 ,Event 8 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x00 7. " DITHMSK_L7 ,Event 7 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x00 6. " DITHMSK_L6 ,Event 6 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x00 5. " DITHMSK_L5 ,Event 5 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x00 4. " DITHMSK_L4 ,Event 4 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x00 3. " DITHMSK_L3 ,Event 3 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x00 2. " DITHMSK_L2 ,Event 2 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x00 1. " DITHMSK_L1 ,Event 1 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x00 0. " DITHMSK_L0 ,Event 0 dither pattern mask" "Not dithered,Dithered"
|
|
line.word 0x02 "DITHER_H,SCT Dither Condition Register"
|
|
bitfld.word 0x02 15. " DITHMSK_H31 ,Event 31 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x02 14. " DITHMSK_H30 ,Event 30 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x02 13. " DITHMSK_H29 ,Event 29 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x02 12. " DITHMSK_H28 ,Event 28 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x02 11. " DITHMSK_H27 ,Event 27 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x02 10. " DITHMSK_H26 ,Event 26 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x02 9. " DITHMSK_H25 ,Event 25 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x02 8. " DITHMSK_H24 ,Event 24 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x02 7. " DITHMSK_H23 ,Event 23 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x02 6. " DITHMSK_H22 ,Event 22 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x02 5. " DITHMSK_H21 ,Event 21 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x02 4. " DITHMSK_H20 ,Event 20 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x02 3. " DITHMSK_H19 ,Event 19 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x02 2. " DITHMSK_H18 ,Event 18 dither pattern mask" "Not dithered,Dithered"
|
|
newline
|
|
bitfld.word 0x02 1. " DITHMSK_H17 ,Event 17 dither pattern mask" "Not dithered,Dithered"
|
|
bitfld.word 0x02 0. " DITHMSK_H16 ,Event 16 dither pattern mask" "Not dithered,Dithered"
|
|
endif
|
|
endif
|
|
newline
|
|
width 15.
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "COUNT,SCT Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CTR_L ,L counter value"
|
|
else
|
|
group.word 0x40++0x03
|
|
line.word 0x00 "COUNT_L,SCT Counter Register Low Counter 16-bit"
|
|
line.word 0x02 "COUNT_H,SCT Counter Register High Counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "STATE,SCT State Register"
|
|
bitfld.long 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word 0x44++0x03
|
|
line.word 0x00 "STATE_L,SCT State Register Low Counter 16-bit"
|
|
bitfld.word 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x02 "STATE_H,SCT State Register High Counter 16-bit"
|
|
bitfld.word 0x02 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT Input Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 23. " SIN7 ,Input 7 state synchronized to the SCT clock" "0,1"
|
|
bitfld.long 0x00 22. " SIN6 ,Input 6 state synchronized to the SCT clock" "0,1"
|
|
bitfld.long 0x00 21. " SIN5 ,Input 5 state synchronized to the SCT clock" "0,1"
|
|
bitfld.long 0x00 20. " SIN4 ,Input 4 state synchronized to the SCT clock" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state synchronized to the SCT clock" "0,1"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state synchronized to the SCT clock" "0,1"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state synchronized to the SCT clock" "0,1"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state synchronized to the SCT clock" "0,1"
|
|
newline
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 7. " AIN7 ,Real-time status of input 7" "0,1"
|
|
bitfld.long 0x00 6. " AIN6 ,Real-time status of input 6" "0,1"
|
|
bitfld.long 0x00 5. " AIN5 ,Real-time status of input 5" "0,1"
|
|
bitfld.long 0x00 4. " AIN4 ,Real-time status of input 4" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " AIN3 ,Real-time status of input 3" "0,1"
|
|
bitfld.long 0x00 2. " AIN2 ,Real-time status of input 2" "0,1"
|
|
bitfld.long 0x00 1. " AIN1 ,Real-time status of input 1" "0,1"
|
|
bitfld.long 0x00 0. " AIN0 ,Real-time status of input 0" "0,1"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "REGMODE,SCT Match/Capture Registers Mode Register"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.long 0x00 4. " REGMOD[4] ,5th pair of match/capture registers" "Match,Capture"
|
|
else
|
|
newline
|
|
bitfld.long 0x00 15. " REGMOD[15] ,16th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
|
|
bitfld.long 0x00 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
|
|
else
|
|
group.word 0x4C++0x03
|
|
line.word 0x00 "REGMODE_L,SCT Match/Capture Registers Mode Register Low Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x00 4. " REGMOD_L[4] ,5th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
else
|
|
bitfld.word 0x00 15. " REGMOD_L[15] ,16th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
bitfld.word 0x00 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
bitfld.word 0x00 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x00 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
|
|
line.word 0x02 "REGMODE_H,SCT Match/Capture Registers Mode Register High Counter 16-bit"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.word 0x02 4. " REGMOD_H[4] ,5th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
else
|
|
bitfld.word 0x02 15. " REGMOD_H[15] ,16th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 14. " [14] ,15th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 13. " [13] ,14th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 12. " [12] ,13th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
bitfld.word 0x02 11. " [11] ,12th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 10. " [10] ,11th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 9. " [9] ,10th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 8. " [8] ,9th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
bitfld.word 0x02 7. " [7] ,8th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 6. " [6] ,7th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 5. " [5] ,6th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 4. " [4] ,5th pair of match/capture registers" "Match,Capture"
|
|
newline
|
|
endif
|
|
bitfld.word 0x02 3. " [3] ,4th pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 2. " [2] ,3rd pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 1. " [1] ,2nd pair of match/capture registers" "Match,Capture"
|
|
bitfld.word 0x02 0. " [0] ,1th pair of match/capture registers" "Match,Capture"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
if (((((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)&&(((per.l(ad:0x40000000))&0x01)==0x00))||((((per.l(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.l(ad:0x40000000))&0x01)==0x01)))
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "OUTPUT,SCT Output Register"
|
|
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
|
|
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
|
|
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
|
|
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
|
|
else
|
|
rgroup.long 0x50++0x13
|
|
line.long 0x00 "OUTPUT,SCT Output Register"
|
|
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
|
|
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
|
|
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
|
|
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
|
|
endif
|
|
else
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "OUTPUT,SCT Output Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 15. " OUT15 ,Output 15" "Low,High"
|
|
bitfld.long 0x00 14. " OUT14 ,Output 14" "Low,High"
|
|
bitfld.long 0x00 13. " OUT13 ,Output 13" "Low,High"
|
|
bitfld.long 0x00 12. " OUT12 ,Output 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " OUT11 ,Output 11" "Low,High"
|
|
bitfld.long 0x00 10. " OUT10 ,Output 10" "Low,High"
|
|
bitfld.long 0x00 9. " OUT9 ,Output 9" "Low,High"
|
|
bitfld.long 0x00 8. " OUT8 ,Output 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " OUT7 ,Output 7" "Low,High"
|
|
bitfld.long 0x00 6. " OUT6 ,Output 6" "Low,High"
|
|
bitfld.long 0x00 5. " OUT5 ,Output 5" "Low,High"
|
|
bitfld.long 0x00 4. " OUT4 ,Output 4" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High"
|
|
bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High"
|
|
bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High"
|
|
bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High"
|
|
endif
|
|
newline
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OUTPUTDIRCTRL,SCT Bidirectional Output Control Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 30.--31. " SETCLR15 ,Set/clear operation on output 15" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 28.--29. " SETCLR14 ,Set/clear operation on output 14" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 26.--27. " SETCLR13 ,Set/clear operation on output 13" "Not depend,L is counting down,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--25. " SETCLR12 ,Set/clear operation on output 12" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 22.--23. " SETCLR11 ,Set/clear operation on output 11" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 20.--21. " SETCLR10 ,Set/clear operation on output 10" "Not depend,L is counting down,?..."
|
|
newline
|
|
bitfld.long 0x00 18.--19. " SETCLR9 ,Set/clear operation on output 9" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 16.--17. " SETCLR8 ,Set/clear operation on output 8" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 14.--15. " SETCLR7 ,Set/clear operation on output 7" "Not depend,L is counting down,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " SETCLR6 ,Set/clear operation on output 6" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,?..."
|
|
bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,?..."
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OUTPUTDIRCTRL,SCT Bidirectional Output Control Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 30.--31. " SETCLR15 ,Set/clear operation on output 15" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 28.--29. " SETCLR14 ,Set/clear operation on output 14" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 26.--27. " SETCLR13 ,Set/clear operation on output 13" "Not depend,L is counting down,H is counting down,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--25. " SETCLR12 ,Set/clear operation on output 12" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 22.--23. " SETCLR11 ,Set/clear operation on output 11" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 20.--21. " SETCLR10 ,Set/clear operation on output 10" "Not depend,L is counting down,H is counting down,?..."
|
|
newline
|
|
bitfld.long 0x00 18.--19. " SETCLR9 ,Set/clear operation on output 9" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 16.--17. " SETCLR8 ,Set/clear operation on output 8" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 14.--15. " SETCLR7 ,Set/clear operation on output 7" "Not depend,L is counting down,H is counting down,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " SETCLR6 ,Set/clear operation on output 6" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,H is counting down,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,H is counting down,?..."
|
|
bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,H is counting down,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,H is counting down,?..."
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "RES,SCT Conflict Resolution Register"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x00 30.--31. " O15RES ,Effect of simultaneous set and clear on output 15" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 28.--29. " O14RES ,Effect of simultaneous set and clear on output 14" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 26.--27. " O13RES ,Effect of simultaneous set and clear on output 13" "No change,Set output,Clear output,Toggle output"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " O12RES ,Effect of simultaneous set and clear on output 12" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 22.--23. " O11RES ,Effect of simultaneous set and clear on output 11" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 20.--21. " O10RES ,Effect of simultaneous set and clear on output 10" "No change,Set output,Clear output,Toggle output"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " O9RES ,Effect of simultaneous set and clear on output 9" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 16.--17. " O8RES ,Effect of simultaneous set and clear on output 8" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 14.--15. " O7RES ,Effect of simultaneous set and clear on output 7" "No change,Set output,Clear output,Toggle output"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " O6RES ,Effect of simultaneous set and clear on output 6" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set output,Clear output,Toggle output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set output,Clear output,Toggle output"
|
|
bitfld.long 0x00 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set output,Clear output,Toggle output"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set output,Clear output,Toggle output"
|
|
line.long 0x04 "DMAREQ0,SCT DMA 0 Request Register"
|
|
rbitfld.long 0x04 31. " DRQ0 ,Indicates the state of DMA request 0" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " DRL0 ,The SCT set DMA request 0 when it loads the match_l/unified registers from the reload_l/unified registers" "Not requested,Requested"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x04 15. " DEV_0[15] ,Event 15 sets DMA request 0" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x04 14. " [14] ,Event 14 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 sets DMA request 0" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 sets DMA request 0" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x04 8. " [8] ,Event 8 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 7. " [7] ,Event 7 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 sets DMA request 0" "Not set,Set"
|
|
endif
|
|
newline
|
|
sif cpuis("LPC11E*")
|
|
bitfld.long 0x04 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set"
|
|
else
|
|
bitfld.long 0x04 5. " [5] ,Event 5 sets DMA request 0" "Not set,Set"
|
|
endif
|
|
bitfld.long 0x04 4. " [4] ,Event 4 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 sets DMA request 0" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 sets DMA request 0" "Not set,Set"
|
|
line.long 0x08 "DMAREQ1,SCT DMA 1 Request Register"
|
|
rbitfld.long 0x08 31. " DRQ1 ,Indicates the state of DMA request 1" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " DRL1 ,The SCT set DMA request 1 when it loads the match_l/unified registers from the reload_l/unified registers" "Not requested,Requested"
|
|
sif !cpuis("LPC11E*")
|
|
bitfld.long 0x08 15. " DEV_1[15] ,Event 15 sets DMA request 1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x08 14. " [14] ,Event 14 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 13. " [13] ,Event 13 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 12. " [12] ,Event 12 sets DMA request 1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x08 11. " [11] ,Event 11 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 10. " [10] ,Event 10 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 9. " [9] ,Event 9 sets DMA request 1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x08 8. " [8] ,Event 8 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 7. " [7] ,Event 7 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 6. " [6] ,Event 6 sets DMA request 1" "Not set,Set"
|
|
endif
|
|
newline
|
|
sif cpuis("LPC11E*")
|
|
bitfld.long 0x08 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set"
|
|
else
|
|
bitfld.long 0x08 5. " [5] ,Event 5 sets DMA request 1" "Not set,Set"
|
|
endif
|
|
bitfld.long 0x08 4. " [4] ,Event 4 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 3. " [3] ,Event 3 sets DMA request 1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x08 2. " [2] ,Event 2 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 1. " [1] ,Event 1 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x08 0. " [0] ,Event 0 sets DMA request 1" "Not set,Set"
|
|
sif cpuis("LPC11E*")
|
|
group.long 0xF0++0x07
|
|
line.long 0x00 "EVEN,SCT Flag Enable Register"
|
|
bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "EVFLAG,SCT Event Flag Register"
|
|
bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 occurred" "Not occurred,Occurred"
|
|
else
|
|
group.long 0xF0++0x07
|
|
line.long 0x00 "EVEN,SCT Flag Enable Register"
|
|
bitfld.long 0x00 15. " IEN15 ,Event 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Event 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Event 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "EVFLAG,SCT Event Flag Register"
|
|
eventfld.long 0x04 15. " FLAG15 ,Event 15occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 14. " [14] ,Event 14 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 13. " [13] ,Event 13 occurred" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 12. " [12] ,Event 12 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 11. " [11] ,Event 11 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 10. " [10] ,Event 10 occurred" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 9. " [9] ,Event 9 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 8. " [8] ,Event 8 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 7. " [7] ,Event 7 occurred" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 6. " [6] ,Event 6 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " [5] ,Event 5 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " [4] ,Event 4 occurred" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 3. " [3] ,Event 3 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 2. " [2] ,Event 2 occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x04 1. " [1] ,Event 1 occurred" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 0. " [0] ,Event 0 occurred" "Not occurred,Occurred"
|
|
endif
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CONEN,SCT Conflict Enable Register"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.long 0x00 3. " NCEN[3] ,No change conflict event 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,No change conflict event 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,No change conflict event 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,No change conflict event 0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 15. " NCEN[15] ,No change conflict event 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,No change conflict event 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,No change conflict event 13 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,No change conflict event 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,No change conflict event 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,No change conflict event 10 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,No change conflict event 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,No change conflict event 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,No change conflict event 7 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,No change conflict event 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,No change conflict event 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,No change conflict event 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,No change conflict event 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,No change conflict event 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,No change conflict event 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,No change conflict event 0 enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CONFLAG,SCT Conflict Flag Register"
|
|
bitfld.long 0x00 31. " BUSERRH ,Bus error from this SCT involved writing CTR H/STATE H/MATCH H/Output register" "No error,Error"
|
|
bitfld.long 0x00 30. " BUSERRL ,Bus error from this SCT involved writing CTR L-Unified/STATE L-Unified/MATCH L-Unified/Output register" "No error,Error"
|
|
bitfld.long 0x00 3. " NCFLAG[3] ,No-change conflict event 3 occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,No-change conflict event 2 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " [1] ,No-change conflict event 1 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,No-change conflict event 0 occurred" "Not occurred,Occurred"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CONFLAG,SCT Conflict Flag Register"
|
|
bitfld.long 0x00 31. " BUSERRH ,Bus error" "No error,Error"
|
|
bitfld.long 0x00 30. " BUSERRL ,Bus error" "No error,Error"
|
|
bitfld.long 0x00 15. " NCFLAG15 ,No-change conflict event 15 occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 14. " NCFLAG14 ,No-change conflict event 14 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " NCFLAG13 ,No-change conflict event 13 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " NCFLAG12 ,No-change conflict event 12 occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " NCFLAG11 ,No-change conflict event 11 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " NCFLAG10 ,No-change conflict event 10 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " NCFLAG9 ,No-change conflict event 9 occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 8. " NCFLAG8 ,No-change conflict event 8 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " NCFLAG7 ,No-change conflict event 7 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " NCFLAG6 ,No-change conflict event 6 occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. " NCFLAG5 ,No-change conflict event 5 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " NCFLAG4 ,No-change conflict event 4 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " NCFLAG3 ,No-change conflict event 3 occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. " NCFLAG2 ,No-change conflict event 2 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " NCFLAG1 ,No-change conflict event 1 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " NCFLAG0 ,No-change conflict event 0 occurred" "Not occurred,Occurred"
|
|
endif
|
|
width 26.
|
|
tree "Event 0 (Regmode0 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<0.))==(1<<0.))
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CAP0,SCT Capture Register 0"
|
|
else
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "MATCH0,SCT Match Register 0"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<0.))==(1<<0.))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CAP0,SCT Capture Register 0"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATCH0,SCT Match Register 0"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<0.))==(1<<0.))
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
|
|
else
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<0.))==(1<<0.))
|
|
group.word (0x100+0x02)++0x01
|
|
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
|
|
else
|
|
group.word (0x100+0x02)++0x01
|
|
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<0.))==(1<<0.))
|
|
rgroup.word 0x100++0x01
|
|
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x100++0x01
|
|
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<0.))==(1<<0.))
|
|
group.word (0x100+0x02)++0x01
|
|
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
|
|
else
|
|
group.word (0x100+0x02)++0x01
|
|
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<0.))==(1<<0.))
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
|
|
else
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<0.))==(1<<0.))
|
|
rgroup.word (0x100+0x02)++0x01
|
|
line.word 0x00 "CAP0_H,SCT Capture Register 0 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x100+0x02)++0x01
|
|
line.word 0x00 "MATCH0_H,SCT Match Register 0 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<0.))==(1<<0.))
|
|
rgroup.word 0x100++0x01
|
|
line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x100++0x01
|
|
line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<0.))==(1<<0.))
|
|
rgroup.word (0x100+0x02)++0x01
|
|
line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x100+0x02)++0x01
|
|
line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "FRACMAT0_L,SCT Fractional Match Register 0"
|
|
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x140++0x03
|
|
line.word 0x00 "FRACMAT0_L,SCT Fractional Match Register 0"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT0_H,SCT Fractional Match Register 0"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x100+0x100)++0x03
|
|
line.long 0x00 "MATCHREL0/CAPCTRL0,SCT Match/capture Reload Register 0"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x100+0x100)++0x03
|
|
line.word 0x00 "MATCHREL0_L/CAPCTRL0_L,SCT Match/capture Reload Register 0"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL0_H/CAPCTRL0_H,SCT Match/capture Reload Register 0"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x140+0x100)++0x03
|
|
line.long 0x00 "FRACMATREL0_L,SCT Fractional Match Reload Register 0"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word (0x140+0x100)++0x03
|
|
line.word 0x00 "FRACMATREL0_L,SCT Fractional Match Reload Register 0"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL0_H,SCT Fractional Match Reload Register 0"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long (0x100+0x200)++0x03
|
|
line.long 0x00 "EV0_STATE,SCT Event State Mask 0"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x100+0x204)++0x03
|
|
line.long 0x00 "EVCTRL0,SCT Event Control Register 0"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x100+0x204)++0x03
|
|
line.long 0x00 "EVCTRL0,SCT Event Control Register 0"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x100+0x400)++0x07
|
|
line.long 0x00 "OUT0_SET,SCT Output Set Register 0"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 0" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 0" "Not set,Set"
|
|
line.long 0x04 "OUT0_CLR,SCT Output Clear Register 0"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 0" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 0" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x100+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET0,SCT Output Set Register 0"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 0" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 0" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 0" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 0" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL0,SCT Output Clear Register 0"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 0" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 0" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 0" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 1 (Regmode1 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<1.))==(1<<1.))
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CAP1,SCT Capture Register 1"
|
|
else
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "MATCH1,SCT Match Register 1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<1.))==(1<<1.))
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CAP1,SCT Capture Register 1"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MATCH1,SCT Match Register 1"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<1.))==(1<<1.))
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
|
|
else
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<1.))==(1<<1.))
|
|
group.word (0x104+0x02)++0x01
|
|
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
|
|
else
|
|
group.word (0x104+0x02)++0x01
|
|
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<1.))==(1<<1.))
|
|
rgroup.word 0x104++0x01
|
|
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x104++0x01
|
|
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<1.))==(1<<1.))
|
|
group.word (0x104+0x02)++0x01
|
|
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
|
|
else
|
|
group.word (0x104+0x02)++0x01
|
|
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<1.))==(1<<1.))
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
|
|
else
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<1.))==(1<<1.))
|
|
rgroup.word (0x104+0x02)++0x01
|
|
line.word 0x00 "CAP1_H,SCT Capture Register 1 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x104+0x02)++0x01
|
|
line.word 0x00 "MATCH1_H,SCT Match Register 1 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<1.))==(1<<1.))
|
|
rgroup.word 0x104++0x01
|
|
line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x104++0x01
|
|
line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<1.))==(1<<1.))
|
|
rgroup.word (0x104+0x02)++0x01
|
|
line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x104+0x02)++0x01
|
|
line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "FRACMAT1_L,SCT Fractional Match Register 1"
|
|
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x144++0x03
|
|
line.word 0x00 "FRACMAT1_L,SCT Fractional Match Register 1"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT1_H,SCT Fractional Match Register 1"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x104+0x100)++0x03
|
|
line.long 0x00 "MATCHREL1/CAPCTRL1,SCT Match/capture Reload Register 1"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x104+0x100)++0x03
|
|
line.word 0x00 "MATCHREL1_L/CAPCTRL1_L,SCT Match/capture Reload Register 1"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL1_H/CAPCTRL1_H,SCT Match/capture Reload Register 1"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x144+0x100)++0x03
|
|
line.long 0x00 "FRACMATREL1_L,SCT Fractional Match Reload Register 1"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word (0x144+0x100)++0x03
|
|
line.word 0x00 "FRACMATREL1_L,SCT Fractional Match Reload Register 1"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL1_H,SCT Fractional Match Reload Register 1"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long (0x108+0x200)++0x03
|
|
line.long 0x00 "EV1_STATE,SCT Event State Mask 1"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x108+0x204)++0x03
|
|
line.long 0x00 "EVCTRL1,SCT Event Control Register 1"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x108+0x204)++0x03
|
|
line.long 0x00 "EVCTRL1,SCT Event Control Register 1"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x108+0x400)++0x07
|
|
line.long 0x00 "OUT1_SET,SCT Output Set Register 1"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 1" "Not set,Set"
|
|
line.long 0x04 "OUT1_CLR,SCT Output Clear Register 1"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 1" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 1" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x108+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET1,SCT Output Set Register 1"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 1" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL1,SCT Output Clear Register 1"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 1" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 1" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 1" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 2 (Regmode2 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<2.))==(1<<2.))
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CAP2,SCT Capture Register 2"
|
|
else
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "MATCH2,SCT Match Register 2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<2.))==(1<<2.))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CAP2,SCT Capture Register 2"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MATCH2,SCT Match Register 2"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<2.))==(1<<2.))
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
|
|
else
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<2.))==(1<<2.))
|
|
group.word (0x108+0x02)++0x01
|
|
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
|
|
else
|
|
group.word (0x108+0x02)++0x01
|
|
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<2.))==(1<<2.))
|
|
rgroup.word 0x108++0x01
|
|
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x108++0x01
|
|
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<2.))==(1<<2.))
|
|
group.word (0x108+0x02)++0x01
|
|
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
|
|
else
|
|
group.word (0x108+0x02)++0x01
|
|
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<2.))==(1<<2.))
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
|
|
else
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<2.))==(1<<2.))
|
|
rgroup.word (0x108+0x02)++0x01
|
|
line.word 0x00 "CAP2_H,SCT Capture Register 2 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x108+0x02)++0x01
|
|
line.word 0x00 "MATCH2_H,SCT Match Register 2 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<2.))==(1<<2.))
|
|
rgroup.word 0x108++0x01
|
|
line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x108++0x01
|
|
line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<2.))==(1<<2.))
|
|
rgroup.word (0x108+0x02)++0x01
|
|
line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x108+0x02)++0x01
|
|
line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "FRACMAT2_L,SCT Fractional Match Register 2"
|
|
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x148++0x03
|
|
line.word 0x00 "FRACMAT2_L,SCT Fractional Match Register 2"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT2_H,SCT Fractional Match Register 2"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x108+0x100)++0x03
|
|
line.long 0x00 "MATCHREL2/CAPCTRL2,SCT Match/capture Reload Register 2"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x108+0x100)++0x03
|
|
line.word 0x00 "MATCHREL2_L/CAPCTRL2_L,SCT Match/capture Reload Register 2"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL2_H/CAPCTRL2_H,SCT Match/capture Reload Register 2"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x148+0x100)++0x03
|
|
line.long 0x00 "FRACMATREL2_L,SCT Fractional Match Reload Register 2"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word (0x148+0x100)++0x03
|
|
line.word 0x00 "FRACMATREL2_L,SCT Fractional Match Reload Register 2"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL2_H,SCT Fractional Match Reload Register 2"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long (0x110+0x200)++0x03
|
|
line.long 0x00 "EV2_STATE,SCT Event State Mask 2"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x110+0x204)++0x03
|
|
line.long 0x00 "EVCTRL2,SCT Event Control Register 2"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x110+0x204)++0x03
|
|
line.long 0x00 "EVCTRL2,SCT Event Control Register 2"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x110+0x400)++0x07
|
|
line.long 0x00 "OUT2_SET,SCT Output Set Register 2"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 2" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 2" "Not set,Set"
|
|
line.long 0x04 "OUT2_CLR,SCT Output Clear Register 2"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 2" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 2" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x110+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET2,SCT Output Set Register 2"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 2" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 2" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 2" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 2" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL2,SCT Output Clear Register 2"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 2" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 2" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 2" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 2" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 3 (Regmode3 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<3.))==(1<<3.))
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CAP3,SCT Capture Register 3"
|
|
else
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "MATCH3,SCT Match Register 3"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<3.))==(1<<3.))
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CAP3,SCT Capture Register 3"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MATCH3,SCT Match Register 3"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<3.))==(1<<3.))
|
|
group.word 0x10C++0x01
|
|
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
|
|
else
|
|
group.word 0x10C++0x01
|
|
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<3.))==(1<<3.))
|
|
group.word (0x10C+0x02)++0x01
|
|
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
|
|
else
|
|
group.word (0x10C+0x02)++0x01
|
|
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<3.))==(1<<3.))
|
|
rgroup.word 0x10C++0x01
|
|
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x10C++0x01
|
|
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<3.))==(1<<3.))
|
|
group.word (0x10C+0x02)++0x01
|
|
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
|
|
else
|
|
group.word (0x10C+0x02)++0x01
|
|
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<3.))==(1<<3.))
|
|
group.word 0x10C++0x01
|
|
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
|
|
else
|
|
group.word 0x10C++0x01
|
|
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<3.))==(1<<3.))
|
|
rgroup.word (0x10C+0x02)++0x01
|
|
line.word 0x00 "CAP3_H,SCT Capture Register 3 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x10C+0x02)++0x01
|
|
line.word 0x00 "MATCH3_H,SCT Match Register 3 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<3.))==(1<<3.))
|
|
rgroup.word 0x10C++0x01
|
|
line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x10C++0x01
|
|
line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<3.))==(1<<3.))
|
|
rgroup.word (0x10C+0x02)++0x01
|
|
line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x10C+0x02)++0x01
|
|
line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "FRACMAT3_L,SCT Fractional Match Register 3"
|
|
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x14C++0x03
|
|
line.word 0x00 "FRACMAT3_L,SCT Fractional Match Register 3"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT3_H,SCT Fractional Match Register 3"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x10C+0x100)++0x03
|
|
line.long 0x00 "MATCHREL3/CAPCTRL3,SCT Match/capture Reload Register 3"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x10C+0x100)++0x03
|
|
line.word 0x00 "MATCHREL3_L/CAPCTRL3_L,SCT Match/capture Reload Register 3"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL3_H/CAPCTRL3_H,SCT Match/capture Reload Register 3"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x14C+0x100)++0x03
|
|
line.long 0x00 "FRACMATREL3_L,SCT Fractional Match Reload Register 3"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word (0x14C+0x100)++0x03
|
|
line.word 0x00 "FRACMATREL3_L,SCT Fractional Match Reload Register 3"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL3_H,SCT Fractional Match Reload Register 3"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long (0x118+0x200)++0x03
|
|
line.long 0x00 "EV3_STATE,SCT Event State Mask 3"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x118+0x204)++0x03
|
|
line.long 0x00 "EVCTRL3,SCT Event Control Register 3"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x118+0x204)++0x03
|
|
line.long 0x00 "EVCTRL3,SCT Event Control Register 3"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x118+0x400)++0x07
|
|
line.long 0x00 "OUT3_SET,SCT Output Set Register 3"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 3" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 3" "Not set,Set"
|
|
line.long 0x04 "OUT3_CLR,SCT Output Clear Register 3"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 3" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 3" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x118+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET3,SCT Output Set Register 3"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 3" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 3" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 3" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 3" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL3,SCT Output Clear Register 3"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 3" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 3" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 3" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 3" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 4 (Regmode4 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<4.))==(1<<4.))
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT Capture Register 4"
|
|
else
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT Match Register 4"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<4.))==(1<<4.))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT Capture Register 4"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT Match Register 4"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<4.))==(1<<4.))
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<4.))==(1<<4.))
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
|
|
else
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<4.))==(1<<4.))
|
|
rgroup.word 0x110++0x01
|
|
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x110++0x01
|
|
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<4.))==(1<<4.))
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
|
|
else
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<4.))==(1<<4.))
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<4.))==(1<<4.))
|
|
rgroup.word (0x110+0x02)++0x01
|
|
line.word 0x00 "CAP4_H,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x110+0x02)++0x01
|
|
line.word 0x00 "MATCH4_H,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<4.))==(1<<4.))
|
|
rgroup.word 0x110++0x01
|
|
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x110++0x01
|
|
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<4.))==(1<<4.))
|
|
rgroup.word (0x110+0x02)++0x01
|
|
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x110+0x02)++0x01
|
|
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "FRACMAT4_L,SCT Fractional Match Register 4"
|
|
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH4_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x150++0x03
|
|
line.word 0x00 "FRACMAT4_L,SCT Fractional Match Register 4"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH4_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT4_H,SCT Fractional Match Register 4"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH4_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x110+0x100)++0x03
|
|
line.long 0x00 "MATCHREL4/CAPCTRL4,SCT Match/capture Reload Register 4"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x110+0x100)++0x03
|
|
line.word 0x00 "MATCHREL4_L/CAPCTRL4_L,SCT Match/capture Reload Register 4"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL4_H/CAPCTRL4_H,SCT Match/capture Reload Register 4"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x150+0x100)++0x03
|
|
line.long 0x00 "FRACMATREL4_L,SCT Fractional Match Reload Register 4"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH4_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word (0x150+0x100)++0x03
|
|
line.word 0x00 "FRACMATREL4_L,SCT Fractional Match Reload Register 4"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH4_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL4_H,SCT Fractional Match Reload Register 4"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH4_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x200)++0x03
|
|
line.long 0x00 "EV4_STATE,SCT Event State Mask 4"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x120+0x204)++0x03
|
|
line.long 0x00 "EVCTRL4,SCT Event Control Register 4"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x120+0x204)++0x03
|
|
line.long 0x00 "EVCTRL4,SCT Event Control Register 4"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x120+0x400)++0x07
|
|
line.long 0x00 "OUT4_SET,SCT Output Set Register 4"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 4" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 4" "Not set,Set"
|
|
line.long 0x04 "OUT4_CLR,SCT Output Clear Register 4"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 4" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 4" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x120+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET4,SCT Output Set Register 4"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 4" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 4" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 4" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 4" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 4" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 4" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL4,SCT Output Clear Register 4"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 4" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 4" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 4" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 4" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 4" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 4" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 5 (Regmode5 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<5.))==(1<<5.))
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "CAP5,SCT Capture Register 5"
|
|
else
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "MATCH5,SCT Match Register 5"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<5.))==(1<<5.))
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CAP5,SCT Capture Register 5"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MATCH5,SCT Match Register 5"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<5.))==(1<<5.))
|
|
group.word 0x114++0x01
|
|
line.word 0x00 "CAP5_L,SCT Capture Register 5 Low Counter 16-bit"
|
|
else
|
|
group.word 0x114++0x01
|
|
line.word 0x00 "MATCH5_L,SCT Match Register 5 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<5.))==(1<<5.))
|
|
group.word (0x114+0x02)++0x01
|
|
line.word 0x00 "CAP5_H,SCT Capture Register 5 High Counter 16-bit"
|
|
else
|
|
group.word (0x114+0x02)++0x01
|
|
line.word 0x00 "MATCH5_H,SCT Match Register 5 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<5.))==(1<<5.))
|
|
rgroup.word 0x114++0x01
|
|
line.word 0x00 "CAP5_L,SCT Capture Register 5 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x114++0x01
|
|
line.word 0x00 "MATCH5_L,SCT Match Register 5 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<5.))==(1<<5.))
|
|
group.word (0x114+0x02)++0x01
|
|
line.word 0x00 "CAP5_H,SCT Capture Register 5 High Counter 16-bit"
|
|
else
|
|
group.word (0x114+0x02)++0x01
|
|
line.word 0x00 "MATCH5_H,SCT Match Register 5 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<5.))==(1<<5.))
|
|
group.word 0x114++0x01
|
|
line.word 0x00 "CAP5_L,SCT Capture Register 5 Low Counter 16-bit"
|
|
else
|
|
group.word 0x114++0x01
|
|
line.word 0x00 "MATCH5_L,SCT Match Register 5 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<5.))==(1<<5.))
|
|
rgroup.word (0x114+0x02)++0x01
|
|
line.word 0x00 "CAP5_H,SCT Capture Register 5 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x114+0x02)++0x01
|
|
line.word 0x00 "MATCH5_H,SCT Match Register 5 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<5.))==(1<<5.))
|
|
rgroup.word 0x114++0x01
|
|
line.word 0x00 "CAP5_L,SCT Capture Register 5 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x114++0x01
|
|
line.word 0x00 "MATCH5_L,SCT Match Register 5 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<5.))==(1<<5.))
|
|
rgroup.word (0x114+0x02)++0x01
|
|
line.word 0x00 "CAP5_H,SCT Capture Register 5 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x114+0x02)++0x01
|
|
line.word 0x00 "MATCH5_H,SCT Match Register 5 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "FRACMAT5_L,SCT Fractional Match Register 5"
|
|
bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH5_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x154++0x03
|
|
line.word 0x00 "FRACMAT5_L,SCT Fractional Match Register 5"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH5_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT5_H,SCT Fractional Match Register 5"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH5_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x114+0x100)++0x03
|
|
line.long 0x00 "MATCHREL5/CAPCTRL5,SCT Match/capture Reload Register 5"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x114+0x100)++0x03
|
|
line.word 0x00 "MATCHREL5_L/CAPCTRL5_L,SCT Match/capture Reload Register 5"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL5_H/CAPCTRL5_H,SCT Match/capture Reload Register 5"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x154+0x100)++0x03
|
|
line.long 0x00 "FRACMATREL5_L,SCT Fractional Match Reload Register 5"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH5_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word (0x154+0x100)++0x03
|
|
line.word 0x00 "FRACMATREL5_L,SCT Fractional Match Reload Register 5"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH5_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL5_H,SCT Fractional Match Reload Register 5"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH5_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long (0x128+0x200)++0x03
|
|
line.long 0x00 "EV5_STATE,SCT Event State Mask 5"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x128+0x204)++0x03
|
|
line.long 0x00 "EVCTRL5,SCT Event Control Register 5"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x128+0x204)++0x03
|
|
line.long 0x00 "EVCTRL5,SCT Event Control Register 5"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x128+0x400)++0x07
|
|
line.long 0x00 "OUT5_SET,SCT Output Set Register 5"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 5" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 5" "Not set,Set"
|
|
line.long 0x04 "OUT5_CLR,SCT Output Clear Register 5"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 5" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 5" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x128+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET5,SCT Output Set Register 5"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 5" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 5" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 5" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 5" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 5" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 5" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL5,SCT Output Clear Register 5"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 5" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 5" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 5" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 5" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 5" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 5" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 6 (Regmode6 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<6.))==(1<<6.))
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "CAP6,SCT Capture Register 6"
|
|
else
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "MATCH6,SCT Match Register 6"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<6.))==(1<<6.))
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CAP6,SCT Capture Register 6"
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MATCH6,SCT Match Register 6"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<6.))==(1<<6.))
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "CAP6_L,SCT Capture Register 6 Low Counter 16-bit"
|
|
else
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "MATCH6_L,SCT Match Register 6 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<6.))==(1<<6.))
|
|
group.word (0x118+0x02)++0x01
|
|
line.word 0x00 "CAP6_H,SCT Capture Register 6 High Counter 16-bit"
|
|
else
|
|
group.word (0x118+0x02)++0x01
|
|
line.word 0x00 "MATCH6_H,SCT Match Register 6 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<6.))==(1<<6.))
|
|
rgroup.word 0x118++0x01
|
|
line.word 0x00 "CAP6_L,SCT Capture Register 6 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x118++0x01
|
|
line.word 0x00 "MATCH6_L,SCT Match Register 6 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<6.))==(1<<6.))
|
|
group.word (0x118+0x02)++0x01
|
|
line.word 0x00 "CAP6_H,SCT Capture Register 6 High Counter 16-bit"
|
|
else
|
|
group.word (0x118+0x02)++0x01
|
|
line.word 0x00 "MATCH6_H,SCT Match Register 6 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<6.))==(1<<6.))
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "CAP6_L,SCT Capture Register 6 Low Counter 16-bit"
|
|
else
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "MATCH6_L,SCT Match Register 6 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<6.))==(1<<6.))
|
|
rgroup.word (0x118+0x02)++0x01
|
|
line.word 0x00 "CAP6_H,SCT Capture Register 6 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x118+0x02)++0x01
|
|
line.word 0x00 "MATCH6_H,SCT Match Register 6 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<6.))==(1<<6.))
|
|
rgroup.word 0x118++0x01
|
|
line.word 0x00 "CAP6_L,SCT Capture Register 6 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x118++0x01
|
|
line.word 0x00 "MATCH6_L,SCT Match Register 6 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<6.))==(1<<6.))
|
|
rgroup.word (0x118+0x02)++0x01
|
|
line.word 0x00 "CAP6_H,SCT Capture Register 6 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x118+0x02)++0x01
|
|
line.word 0x00 "MATCH6_H,SCT Match Register 6 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x118+0x100)++0x03
|
|
line.long 0x00 "MATCHREL6/CAPCTRL6,SCT Match/capture Reload Register 6"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x118+0x100)++0x03
|
|
line.word 0x00 "MATCHREL6_L/CAPCTRL6_L,SCT Match/capture Reload Register 6"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL6_H/CAPCTRL6_H,SCT Match/capture Reload Register 6"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x130+0x200)++0x03
|
|
line.long 0x00 "EV6_STATE,SCT Event State Mask 6"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x130+0x204)++0x03
|
|
line.long 0x00 "EVCTRL6,SCT Event Control Register 6"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x130+0x204)++0x03
|
|
line.long 0x00 "EVCTRL6,SCT Event Control Register 6"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x130+0x400)++0x07
|
|
line.long 0x00 "OUT6_SET,SCT Output Set Register 6"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 6" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 6" "Not set,Set"
|
|
line.long 0x04 "OUT6_CLR,SCT Output Clear Register 6"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 6" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 6" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x130+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET6,SCT Output Set Register 6"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 6" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 6" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 6" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 6" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 6" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 6" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL6,SCT Output Clear Register 6"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 6" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 6" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 6" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 6" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 6" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 6" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 7 (Regmode7 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<7.))==(1<<7.))
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "CAP7,SCT Capture Register 7"
|
|
else
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "MATCH7,SCT Match Register 7"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<7.))==(1<<7.))
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CAP7,SCT Capture Register 7"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MATCH7,SCT Match Register 7"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<7.))==(1<<7.))
|
|
group.word 0x11C++0x01
|
|
line.word 0x00 "CAP7_L,SCT Capture Register 7 Low Counter 16-bit"
|
|
else
|
|
group.word 0x11C++0x01
|
|
line.word 0x00 "MATCH7_L,SCT Match Register 7 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<7.))==(1<<7.))
|
|
group.word (0x11C+0x02)++0x01
|
|
line.word 0x00 "CAP7_H,SCT Capture Register 7 High Counter 16-bit"
|
|
else
|
|
group.word (0x11C+0x02)++0x01
|
|
line.word 0x00 "MATCH7_H,SCT Match Register 7 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<7.))==(1<<7.))
|
|
rgroup.word 0x11C++0x01
|
|
line.word 0x00 "CAP7_L,SCT Capture Register 7 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x11C++0x01
|
|
line.word 0x00 "MATCH7_L,SCT Match Register 7 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<7.))==(1<<7.))
|
|
group.word (0x11C+0x02)++0x01
|
|
line.word 0x00 "CAP7_H,SCT Capture Register 7 High Counter 16-bit"
|
|
else
|
|
group.word (0x11C+0x02)++0x01
|
|
line.word 0x00 "MATCH7_H,SCT Match Register 7 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<7.))==(1<<7.))
|
|
group.word 0x11C++0x01
|
|
line.word 0x00 "CAP7_L,SCT Capture Register 7 Low Counter 16-bit"
|
|
else
|
|
group.word 0x11C++0x01
|
|
line.word 0x00 "MATCH7_L,SCT Match Register 7 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<7.))==(1<<7.))
|
|
rgroup.word (0x11C+0x02)++0x01
|
|
line.word 0x00 "CAP7_H,SCT Capture Register 7 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x11C+0x02)++0x01
|
|
line.word 0x00 "MATCH7_H,SCT Match Register 7 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<7.))==(1<<7.))
|
|
rgroup.word 0x11C++0x01
|
|
line.word 0x00 "CAP7_L,SCT Capture Register 7 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x11C++0x01
|
|
line.word 0x00 "MATCH7_L,SCT Match Register 7 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<7.))==(1<<7.))
|
|
rgroup.word (0x11C+0x02)++0x01
|
|
line.word 0x00 "CAP7_H,SCT Capture Register 7 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x11C+0x02)++0x01
|
|
line.word 0x00 "MATCH7_H,SCT Match Register 7 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x11C+0x100)++0x03
|
|
line.long 0x00 "MATCHREL7/CAPCTRL7,SCT Match/capture Reload Register 7"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x11C+0x100)++0x03
|
|
line.word 0x00 "MATCHREL7_L/CAPCTRL7_L,SCT Match/capture Reload Register 7"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL7_H/CAPCTRL7_H,SCT Match/capture Reload Register 7"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x138+0x200)++0x03
|
|
line.long 0x00 "EV7_STATE,SCT Event State Mask 7"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x138+0x204)++0x03
|
|
line.long 0x00 "EVCTRL7,SCT Event Control Register 7"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x138+0x204)++0x03
|
|
line.long 0x00 "EVCTRL7,SCT Event Control Register 7"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x138+0x400)++0x07
|
|
line.long 0x00 "OUT7_SET,SCT Output Set Register 7"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 7" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 7" "Not set,Set"
|
|
line.long 0x04 "OUT7_CLR,SCT Output Clear Register 7"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 7" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 7" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x138+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET7,SCT Output Set Register 7"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 7" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 7" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 7" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 7" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 7" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 7" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL7,SCT Output Clear Register 7"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 7" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 7" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 7" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 7" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 7" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 7" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 8 (Regmode8 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<8.))==(1<<8.))
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CAP8,SCT Capture Register 8"
|
|
else
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "MATCH8,SCT Match Register 8"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<8.))==(1<<8.))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CAP8,SCT Capture Register 8"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MATCH8,SCT Match Register 8"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<8.))==(1<<8.))
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "CAP8_L,SCT Capture Register 8 Low Counter 16-bit"
|
|
else
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "MATCH8_L,SCT Match Register 8 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<8.))==(1<<8.))
|
|
group.word (0x120+0x02)++0x01
|
|
line.word 0x00 "CAP8_H,SCT Capture Register 8 High Counter 16-bit"
|
|
else
|
|
group.word (0x120+0x02)++0x01
|
|
line.word 0x00 "MATCH8_H,SCT Match Register 8 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<8.))==(1<<8.))
|
|
rgroup.word 0x120++0x01
|
|
line.word 0x00 "CAP8_L,SCT Capture Register 8 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x120++0x01
|
|
line.word 0x00 "MATCH8_L,SCT Match Register 8 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<8.))==(1<<8.))
|
|
group.word (0x120+0x02)++0x01
|
|
line.word 0x00 "CAP8_H,SCT Capture Register 8 High Counter 16-bit"
|
|
else
|
|
group.word (0x120+0x02)++0x01
|
|
line.word 0x00 "MATCH8_H,SCT Match Register 8 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<8.))==(1<<8.))
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "CAP8_L,SCT Capture Register 8 Low Counter 16-bit"
|
|
else
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "MATCH8_L,SCT Match Register 8 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<8.))==(1<<8.))
|
|
rgroup.word (0x120+0x02)++0x01
|
|
line.word 0x00 "CAP8_H,SCT Capture Register 8 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x120+0x02)++0x01
|
|
line.word 0x00 "MATCH8_H,SCT Match Register 8 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<8.))==(1<<8.))
|
|
rgroup.word 0x120++0x01
|
|
line.word 0x00 "CAP8_L,SCT Capture Register 8 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x120++0x01
|
|
line.word 0x00 "MATCH8_L,SCT Match Register 8 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<8.))==(1<<8.))
|
|
rgroup.word (0x120+0x02)++0x01
|
|
line.word 0x00 "CAP8_H,SCT Capture Register 8 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x120+0x02)++0x01
|
|
line.word 0x00 "MATCH8_H,SCT Match Register 8 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x120+0x100)++0x03
|
|
line.long 0x00 "MATCHREL8/CAPCTRL8,SCT Match/capture Reload Register 8"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x120+0x100)++0x03
|
|
line.word 0x00 "MATCHREL8_L/CAPCTRL8_L,SCT Match/capture Reload Register 8"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL8_H/CAPCTRL8_H,SCT Match/capture Reload Register 8"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x140+0x200)++0x03
|
|
line.long 0x00 "EV8_STATE,SCT Event State Mask 8"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x140+0x204)++0x03
|
|
line.long 0x00 "EVCTRL8,SCT Event Control Register 8"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x140+0x204)++0x03
|
|
line.long 0x00 "EVCTRL8,SCT Event Control Register 8"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x140+0x400)++0x07
|
|
line.long 0x00 "OUT8_SET,SCT Output Set Register 8"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 8" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 8" "Not set,Set"
|
|
line.long 0x04 "OUT8_CLR,SCT Output Clear Register 8"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 8" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 8" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x140+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET8,SCT Output Set Register 8"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 8" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 8" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 8" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 8" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 8" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 8" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL8,SCT Output Clear Register 8"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 8" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 8" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 8" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 8" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 8" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 8" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 9 (Regmode9 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<9.))==(1<<9.))
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "CAP9,SCT Capture Register 9"
|
|
else
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MATCH9,SCT Match Register 9"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<9.))==(1<<9.))
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CAP9,SCT Capture Register 9"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MATCH9,SCT Match Register 9"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<9.))==(1<<9.))
|
|
group.word 0x124++0x01
|
|
line.word 0x00 "CAP9_L,SCT Capture Register 9 Low Counter 16-bit"
|
|
else
|
|
group.word 0x124++0x01
|
|
line.word 0x00 "MATCH9_L,SCT Match Register 9 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<9.))==(1<<9.))
|
|
group.word (0x124+0x02)++0x01
|
|
line.word 0x00 "CAP9_H,SCT Capture Register 9 High Counter 16-bit"
|
|
else
|
|
group.word (0x124+0x02)++0x01
|
|
line.word 0x00 "MATCH9_H,SCT Match Register 9 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<9.))==(1<<9.))
|
|
rgroup.word 0x124++0x01
|
|
line.word 0x00 "CAP9_L,SCT Capture Register 9 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x124++0x01
|
|
line.word 0x00 "MATCH9_L,SCT Match Register 9 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<9.))==(1<<9.))
|
|
group.word (0x124+0x02)++0x01
|
|
line.word 0x00 "CAP9_H,SCT Capture Register 9 High Counter 16-bit"
|
|
else
|
|
group.word (0x124+0x02)++0x01
|
|
line.word 0x00 "MATCH9_H,SCT Match Register 9 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<9.))==(1<<9.))
|
|
group.word 0x124++0x01
|
|
line.word 0x00 "CAP9_L,SCT Capture Register 9 Low Counter 16-bit"
|
|
else
|
|
group.word 0x124++0x01
|
|
line.word 0x00 "MATCH9_L,SCT Match Register 9 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<9.))==(1<<9.))
|
|
rgroup.word (0x124+0x02)++0x01
|
|
line.word 0x00 "CAP9_H,SCT Capture Register 9 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x124+0x02)++0x01
|
|
line.word 0x00 "MATCH9_H,SCT Match Register 9 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<9.))==(1<<9.))
|
|
rgroup.word 0x124++0x01
|
|
line.word 0x00 "CAP9_L,SCT Capture Register 9 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x124++0x01
|
|
line.word 0x00 "MATCH9_L,SCT Match Register 9 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<9.))==(1<<9.))
|
|
rgroup.word (0x124+0x02)++0x01
|
|
line.word 0x00 "CAP9_H,SCT Capture Register 9 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x124+0x02)++0x01
|
|
line.word 0x00 "MATCH9_H,SCT Match Register 9 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x124+0x100)++0x03
|
|
line.long 0x00 "MATCHREL9/CAPCTRL9,SCT Match/capture Reload Register 9"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x124+0x100)++0x03
|
|
line.word 0x00 "MATCHREL9_L/CAPCTRL9_L,SCT Match/capture Reload Register 9"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL9_H/CAPCTRL9_H,SCT Match/capture Reload Register 9"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x148+0x200)++0x03
|
|
line.long 0x00 "EV9_STATE,SCT Event State Mask 9"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x148+0x204)++0x03
|
|
line.long 0x00 "EVCTRL9,SCT Event Control Register 9"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x148+0x204)++0x03
|
|
line.long 0x00 "EVCTRL9,SCT Event Control Register 9"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x148+0x400)++0x07
|
|
line.long 0x00 "OUT9_SET,SCT Output Set Register 9"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 9" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 9" "Not set,Set"
|
|
line.long 0x04 "OUT9_CLR,SCT Output Clear Register 9"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 9" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 9" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x148+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET9,SCT Output Set Register 9"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 9" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 9" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 9" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 9" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 9" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 9" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL9,SCT Output Clear Register 9"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 9" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 9" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 9" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 9" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 9" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 9" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 10 (Regmode10 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<10.))==(1<<10.))
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "CAP10,SCT Capture Register 10"
|
|
else
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "MATCH10,SCT Match Register 10"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<10.))==(1<<10.))
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CAP10,SCT Capture Register 10"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MATCH10,SCT Match Register 10"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<10.))==(1<<10.))
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "CAP10_L,SCT Capture Register 10 Low Counter 16-bit"
|
|
else
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "MATCH10_L,SCT Match Register 10 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<10.))==(1<<10.))
|
|
group.word (0x128+0x02)++0x01
|
|
line.word 0x00 "CAP10_H,SCT Capture Register 10 High Counter 16-bit"
|
|
else
|
|
group.word (0x128+0x02)++0x01
|
|
line.word 0x00 "MATCH10_H,SCT Match Register 10 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<10.))==(1<<10.))
|
|
rgroup.word 0x128++0x01
|
|
line.word 0x00 "CAP10_L,SCT Capture Register 10 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x128++0x01
|
|
line.word 0x00 "MATCH10_L,SCT Match Register 10 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<10.))==(1<<10.))
|
|
group.word (0x128+0x02)++0x01
|
|
line.word 0x00 "CAP10_H,SCT Capture Register 10 High Counter 16-bit"
|
|
else
|
|
group.word (0x128+0x02)++0x01
|
|
line.word 0x00 "MATCH10_H,SCT Match Register 10 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<10.))==(1<<10.))
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "CAP10_L,SCT Capture Register 10 Low Counter 16-bit"
|
|
else
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "MATCH10_L,SCT Match Register 10 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<10.))==(1<<10.))
|
|
rgroup.word (0x128+0x02)++0x01
|
|
line.word 0x00 "CAP10_H,SCT Capture Register 10 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x128+0x02)++0x01
|
|
line.word 0x00 "MATCH10_H,SCT Match Register 10 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<10.))==(1<<10.))
|
|
rgroup.word 0x128++0x01
|
|
line.word 0x00 "CAP10_L,SCT Capture Register 10 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x128++0x01
|
|
line.word 0x00 "MATCH10_L,SCT Match Register 10 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<10.))==(1<<10.))
|
|
rgroup.word (0x128+0x02)++0x01
|
|
line.word 0x00 "CAP10_H,SCT Capture Register 10 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x128+0x02)++0x01
|
|
line.word 0x00 "MATCH10_H,SCT Match Register 10 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x128+0x100)++0x03
|
|
line.long 0x00 "MATCHREL10/CAPCTRL10,SCT Match/capture Reload Register 10"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x128+0x100)++0x03
|
|
line.word 0x00 "MATCHREL10_L/CAPCTRL10_L,SCT Match/capture Reload Register 10"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL10_H/CAPCTRL10_H,SCT Match/capture Reload Register 10"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x150+0x200)++0x03
|
|
line.long 0x00 "EV10_STATE,SCT Event State Mask 10"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x150+0x204)++0x03
|
|
line.long 0x00 "EVCTRL10,SCT Event Control Register 10"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x150+0x204)++0x03
|
|
line.long 0x00 "EVCTRL10,SCT Event Control Register 10"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x150+0x400)++0x07
|
|
line.long 0x00 "OUT10_SET,SCT Output Set Register 10"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 10" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 10" "Not set,Set"
|
|
line.long 0x04 "OUT10_CLR,SCT Output Clear Register 10"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 10" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 10" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x150+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET10,SCT Output Set Register 10"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 10" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 10" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 10" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 10" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 10" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 10" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL10,SCT Output Clear Register 10"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 10" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 10" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 10" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 10" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 10" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 10" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 11 (Regmode11 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<11.))==(1<<11.))
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "CAP11,SCT Capture Register 11"
|
|
else
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "MATCH11,SCT Match Register 11"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<11.))==(1<<11.))
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CAP11,SCT Capture Register 11"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MATCH11,SCT Match Register 11"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<11.))==(1<<11.))
|
|
group.word 0x12C++0x01
|
|
line.word 0x00 "CAP11_L,SCT Capture Register 11 Low Counter 16-bit"
|
|
else
|
|
group.word 0x12C++0x01
|
|
line.word 0x00 "MATCH11_L,SCT Match Register 11 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<11.))==(1<<11.))
|
|
group.word (0x12C+0x02)++0x01
|
|
line.word 0x00 "CAP11_H,SCT Capture Register 11 High Counter 16-bit"
|
|
else
|
|
group.word (0x12C+0x02)++0x01
|
|
line.word 0x00 "MATCH11_H,SCT Match Register 11 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<11.))==(1<<11.))
|
|
rgroup.word 0x12C++0x01
|
|
line.word 0x00 "CAP11_L,SCT Capture Register 11 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x12C++0x01
|
|
line.word 0x00 "MATCH11_L,SCT Match Register 11 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<11.))==(1<<11.))
|
|
group.word (0x12C+0x02)++0x01
|
|
line.word 0x00 "CAP11_H,SCT Capture Register 11 High Counter 16-bit"
|
|
else
|
|
group.word (0x12C+0x02)++0x01
|
|
line.word 0x00 "MATCH11_H,SCT Match Register 11 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<11.))==(1<<11.))
|
|
group.word 0x12C++0x01
|
|
line.word 0x00 "CAP11_L,SCT Capture Register 11 Low Counter 16-bit"
|
|
else
|
|
group.word 0x12C++0x01
|
|
line.word 0x00 "MATCH11_L,SCT Match Register 11 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<11.))==(1<<11.))
|
|
rgroup.word (0x12C+0x02)++0x01
|
|
line.word 0x00 "CAP11_H,SCT Capture Register 11 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x12C+0x02)++0x01
|
|
line.word 0x00 "MATCH11_H,SCT Match Register 11 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<11.))==(1<<11.))
|
|
rgroup.word 0x12C++0x01
|
|
line.word 0x00 "CAP11_L,SCT Capture Register 11 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x12C++0x01
|
|
line.word 0x00 "MATCH11_L,SCT Match Register 11 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<11.))==(1<<11.))
|
|
rgroup.word (0x12C+0x02)++0x01
|
|
line.word 0x00 "CAP11_H,SCT Capture Register 11 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x12C+0x02)++0x01
|
|
line.word 0x00 "MATCH11_H,SCT Match Register 11 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x12C+0x100)++0x03
|
|
line.long 0x00 "MATCHREL11/CAPCTRL11,SCT Match/capture Reload Register 11"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x12C+0x100)++0x03
|
|
line.word 0x00 "MATCHREL11_L/CAPCTRL11_L,SCT Match/capture Reload Register 11"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL11_H/CAPCTRL11_H,SCT Match/capture Reload Register 11"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x158+0x200)++0x03
|
|
line.long 0x00 "EV11_STATE,SCT Event State Mask 11"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x158+0x204)++0x03
|
|
line.long 0x00 "EVCTRL11,SCT Event Control Register 11"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x158+0x204)++0x03
|
|
line.long 0x00 "EVCTRL11,SCT Event Control Register 11"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x158+0x400)++0x07
|
|
line.long 0x00 "OUT11_SET,SCT Output Set Register 11"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 11" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 11" "Not set,Set"
|
|
line.long 0x04 "OUT11_CLR,SCT Output Clear Register 11"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 11" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 11" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x158+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET11,SCT Output Set Register 11"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 11" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 11" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 11" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 11" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 11" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 11" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL11,SCT Output Clear Register 11"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 11" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 11" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 11" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 11" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 11" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 11" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 12 (Regmode12 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<12.))==(1<<12.))
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "CAP12,SCT Capture Register 12"
|
|
else
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "MATCH12,SCT Match Register 12"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<12.))==(1<<12.))
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CAP12,SCT Capture Register 12"
|
|
else
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MATCH12,SCT Match Register 12"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<12.))==(1<<12.))
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "CAP12_L,SCT Capture Register 12 Low Counter 16-bit"
|
|
else
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "MATCH12_L,SCT Match Register 12 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<12.))==(1<<12.))
|
|
group.word (0x130+0x02)++0x01
|
|
line.word 0x00 "CAP12_H,SCT Capture Register 12 High Counter 16-bit"
|
|
else
|
|
group.word (0x130+0x02)++0x01
|
|
line.word 0x00 "MATCH12_H,SCT Match Register 12 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<12.))==(1<<12.))
|
|
rgroup.word 0x130++0x01
|
|
line.word 0x00 "CAP12_L,SCT Capture Register 12 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x130++0x01
|
|
line.word 0x00 "MATCH12_L,SCT Match Register 12 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<12.))==(1<<12.))
|
|
group.word (0x130+0x02)++0x01
|
|
line.word 0x00 "CAP12_H,SCT Capture Register 12 High Counter 16-bit"
|
|
else
|
|
group.word (0x130+0x02)++0x01
|
|
line.word 0x00 "MATCH12_H,SCT Match Register 12 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<12.))==(1<<12.))
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "CAP12_L,SCT Capture Register 12 Low Counter 16-bit"
|
|
else
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "MATCH12_L,SCT Match Register 12 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<12.))==(1<<12.))
|
|
rgroup.word (0x130+0x02)++0x01
|
|
line.word 0x00 "CAP12_H,SCT Capture Register 12 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x130+0x02)++0x01
|
|
line.word 0x00 "MATCH12_H,SCT Match Register 12 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<12.))==(1<<12.))
|
|
rgroup.word 0x130++0x01
|
|
line.word 0x00 "CAP12_L,SCT Capture Register 12 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x130++0x01
|
|
line.word 0x00 "MATCH12_L,SCT Match Register 12 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<12.))==(1<<12.))
|
|
rgroup.word (0x130+0x02)++0x01
|
|
line.word 0x00 "CAP12_H,SCT Capture Register 12 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x130+0x02)++0x01
|
|
line.word 0x00 "MATCH12_H,SCT Match Register 12 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x130+0x100)++0x03
|
|
line.long 0x00 "MATCHREL12/CAPCTRL12,SCT Match/capture Reload Register 12"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x130+0x100)++0x03
|
|
line.word 0x00 "MATCHREL12_L/CAPCTRL12_L,SCT Match/capture Reload Register 12"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL12_H/CAPCTRL12_H,SCT Match/capture Reload Register 12"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x160+0x200)++0x03
|
|
line.long 0x00 "EV12_STATE,SCT Event State Mask 12"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x160+0x204)++0x03
|
|
line.long 0x00 "EVCTRL12,SCT Event Control Register 12"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x160+0x204)++0x03
|
|
line.long 0x00 "EVCTRL12,SCT Event Control Register 12"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x160+0x400)++0x07
|
|
line.long 0x00 "OUT12_SET,SCT Output Set Register 12"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 12" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 12" "Not set,Set"
|
|
line.long 0x04 "OUT12_CLR,SCT Output Clear Register 12"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 12" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 12" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x160+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET12,SCT Output Set Register 12"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 12" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 12" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 12" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 12" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 12" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 12" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL12,SCT Output Clear Register 12"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 12" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 12" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 12" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 12" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 12" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 12" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 13 (Regmode13 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<13.))==(1<<13.))
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "CAP13,SCT Capture Register 13"
|
|
else
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "MATCH13,SCT Match Register 13"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<13.))==(1<<13.))
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CAP13,SCT Capture Register 13"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MATCH13,SCT Match Register 13"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<13.))==(1<<13.))
|
|
group.word 0x134++0x01
|
|
line.word 0x00 "CAP13_L,SCT Capture Register 13 Low Counter 16-bit"
|
|
else
|
|
group.word 0x134++0x01
|
|
line.word 0x00 "MATCH13_L,SCT Match Register 13 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<13.))==(1<<13.))
|
|
group.word (0x134+0x02)++0x01
|
|
line.word 0x00 "CAP13_H,SCT Capture Register 13 High Counter 16-bit"
|
|
else
|
|
group.word (0x134+0x02)++0x01
|
|
line.word 0x00 "MATCH13_H,SCT Match Register 13 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<13.))==(1<<13.))
|
|
rgroup.word 0x134++0x01
|
|
line.word 0x00 "CAP13_L,SCT Capture Register 13 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x134++0x01
|
|
line.word 0x00 "MATCH13_L,SCT Match Register 13 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<13.))==(1<<13.))
|
|
group.word (0x134+0x02)++0x01
|
|
line.word 0x00 "CAP13_H,SCT Capture Register 13 High Counter 16-bit"
|
|
else
|
|
group.word (0x134+0x02)++0x01
|
|
line.word 0x00 "MATCH13_H,SCT Match Register 13 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<13.))==(1<<13.))
|
|
group.word 0x134++0x01
|
|
line.word 0x00 "CAP13_L,SCT Capture Register 13 Low Counter 16-bit"
|
|
else
|
|
group.word 0x134++0x01
|
|
line.word 0x00 "MATCH13_L,SCT Match Register 13 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<13.))==(1<<13.))
|
|
rgroup.word (0x134+0x02)++0x01
|
|
line.word 0x00 "CAP13_H,SCT Capture Register 13 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x134+0x02)++0x01
|
|
line.word 0x00 "MATCH13_H,SCT Match Register 13 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<13.))==(1<<13.))
|
|
rgroup.word 0x134++0x01
|
|
line.word 0x00 "CAP13_L,SCT Capture Register 13 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x134++0x01
|
|
line.word 0x00 "MATCH13_L,SCT Match Register 13 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<13.))==(1<<13.))
|
|
rgroup.word (0x134+0x02)++0x01
|
|
line.word 0x00 "CAP13_H,SCT Capture Register 13 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x134+0x02)++0x01
|
|
line.word 0x00 "MATCH13_H,SCT Match Register 13 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x134+0x100)++0x03
|
|
line.long 0x00 "MATCHREL13/CAPCTRL13,SCT Match/capture Reload Register 13"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x134+0x100)++0x03
|
|
line.word 0x00 "MATCHREL13_L/CAPCTRL13_L,SCT Match/capture Reload Register 13"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL13_H/CAPCTRL13_H,SCT Match/capture Reload Register 13"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x168+0x200)++0x03
|
|
line.long 0x00 "EV13_STATE,SCT Event State Mask 13"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x168+0x204)++0x03
|
|
line.long 0x00 "EVCTRL13,SCT Event Control Register 13"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x168+0x204)++0x03
|
|
line.long 0x00 "EVCTRL13,SCT Event Control Register 13"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x168+0x400)++0x07
|
|
line.long 0x00 "OUT13_SET,SCT Output Set Register 13"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 13" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 13" "Not set,Set"
|
|
line.long 0x04 "OUT13_CLR,SCT Output Clear Register 13"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 13" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 13" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x168+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET13,SCT Output Set Register 13"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 13" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 13" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 13" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 13" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 13" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 13" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL13,SCT Output Clear Register 13"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 13" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 13" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 13" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 13" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 13" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 13" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 14 (Regmode14 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<14.))==(1<<14.))
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "CAP14,SCT Capture Register 14"
|
|
else
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "MATCH14,SCT Match Register 14"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<14.))==(1<<14.))
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CAP14,SCT Capture Register 14"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MATCH14,SCT Match Register 14"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<14.))==(1<<14.))
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "CAP14_L,SCT Capture Register 14 Low Counter 16-bit"
|
|
else
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "MATCH14_L,SCT Match Register 14 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<14.))==(1<<14.))
|
|
group.word (0x138+0x02)++0x01
|
|
line.word 0x00 "CAP14_H,SCT Capture Register 14 High Counter 16-bit"
|
|
else
|
|
group.word (0x138+0x02)++0x01
|
|
line.word 0x00 "MATCH14_H,SCT Match Register 14 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<14.))==(1<<14.))
|
|
rgroup.word 0x138++0x01
|
|
line.word 0x00 "CAP14_L,SCT Capture Register 14 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x138++0x01
|
|
line.word 0x00 "MATCH14_L,SCT Match Register 14 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<14.))==(1<<14.))
|
|
group.word (0x138+0x02)++0x01
|
|
line.word 0x00 "CAP14_H,SCT Capture Register 14 High Counter 16-bit"
|
|
else
|
|
group.word (0x138+0x02)++0x01
|
|
line.word 0x00 "MATCH14_H,SCT Match Register 14 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<14.))==(1<<14.))
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "CAP14_L,SCT Capture Register 14 Low Counter 16-bit"
|
|
else
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "MATCH14_L,SCT Match Register 14 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<14.))==(1<<14.))
|
|
rgroup.word (0x138+0x02)++0x01
|
|
line.word 0x00 "CAP14_H,SCT Capture Register 14 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x138+0x02)++0x01
|
|
line.word 0x00 "MATCH14_H,SCT Match Register 14 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<14.))==(1<<14.))
|
|
rgroup.word 0x138++0x01
|
|
line.word 0x00 "CAP14_L,SCT Capture Register 14 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x138++0x01
|
|
line.word 0x00 "MATCH14_L,SCT Match Register 14 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<14.))==(1<<14.))
|
|
rgroup.word (0x138+0x02)++0x01
|
|
line.word 0x00 "CAP14_H,SCT Capture Register 14 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x138+0x02)++0x01
|
|
line.word 0x00 "MATCH14_H,SCT Match Register 14 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x138+0x100)++0x03
|
|
line.long 0x00 "MATCHREL14/CAPCTRL14,SCT Match/capture Reload Register 14"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x138+0x100)++0x03
|
|
line.word 0x00 "MATCHREL14_L/CAPCTRL14_L,SCT Match/capture Reload Register 14"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL14_H/CAPCTRL14_H,SCT Match/capture Reload Register 14"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x170+0x200)++0x03
|
|
line.long 0x00 "EV14_STATE,SCT Event State Mask 14"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x170+0x204)++0x03
|
|
line.long 0x00 "EVCTRL14,SCT Event Control Register 14"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x170+0x204)++0x03
|
|
line.long 0x00 "EVCTRL14,SCT Event Control Register 14"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x170+0x400)++0x07
|
|
line.long 0x00 "OUT14_SET,SCT Output Set Register 14"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 14" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 14" "Not set,Set"
|
|
line.long 0x04 "OUT14_CLR,SCT Output Clear Register 14"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 14" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 14" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x170+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET14,SCT Output Set Register 14"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 14" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 14" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 14" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 14" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 14" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 14" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL14,SCT Output Clear Register 14"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 14" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 14" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 14" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 14" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 14" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 14" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
tree "Event 15 (Regmode15 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<15.))==(1<<15.))
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "CAP15,SCT Capture Register 15"
|
|
else
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "MATCH15,SCT Match Register 15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&(1<<15.))==(1<<15.))
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CAP15,SCT Capture Register 15"
|
|
else
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MATCH15,SCT Match Register 15"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<15.))==(1<<15.))
|
|
group.word 0x13C++0x01
|
|
line.word 0x00 "CAP15_L,SCT Capture Register 15 Low Counter 16-bit"
|
|
else
|
|
group.word 0x13C++0x01
|
|
line.word 0x00 "MATCH15_L,SCT Match Register 15 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<15.))==(1<<15.))
|
|
group.word (0x13C+0x02)++0x01
|
|
line.word 0x00 "CAP15_H,SCT Capture Register 15 High Counter 16-bit"
|
|
else
|
|
group.word (0x13C+0x02)++0x01
|
|
line.word 0x00 "MATCH15_H,SCT Match Register 15 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<15.))==(1<<15.))
|
|
rgroup.word 0x13C++0x01
|
|
line.word 0x00 "CAP15_L,SCT Capture Register 15 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x13C++0x01
|
|
line.word 0x00 "MATCH15_L,SCT Match Register 15 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<15.))==(1<<15.))
|
|
group.word (0x13C+0x02)++0x01
|
|
line.word 0x00 "CAP15_H,SCT Capture Register 15 High Counter 16-bit"
|
|
else
|
|
group.word (0x13C+0x02)++0x01
|
|
line.word 0x00 "MATCH15_H,SCT Match Register 15 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<15.))==(1<<15.))
|
|
group.word 0x13C++0x01
|
|
line.word 0x00 "CAP15_L,SCT Capture Register 15 Low Counter 16-bit"
|
|
else
|
|
group.word 0x13C++0x01
|
|
line.word 0x00 "MATCH15_L,SCT Match Register 15 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<15.))==(1<<15.))
|
|
rgroup.word (0x13C+0x02)++0x01
|
|
line.word 0x00 "CAP15_H,SCT Capture Register 15 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x13C+0x02)++0x01
|
|
line.word 0x00 "MATCH15_H,SCT Match Register 15 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&(1<<15.))==(1<<15.))
|
|
rgroup.word 0x13C++0x01
|
|
line.word 0x00 "CAP15_L,SCT Capture Register 15 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x13C++0x01
|
|
line.word 0x00 "MATCH15_L,SCT Match Register 15 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&(1<<15.))==(1<<15.))
|
|
rgroup.word (0x13C+0x02)++0x01
|
|
line.word 0x00 "CAP15_H,SCT Capture Register 15 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x13C+0x02)++0x01
|
|
line.word 0x00 "MATCH15_H,SCT Match Register 15 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x13C+0x100)++0x03
|
|
line.long 0x00 "MATCHREL15/CAPCTRL15,SCT Match/capture Reload Register 15"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x13C+0x100)++0x03
|
|
line.word 0x00 "MATCHREL15_L/CAPCTRL15_L,SCT Match/capture Reload Register 15"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL15_H/CAPCTRL15_H,SCT Match/capture Reload Register 15"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")
|
|
endif
|
|
group.long (0x178+0x200)++0x03
|
|
line.long 0x00 "EV15_STATE,SCT Event State Mask 15"
|
|
sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x178+0x204)++0x03
|
|
line.long 0x00 "EVCTRL15,SCT Event Control Register 15"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x178+0x204)++0x03
|
|
line.long 0x00 "EVCTRL15,SCT Event Control Register 15"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("LPC11E*")
|
|
group.long (0x178+0x400)++0x07
|
|
line.long 0x00 "OUT15_SET,SCT Output Set Register 15"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 15" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 15" "Not set,Set"
|
|
line.long 0x04 "OUT15_CLR,SCT Output Clear Register 15"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 15" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 15" "Not cleared,Cleared"
|
|
else
|
|
group.long (0x178+0x400)++0x07
|
|
line.long 0x00 "OUTPUTSET15,SCT Output Set Register 15"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 15" "Not set,Set"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,Event 14 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 to set output 15" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event 11 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,Event 8 to set output 15" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event 7 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,Event 5 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 to set output 15" "Not set,Set"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " [3] ,Event 3 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,Event 2 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 to set output 15" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 to set output 15" "Not set,Set"
|
|
line.long 0x04 "OUTPUTCL15,SCT Output Clear Register 15"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 15" "Not cleared,Cleared"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,Event 14 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 to clear output 15" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,Event 8 to clear output 15" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Event 7 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,Event 5 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 to clear output 15" "Not cleared,Cleared"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Event 3 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Event 2 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 to clear output 15" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 to clear output 15" "Not cleared,Cleared"
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")||cpuis("LPC11E*")
|
|
tree "Event 4 (Regmode4 0/1)"
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
if (((per.l(ad:0x40000000+0x04))&0x04)==0x00)
|
|
if (((per.l(ad:0x40000000+0x4C))&0x10)==0x10)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT Capture Register 4"
|
|
else
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT Match Register 4"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x4C))&0x10)==0x10)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT Capture Register 4"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT Match Register 4"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x04))&0x04)==0x04)&&(((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&0x10)==0x10)
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&0x10)==0x10)
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
|
|
else
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x06))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&0x10)==0x10)
|
|
rgroup.word 0x110++0x01
|
|
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x110++0x01
|
|
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&0x10)==0x10)
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
|
|
else
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x04))&0x04)==0x04)
|
|
if (((per.w(ad:0x40000000+0x4C))&0x10)==0x10)
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&0x10)==0x10)
|
|
rgroup.word (0x110+0x02)++0x01
|
|
line.word 0x00 "CAP4_H,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
rgroup.word (0x110+0x02)++0x01
|
|
line.word 0x00 "MATCH4_H,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40000000+0x4C))&0x10)==0x10)
|
|
rgroup.word 0x110++0x01
|
|
line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit"
|
|
else
|
|
rgroup.word 0x110++0x01
|
|
line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit"
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x4E))&0x10)==0x10)
|
|
rgroup.word (0x110+0x02)++0x01
|
|
line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit"
|
|
else
|
|
rgroup.word (0x110+0x02)++0x01
|
|
line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.long (0x210)++0x03
|
|
line.long 0x00 "MATCHREL4/CAPCTRL4,SCT Match/capture Reload Register 4"
|
|
bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
else
|
|
group.word (0x210)++0x03
|
|
line.word 0x00 "MATCHREL4_L/CAPCTRL4_L,SCT Match/capture Reload Register 4"
|
|
bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
line.word 0x02 "MATCHREL4_H/CAPCTRL4_H,SCT Match/capture Reload Register 4"
|
|
bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x320)++0x07
|
|
line.long 0x00 "EVSTATEMSK4,SCT Event State Mask 4"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
line.long 0x04 "EVCTRL4,SCT Event Control Register 4"
|
|
bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Event 5 (Regmode5 0/1)"
|
|
group.long (0x328)++0x07
|
|
line.long 0x00 "EVSTATEMSK5,SCT Event State Mask 5"
|
|
sif cpuis("LPC11E*")
|
|
bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked"
|
|
line.long 0x04 "EVCTRL5,SCT Event Control Register 5"
|
|
bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal"
|
|
newline
|
|
bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH"
|
|
newline
|
|
bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H"
|
|
bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TIMER 0/1/2/3"
|
|
tree "Timer 0"
|
|
base ad:0x40084000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "T0IR,Timer0 Interrupt Register"
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
eventfld.long 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "T0TCR,Timer0 Timer Control Register"
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
if ((per.long(ad:0x40084000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "T0CTCR,Timer0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "T0CTCR,Timer0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,CAP0.1,CAP0.2,CAP0.3"
|
|
else
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,CAP0.1,?..."
|
|
endif
|
|
endif
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T0TC,Timer0 Timer Counter Register"
|
|
line.long 0x04 "T0PR,Timer0 Prescale Register"
|
|
line.long 0x08 "T0PC,Timer0 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T0MR0,Timer0 Match Register 0"
|
|
line.long 0x04 "T0MR1,Timer0 Match Register 1"
|
|
line.long 0x08 "T0MR2,Timer0 Match Register 2"
|
|
line.long 0x0C "T0MR3,Timer0 Match Register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "T0MCR,Timer0 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "T0CR0,Timer0 Capture Register 0"
|
|
line.long 0x04 "T0CR1,Timer0 Capture Register 1"
|
|
else
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "T0CR0,Timer0 Capture Register 0"
|
|
line.long 0x04 "T0CR1,Timer0 Capture Register 1"
|
|
line.long 0x08 "T0CR2,Timer0 Capture Register 2"
|
|
line.long 0x0C "T0CR3,Timer0 Capture Register 3"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "T0CCR,Timer0 Capture Control Register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on CAP0.3 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on CAP0.3 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on CAP0.3 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on CAP0.2 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on CAP0.2 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on CAP0.2 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CAP0.1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CAP0.1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CAP0.1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CAP0.0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CAP0.0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CAP0.0 rising edge" "Disabled,Enabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "T0EMR,Timer0 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 1"
|
|
base ad:0x40085000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "T1IR,Timer1 Interrupt Register"
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
eventfld.long 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "T1TCR,Timer1 Timer Control Register"
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
if ((per.long(ad:0x40085000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "T1CTCR,Timer1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "T1CTCR,Timer1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP1.0,CAP1.1,CAP1.2,CAP1.3"
|
|
else
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP1.0,CAP1.1,?..."
|
|
endif
|
|
endif
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T1TC,Timer1 Timer Counter Register"
|
|
line.long 0x04 "T1PR,Timer1 Prescale Register"
|
|
line.long 0x08 "T1PC,Timer1 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T1MR0,Timer1 Match Register 0"
|
|
line.long 0x04 "T1MR1,Timer1 Match Register 1"
|
|
line.long 0x08 "T1MR2,Timer1 Match Register 2"
|
|
line.long 0x0C "T1MR3,Timer1 Match Register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "T1MCR,Timer1 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "T1CR0,Timer1 Capture Register 0"
|
|
line.long 0x04 "T1CR1,Timer1 Capture Register 1"
|
|
else
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "T1CR0,Timer1 Capture Register 0"
|
|
line.long 0x04 "T1CR1,Timer1 Capture Register 1"
|
|
line.long 0x08 "T1CR2,Timer1 Capture Register 2"
|
|
line.long 0x0C "T1CR3,Timer1 Capture Register 3"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "T1CCR,Timer1 Capture Control Register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on CAP1.3 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on CAP1.3 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on CAP1.3 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on CAP1.2 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on CAP1.2 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on CAP1.2 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CAP1.1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CAP1.1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CAP1.1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CAP1.0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CAP1.0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CAP1.0 rising edge" "Disabled,Enabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "T1EMR,Timer1 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 2"
|
|
base ad:0x400C3000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "T2IR,Timer2 Interrupt Register"
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
eventfld.long 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "T2TCR,Timer2 Timer Control Register"
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
if ((per.long(ad:0x400C3000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "T2CTCR,Timer2 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "T2CTCR,Timer2 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP2.0,CAP2.1,CAP2.2,CAP2.3"
|
|
else
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP2.0,CAP2.1,?..."
|
|
endif
|
|
endif
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T2TC,Timer2 Timer Counter Register"
|
|
line.long 0x04 "T2PR,Timer2 Prescale Register"
|
|
line.long 0x08 "T2PC,Timer2 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T2MR0,Timer2 Match Register 0"
|
|
line.long 0x04 "T2MR1,Timer2 Match Register 1"
|
|
line.long 0x08 "T2MR2,Timer2 Match Register 2"
|
|
line.long 0x0C "T2MR3,Timer2 Match Register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "T2MCR,Timer2 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "T2CR0,Timer2 Capture Register 0"
|
|
line.long 0x04 "T2CR1,Timer2 Capture Register 1"
|
|
else
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "T2CR0,Timer2 Capture Register 0"
|
|
line.long 0x04 "T2CR1,Timer2 Capture Register 1"
|
|
line.long 0x08 "T2CR2,Timer2 Capture Register 2"
|
|
line.long 0x0C "T2CR3,Timer2 Capture Register 3"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "T2CCR,Timer2 Capture Control Register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on CAP2.3 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on CAP2.3 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on CAP2.3 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on CAP2.2 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on CAP2.2 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on CAP2.2 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CAP2.1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CAP2.1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CAP2.1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CAP2.0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CAP2.0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CAP2.0 rising edge" "Disabled,Enabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "T2EMR,Timer2 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 3"
|
|
base ad:0x400C4000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "T3IR,Timer3 Interrupt Register"
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
eventfld.long 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "T3TCR,Timer3 Timer Control Register"
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
if ((per.long(ad:0x400C4000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "T3CTCR,Timer3 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "T3CTCR,Timer3 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP3.0,CAP3.1,CAP3.2,CAP3.3"
|
|
else
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP3.0,CAP3.1,?..."
|
|
endif
|
|
endif
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T3TC,Timer3 Timer Counter Register"
|
|
line.long 0x04 "T3PR,Timer3 Prescale Register"
|
|
line.long 0x08 "T3PC,Timer3 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T3MR0,Timer3 Match Register 0"
|
|
line.long 0x04 "T3MR1,Timer3 Match Register 1"
|
|
line.long 0x08 "T3MR2,Timer3 Match Register 2"
|
|
line.long 0x0C "T3MR3,Timer3 Match Register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "T3MCR,Timer3 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "T3CR0,Timer3 Capture Register 0"
|
|
line.long 0x04 "T3CR1,Timer3 Capture Register 1"
|
|
else
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "T3CR0,Timer3 Capture Register 0"
|
|
line.long 0x04 "T3CR1,Timer3 Capture Register 1"
|
|
line.long 0x08 "T3CR2,Timer3 Capture Register 2"
|
|
line.long 0x0C "T3CR3,Timer3 Capture Register 3"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "T3CCR,Timer3 Capture Control Register"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on CAP3.3 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on CAP3.3 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on CAP3.3 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on CAP3.2 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on CAP3.2 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on CAP3.2 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CAP3.1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CAP3.1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CAP3.1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CAP3.0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CAP3.0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CAP3.0 rising edge" "Disabled,Enabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "T3EMR,Timer3 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "MC PWM (Motor Control Pulse Width Modulator)"
|
|
base ad:0x400A0000
|
|
width 11.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MCCON,MCPWM control register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " DCMODE_set/clr ,3-phase DC mode select" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " ACMODE_set/clr ,3-phase AC mode select" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " INVBDC_set/clr ,Invert MCOB outputs for channels 0 to 2." "Not inverted,Inverted"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DISUP2_set/clr ,Enable/disable updates of functional registers, channel 2" "Updated,Not updated"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " DTE2_set/clr ,Dead-time, channel 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " POLA2_set/clr ,Selects polarity of the MCOA2 and MCOB2 pins" "Active High,Active Low"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " CENTER2_set/clr ,Edge/center aligned operation, channel 2" "Edge,Center"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " RUN2_set/clr ,Stops/starts the timer, channel 2" "Stop,Run"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " DISUP1_set/clr ,Enable/disable updates of functional registers, channel 1" "Updated,Not updated"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DTE1_set/clr ,Controls the dead-time feature for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " POLA1_set/clr ,Selects polarity of the MCOA1 and MCOB1 pins" "Active High,Active Low"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CENTER1_set/clr ,Edge/center aligned operation, channel 1" "Edge,Center"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " RUN1_set/clr ,Stops/starts the timer, channel 1" "Stop,Run"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DISUP0_set/clr ,Enable/disable updates of functional registers, channel 0" "Updated,Not updated"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DTE0_set/clr ,Controls the dead-time feature for channel 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " POLA0_set/clr ,Selects polarity of the MCOA0 and MCOB0 pins" "Active High,Active Low"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CENTER0_set/clr ,Edge/center aligned operation, channel 0" "Edge,Center"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN0_set/clr ,Stops/starts the timer, channel 0" "Stop,Run"
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "MCCAPCON,MCPWM Capture control register"
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " HNFCAP2/clr ,Hardware noise filter-channel 2" "Normal,Delayed"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " HNFCAP1/clr ,Hardware noise filter-channel 1" "Normal,Delayed"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " HNFCAP0/clr ,Hardware noise filter-channel 0" "Normal,Delayed"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " RT2_set/clr ,Reset MCTC2 register for any enabled capture event on channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " RT2_set/clr ,Reset MCTC2 register for any enabled capture event on channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " RT1_set/clr ,Reset MCTC1 register for any enabled capture event on channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " RT0_set/clr ,Reset MCTC0 register for any enabled capture event on channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " CAP2MCI2_FE_set/clr ,Enable capture event on channel 2 on the falling edge of the MCI2 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " CAP2MCI2_RE_set/clr ,Enable capture event on channel 2 on the rising edge of the MCI2 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CAP2MCI1_FE_set/clr ,Enable capture event on channel 2 on the falling edge of the MCI1 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " CAP2MCI1_RE_set/clr ,Enable capture event on channel 2 on the rising edge of the MCI1 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " CAP2MCI0_FE_set/clr ,Enable capture event on channel 2 on the falling edge of the MCI0 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CAP2MCI0_RE_set/clr ,Enable capture event on channel 2 on the rising edge of the MCI0 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " CAP1MCI2_FE_set/clr ,Enable capture event on channel 1 on the falling edge of the MCI2 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " CAP1MCI2_RE_set/clr ,Enable capture event on channel 1 on the rising edge of the MCI2 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CAP1MCI1_FE_set/clr ,Enable capture event on channel 1 on the falling edge of the MCI1 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " CAP1MCI1_RE_set/clr ,Enable capture event on channel 1 on the rising edge of the MCI1 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CAP1MCI0_FE_set/clr ,Enable capture event on channel 1 on the falling edge of the MCI0 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CAP1MCI0_RE_set/clr ,Enable capture event on channel 1 on the rising edge of the MCI0 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CAP0MCI2_FE_set/clr ,Enable capture event on channel 0 on the falling edge of the MCI2 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CAP0MCI2_RE_set/clr ,Enable capture event on channel 0 on the rising edge of the MCI2 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CAP0MCI1_FE_set/clr ,Enable capture event on channel 0 on the falling edge of the MCI1 input." "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CAP0MCI1_RE_set/clr ,Enable capture event on channel 0 on the rising edge of the MCI1 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CAP0MCI0_FE_set/clr ,Enable capture event on channel 0 on the falling edge of the MCI0 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CAP0MCI0_RE_set/clr ,Enable capture event on channel 0 on the rising edge of the MCI0 input" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "MCINTEN,MCPWM interrupt enable register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " ABORT_set/clr ,Fast abort interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICAP2_set/clr ,Capture interrupt for channels 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " IMAT2_set/clr ,Match interrupt for channels 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ILIM2_set/clr ,Limit interrupt for channels 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ICAP1_set/clr ,Capture interrupt for channels 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " IMAT1_set/clr ,Match interrupt for channels 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " ILIM1_set/clr ,Limit interrupt for channels 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ICAP0_set/clr ,Capture interrupt for channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IMAT0_set/clr ,Match interrupt for channel 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ILIM0_set/clr ,Limit interrupt for channel 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "MCINTF,MCPWM interrupt flags register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " ABORT_set/clr ,Fast abort interrupt" "Cleared,Set"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICAP2_set/clr ,Capture interrupt for channels 2" "Cleared,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " IMAT2_set/clr ,Match interrupt for channels 2" "Cleared,Set"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ILIM2_set/clr ,Limit interrupt for channels 2" "Cleared,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ICAP1_set/clr ,Capture interrupt for channels 1" "Cleared,Set"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " IMAT1_set/clr ,Match interrupt for channels 1" "Cleared,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " ILIM1_set/clr ,Limit interrupt for channels 1" "Cleared,Set"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ICAP0_set/clr ,Capture interrupt for channel 0" "Cleared,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IMAT0_set/clr ,Match interrupt for channel 0" "Cleared,Set"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ILIM0_set/clr ,Limit interrupt for channel 0" "Cleared,Set"
|
|
group.long 0x5c++0x3
|
|
line.long 0x00 "MCCNTCON,MCPWM Count Control Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " CNTR2_set/clr ,Channel 2 mode" "Timer,Counter"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CNTR1_set/clr ,Channel 1 mode" "Timer,Counter"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " CNTR0_set/clr ,Channel 0 mode" "Timer,Counter"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " TC2MCI2_FE_set/clr ,Counter 2 advances on a falling edge on MCI2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " TC2MCI2_RE_set/clr ,Counter 2 advances on a rising edge on MCI2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " TC2MCI1_FE_set/clr ,Counter 2 advances on a falling edge on MCI1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " TC2MCI1_RE_set/clr ,Counter 2 advances on a rising edge on MCI1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " TC2MCI0_FE_set/clr ,counter 2 advances on a falling edge on MCI0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " TC2MCI0_RE_set/clr ,Counter 2 advances on a rising edge on MCI0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " TC1MCI2_FE_set/clr ,counter 1 advances on a falling edge on MCI2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " TC1MCI2_RE_set/clr ,Counter 1 advances on a rising edge on MCI2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " TC1MCI1_FE_set/clr ,Counter 1 advances on a falling edge on MCI1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " TC1MCI1_RE_set/clr ,Counter 1 advances on a rising edge on MCI1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TC1MCI0_FE_set/clr ,Counter 1 advances on a falling edge on MCI0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TC1MCI0_RE_set/clr ,Counter 1 advances on a rising edge on MCI0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TC0MCI2_FE_set/clr ,Counter 0 advances on a falling edge on MCI2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TC0MCI2_RE_set/clr , Counter 0 advances on a rising edge on MCI2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TC0MCI1_FE_set/clr ,Counter 0 advances on a falling edge on MCI1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TC0MCI1_RE_set/clr ,Counter 0 advances on a rising edge on MCI1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TC0MCI0_FE_set/clr ,Counter 0 advances on a falling edge on MCI0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TC0MCI0_RE_set/clr ,Counter 0 advances on a rising edge on MCI0" "Disabled,Enabled"
|
|
group.long 0x18++0x23
|
|
line.long 0x00 "MCTC0,MCPWM Timer value registers 0"
|
|
line.long 0x04 "MCTC1,MCPWM Timer value registers 1"
|
|
line.long 0x08 "MCTC2,MCPWM Timer value registers 2"
|
|
line.long 0x0C "MCLIM0,MCPWM Limit value register 0"
|
|
line.long 0x10 "MCLIM1,MCPWM Limit value register 1"
|
|
line.long 0x14 "MCLIM2,MCPWM Limit value register 2"
|
|
line.long 0x18 "MCMAT0,MCPWM Match value register 0"
|
|
line.long 0x1C "MCMAT1,MCPWM Match value register 1"
|
|
line.long 0x20 "MCMAT2,MCPWM Match value register 2"
|
|
width 11.
|
|
if ((per.l(ad:0x400B8000)&0x40000000)==0x0)
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "MCDT,MCPWM Dead-time register"
|
|
hexmask.long.word 0x00 20.--29. 1. " DT2 ,Dead time for channel 2"
|
|
hexmask.long.word 0x00 10.--19. 1. " DT1 ,Dead time for channel 1"
|
|
hexmask.long.word 0x00 0.--9. 1. " DT0 ,Dead time for channel 0"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "MCDT,MCPWM Dead-time register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DT0 ,Dead time for all three channels"
|
|
endif
|
|
if ((per.l(ad:0x400B8000)&0x80000000)==0x80000000)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "MCCP,MCPWM Communication pattern register"
|
|
bitfld.long 0x00 5. " CCPB2 ,MCO2B control" "Off,Tracks MCOA0"
|
|
bitfld.long 0x00 4. " CCPA2 ,MCO2A control" "Off,Tracks MCOA0"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CCPB1 ,MCO1B control" "Off,Tracks MCOA0"
|
|
bitfld.long 0x00 2. " CCPA1 ,MCO1A control" "Off,Tracks MCOA0"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CCPB0 ,MCO0B control" "Off,Tracks MCOA0"
|
|
bitfld.long 0x00 0. " CCPA0 ,MCO0A control" "Off,Active"
|
|
else
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "MCCP,MCPWM Communication pattern register"
|
|
endif
|
|
rgroup.long 0x44++0xB
|
|
line.long 0x00 "MCCAP0,TC value at a capture event for channel 0"
|
|
line.long 0x04 "MCCAP1,TC value at a capture event for channel 1"
|
|
line.long 0x08 "MCCAP2,TC value at a capture event for channel 2"
|
|
wgroup.long 0x74++0x3
|
|
line.long 0x00 "MCCAP_CLR,MCPWM Capture register"
|
|
bitfld.long 0x00 2. " CAP_CLR2 ,Clears the MCCAP2 register" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CAP_CLR1 ,Clears the MCCAP1 register" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CAP_CLR0 ,Clears the MCCAP0 register" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
sif cpuis("LPC183*")||cpuis("LPC185*")
|
|
tree "QEI (Quadrature Encoder Interface)"
|
|
base ad:0x400C6000
|
|
width 12.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "QEICON,QEI Control Register"
|
|
bitfld.long 0x00 3. " RESI ,Reset index counter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RESV ,Reset velocity" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESPI ,Reset position counter on index" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RESP ,Reset position counter" "No effect,Reset"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "QEICONF,QEI Configuration Register"
|
|
sif (cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x00 19. " INXGATE[19] ,Index gating configuration(PHA=0,PHB=0)" "Not gated,Gated"
|
|
bitfld.long 0x00 18. " INXGATE[18] ,Index gating configuration(PHA=0,PHB=1)" "Not gated,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INXGATE[17] ,Index gating configuration(PHA=1,PHB=1)" "Not gated,Gated"
|
|
bitfld.long 0x00 16. " INXGATE[16] ,Index gating configuration(PHA=1,PHB=0)" "Not gated,Gated"
|
|
textline " "
|
|
sif (cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
bitfld.long 0x00 3. " CRESPI ,Continuously reset the position counter on index" "No reset,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4. " CRESPI ,Continuously reset the position counter on index" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " INVINX ,Invert Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " CAPMODE ,Capture Mode" "Only PhA,PhA/PhB"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SIGMODE ,Signal Mode" "PhA/PhB quad,PhA-Dir/PhB-Clk"
|
|
bitfld.long 0x00 0. " DIRINV ,Direction invert" "Not inverted,Inverted"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "QEISTAT,Encoder Status Register"
|
|
bitfld.long 0x00 0. " DIR ,Direction bit" "Forward,Reverse"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "QEIPOS,QEI Position Register"
|
|
group.long 0x10++0xF
|
|
line.long 0x00 "QEIMAXPOS,QEI Maximum Position Register"
|
|
line.long 0x04 "CMPOS0,Position Compare Register 0"
|
|
line.long 0x08 "CMPOS1,Position Compare Register 1"
|
|
line.long 0x0C "CMPOS2,Position Compare Register 2"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "INXCNT,Index Count Register"
|
|
sif (cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "INXCMP0,Index compare register 0"
|
|
group.long 0x4C++0x7
|
|
line.long 0x00 "INXCMP1,Index compare register 1"
|
|
line.long 0x04 "INXCMP2,Index compare register 2"
|
|
elif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INXCMP0,Index compare register 0"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "INXCMP,Index compare register"
|
|
endif
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "QEILOAD,Velocity timer reload register"
|
|
rgroup.long 0x2C++0xB
|
|
line.long 0x00 "QEITIME,Velocity timer register"
|
|
line.long 0x04 "QEIVEL,Velocity counter register"
|
|
line.long 0x08 "QEICAP,Velocity capture register"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "VELCOMP,Velocity compare register"
|
|
sif (cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x3C++0x0F
|
|
line.long 0x00 "FILTERPHA,Digital filter on PHA register"
|
|
line.long 0x04 "FILTERPHB,Digital filter on PHB register"
|
|
line.long 0x08 "FILTERINX,Digital Filter on INX register"
|
|
line.long 0x0C "WINDOW,QEI index acceptance Window"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "FILTER,Digital filter register"
|
|
endif
|
|
group.long 0xFE0++0x7
|
|
line.long 0x00 "QEIINTSTAT,QEI Interrupt Status Register"
|
|
sif (cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " MAXPOS_Int_set/clr ,The current position count goes through the MAXPOS value to zero in the forward direction" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x0C 14. 0x08 14. " REV2_Int_set/clr ,The index compare 2 value is equal to the current index count" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " REV1_Int_set/clr ,The index compare 1 value is equal to the current index count" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. 0x0C 12. 0x08 12. " POS2REV_Int_set/clr ,Combined position 2 and revolution count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x0C 11. 0x08 11. " POS1REV_Int_set/clr ,Combined position 1 and revolution count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x0C 10. 0x08 10. " POS0REV_Int_set/clr ,Combined position 0 and revolution count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x0C 9. 0x08 9. " REV0_Int_set/clr ,The index compare value is equal to the current index count" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " POS2_Int_set/clr ,The position 2 compare value is equal to the current position" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " POS1_Int_set/clr ,The position 1 compare value is equal to the current position" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " POS0_Int_set/clr ,The position 0 compare value is equal to the current position" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " ENCLK_Int_set/clr ,Encoder clock pulse was detected" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x0C 4. 0x08 4. " ERR_Int_set/clr ,Encoder phase error was detected" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x0C 3. 0x08 3. " DIR_Int_set/clr ,Change of direction was detected" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x0C 2. 0x08 2. " VELC_Int_set/clr ,Captured velocity is less than compare velocity" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x0C 1. 0x08 1. " TIM_Int_set/clr ,Velocity timer overflow occured" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x0C 0. 0x08 0. " INX_Int_set/clr ,Index pulse was detected" "No interrupt,Interrupt"
|
|
line.long 0x04 "QEIIE,QEI Interrupt Enable Register"
|
|
sif (cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
setclrfld.long 0x04 15. -0x04 15. -0x08 15. " MAXPOS_Int_set/clr ,The current position count goes through the MAXPOS value to zero in the forward direction" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 14. -0x04 14. -0x08 14. " REV2_Int_set/clr ,The index compare 2 value is equal to the current index count" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. -0x04 13. -0x08 13. " REV1_Int_set/clr ,The index compare 1 value is equal to the current index count" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x04 12. -0x04 12. -0x08 12. " POS2REV_Int_set/clr ,Combined position 2 and revolution count interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. -0x04 11. -0x08 11. " POS1REV_Int_set/clr ,Combined position 1 and revolution count interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 10. -0x04 10. -0x08 10. " POS0REV_Int_set/clr ,Combined position 0 and revolution count interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. -0x04 9. -0x08 9. " REV_Int_set/clr ,The index compare value is equal to the current index count" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 8. -0x04 8. -0x08 8. " POS2_Int_set/clr ,The position 2 compare value is equal to the current position" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. -0x04 7. -0x08 7. " POS1_Int_set/clr ,The position 1 compare value is equal to the current position" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 6. -0x04 6. -0x08 6. " POS0_Int_set/clr ,The position 0 compare value is equal to the current position" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. -0x04 5. -0x08 5. " ENCLK_Int_set/clr ,Encoder clock pulse was detected" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 4. -0x04 4. -0x08 4. " ERR_Int_set/clr ,Encoder phase error was detected" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. -0x04 3. -0x08 3. " DIR_Int_set/clr ,Change of direction was detected" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 2. -0x04 2. -0x08 2. " VELC_Int_set/clr ,Captured velocity is less than compare velocity" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. -0x04 1. -0x08 1. " TIM_Int_set/clr ,Velocity timer overflow occured" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 0. -0x04 0. -0x08 0. " INX_Int_set/clr ,Index pulse was detected" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "RIT (Repetitive Interrupt Timer)"
|
|
base ad:0x400C0000
|
|
width 11.
|
|
group.long 0x00++0xf
|
|
line.long 0x00 "RICOMPVAL,Compare Register"
|
|
line.long 0x04 "RIMASK,Mask Register"
|
|
bitfld.long 0x04 31. " RIMASK_31 ,Forces compare on the 31 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 30. " RIMASK_30 ,Forces compare on the 30 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 29. " RIMASK_29 ,Forces compare on the 29 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 28. " RIMASK_28 ,Forces compare on the 28 bit of the counter and compare register" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 27. " RIMASK_27 ,Forces compare on the 27 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 26. " RIMASK_26 ,Forces compare on the 26 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 25. " RIMASK_25 ,Forces compare on the 25 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 24. " RIMASK_24 ,Forces compare on the 24 bit of the counter and compare register" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 23. " RIMASK_23 ,Forces compare on the 23 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 22. " RIMASK_22 ,Forces compare on the 22 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 21. " RIMASK_21 ,Forces compare on the 21 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 20. " RIMASK_20 ,Forces compare on the 20 bit of the counter and compare register" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RIMASK_19 ,Forces compare on the 19 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 18. " RIMASK_18 ,Forces compare on the 18 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 17. " RIMASK_17 ,Forces compare on the 17 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 16. " RIMASK_16 ,Forces compare on the 16 bit of the counter and compare register" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 15. " RIMASK_15 ,Forces compare on the 15 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 14. " RIMASK_14 ,Forces compare on the 14 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 13. " RIMASK_13 ,Forces compare on the 13 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 12. " RIMASK_12 ,Forces compare on the 12 bit of the counter and compare register" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RIMASK_11 ,Forces compare on the 11 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 10. " RIMASK_10 ,Forces compare on the 10 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 9. " RIMASK_9 ,Forces compare on the 9 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 8. " RIMASK_8 ,Forces compare on the 8 bit of the counter and compare register" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RIMASK_7 ,Forces compare on the 7 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 6. " RIMASK_6 ,Forces compare on the 6 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 5. " RIMASK_5 ,Forces compare on the 5 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 4. " RIMASK_4 ,Forces compare on the 4 bit of the counter and compare register" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RIMASK_3 ,Forces compare on the 3 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 2. " RIMASK_2 ,Forces compare on the 2 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 1. " RIMASK_1 ,Forces compare on the 1 bit of the counter and compare register" "Not forced,Forced"
|
|
bitfld.long 0x04 0. " RIMASK_0 ,Forces compare on the 0 bit of the counter and compare register" "Not forced,Forced"
|
|
textline ""
|
|
line.long 0x08 "RICTRL,Control Register"
|
|
bitfld.long 0x08 3. " RITEN ,Timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RITENBR ,Timer enable for debug" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RITENCLR ,Timer enable clear" "Disabled,Enabled"
|
|
eventfld.long 0x08 0. " RITINT ,Counter value equals the masked compare value (RICOMPVAL and RIMASK)" "Not occurred,Occurred"
|
|
line.long 0x0c "RICOUNTER,32-bit Counter"
|
|
width 0xb
|
|
tree.end
|
|
tree "AT (Alarm timer)"
|
|
base ad:0x40040000
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DOWNCOUNTER,Downcounter register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVAL ,When equal to zero an interrupt is raised"
|
|
line.long 0x04 "PRESET,Preset value register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PRESETVAL ,Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero"
|
|
group.long 0xFE0++0x7
|
|
line.long 0x00 "STATUS,Interrupt status register"
|
|
setclrfld.long 0x00 0. 0x0C 0. 0x08 0. " STAT_set/clr ,A 1 in this bit shows that the STATUS interrupt has been raised" "Not raised,Raised"
|
|
line.long 0x04 "ENABLE,Interrupt enable register"
|
|
setclrfld.long 0x04 0. -0x04 0. -0x08 0. " EN_set/clr ,A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "WWDT (Windowed Watchdog timer)"
|
|
base ad:0x40080000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "WDMOD,Watchdog Mode Register"
|
|
sif cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC11E*")||cpuis("LPC11U6*"))
|
|
bitfld.long 0x00 5. " CSLOCK ,Clock source lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))
|
|
bitfld.long 0x00 5. " LOCK ,Watchdog oscillator lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 7. " WDLOCKEN ,Watchdog enable and reset lockout" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " WDLOCKDP ,Deep Power-down enable lock" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSLOCK ,Clock source lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
endif
|
|
sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04")
|
|
eventfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "Not occurred,Occurred"
|
|
else
|
|
bitfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "Not occurred,Occurred"
|
|
endif
|
|
bitfld.long 0x00 2. " WDTOF ,Watchdog Time-out flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable" "Disabled,Enabled"
|
|
sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04")
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="EM773"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpu()=="LPC11U24"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC43S*")||cpuis("LPC11U6")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")||cpu()==("LPC8N04")||cpuis("LPC11D14"))
|
|
line.long 0x04 "WDTC,Watchdog Timer Constant Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out value"
|
|
else
|
|
line.long 0x04 "WDTC,Watchdog Timer Constant Register"
|
|
hexmask.long 0x04 0.--31. 1. " COUNT ,Watchdog time-out interval"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "WDFEED,Watchdog Feed Sequence Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value"
|
|
sif (cpu()=="EM773"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*"))||cpuis("LPC43S*")||cpuis("LPC11U6")||cpuis("LPC84*")||(cpu()=="LPC811M001JDH16")||(cpu()=="LPC832M101FDH20")||(cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))||cpu()=="LPC8N04"||cpuis("LPC11D14")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "WDTV,Watchdog Timer Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "WDTV,Watchdog Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " COUNT ,Counter timer value"
|
|
endif
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&!cpuis("LPC1111*")&&cpu()!="LPC11D14"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850"&&cpu()!="LPC1853"&&cpu()!="LPC1857"&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC43*")&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&!cpuis("LPC43S*")&&!cpuis("LPC84*")&&cpu()!="LPC811M001JDH16"&&cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&cpu()!="LPC8N04"&&!cpuis("LPC802*")&&!cpuis("LPC804*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WDCLKSEL,Watchdog Timer Clock Source Selection Register"
|
|
bitfld.long 0x00 31. " WDLOCK ,Watchdog lock" "Not locked,Locked"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 0.--1. " WDSEL1 ,Select the clock source for the watchdog timer" "Internal RC,Watchdog,?..."
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11U6*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKSEL ,Selects source of WDT clock" "IRC,Watchdog oscillator"
|
|
else
|
|
bitfld.long 0x00 0.--1. " WDSEL2 ,Select the clock source for the watchdog timer" "RC,APB clock,RTC,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U6*")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "WDWARNINT,Watchdog Timer Warning Interrupt Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " WARNINT ,Watchdog warning interrupt compare value"
|
|
line.long 0x04 "WDWINDOW,Watchdog Timer Window Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " WINDOW ,Watchdog window value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40046000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ILR,Interrupt Location Register"
|
|
bitfld.long 0x00 1. " RTCALF ,RTC Alarm Register Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " RTCCIF ,RTC Counter Increment Interrupt" "Not occurred,Occurred"
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "CCR,Clock Control Register"
|
|
bitfld.long 0x00 4. " CCALEN ,Calibration counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTCRST ,CTC Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "CCR,Clock Control Register"
|
|
bitfld.long 0x00 4. " CCALEN ,Calibration counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " TEST ,Internal test mode control" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTCRST ,CTC Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "CIIR,Counter Increment Interrupt Register"
|
|
bitfld.long 0x04 7. " IMYEAR ,Year Value Increment Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " IMMON ,Month Value Increment Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMDOY ,Day of Year Value Increment Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " IMDOW ,Day of Week Value Increment Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMDOM ,Day of Month Value Increment Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " IMHOUR ,Hour Value Increment Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IMMIN ,Minute Value Increment Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " IMSEC ,Second Value Increment Interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "AMR,Alarm Mask Register"
|
|
bitfld.long 0x08 7. " AMRYEAR ,Year Value Alarm Comparison" "Enabled,Disabled"
|
|
bitfld.long 0x08 6. " AMRMON ,Month Value Alarm Comparison" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " AMRDOY ,Fay of Year Value Alarm Comparison" "Enabled,Disabled"
|
|
bitfld.long 0x08 4. " AMRDOW ,Day of Value Alarm Comparison" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " AMRDOM ,Day of Month Value Alarm Comparison" "Enabled,Disabled"
|
|
bitfld.long 0x08 2. " AMRHOUR ,Hour Value Alarm Comparison" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " AMRMIN ,Minutes Value Alarm Comparison" "Enabled,Disabled"
|
|
bitfld.long 0x08 0. " AMRSEC ,Second Value Alarm Comparison" "Enabled,Disabled"
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850"&&cpu()!="LPC1853"&&cpu()!="LPC1857"&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x58++0x7
|
|
line.long 0x04 "RTC_AUX,RTC Auxiliary control register"
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
bitfld.long 0x04 6. " RTC_PDOUT ,Deep Power-down mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x04 4. " RTC_OSCF ,RTC Oscillator Fail detect flag" "Not occurred,Occurred"
|
|
line.long 0x00 "RTC_AUXEN,RTC Auxiliary Enable register"
|
|
bitfld.long 0x00 4. " RTC_OSCFEN ,Oscillator Fail Detect interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CTIME0,Consolidated Time Register 0"
|
|
bitfld.long 0x00 24.--26. " DAY_OF_WEEK ,Day of week" "Sun,Mon,Tue,Wed,Thu,Fri,Sat,?..."
|
|
bitfld.long 0x00 16.--20. " HOURS ,Hour" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " MINUTES ,Minutes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SECONDS ,Seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
if (((per.l(ad:0x40046000+0x18)&0xF00)==0x200)&&(per.l(ad:0x40046000+0x18)&0x30000)==0)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x0 "CTIME1,Consolidated Time Register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. " YEAR ,Year"
|
|
bitfld.long 0x0 8.--11. " MONTH ,Month" "Reserved,Jan,Feb,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--4. " DAY_OF_MONTH ,Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,?..."
|
|
elif ((per.l(ad:0x40046000+0x18)&0xF00)==0x200)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x0 "CTIME1,Consolidated Time Register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. " YEAR ,Year"
|
|
bitfld.long 0x0 8.--11. " MONTH ,Month" "Reserved,Jan,Feb,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--4. " DAY_OF_MONTH ,Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,?..."
|
|
elif ((per.l(ad:0x40046000+0x18)&0xF00)==(0x400||0x600||0x900||0xB00))
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x0 "CTIME1,Consolidated Time Register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. " YEAR ,Year"
|
|
bitfld.long 0x0 8.--11. " MONTH ,Month" "Reserved,Jan,Feb,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--4. " DAY_OF_MONTH ,Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x0 "CTIME1,Consolidated Time Register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. " YEAR ,Year"
|
|
bitfld.long 0x0 8.--11. " MONTH ,Month" "Reserved,Jan,Feb,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--4. " DAY_OF_MONTH ,Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x0 "CTIME2,Consolidated Time Register 2"
|
|
hexmask.long.word 0x0 0.--11. 1. " DAY_OF_YEAR ,Day of Year"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SEC,Seconds Register"
|
|
bitfld.long 0x00 0.--5. " SEC ,Seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
line.long 0x04 "MIN,Minutes Register"
|
|
bitfld.long 0x04 0.--5. " MIN ,Minutes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
line.long 0x08 "HOUR,Hours Register"
|
|
bitfld.long 0x08 0.--4. " HOUR ,Hours" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
if (((per.l(ad:0x40046000+0x38)&0xF)==0x02)&&((per.l(ad:0x40046000+0x3c)&0x3)==0x0))
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "DOM,Day of Month Register"
|
|
bitfld.long 0x0 0.--4. " DOM ,Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,?..."
|
|
elif ((per.l(ad:0x40046000+0x38)&0xF)==0x02)
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "DOM,Day of Month Register"
|
|
bitfld.long 0x0 0.--4. " DOM ,Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,?..."
|
|
elif ((per.l(ad:0x40046000+0x38)&0xF)==(0x04||0x06||0x09||0x0B))
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "DOM,Day of Month Register"
|
|
bitfld.long 0x0 0.--4. " DOM ,Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "DOM,Day of Month Register"
|
|
bitfld.long 0x0 0.--4. " DOM ,Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x30++0x27
|
|
line.long 0x0 "DOW,Day of Week Register"
|
|
bitfld.long 0x0 0.--2. " DOW ,Day of Week" "Sun,Mon,Tue,Wed,Thu,Fri,Sat,?..."
|
|
line.long 0x4 "DOY,Day of Year Register"
|
|
hexmask.long.word 0x4 0.--8. 1. " DOY ,Day of Year"
|
|
line.long 0x8 "MONTH,Months Register"
|
|
bitfld.long 0x8 0.--3. " MONTH ,Month" "Reserved,Jan,Feb,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
line.long 0xC "YEAR,Years Register"
|
|
hexmask.long.word 0xC 0.--11. 1. " YEAR ,Year"
|
|
line.long 0x10 "CALIBRATION,Calibration Register"
|
|
bitfld.long 0x10 17. " CALDIR ,Calibration direction" "Forward,Backward"
|
|
hexmask.long.tbyte 0x10 0.--16. 1. " CALVAL ,Calibration value"
|
|
sif (cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850"&&cpu()!="LPC1853"&&cpu()!="LPC1857"&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
line.long 0x14 "GPREG0,General Purpose Registers 0"
|
|
line.long 0x18 "GPREG1,General Purpose Registers 1"
|
|
line.long 0x1c "GPREG2,General Purpose Registers 2"
|
|
line.long 0x20 "GPREG3,General Purpose Registers 3"
|
|
line.long 0x24 "GPREG4,General Purpose Registers 4"
|
|
endif
|
|
group.long 0x60++0xB
|
|
line.long 0x0 "ALSEC,Alarm value for Seconds"
|
|
bitfld.long 0x0 0.--5. " ALSEC ,Alarm Value for Seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
line.long 0x04 "ALMIN,Alarm value for Minutes"
|
|
bitfld.long 0x04 0.--5. " ALMIN ,Alarm Value for Minutes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
line.long 0x08 "ALHOUR,Alarm value for Hours"
|
|
bitfld.long 0x08 0.--4. " ALHOUR ,Alarm Value for Hours" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
if (((per.l(ad:0x40046000+0x78)&0xF)==0x02)&&((per.l(ad:0x40046000+0x7c)&0x3)==0x0))
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "ALDOM,Alarm value for Day of Month"
|
|
bitfld.long 0x0 0.--4. " ALDOM ,Alarm Value for Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,?..."
|
|
elif ((per.l(ad:0x40046000+0x78)&0xF)==0x02)
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "ALDOM,Alarm value for Day of Month"
|
|
bitfld.long 0x0 0.--4. " ALDOM ,Alarm Value for Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,?..."
|
|
elif ((per.l(ad:0x40046000+0x78)&0xF)==(0x04||0x06||0x09||0x78||0x0B))
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "ALDOM,Alarm value for Day of Month"
|
|
bitfld.long 0x0 0.--4. " ALDOM ,Alarm Value for Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
|
|
else
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "ALDOM,Alarm value for Day of Month"
|
|
bitfld.long 0x0 0.--4. " ALDOM ,Alarm Value for Day of Month" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x70++0xF
|
|
line.long 0x0 "ALDOW,Alarm value for Day of Week"
|
|
bitfld.long 0x0 0.--2. " ALDOW ,Alarm Value for Day of Week" "Sun,Mon,Tue,Wed,Thu,Fri,Sat,?..."
|
|
line.long 0x4 "ALDOY,Alarm value for Day of Year"
|
|
hexmask.long.word 0x4 0.--8. 1. " ALDOY ,Alarm Value for Day of Year"
|
|
line.long 0x8 "ALMON,Alarm value for Months"
|
|
bitfld.long 0x8 0.--3. " ALMONTH ,Alarm Value for Month" "Reserved,Jan,Feb,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec,?..."
|
|
line.long 0xC "ALYEAR,Alarm value for Year"
|
|
hexmask.long.word 0xC 0.--11. 1. " ALYEAR ,Alarm Value for Year"
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("LPC1810")&&!cpuis("LPC1820")&&!cpuis("LPC1830")&&!cpuis("LPC1850")
|
|
tree "EMR (Event monitor/recorder)"
|
|
base ad:0x40046000
|
|
width 15.
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "ERCONTROL,Event Monitor/Recorder Control Register"
|
|
bitfld.long 0x00 30.--31. " ERMODE ,Event Monitor/Recorder enable and operating frequency select" "Disabled,Enabled (16Hz),Enabled (64Hz),Enabled (1kHz)"
|
|
bitfld.long 0x00 23. " EV2_INPUT_EN ,Event enable control for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " POL2 ,Polarity of an event on input pin RTC_EV2 select" "Negative,Positive"
|
|
sif cpuis("LPC43S*")
|
|
bitfld.long 0x00 21. " GPCLEAR_EN2 ,RTC general purpose registers clear when an event occurs on channel 2" "Not cleared,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " INTWAKE_EN2 ,Interrupt and wakeup enable for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EV1_INPUT_EN ,Event enable control for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " POL1 ,Polarity of an event on input pin RTC_EV1 select" "Negative,Positive"
|
|
sif cpuis("LPC43*")
|
|
bitfld.long 0x00 11. " GPCLEAR_EN1 ,RTC general purpose registers clear when an event occurs on channel 1" "Not cleared,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " INTWAKE_EN1 ,Interrupt and wakeup enable for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EV0_INPUT_EN ,Event enable control for channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " POL0 ,Polarity of an event on input pin RTC_EV0 select" "Negative,Positive"
|
|
bitfld.long 0x00 1. " GPCLEAR_EN0 ,RTC general purpose registers clear when an event occurs on channel 0" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INTWAKE_EN0 ,Interrupt and wakeup enable for channel 0" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "ERSTATUS,Event Monitor/Recorder Status Register"
|
|
eventfld.long 0x00 31. " WAKEUP ,Interrupt/wakeup request flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " GP_CLEARED ,General purpose register asynchronous clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EV2 ,Event flag for channel 2 (RTC_EV2 pin)" "No event,Event"
|
|
eventfld.long 0x00 1. " EV1 ,Event flag for channel 1 (RTC_EV1 pin)" "No event,Event"
|
|
textline " "
|
|
eventfld.long 0x00 0. " EV0 ,Event flag for channel 0 (RTC_EV0 pin)" "No event,Event"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x00 "ERCOUNTERS,Event Monitor/Recorder Counters Register"
|
|
bitfld.long 0x00 16.--18. " COUNTER2 ,Value of the counter for event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " COUNTER1 ,Value of the counter for event 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " COUNTER0 ,Value of the counter for event 0" "0,1,2,3,4,5,6,7"
|
|
if ((per.l(ad:0x40046000+0x80)&0x1)==0x1)
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x00 "ERFIRSTSTAMP0,Event Monitor/Recorder First Stamp Register for Channel 0"
|
|
hexmask.long.word 0x00 17.--25. 1. " DAY ,Day of Year value in the range of 1 to 366"
|
|
bitfld.long 0x00 12.--16. " HOUR ,Hours value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--11. " MIN ,Minutes value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SEC ,Seconds value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x00 "ERLASTSTAMP0,Event Monitor/Recorder Last Stamp Register for Channel 0"
|
|
hexmask.long.word 0x00 17.--25. 1. " DAY ,Day of Year value in the range of 1 to 366"
|
|
bitfld.long 0x00 12.--16. " HOUR ,Hours value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--11. " MIN ,Minutes value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SEC ,Seconds value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
else
|
|
hgroup.long 0x90++0x3
|
|
hide.long 0x00 "ERFIRSTSTAMP0,Event Monitor/Recorder First Stamp Register for Channel 0"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "ERLASTSTAMP0,Event Monitor/Recorder Last Stamp Register for Channel 0"
|
|
endif
|
|
if ((per.l(ad:0x40046000+0x80)&0x2)==0x2)
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x00 "ERFIRSTSTAMP1,Event Monitor/Recorder First Stamp Register for Channel 1"
|
|
hexmask.long.word 0x00 17.--25. 1. " DAY ,Day of Year value in the range of 1 to 366"
|
|
bitfld.long 0x00 12.--16. " HOUR ,Hours value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--11. " MIN ,Minutes value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SEC ,Seconds value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x00 "ERLASTSTAMP1,Event Monitor/Recorder Last Stamp Register for Channel 1"
|
|
hexmask.long.word 0x00 17.--25. 1. " DAY ,Day of Year value in the range of 1 to 366"
|
|
bitfld.long 0x00 12.--16. " HOUR ,Hours value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--11. " MIN ,Minutes value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SEC ,Seconds value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
else
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "ERFIRSTSTAMP1,Event Monitor/Recorder First Stamp Register for Channel 1"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "ERLASTSTAMP1,Event Monitor/Recorder Last Stamp Register for Channel 1"
|
|
endif
|
|
if ((per.l(ad:0x40046000+0x80)&0x4)==0x4)
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "ERFIRSTSTAMP2,Event Monitor/Recorder First Stamp Register for Channel 2"
|
|
hexmask.long.word 0x00 17.--25. 1. " DAY ,Day of Year value in the range of 1 to 366"
|
|
bitfld.long 0x00 12.--16. " HOUR ,Hours value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--11. " MIN ,Minutes value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SEC ,Seconds value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x00 "ERLASTSTAMP2,Event Monitor/Recorder Last Stamp Register for Channel 2"
|
|
hexmask.long.word 0x00 17.--25. 1. " DAY ,Day of Year value in the range of 1 to 366"
|
|
bitfld.long 0x00 12.--16. " HOUR ,Hours value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--11. " MIN ,Minutes value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x00 0.--5. " SEC ,Seconds value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
else
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "ERFIRSTSTAMP2,Event Monitor/Recorder First Stamp Register for Channel 2"
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "ERLASTSTAMP2,Event Monitor/Recorder Last Stamp Register for Channel 2"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.open "USART"
|
|
tree "USART0"
|
|
base ad:0x40081000
|
|
width 11.
|
|
if (((per.l((ad:0x40081000+0xC)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "U0RBR/THR,Receiver/Transmit Buffer Register"
|
|
in
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U0IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud Time-out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of Auto-baud Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLSIE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THREIE ,THRE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RBRIE ,RBR Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "U0DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,UARTn Divisor Latch LSB"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U0DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLMSB ,UARTn Divisor Latch MSB"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "U0IIR,Interrupt ID"
|
|
in
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "U0FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTRIGLVL ,Rx Trigger Level Select" "Level 0(1 char.),Level 1(4 char.),Level 2(8 char.),Level 3(14 char.)"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC11D14"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x0 3. " DMAMODE ,DMA Mode Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 2. " TXFIFORES ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " RXFIFORES ,Receiver FIFO Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOENABLE ,FIFO Enable" "Disable,Enable"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "U0MCR,USART Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback Mode Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTSCON ,Source for modem output pin RTS" "Active,Inactive"
|
|
bitfld.long 0x00 0. " DTRCON ,Source for modem output pin DTR" "Active,Inactive"
|
|
endif
|
|
if ((per.l((ad:0x40081000+0xC))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U0LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U0LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC11D14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U0MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Low,High"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "U0LSR,Line Status Register"
|
|
in
|
|
sif (cpu()=="EM773"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U0MSR,Modem Status Register"
|
|
in
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "U0SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Pad ,A readable/writable byte"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "U0ACR,Auto-baud Control Register"
|
|
bitfld.long 0x00 9. " ABTOINTCLR ,Auto-baud Time-out Interrupt Clear Bit" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " ABEOINTCLR ,End of Auto-baud Interrupt Clear Bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTORESTART ,Auto Restart" "Not restarted,Restarted"
|
|
bitfld.long 0x00 1. " MODE ,Auto-baud Mode Select" "Mode 0,Mode 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Auto-baud Start" "Stopped,Started"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
elif (cpu()!="EM773"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
if (((per.l((ad:0x40081000+0x24)))&0x4)==0x4)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U0ICR,IrDA Control Register"
|
|
sif cpu()=="LPC11U12/201"||cpu()=="LPC11U13/x201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "3/(16 * baud rate),2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk"
|
|
else
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U0ICR,IrDA Control Register"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
endif
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "U0FDR,Fractional Divider Register"
|
|
bitfld.long 0x00 4.--7. " MULVAL , Pre-scaler Multiplier Value" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "No effect,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
endif
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times (ETUs)"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40081000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
width 17.
|
|
if (((per.l((ad:0x40081000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("LPC176*")&&!cpuis("LPC175*")&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "U0FIFOLVL,FIFO Level Register"
|
|
bitfld.long 0x00 8.--11. " TXFIFOLVL ,Level of the UART transmitter FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
bitfld.long 0x00 0.--3. " RXFIFILVL ,Level of the UART receiver FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
width 17.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x04 "U0RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
line.long 0x08 "SYNCCTRL,Synchronous mode control register"
|
|
bitfld.long 0x08 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x08 5. " SSSDIS ,Start/stop bits" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x08 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x08 1. " CSRC ,Clock source select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SYNC ,Enables synchronous mode" "Disabled,Enabled"
|
|
line.long 0x0C "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x0C 0. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
width 17.
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
sif (cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
textline " "
|
|
bitfld.long 0x00 3. " SEL ,Direction control pin select" "/RTS,/DTR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "U0RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
sif (cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11D14"&&cpu()!="LPC1112LV"&&cpu()!="LPC1114LV")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNCCTRL,Synchronous mode control register"
|
|
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x00 5. " SSSDIS ,Start/stop bits" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC ,Enables synchronous mode" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
width 16.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "USART1"
|
|
base ad:0x40082000
|
|
width 11.
|
|
if (((per.l((ad:0x40082000+0xC)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "U1RBR/THR,Receiver/Transmit Buffer Register"
|
|
in
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U1IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud Time-out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of Auto-baud Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTSIE ,Modem status interrupt generation on a CTS1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLSIE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THREIE ,THRE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RBRIE ,RBR Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "U1DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,UARTn Divisor Latch LSB"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U1DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLMSB ,UARTn Divisor Latch MSB"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "U1IIR,Interrupt ID"
|
|
in
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "U1FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTRIGLVL ,Rx Trigger Level Select" "Level 0(1 char.),Level 1(4 char.),Level 2(8 char.),Level 3(14 char.)"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC11D14"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x0 3. " DMAMODE ,DMA Mode Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 2. " TXFIFORES ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " RXFIFORES ,Receiver FIFO Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOENABLE ,FIFO Enable" "Disable,Enable"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "U1MCR,USART Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback Mode Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTSCON ,Source for modem output pin RTS" "Active,Inactive"
|
|
bitfld.long 0x00 0. " DTRCON ,Source for modem output pin DTR" "Active,Inactive"
|
|
endif
|
|
if ((per.l((ad:0x40082000+0xC))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U1LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U1LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U1MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin, DTR" "Low,High"
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC11D14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U1MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Low,High"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "U1LSR,Line Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U1MSR,Modem Status Register"
|
|
in
|
|
sif (cpu()=="EM773"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U1MSR,Modem Status Register"
|
|
in
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "U1SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Pad ,A readable/writable byte"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "U1ACR,Auto-baud Control Register"
|
|
bitfld.long 0x00 9. " ABTOINTCLR ,Auto-baud Time-out Interrupt Clear Bit" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " ABEOINTCLR ,End of Auto-baud Interrupt Clear Bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTORESTART ,Auto Restart" "Not restarted,Restarted"
|
|
bitfld.long 0x00 1. " MODE ,Auto-baud Mode Select" "Mode 0,Mode 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Auto-baud Start" "Stopped,Started"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
elif (cpu()!="EM773"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
if (((per.l((ad:0x40082000+0x24)))&0x4)==0x4)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U1ICR,IrDA Control Register"
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U1ICR,IrDA Control Register"
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "U1FDR,Fractional Divider Register"
|
|
bitfld.long 0x00 4.--7. " MULVAL , Pre-scaler Multiplier Value" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "No effect,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
endif
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U1OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U1TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U1HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U1SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times (ETUs)"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U1TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U1TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
endif
|
|
sif (!cpuis("LPC176*")&&!cpuis("LPC175*")&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "U1FIFOLVL,FIFO Level Register"
|
|
bitfld.long 0x00 8.--11. " TXFIFOLVL ,Level of the UART transmitter FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
bitfld.long 0x00 0.--3. " RXFIFILVL ,Level of the UART receiver FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
width 17.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U1RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SEL ,Direction control pin select" "/RTS,/DTR"
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "U1RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x04 "U1RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "U1TER,Transmit Enable Register"
|
|
bitfld.long 0x00 0. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "USART2"
|
|
base ad:0x400C1000
|
|
width 11.
|
|
if (((per.l((ad:0x400C1000+0xC)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "U2RBR/THR,Receiver/Transmit Buffer Register"
|
|
in
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U2IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud Time-out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of Auto-baud Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLSIE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THREIE ,THRE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RBRIE ,RBR Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "U2DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,UARTn Divisor Latch LSB"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U2DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLMSB ,UARTn Divisor Latch MSB"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "U2IIR,Interrupt ID"
|
|
in
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "U2FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTRIGLVL ,Rx Trigger Level Select" "Level 0(1 char.),Level 1(4 char.),Level 2(8 char.),Level 3(14 char.)"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC11D14"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x0 3. " DMAMODE ,DMA Mode Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 2. " TXFIFORES ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " RXFIFORES ,Receiver FIFO Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOENABLE ,FIFO Enable" "Disable,Enable"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "U2MCR,USART Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback Mode Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTSCON ,Source for modem output pin RTS" "Active,Inactive"
|
|
bitfld.long 0x00 0. " DTRCON ,Source for modem output pin DTR" "Active,Inactive"
|
|
endif
|
|
if ((per.l((ad:0x400C1000+0xC))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U2LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U2LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC11D14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U2MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Low,High"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "U2LSR,Line Status Register"
|
|
in
|
|
sif (cpu()=="EM773"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U2MSR,Modem Status Register"
|
|
in
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "U2SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Pad ,A readable/writable byte"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "U2ACR,Auto-baud Control Register"
|
|
bitfld.long 0x00 9. " ABTOINTCLR ,Auto-baud Time-out Interrupt Clear Bit" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " ABEOINTCLR ,End of Auto-baud Interrupt Clear Bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTORESTART ,Auto Restart" "Not restarted,Restarted"
|
|
bitfld.long 0x00 1. " MODE ,Auto-baud Mode Select" "Mode 0,Mode 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Auto-baud Start" "Stopped,Started"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
elif (cpu()!="EM773"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
if (((per.l((ad:0x400C1000+0x24)))&0x4)==0x4)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U2ICR,IrDA Control Register"
|
|
sif cpu()=="LPC11U12/201"||cpu()=="LPC11U13/x201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "3/(16 * baud rate),2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk"
|
|
else
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U2ICR,IrDA Control Register"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
endif
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "U2FDR,Fractional Divider Register"
|
|
bitfld.long 0x00 4.--7. " MULVAL , Pre-scaler Multiplier Value" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "No effect,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
endif
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U2OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U2TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U2HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U2SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times (ETUs)"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U2OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U2HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x400C1000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U2SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U2SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U2TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "U2OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U2HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
width 17.
|
|
if (((per.l((ad:0x400C1000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U2SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U2SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("LPC176*")&&!cpuis("LPC175*")&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "U2FIFOLVL,FIFO Level Register"
|
|
bitfld.long 0x00 8.--11. " TXFIFOLVL ,Level of the UART transmitter FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
bitfld.long 0x00 0.--3. " RXFIFILVL ,Level of the UART receiver FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
width 17.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U2RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "U2RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x04 "U2RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
line.long 0x08 "SYNCCTRL,Synchronous mode control register"
|
|
bitfld.long 0x08 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x08 5. " SSSDIS ,Start/stop bits" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x08 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x08 1. " CSRC ,Clock source select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SYNC ,Enables synchronous mode" "Disabled,Enabled"
|
|
line.long 0x0C "U2TER,Transmit Enable Register"
|
|
bitfld.long 0x0C 0. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "USART3"
|
|
base ad:0x400C2000
|
|
width 11.
|
|
if (((per.l((ad:0x400C2000+0xC)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "U3RBR/THR,Receiver/Transmit Buffer Register"
|
|
in
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U3IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud Time-out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of Auto-baud Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLSIE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THREIE ,THRE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RBRIE ,RBR Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "U3DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,UARTn Divisor Latch LSB"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U3DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLMSB ,UARTn Divisor Latch MSB"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "U3IIR,Interrupt ID"
|
|
in
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "U3FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTRIGLVL ,Rx Trigger Level Select" "Level 0(1 char.),Level 1(4 char.),Level 2(8 char.),Level 3(14 char.)"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC11D14"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x0 3. " DMAMODE ,DMA Mode Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 2. " TXFIFORES ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " RXFIFORES ,Receiver FIFO Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOENABLE ,FIFO Enable" "Disable,Enable"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "U3MCR,USART Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback Mode Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTSCON ,Source for modem output pin RTS" "Active,Inactive"
|
|
bitfld.long 0x00 0. " DTRCON ,Source for modem output pin DTR" "Active,Inactive"
|
|
endif
|
|
if ((per.l((ad:0x400C2000+0xC))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U3LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U3LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC11D14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U3MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Low,High"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "U3LSR,Line Status Register"
|
|
in
|
|
sif (cpu()=="EM773"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U3MSR,Modem Status Register"
|
|
in
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "U3SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Pad ,A readable/writable byte"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "U3ACR,Auto-baud Control Register"
|
|
bitfld.long 0x00 9. " ABTOINTCLR ,Auto-baud Time-out Interrupt Clear Bit" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " ABEOINTCLR ,End of Auto-baud Interrupt Clear Bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTORESTART ,Auto Restart" "Not restarted,Restarted"
|
|
bitfld.long 0x00 1. " MODE ,Auto-baud Mode Select" "Mode 0,Mode 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Auto-baud Start" "Stopped,Started"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
if (((per.l((ad:0x400C2000+0x24)))&0x4)==0x4)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U3ICR,IrDA Control Register"
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk"
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U3ICR,IrDA Control Register"
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
endif
|
|
elif (cpu()!="EM773"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
if (((per.l((ad:0x400C2000+0x24)))&0x4)==0x4)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U3ICR,IrDA Control Register"
|
|
sif cpu()=="LPC11U12/201"||cpu()=="LPC11U13/x201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "3/(16 * baud rate),2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk"
|
|
else
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U3ICR,IrDA Control Register"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
endif
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "U3FDR,Fractional Divider Register"
|
|
bitfld.long 0x00 4.--7. " MULVAL , Pre-scaler Multiplier Value" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "No effect,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
endif
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U3OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U3TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U3HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U3SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times (ETUs)"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U3OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U3HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x400C2000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U3SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U3SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U3TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "U3OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U3HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
width 17.
|
|
if (((per.l((ad:0x400C2000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U3SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U3SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("LPC176*")&&!cpuis("LPC175*")&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "U3FIFOLVL,FIFO Level Register"
|
|
bitfld.long 0x00 8.--11. " TXFIFOLVL ,Level of the UART transmitter FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
bitfld.long 0x00 0.--3. " RXFIFILVL ,Level of the UART receiver FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
width 17.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U3RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "U3RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x04 "U3RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
line.long 0x08 "SYNCCTRL,Synchronous mode control register"
|
|
bitfld.long 0x08 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x08 5. " SSSDIS ,Start/stop bits" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x08 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x08 1. " CSRC ,Clock source select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SYNC ,Enables synchronous mode" "Disabled,Enabled"
|
|
line.long 0x0C "U3TER,Transmit Enable Register"
|
|
bitfld.long 0x0C 0. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "SSP (Synchronous Serial Port)"
|
|
tree "SSP0"
|
|
base ad:0x40083000
|
|
width 11.
|
|
if ((per.l(ad:0x40083000)&0x30)==0x00)
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SSP0CR0,SSP0 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock Out Phase" "First clock,Second clock"
|
|
bitfld.long 0x00 6. " CPOL ,Clock Out Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP0CR0,SSP0 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
endif
|
|
if ((per.l(ad:0x40083000+0x04)&0x4)==0x04)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave Output Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
endif
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSP0DR,SSP0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SSP0DR,SSP0 Data Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSP0SR,SSP0 Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO Not Empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO Not Full" "Full,Not Full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SSP0CPSR,SSP0 Clock Prescale Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CPSDVSR ,PCLK Divisor (even value between 2 and 254)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SSP0IMSC,SSP0 Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x00 3. " TXIM ,Tx FIFO Half Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIM ,Rx FIFO Half Full Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTIM ,Receive Timeout Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORIM ,Receive Overrun Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SSP0RIS,SSP0 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO Half Empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO Half Full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive Timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORRIS ,Frame Received When RxFIFO Full" "Not received,Received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SSP0MIS,SSP0 Masked Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXMIS ,Tx FIFO Half Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXMIS ,Rx FIFO Half Full Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RTMIS ,Receive Timeout Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORMIS ,Frame Received When RxFIFO Full Interrupt" "No interrupt,Interrupt"
|
|
sif (cpu()=="EM773"||cpuis("LPC11E*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC11U3*")||cpuis("LPC11U6*"))
|
|
wgroup.long 0x20++0x03
|
|
else
|
|
group.long 0x20++0x03
|
|
endif
|
|
line.long 0x00 "SSP0ICR,SSP0 Interrupt Clear Register"
|
|
bitfld.long 0x0 1. " RTIC ,Receive Timeout Clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " RORIC ,Clear Frame Received When RxFIFO Full" "No effect,Clear"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SSP0DMACR,SSP0 DMA Control Register"
|
|
bitfld.long 0x0 1. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSP1"
|
|
base ad:0x400C5000
|
|
width 11.
|
|
if ((per.l(ad:0x400C5000)&0x30)==0x00)
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SSP1CR0,SSP1 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock Out Phase" "First clock,Second clock"
|
|
bitfld.long 0x00 6. " CPOL ,Clock Out Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP1CR0,SSP1 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
endif
|
|
if ((per.l(ad:0x400C5000+0x04)&0x4)==0x04)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave Output Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
endif
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSP1DR,SSP1 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SSP1DR,SSP1 Data Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSP1SR,SSP1 Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO Not Empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO Not Full" "Full,Not Full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SSP1CPSR,SSP1 Clock Prescale Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CPSDVSR ,PCLK Divisor (even value between 2 and 254)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SSP1IMSC,SSP1 Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x00 3. " TXIM ,Tx FIFO Half Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIM ,Rx FIFO Half Full Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTIM ,Receive Timeout Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORIM ,Receive Overrun Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SSP1RIS,SSP1 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO Half Empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO Half Full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive Timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORRIS ,Frame Received When RxFIFO Full" "Not received,Received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SSP1MIS,SSP1 Masked Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXMIS ,Tx FIFO Half Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXMIS ,Rx FIFO Half Full Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RTMIS ,Receive Timeout Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORMIS ,Frame Received When RxFIFO Full Interrupt" "No interrupt,Interrupt"
|
|
sif (cpu()=="EM773"||cpuis("LPC11E*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC11U3*")||cpuis("LPC11U6*"))
|
|
wgroup.long 0x20++0x03
|
|
else
|
|
group.long 0x20++0x03
|
|
endif
|
|
line.long 0x00 "SSP1ICR,SSP1 Interrupt Clear Register"
|
|
bitfld.long 0x0 1. " RTIC ,Receive Timeout Clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " RORIC ,Clear Frame Received When RxFIFO Full" "No effect,Clear"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SSP1DMACR,SSP1 DMA Control Register"
|
|
bitfld.long 0x0 1. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2S interface"
|
|
tree "I2S0"
|
|
base ad:0x400A2000
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2SDAO,Digital Audio Output Register"
|
|
bitfld.long 0x00 15. " MUTE ,The transmit channel sends only zeroes" "Not muted,Muted"
|
|
hexmask.long.word 0x00 6.--14. 1. " WS_HALFPERIOD ,Word select half period minus 1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WS_SEL ,Master/Slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 4. " RESET ,Asynchronously reset the transmit channel and FIFO" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STOP ,Disables accesses on FIFOs/places the transmit channel in mute mode" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " MONO ,Data format select" "Stereo,Monaural"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WORDWIDTH ,Selects the number of bytes in data" "8 bit,16 bit,,32 bit"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "I2SDAI,Digital Audio Input Register"
|
|
hexmask.long.word 0x00 6.--14. 1. " WS_HALFPERIOD ,Word select half period minus 1"
|
|
bitfld.long 0x00 5. " WS_SEL ,Master/Slave mode select" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RESET ,Asynchronously reset the transmit channel and FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 3. " STOP ,Disables accesses on FIFOs/places the transmit channel in mute mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MONO ,Data of monaural format" "Stereo,Monaural"
|
|
bitfld.long 0x00 0.--1. " WORDWIDTH ,Selects the number of bytes in data" "8 bit,16 bit,,32 bit"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "I2STXFIFO,Transmit FIFO Register"
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "I2SRXFIFO,Receive FIFO Register"
|
|
else
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x0 "I2SRXFIFO,Receive FIFO Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "I2SSTATE,Status Feedback Register"
|
|
sif (cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*"))
|
|
bitfld.long 0x00 16.--19. " TX_LEVEL ,Current level of the Transmit FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RX_LEVEL ,Current level of the Receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 16.--18. " TX_LEVEL ,Current level of the Transmit FIFO" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " RX_LEVEL ,Current level of the Receive FIFO" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAREQ2 ,Presence of Receive or Transmit DMA Request 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DMAREQ1 ,Presence of Receive or Transmit DMA Request 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRQ ,Presence of Receive Interrupt or Transmit Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x0 "I2SDMA1,DMA Configuration Register 1"
|
|
sif (cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*"))
|
|
bitfld.long 0x00 16.--19. " TX_DEPTH_DMA1 ,Set the FIFO level that triggers a transmit DMA request on DMA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RX_DEPTH_DMA1 ,FIFO level that triggers a receive DMA request on DMA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 16.--18. " TX_DEPTH_DMA1 ,Set the FIFO level that triggers a transmit DMA request on DMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " RX_DEPTH_DMA1 ,FIFO level that triggers a receive DMA request on DMA1" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_DMA1_ENABLE ,Enables DMA1 for I2S transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_DMA1_ENABLE ,Enables DMA1 for I2S receive" "Disabled,Enabled"
|
|
line.long 0x4 "I2SDMA2,DMA Configuration Register 2"
|
|
sif (cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*"))
|
|
bitfld.long 0x04 16.--19. " TX_DEPTH_DMA2 ,FIFO level that triggers a transmit DMA request on DMA2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " RX_DEPTH_DMA2 ,FIFO level that triggers a receive DMA request on DMA2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x04 16.--18. " TX_DEPTH_DMA2 ,FIFO level that triggers a transmit DMA request on DMA2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " RX_DEPTH_DMA2 ,FIFO level that triggers a receive DMA request on DMA2" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX_DMA2_ENABLE ,Enables DMA2 for I2S transmit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RX_DMA2_ENABLE ,Enables DMA2 for I2S receive" "Disabled,Enabled"
|
|
line.long 0x8 "I2SIRQ,Interrupt Request Control Register"
|
|
sif (cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*"))
|
|
bitfld.long 0x08 16.--19. " TX_DEPTH_IRQ ,FIFO level on which to create an irq request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " RX_DEPTH_IRQ ,FIFO level on which to create an irq request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x08 16.--18. " TX_DEPTH_IRQ ,FIFO level on which to create an irq request" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " RX_DEPTH_IRQ ,FIFO level on which to create an irq request" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 1. " TX_IRQ_ENABLE ,Enables I2S transmit interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RX_IRQ_ENABLE ,Enables I2S receive interrupt" "Disabled,Enabled"
|
|
line.long 0x0c "I2STXRATE,Transmit bit (Clock) rate divider Register"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " X_DIVIDER ,I2S transmit bit rate numerator"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " Y_DIVIDER ,I2S transmit bit rate denominator"
|
|
line.long 0x10 "I2SRXRATE,Receive bit (Clock) rate divider Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " X_DIVIDER ,I2S receive bit rate numerator"
|
|
hexmask.long.byte 0x10 0.--7. 1. " Y_DIVIDER ,I2S receive bit rate denominator"
|
|
line.long 0x14 "I2STXBITRATE,Transmit Clock Bit Rate Register"
|
|
bitfld.long 0x14 0.--5. " TX_BITRATE ,I2S transmit bit rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "I2SRXBITRATE,Receive Clock Bit Rate Register"
|
|
bitfld.long 0x18 0.--5. " RX_BITRATE ,I2S receive bit rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1c "I2STXMODE,Transmit Mode Control Register"
|
|
bitfld.long 0x1c 3. " TXMCENA ,TX_MCLK output enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 2. " TX4PIN ,Transmit 4-pin mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 0.--1. " TXCLKSEL ,Clock source selection for the transmit bit clock divider" "TX fract. rate divider clk,,RX_MCLK,?..."
|
|
line.long 0x20 "I2SRXMODE,Receive Mode Control Register"
|
|
bitfld.long 0x20 3. " RXMCENA ,RX_MCLK output enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " RX4PIN ,Receive 4-pin mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--1. " RXCLKSEL ,Clock source selection for the receive bit clock divider" "RX fract. rate divider clk,,TX_MCLK,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "I2S1"
|
|
base ad:0x400A3000
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2SDAO,Digital Audio Output Register"
|
|
bitfld.long 0x00 15. " MUTE ,The transmit channel sends only zeroes" "Not muted,Muted"
|
|
hexmask.long.word 0x00 6.--14. 1. " WS_HALFPERIOD ,Word select half period minus 1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WS_SEL ,Master/Slave mode select" "Master,Slave"
|
|
bitfld.long 0x00 4. " RESET ,Asynchronously reset the transmit channel and FIFO" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STOP ,Disables accesses on FIFOs/places the transmit channel in mute mode" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " MONO ,Data format select" "Stereo,Monaural"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WORDWIDTH ,Selects the number of bytes in data" "8 bit,16 bit,,32 bit"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "I2SDAI,Digital Audio Input Register"
|
|
hexmask.long.word 0x00 6.--14. 1. " WS_HALFPERIOD ,Word select half period minus 1"
|
|
bitfld.long 0x00 5. " WS_SEL ,Master/Slave mode select" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RESET ,Asynchronously reset the transmit channel and FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 3. " STOP ,Disables accesses on FIFOs/places the transmit channel in mute mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MONO ,Data of monaural format" "Stereo,Monaural"
|
|
bitfld.long 0x00 0.--1. " WORDWIDTH ,Selects the number of bytes in data" "8 bit,16 bit,,32 bit"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "I2STXFIFO,Transmit FIFO Register"
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "I2SRXFIFO,Receive FIFO Register"
|
|
else
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x0 "I2SRXFIFO,Receive FIFO Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "I2SSTATE,Status Feedback Register"
|
|
sif (cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*"))
|
|
bitfld.long 0x00 16.--19. " TX_LEVEL ,Current level of the Transmit FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RX_LEVEL ,Current level of the Receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 16.--18. " TX_LEVEL ,Current level of the Transmit FIFO" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " RX_LEVEL ,Current level of the Receive FIFO" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAREQ2 ,Presence of Receive or Transmit DMA Request 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DMAREQ1 ,Presence of Receive or Transmit DMA Request 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRQ ,Presence of Receive Interrupt or Transmit Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x0 "I2SDMA1,DMA Configuration Register 1"
|
|
sif (cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*"))
|
|
bitfld.long 0x00 16.--19. " TX_DEPTH_DMA1 ,Set the FIFO level that triggers a transmit DMA request on DMA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RX_DEPTH_DMA1 ,FIFO level that triggers a receive DMA request on DMA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 16.--18. " TX_DEPTH_DMA1 ,Set the FIFO level that triggers a transmit DMA request on DMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " RX_DEPTH_DMA1 ,FIFO level that triggers a receive DMA request on DMA1" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_DMA1_ENABLE ,Enables DMA1 for I2S transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_DMA1_ENABLE ,Enables DMA1 for I2S receive" "Disabled,Enabled"
|
|
line.long 0x4 "I2SDMA2,DMA Configuration Register 2"
|
|
sif (cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*"))
|
|
bitfld.long 0x04 16.--19. " TX_DEPTH_DMA2 ,FIFO level that triggers a transmit DMA request on DMA2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " RX_DEPTH_DMA2 ,FIFO level that triggers a receive DMA request on DMA2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x04 16.--18. " TX_DEPTH_DMA2 ,FIFO level that triggers a transmit DMA request on DMA2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " RX_DEPTH_DMA2 ,FIFO level that triggers a receive DMA request on DMA2" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX_DMA2_ENABLE ,Enables DMA2 for I2S transmit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RX_DMA2_ENABLE ,Enables DMA2 for I2S receive" "Disabled,Enabled"
|
|
line.long 0x8 "I2SIRQ,Interrupt Request Control Register"
|
|
sif (cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*"))
|
|
bitfld.long 0x08 16.--19. " TX_DEPTH_IRQ ,FIFO level on which to create an irq request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " RX_DEPTH_IRQ ,FIFO level on which to create an irq request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x08 16.--18. " TX_DEPTH_IRQ ,FIFO level on which to create an irq request" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " RX_DEPTH_IRQ ,FIFO level on which to create an irq request" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 1. " TX_IRQ_ENABLE ,Enables I2S transmit interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RX_IRQ_ENABLE ,Enables I2S receive interrupt" "Disabled,Enabled"
|
|
line.long 0x0c "I2STXRATE,Transmit bit (Clock) rate divider Register"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " X_DIVIDER ,I2S transmit bit rate numerator"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " Y_DIVIDER ,I2S transmit bit rate denominator"
|
|
line.long 0x10 "I2SRXRATE,Receive bit (Clock) rate divider Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " X_DIVIDER ,I2S receive bit rate numerator"
|
|
hexmask.long.byte 0x10 0.--7. 1. " Y_DIVIDER ,I2S receive bit rate denominator"
|
|
line.long 0x14 "I2STXBITRATE,Transmit Clock Bit Rate Register"
|
|
bitfld.long 0x14 0.--5. " TX_BITRATE ,I2S transmit bit rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "I2SRXBITRATE,Receive Clock Bit Rate Register"
|
|
bitfld.long 0x18 0.--5. " RX_BITRATE ,I2S receive bit rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1c "I2STXMODE,Transmit Mode Control Register"
|
|
bitfld.long 0x1c 3. " TXMCENA ,TX_MCLK output enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 2. " TX4PIN ,Transmit 4-pin mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 0.--1. " TXCLKSEL ,Clock source selection for the transmit bit clock divider" "TX fract. rate divider clk,,RX_MCLK,?..."
|
|
line.long 0x20 "I2SRXMODE,Receive Mode Control Register"
|
|
bitfld.long 0x20 3. " RXMCENA ,RX_MCLK output enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " RX4PIN ,Receive 4-pin mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--1. " RXCLKSEL ,Clock source selection for the receive bit clock divider" "RX fract. rate divider clk,,TX_MCLK,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C-bus interface"
|
|
tree "I2C0"
|
|
base ad:0x400A1000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CON,I2C0 Control Register"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_set/clr ,I2C interface enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_set/clr ,START flag" "Not started,Started"
|
|
bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stop"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_set/clr ,I2C interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_set/clr ,Assert acknowledge flag" "Not asserted,Asserted"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STAT,I2C0 Status Register"
|
|
bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "Bus error/undefined,START transmitted,Repeated START transmitted,SLA+W transmitted/ACK,SLA+W transmitted/NOT ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Arbitration lost SLA+R/W/Data/NOT ACK,SLA+R transmitted/ACK,SLA+R transmitted/NOT ACK,Data received/ACK,Data received/NOT ACK,Own SLA+W received/ACK,Arbitration lost SLA+R/W/Own SLA+W received/ACK,GCA (0x00) received/ACK,Arbitration lost SLA+R/W/GCA received/ACK,Own SLV/DATA received/ACK,Own SLA/DATA received/NOT ACK,General Call/DATA received/ACK,General Call/DATA received/NOT ACK,STOP/repeated START received SLV/REC/SLV/TRX,Own SLA+R received/ACK,Arbitration lost SLA+R/W/Own SLA+R received/ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Last I2DAT transmitted/ACK,,,,,,No information/SI = 0"
|
|
newline
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "DAT,I2C0 Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
line.long 0x04 "ADR0,I2C0 Slave Address Register 0"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Slave mode address"
|
|
bitfld.long 0x04 0. " GC ,General call enable bit" "Disabled,Enabled"
|
|
line.long 0x08 "SCLH,I2C0 SCL High Duty Cycle Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL HIGH time period selection"
|
|
line.long 0x0C "SCLL,I2C0 SCL Low Duty Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SCLL ,Count for SCL LOW time period selection"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MMCTRL,I2C0 Monitor Mode Control Register"
|
|
sif cpuis("LPC1311")||cpuis("LPC1313")||cpuis("LPC1342")||cpuis("LPC1343")||cpuis("EM773")||cpuis("LPC11A02")||cpuis("LPC11A04")||cpuis("LPC11A11")||cpuis("LPC11A12")||cpuis("LPC11A13")||cpuis("LPC11A14")
|
|
bitfld.long 0x00 3. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
else
|
|
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
endif
|
|
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADR1,I2C0 Slave Address Register 1"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADR2,I2C0 Slave Address Register 2"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADR3,I2C0 Slave Address Register 3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
sif cpuis("LPC4072FBD80")||cpuis("LPC4072FET80")||cpuis("LPC4074FBD144")||cpuis("LPC4076FBD144")||cpuis("LPC4076FET180")||cpuis("LPC4078FBD100")||cpuis("LPC4078FBD144")||cpuis("LPC4078FBD208")||cpuis("LPC4078FBD80")||cpuis("LPC4078FET180")||cpuis("LPC4078FET208")||(cpu()=="LPC4088FBD144")||cpuis("LPC4088FBD208")||cpuis("LPC4088FET180")||cpuis("LPC4088FET208")||cpuis("LPC11E*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
elif cpuis("LPC111*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC112*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
else
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
in
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MASK0,I2C0 Mask Register 0"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MASK1,I2C0 Mask Register 1"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MASK2,I2C0 Mask Register 2"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MASK3,I2C0 Mask Register 3"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C1"
|
|
base ad:0x400E0000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CON,I2C1 Control Register"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_set/clr ,I2C interface enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_set/clr ,START flag" "Not started,Started"
|
|
bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stop"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_set/clr ,I2C interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_set/clr ,Assert acknowledge flag" "Not asserted,Asserted"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STAT,I2C1 Status Register"
|
|
bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "Bus error/undefined,START transmitted,Repeated START transmitted,SLA+W transmitted/ACK,SLA+W transmitted/NOT ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Arbitration lost SLA+R/W/Data/NOT ACK,SLA+R transmitted/ACK,SLA+R transmitted/NOT ACK,Data received/ACK,Data received/NOT ACK,Own SLA+W received/ACK,Arbitration lost SLA+R/W/Own SLA+W received/ACK,GCA (0x00) received/ACK,Arbitration lost SLA+R/W/GCA received/ACK,Own SLV/DATA received/ACK,Own SLA/DATA received/NOT ACK,General Call/DATA received/ACK,General Call/DATA received/NOT ACK,STOP/repeated START received SLV/REC/SLV/TRX,Own SLA+R received/ACK,Arbitration lost SLA+R/W/Own SLA+R received/ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Last I2DAT transmitted/ACK,,,,,,No information/SI = 0"
|
|
newline
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "DAT,I2C1 Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
line.long 0x04 "ADR0,I2C1 Slave Address Register 0"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Slave mode address"
|
|
bitfld.long 0x04 0. " GC ,General call enable bit" "Disabled,Enabled"
|
|
line.long 0x08 "SCLH,I2C1 SCL High Duty Cycle Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL HIGH time period selection"
|
|
line.long 0x0C "SCLL,I2C1 SCL Low Duty Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SCLL ,Count for SCL LOW time period selection"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MMCTRL,I2C1 Monitor Mode Control Register"
|
|
sif cpuis("LPC1311")||cpuis("LPC1313")||cpuis("LPC1342")||cpuis("LPC1343")||cpuis("EM773")||cpuis("LPC11A02")||cpuis("LPC11A04")||cpuis("LPC11A11")||cpuis("LPC11A12")||cpuis("LPC11A13")||cpuis("LPC11A14")
|
|
bitfld.long 0x00 3. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
else
|
|
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
endif
|
|
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADR1,I2C1 Slave Address Register 1"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADR2,I2C1 Slave Address Register 2"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADR3,I2C1 Slave Address Register 3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
sif cpuis("LPC4072FBD80")||cpuis("LPC4072FET80")||cpuis("LPC4074FBD144")||cpuis("LPC4076FBD144")||cpuis("LPC4076FET180")||cpuis("LPC4078FBD100")||cpuis("LPC4078FBD144")||cpuis("LPC4078FBD208")||cpuis("LPC4078FBD80")||cpuis("LPC4078FET180")||cpuis("LPC4078FET208")||(cpu()=="LPC4088FBD144")||cpuis("LPC4088FBD208")||cpuis("LPC4088FET180")||cpuis("LPC4088FET208")||cpuis("LPC11E*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,I2C1 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
elif cpuis("LPC111*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC112*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,I2C1 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
else
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "DATA_BUFFER,I2C1 Data Buffer Register"
|
|
in
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MASK0,I2C1 Mask Register 0"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MASK1,I2C1 Mask Register 1"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MASK2,I2C1 Mask Register 2"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MASK3,I2C1 Mask Register 3"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "CAN"
|
|
tree "C_CAN0"
|
|
base ad:0x400E2000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CANCNTL,CAN Control Register"
|
|
bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status change interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,Module interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Stopped,Started"
|
|
line.long 0x04 "CANSTAT,Status Register"
|
|
sif cpuis("LPC43*")||cpuis("LPC11C*")
|
|
rbitfld.long 0x04 7. " BOFF ,Busoff status" "Not in busoff,In busoff"
|
|
rbitfld.long 0x04 6. " EWARN ,Warning status" "No warning,Warning"
|
|
newline
|
|
rbitfld.long 0x04 5. " EPASS ,Error passive" "Active,Passive"
|
|
else
|
|
bitfld.long 0x04 7. " BOFF ,Busoff status" "Not in busoff,In busoff"
|
|
bitfld.long 0x04 6. " EWARN ,Warning status" "No warning,Warning"
|
|
newline
|
|
bitfld.long 0x04 5. " EPASS ,Error passive" "Active,Passive"
|
|
endif
|
|
bitfld.long 0x04 4. " RXOK ,Received a message successfully" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 3. " TXOK ,Transmitted a message successfully" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0.--2. " LEC ,Last error code" "No error,Stuff error,Form error,AckError,Bit1Error,Bit0Error,CRCError,Unused"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CANEC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive error passive" "Not reached,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC[6:0] ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC[7:0] ,Transmit error counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CANBT,Bit Timing Register"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " SJW ,(Re)synchronization jump width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud rate prescaler" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CANINT,Interrupt Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID ,Interrupt ID"
|
|
sif cpuis("LPC11C*")
|
|
if (((per.l(ad:0x400E2000))&0x80)==0x80)
|
|
group.long 0x014++0x03
|
|
line.long 0x00 "CANTEST,Test Register"
|
|
bitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TXD pins" "Controlled by CAN,Sample point,LOW/dominant,HIGH/recessive"
|
|
bitfld.long 0x00 4. "LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x014++0x03
|
|
line.long 0x00 "CANTEST,Test Register"
|
|
bitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TXD pins" "Controlled by CAN,Sample point,LOW/dominant,HIGH/recessive"
|
|
bitfld.long 0x00 4. "LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CANTEST,Test Register"
|
|
sif cpuis("LPC43*")
|
|
rbitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
else
|
|
bitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
endif
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TXD pins" "Controlled by CAN,Sample point,LOW/dominant,HIGH/recessive"
|
|
bitfld.long 0x00 4. "LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CANBRPE,Baud Rate Prescaler Extension Register"
|
|
bitfld.long 0x00 0.--3. " BRPE ,Baud rate prescaler extension" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CANIF1_CMDREQ,Message Interface 1 Command Request Register"
|
|
sif cpuis("LPC43*")||cpuis("LPC11C*")
|
|
rbitfld.long 0x00 15. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 15. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 0.--5. " MN ,Message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0x400E2000+0x20+0x04))&0x80)==0x80)
|
|
group.long (0x20+0x04)++0x3
|
|
line.long 0x00 "CANIF1_CMDMSK,Message Interface 1 Command Mask Register"
|
|
bitfld.long 0x00 7. " WR/RD ,Write/Read transfer" "Read,Write"
|
|
bitfld.long 0x00 6. " MASK ,Access mask bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " ARB ,Access arbitration bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " CTRL ,Access control bits" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRQST ,Access transmission request bit" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DATA_A ,Access data bytes 0-3" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " DATA_B ,Access data bytes 4-7" "Not transferred,Transferred"
|
|
else
|
|
group.long (0x20+0x04)++0x03
|
|
line.long 0x00 "CANIF1_CMDMSK,Message Interface 1 Command Mask"
|
|
bitfld.long 0x00 7. " WR/RD ,Write/Read transfer" "Read,Write"
|
|
bitfld.long 0x00 6. " MASK ,Access mask bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " ARB ,Access arbitration bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " CTRL ,Access control bits" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " NEWDAT ,Access new data bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " DATA_A ,Access data bytes 0-3" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " DATA_B ,Access data bytes 4-7" "Not transferred,Transferred"
|
|
endif
|
|
if (((per.l(ad:0x400E2000+0x20+0x14))&0x4000)==0x4000)
|
|
group.long (0x20+0x08)++0x0F
|
|
line.long 0x00 "CANIF1_MSK1,Message Interface 1 Mask Register 1"
|
|
bitfld.long 0x00 15. " MSK[15] ,Identifier mask bit 15" "Matched,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Identifier mask bit 14" "Matched,Masked"
|
|
bitfld.long 0x00 13. " [13] ,Identifier mask bit 13" "Matched,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Identifier mask bit 12" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Identifier mask bit 11" "Matched,Masked"
|
|
bitfld.long 0x00 10. " [10] ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Identifier mask bit 8" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Identifier mask bit 7" "Matched,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Identifier mask bit 4" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Identifier mask bit 3" "Matched,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x04 "CANIF1_MSK2,Message Interface 1 Mask Register 2"
|
|
bitfld.long 0x04 15. " MXTD ,Mask extend identifier" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MDIR ,Mask message direction" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x04 12. " MSK[28] ,Identifier mask bit 28" "Matched,Masked"
|
|
bitfld.long 0x04 11. " [27] ,Identifier mask bit 27" "Matched,Masked"
|
|
bitfld.long 0x04 10. " [26] ,Identifier mask bit 26" "Matched,Masked"
|
|
bitfld.long 0x04 9. " [25] ,Identifier mask bit 25" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 8. " [24] ,Identifier mask bit 24" "Matched,Masked"
|
|
bitfld.long 0x04 7. " [23] ,Identifier mask bit 23" "Matched,Masked"
|
|
bitfld.long 0x04 6. " [22] ,Identifier mask bit 22" "Matched,Masked"
|
|
bitfld.long 0x04 5. " [21] ,Identifier mask bit 21" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 4. " [20] ,Identifier mask bit 20" "Matched,Masked"
|
|
bitfld.long 0x04 3. " [19] ,Identifier mask bit 19" "Matched,Masked"
|
|
bitfld.long 0x04 2. " [18] ,Identifier mask bit 18" "Matched,Masked"
|
|
bitfld.long 0x04 1. " [17] ,Identifier mask bit 17" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 0. " [16] ,Identifier mask bit 16" "Matched,Masked"
|
|
line.long 0x08 "CANIF1_ARB1,Message Interface 1 Arbitration Register 1"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID[15:0] ,Message identifier"
|
|
line.long 0x0C "CANIF1_ARB2,Message Interface 1 Arbitration Register 2"
|
|
bitfld.long 0x0C 15. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 14. " XTD ,Extend identifier" "11-bit,29-bit"
|
|
newline
|
|
bitfld.long 0x0C 13. " DIR ,Message direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--12. 1. " ID[28:16] ,Message identifier"
|
|
else
|
|
group.long (0x20+0x08)++0x0F
|
|
line.long 0x00 "CANIF1_MSK1,Message Interface 1 Mask Register 1"
|
|
bitfld.long 0x00 10. " MSK[10] ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Identifier mask bit 8" "Matched,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Identifier mask bit 7" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Identifier mask bit 4" "Matched,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Identifier mask bit 3" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x04 "CANIF1_MSK2,Message Interface 1 Mask Register 2"
|
|
bitfld.long 0x04 15. " MXTD ,Mask extend identifier" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MDIR ,Mask message direction" "Masked,Not masked"
|
|
newline
|
|
line.long 0x08 "CANIF1_ARB1,Message Interface 1 Arbitration Register 1"
|
|
hexmask.long.word 0x08 0.--10. 1. " ID[10:0] ,Message identifier"
|
|
line.long 0x0C "CANIF1_ARB2,Message Interface 1 Arbitration Register 2"
|
|
bitfld.long 0x0C 15. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 14. " XTD ,Extend identifier" "11-bit,29-bit"
|
|
newline
|
|
bitfld.long 0x0C 13. " DIR ,Message direction" "Receive,Transmit"
|
|
newline
|
|
endif
|
|
group.long (0x20+0x18)++0x13
|
|
line.long 0x00 "CANIF1_MCTRL,Message Interface 1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--3. " DLC[3:0] ,Data length code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "CANIF1_DA1,Message Interface 1 Data A1 Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA_1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA_0 ,Data byte 0"
|
|
line.long 0x08 "CANIF1_DA2,Message Interface 1 Data A2 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_3 ,Data byte 3"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_2 ,Data byte 2"
|
|
else
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_2 ,Data byte 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_3 ,Data byte 3"
|
|
endif
|
|
line.long 0x0C "CANIF1_DB1,Message Interface 1 Data B1 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_5 ,Data byte 5"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DATA_4 ,Data byte 4"
|
|
else
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_4 ,Data byte 4"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DATA_5 ,Data byte 5"
|
|
endif
|
|
line.long 0x10 "CANIF1_DB2,Message Interface 1 Data B2 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_7 ,Data byte 7"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_6 ,Data byte 6"
|
|
else
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_6 ,Data byte 6"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_7 ,Data byte 7"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CANIF2_CMDREQ,Message Interface 2 Command Request Register"
|
|
sif cpuis("LPC43*")||cpuis("LPC11C*")
|
|
rbitfld.long 0x00 15. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 15. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 0.--5. " MN ,Message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0x400E2000+0x80+0x04))&0x80)==0x80)
|
|
group.long (0x80+0x04)++0x3
|
|
line.long 0x00 "CANIF2_CMDMSK,Message Interface 2 Command Mask Register"
|
|
bitfld.long 0x00 7. " WR/RD ,Write/Read transfer" "Read,Write"
|
|
bitfld.long 0x00 6. " MASK ,Access mask bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " ARB ,Access arbitration bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " CTRL ,Access control bits" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRQST ,Access transmission request bit" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DATA_A ,Access data bytes 0-3" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " DATA_B ,Access data bytes 4-7" "Not transferred,Transferred"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CANIF2_CMDMSK,Message Interface 2 Command Mask"
|
|
bitfld.long 0x00 7. " WR/RD ,Write/Read transfer" "Read,Write"
|
|
bitfld.long 0x00 6. " MASK ,Access mask bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " ARB ,Access arbitration bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " CTRL ,Access control bits" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " NEWDAT ,Access new data bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " DATA_A ,Access data bytes 0-3" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " DATA_B ,Access data bytes 4-7" "Not transferred,Transferred"
|
|
endif
|
|
if (((per.l(ad:0x400E2000+0x80+0x14))&0x4000)==0x4000)
|
|
group.long (0x80+0x08)++0x0F
|
|
line.long 0x00 "CANIF2_MSK1,Message Interface 2 Mask Register 1"
|
|
bitfld.long 0x00 15. " MSK[15] ,Identifier mask bit 15" "Matched,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Identifier mask bit 14" "Matched,Masked"
|
|
bitfld.long 0x00 13. " [13] ,Identifier mask bit 13" "Matched,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Identifier mask bit 12" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Identifier mask bit 11" "Matched,Masked"
|
|
bitfld.long 0x00 10. " [10] ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Identifier mask bit 8" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Identifier mask bit 7" "Matched,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Identifier mask bit 4" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Identifier mask bit 3" "Matched,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x04 "CANIF2_MSK2,Message Interface 2 Mask Register 2"
|
|
bitfld.long 0x04 15. " MXTD ,Mask extend identifier" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MDIR ,Mask message direction" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x04 12. " MSK[28] ,Identifier mask bit 28" "Matched,Masked"
|
|
bitfld.long 0x04 11. " [27] ,Identifier mask bit 27" "Matched,Masked"
|
|
bitfld.long 0x04 10. " [26] ,Identifier mask bit 26" "Matched,Masked"
|
|
bitfld.long 0x04 9. " [25] ,Identifier mask bit 25" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 8. " [24] ,Identifier mask bit 24" "Matched,Masked"
|
|
bitfld.long 0x04 7. " [23] ,Identifier mask bit 23" "Matched,Masked"
|
|
bitfld.long 0x04 6. " [22] ,Identifier mask bit 22" "Matched,Masked"
|
|
bitfld.long 0x04 5. " [21] ,Identifier mask bit 21" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 4. " [20] ,Identifier mask bit 20" "Matched,Masked"
|
|
bitfld.long 0x04 3. " [19] ,Identifier mask bit 19" "Matched,Masked"
|
|
bitfld.long 0x04 2. " [18] ,Identifier mask bit 18" "Matched,Masked"
|
|
bitfld.long 0x04 1. " [17] ,Identifier mask bit 17" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 0. " [16] ,Identifier mask bit 16" "Matched,Masked"
|
|
line.long 0x08 "CANIF2_ARB1,Message Interface 2 Arbitration Register 1"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID[15:0] ,Message identifier"
|
|
line.long 0x0C "CANIF2_ARB2,Message Interface 2 Arbitration Register 2"
|
|
bitfld.long 0x0C 15. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 14. " XTD ,Extend identifier" "11-bit,29-bit"
|
|
newline
|
|
bitfld.long 0x0C 13. " DIR ,Message direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--12. 1. " ID[28:16] ,Message identifier"
|
|
else
|
|
group.long (0x80+0x08)++0x0F
|
|
line.long 0x00 "CANIF2_MSK1,Message Interface 2 Mask Register 1"
|
|
bitfld.long 0x00 10. " MSK[10] ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Identifier mask bit 8" "Matched,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Identifier mask bit 7" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Identifier mask bit 4" "Matched,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Identifier mask bit 3" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x04 "CANIF2_MSK2,Message Interface 2 Mask Register 2"
|
|
bitfld.long 0x04 15. " MXTD ,Mask extend identifier" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MDIR ,Mask message direction" "Masked,Not masked"
|
|
newline
|
|
line.long 0x08 "CANIF2_ARB1,Message Interface 2 Arbitration Register 1"
|
|
hexmask.long.word 0x08 0.--10. 1. " ID[10:0] ,Message identifier"
|
|
line.long 0x0C "CANIF2_ARB2,Message Interface 2 Arbitration Register 2"
|
|
bitfld.long 0x0C 15. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 14. " XTD ,Extend identifier" "11-bit,29-bit"
|
|
newline
|
|
bitfld.long 0x0C 13. " DIR ,Message direction" "Receive,Transmit"
|
|
newline
|
|
endif
|
|
group.long (0x80+0x18)++0x13
|
|
line.long 0x00 "CANIF2_MCTRL,Message Interface 2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--3. " DLC[3:0] ,Data length code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "CANIF2_DA1,Message Interface 2 Data A1 Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA_1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA_0 ,Data byte 0"
|
|
line.long 0x08 "CANIF2_DA2,Message Interface 2 Data A2 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_3 ,Data byte 3"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_2 ,Data byte 2"
|
|
else
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_2 ,Data byte 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_3 ,Data byte 3"
|
|
endif
|
|
line.long 0x0C "CANIF2_DB1,Message Interface 2 Data B1 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_5 ,Data byte 5"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DATA_4 ,Data byte 4"
|
|
else
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_4 ,Data byte 4"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DATA_5 ,Data byte 5"
|
|
endif
|
|
line.long 0x10 "CANIF2_DB2,Message Interface 2 Data B2 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_7 ,Data byte 7"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_6 ,Data byte 6"
|
|
else
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_6 ,Data byte 6"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_7 ,Data byte 7"
|
|
endif
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "CANTXREQ1,Transmission Request Register 1"
|
|
bitfld.long 0x00 15. " TXRQST16 ,Transmission request bit of message object 16" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " TXRQST15 ,Transmission request bit of message object 15" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " TXRQST14 ,Transmission request bit of message object 14" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " TXRQST13 ,Transmission request bit of message object 13" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " TXRQST12 ,Transmission request bit of message object 12" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " TXRQST11 ,Transmission request bit of message object 11" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " TXRQST10 ,Transmission request bit of message object 10" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " TXRQST9 ,Transmission request bit of message object 9" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " TXRQST8 ,Transmission request bit of message object 8" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " TXRQST7 ,Transmission request bit of message object 7" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " TXRQST6 ,Transmission request bit of message object 6" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " TXRQST5 ,Transmission request bit of message object 5" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " TXRQST4 ,Transmission request bit of message object 4" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " TXRQST3 ,Transmission request bit of message object 3" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " TXRQST2 ,Transmission request bit of message object 2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " TXRQST1 ,Transmission request bit of message object 1" "Not requested,Requested"
|
|
line.long 0x04 "CANTXREQ2,Transmission Request Register 2"
|
|
bitfld.long 0x04 15. " TXRQST32 ,Transmission request bit of message object 32" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " TXRQST31 ,Transmission request bit of message object 31" "Not requested,Requested"
|
|
bitfld.long 0x04 13. " TXRQST30 ,Transmission request bit of message object 30" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " TXRQST29 ,Transmission request bit of message object 29" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " TXRQST28 ,Transmission request bit of message object 28" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " TXRQST27 ,Transmission request bit of message object 27" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " TXRQST26 ,Transmission request bit of message object 26" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " TXRQST25 ,Transmission request bit of message object 25" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " TXRQST24 ,Transmission request bit of message object 24" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " TXRQST23 ,Transmission request bit of message object 23" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " TXRQST22 ,Transmission request bit of message object 22" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " TXRQST21 ,Transmission request bit of message object 21" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " TXRQST20 ,Transmission request bit of message object 20" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " TXRQST19 ,Transmission request bit of message object 19" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " TXRQST18 ,Transmission request bit of message object 18" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " TXRQST17 ,Transmission request bit of message object 17" "Not requested,Requested"
|
|
rgroup.long 0x120++0x07
|
|
line.long 0x00 "CANND1,New Data Register 1"
|
|
bitfld.long 0x00 15. " NEWDAT16 ,New data bit of message object 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " NEWDAT15 ,New data bit of message object 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " NEWDAT14 ,New data bit of message object 14" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " NEWDAT13 ,New data bit of message object 13" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " NEWDAT12 ,New data bit of message object 12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " NEWDAT11 ,New data bit of message object 11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " NEWDAT10 ,New data bit of message object 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " NEWDAT9 ,New data bit of message object 9" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " NEWDAT8 ,New data bit of message object 8" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " NEWDAT7 ,New data bit of message object 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " NEWDAT6 ,New data bit of message object 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " NEWDAT5 ,New data bit of message object 5" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " NEWDAT4 ,New data bit of message object 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " NEWDAT3 ,New data bit of message object 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " NEWDAT2 ,New data bit of message object 2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " NEWDAT1 ,New data bit of message object 1" "Not occurred,Occurred"
|
|
line.long 0x04 "CANND2,New Data Register 2"
|
|
bitfld.long 0x04 15. " NEWDAT32 ,New data bit of message object 32" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " NEWDAT31 ,New data bit of message object 31" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " NEWDAT30 ,New data bit of message object 30" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " NEWDAT29 ,New data bit of message object 29" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 11. " NEWDAT28 ,New data bit of message object 28" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " NEWDAT27 ,New data bit of message object 27" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " NEWDAT26 ,New data bit of message object 26" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " NEWDAT25 ,New data bit of message object 25" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 7. " NEWDAT24 ,New data bit of message object 24" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " NEWDAT23 ,New data bit of message object 23" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " NEWDAT22 ,New data bit of message object 22" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " NEWDAT21 ,New data bit of message object 21" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 3. " NEWDAT20 ,New data bit of message object 20" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " NEWDAT19 ,New data bit of message object 19" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " NEWDAT18 ,New data bit of message object 18" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " NEWDAT17 ,New data bit of message object 17" "Not occurred,Occurred"
|
|
rgroup.long 0x140++0x07
|
|
line.long 0x00 "CANIR1,Interrupt Pending Register 1"
|
|
bitfld.long 0x00 15. " INTPND16 ,Interrupt pending bit of message object 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTPND15 ,Interrupt pending bit of message object 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTPND14 ,Interrupt pending bit of message object 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTPND13 ,Interrupt pending bit of message object 13" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " INTPND12 ,Interrupt pending bit of message object 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTPND11 ,Interrupt pending bit of message object 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTPND10 ,Interrupt pending bit of message object 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTPND9 ,Interrupt pending bit of message object 9" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " INTPND8 ,Interrupt pending bit of message object 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTPND7 ,Interrupt pending bit of message object 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTPND6 ,Interrupt pending bit of message object 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTPND5 ,Interrupt pending bit of message object 5" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " INTPND4 ,Interrupt pending bit of message object 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTPND3 ,Interrupt pending bit of message object 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTPND2 ,Interrupt pending bit of message object 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTPND1 ,Interrupt pending bit of message object 1" "No interrupt,Interrupt"
|
|
line.long 0x04 "CANIR2,Interrupt pending 2"
|
|
bitfld.long 0x04 15. " INTPND32 ,Interrupt pending bit of message object 32" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTPND31 ,Interrupt pending bit of message object 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " INTPND30 ,Interrupt pending bit of message object 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTPND29 ,Interrupt pending bit of message object 29" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 11. " INTPND28 ,Interrupt pending bit of message object 28" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTPND27 ,Interrupt pending bit of message object 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " INTPND26 ,Interrupt pending bit of message object 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTPND25 ,Interrupt pending bit of message object 25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " INTPND24 ,Interrupt pending bit of message object 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTPND23 ,Interrupt pending bit of message object 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTPND22 ,Interrupt pending bit of message object 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTPND21 ,Interrupt pending bit of message object 21" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " INTPND20 ,Interrupt pending bit of message object 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTPND19 ,Interrupt pending bit of message object 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTPND18 ,Interrupt pending bit of message object 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTPND17 ,Interrupt pending bit of message object 17" "No interrupt,Interrupt"
|
|
rgroup.long 0x160++0x07
|
|
line.long 0x00 "CANMSGV1,Message Valid Register 1"
|
|
bitfld.long 0x00 15. " MSGVAL16 ,Message valid bit of message object 16" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " MSGVAL15 ,Message valid bit of message object 15" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " MSGVAL14 ,Message valid bit of message object 14" "Not valid,Valid"
|
|
bitfld.long 0x00 12. " MSGVAL13 ,Message valid bit of message object 13" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " MSGVAL12 ,Message valid bit of message object 12" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " MSGVAL11 ,Message valid bit of message object 11" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " MSGVAL10 ,Message valid bit of message object 10" "Not valid,Valid"
|
|
bitfld.long 0x00 8. " MSGVAL9 ,Message valid bit of message object 9" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 7. " MSGVAL8 ,Message valid bit of message object 8" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " MSGVAL7 ,Message valid bit of message object 7" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " MSGVAL6 ,Message valid bit of message object 6" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " MSGVAL5 ,Message valid bit of message object 5" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 3. " MSGVAL4 ,Message valid bit of message object 4" "Not valid,Valid"
|
|
bitfld.long 0x00 2. " MSGVAL3 ,Message valid bit of message object 3" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " MSGVAL2 ,Message valid bit of message object 2" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " MSGVAL1 ,Message valid bit of message object 1" "Not valid,Valid"
|
|
line.long 0x04 "CANMSGV2,Message Valid Register 2"
|
|
bitfld.long 0x04 15. " MSGVAL32 ,Message valid bit of message object 32" "Not valid,Valid"
|
|
bitfld.long 0x04 14. " MSGVAL31 ,Message valid bit of message object 31" "Not valid,Valid"
|
|
bitfld.long 0x04 13. " MSGVAL30 ,Message valid bit of message object 30" "Not valid,Valid"
|
|
bitfld.long 0x04 12. " MSGVAL29 ,Message valid bit of message object 29" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x04 11. " MSGVAL28 ,Message valid bit of message object 28" "Not valid,Valid"
|
|
bitfld.long 0x04 10. " MSGVAL27 ,Message valid bit of message object 27" "Not valid,Valid"
|
|
bitfld.long 0x04 9. " MSGVAL26 ,Message valid bit of message object 26" "Not valid,Valid"
|
|
bitfld.long 0x04 8. " MSGVAL25 ,Message valid bit of message object 25" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x04 7. " MSGVAL24 ,Message valid bit of message object 24" "Not valid,Valid"
|
|
bitfld.long 0x04 6. " MSGVAL23 ,Message valid bit of message object 23" "Not valid,Valid"
|
|
bitfld.long 0x04 5. " MSGVAL22 ,Message valid bit of message object 22" "Not valid,Valid"
|
|
bitfld.long 0x04 4. " MSGVAL21 ,Message valid bit of message object 21" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x04 3. " MSGVAL20 ,Message valid bit of message object 20" "Not valid,Valid"
|
|
bitfld.long 0x04 2. " MSGVAL19 ,Message valid bit of message object 19" "Not valid,Valid"
|
|
bitfld.long 0x04 1. " MSGVAL18 ,Message valid bit of message object 18" "Not valid,Valid"
|
|
bitfld.long 0x04 0. " MSGVAL17 ,Message valid bit of message object 17" "Not valid,Valid"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CANCLKDIV,Can Clock Divider Register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 0.--3. " CLKDIVVAL ,Clock divider value" "/1,/2,/3,/5,/9,/17,/33,/65,/129,/257,/513,/1025,/2049,/4097,/8193,/16385"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CLKDIVVAL ,Clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "C_CAN1"
|
|
base ad:0x400A4000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CANCNTL,CAN Control Register"
|
|
bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status change interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,Module interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Stopped,Started"
|
|
line.long 0x04 "CANSTAT,Status Register"
|
|
sif cpuis("LPC43*")||cpuis("LPC11C*")
|
|
rbitfld.long 0x04 7. " BOFF ,Busoff status" "Not in busoff,In busoff"
|
|
rbitfld.long 0x04 6. " EWARN ,Warning status" "No warning,Warning"
|
|
newline
|
|
rbitfld.long 0x04 5. " EPASS ,Error passive" "Active,Passive"
|
|
else
|
|
bitfld.long 0x04 7. " BOFF ,Busoff status" "Not in busoff,In busoff"
|
|
bitfld.long 0x04 6. " EWARN ,Warning status" "No warning,Warning"
|
|
newline
|
|
bitfld.long 0x04 5. " EPASS ,Error passive" "Active,Passive"
|
|
endif
|
|
bitfld.long 0x04 4. " RXOK ,Received a message successfully" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 3. " TXOK ,Transmitted a message successfully" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0.--2. " LEC ,Last error code" "No error,Stuff error,Form error,AckError,Bit1Error,Bit0Error,CRCError,Unused"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CANEC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive error passive" "Not reached,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC[6:0] ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC[7:0] ,Transmit error counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CANBT,Bit Timing Register"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " SJW ,(Re)synchronization jump width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud rate prescaler" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CANINT,Interrupt Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID ,Interrupt ID"
|
|
sif cpuis("LPC11C*")
|
|
if (((per.l(ad:0x400A4000))&0x80)==0x80)
|
|
group.long 0x014++0x03
|
|
line.long 0x00 "CANTEST,Test Register"
|
|
bitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TXD pins" "Controlled by CAN,Sample point,LOW/dominant,HIGH/recessive"
|
|
bitfld.long 0x00 4. "LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x014++0x03
|
|
line.long 0x00 "CANTEST,Test Register"
|
|
bitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TXD pins" "Controlled by CAN,Sample point,LOW/dominant,HIGH/recessive"
|
|
bitfld.long 0x00 4. "LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CANTEST,Test Register"
|
|
sif cpuis("LPC43*")
|
|
rbitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
else
|
|
bitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
endif
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TXD pins" "Controlled by CAN,Sample point,LOW/dominant,HIGH/recessive"
|
|
bitfld.long 0x00 4. "LBACK ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CANBRPE,Baud Rate Prescaler Extension Register"
|
|
bitfld.long 0x00 0.--3. " BRPE ,Baud rate prescaler extension" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CANIF1_CMDREQ,Message Interface 1 Command Request Register"
|
|
sif cpuis("LPC43*")||cpuis("LPC11C*")
|
|
rbitfld.long 0x00 15. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 15. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 0.--5. " MN ,Message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0x400A4000+0x20+0x04))&0x80)==0x80)
|
|
group.long (0x20+0x04)++0x3
|
|
line.long 0x00 "CANIF1_CMDMSK,Message Interface 1 Command Mask Register"
|
|
bitfld.long 0x00 7. " WR/RD ,Write/Read transfer" "Read,Write"
|
|
bitfld.long 0x00 6. " MASK ,Access mask bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " ARB ,Access arbitration bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " CTRL ,Access control bits" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRQST ,Access transmission request bit" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DATA_A ,Access data bytes 0-3" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " DATA_B ,Access data bytes 4-7" "Not transferred,Transferred"
|
|
else
|
|
group.long (0x20+0x04)++0x03
|
|
line.long 0x00 "CANIF1_CMDMSK,Message Interface 1 Command Mask"
|
|
bitfld.long 0x00 7. " WR/RD ,Write/Read transfer" "Read,Write"
|
|
bitfld.long 0x00 6. " MASK ,Access mask bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " ARB ,Access arbitration bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " CTRL ,Access control bits" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " NEWDAT ,Access new data bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " DATA_A ,Access data bytes 0-3" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " DATA_B ,Access data bytes 4-7" "Not transferred,Transferred"
|
|
endif
|
|
if (((per.l(ad:0x400A4000+0x20+0x14))&0x4000)==0x4000)
|
|
group.long (0x20+0x08)++0x0F
|
|
line.long 0x00 "CANIF1_MSK1,Message Interface 1 Mask Register 1"
|
|
bitfld.long 0x00 15. " MSK[15] ,Identifier mask bit 15" "Matched,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Identifier mask bit 14" "Matched,Masked"
|
|
bitfld.long 0x00 13. " [13] ,Identifier mask bit 13" "Matched,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Identifier mask bit 12" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Identifier mask bit 11" "Matched,Masked"
|
|
bitfld.long 0x00 10. " [10] ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Identifier mask bit 8" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Identifier mask bit 7" "Matched,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Identifier mask bit 4" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Identifier mask bit 3" "Matched,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x04 "CANIF1_MSK2,Message Interface 1 Mask Register 2"
|
|
bitfld.long 0x04 15. " MXTD ,Mask extend identifier" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MDIR ,Mask message direction" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x04 12. " MSK[28] ,Identifier mask bit 28" "Matched,Masked"
|
|
bitfld.long 0x04 11. " [27] ,Identifier mask bit 27" "Matched,Masked"
|
|
bitfld.long 0x04 10. " [26] ,Identifier mask bit 26" "Matched,Masked"
|
|
bitfld.long 0x04 9. " [25] ,Identifier mask bit 25" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 8. " [24] ,Identifier mask bit 24" "Matched,Masked"
|
|
bitfld.long 0x04 7. " [23] ,Identifier mask bit 23" "Matched,Masked"
|
|
bitfld.long 0x04 6. " [22] ,Identifier mask bit 22" "Matched,Masked"
|
|
bitfld.long 0x04 5. " [21] ,Identifier mask bit 21" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 4. " [20] ,Identifier mask bit 20" "Matched,Masked"
|
|
bitfld.long 0x04 3. " [19] ,Identifier mask bit 19" "Matched,Masked"
|
|
bitfld.long 0x04 2. " [18] ,Identifier mask bit 18" "Matched,Masked"
|
|
bitfld.long 0x04 1. " [17] ,Identifier mask bit 17" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 0. " [16] ,Identifier mask bit 16" "Matched,Masked"
|
|
line.long 0x08 "CANIF1_ARB1,Message Interface 1 Arbitration Register 1"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID[15:0] ,Message identifier"
|
|
line.long 0x0C "CANIF1_ARB2,Message Interface 1 Arbitration Register 2"
|
|
bitfld.long 0x0C 15. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 14. " XTD ,Extend identifier" "11-bit,29-bit"
|
|
newline
|
|
bitfld.long 0x0C 13. " DIR ,Message direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--12. 1. " ID[28:16] ,Message identifier"
|
|
else
|
|
group.long (0x20+0x08)++0x0F
|
|
line.long 0x00 "CANIF1_MSK1,Message Interface 1 Mask Register 1"
|
|
bitfld.long 0x00 10. " MSK[10] ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Identifier mask bit 8" "Matched,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Identifier mask bit 7" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Identifier mask bit 4" "Matched,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Identifier mask bit 3" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x04 "CANIF1_MSK2,Message Interface 1 Mask Register 2"
|
|
bitfld.long 0x04 15. " MXTD ,Mask extend identifier" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MDIR ,Mask message direction" "Masked,Not masked"
|
|
newline
|
|
line.long 0x08 "CANIF1_ARB1,Message Interface 1 Arbitration Register 1"
|
|
hexmask.long.word 0x08 0.--10. 1. " ID[10:0] ,Message identifier"
|
|
line.long 0x0C "CANIF1_ARB2,Message Interface 1 Arbitration Register 2"
|
|
bitfld.long 0x0C 15. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 14. " XTD ,Extend identifier" "11-bit,29-bit"
|
|
newline
|
|
bitfld.long 0x0C 13. " DIR ,Message direction" "Receive,Transmit"
|
|
newline
|
|
endif
|
|
group.long (0x20+0x18)++0x13
|
|
line.long 0x00 "CANIF1_MCTRL,Message Interface 1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--3. " DLC[3:0] ,Data length code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "CANIF1_DA1,Message Interface 1 Data A1 Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA_1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA_0 ,Data byte 0"
|
|
line.long 0x08 "CANIF1_DA2,Message Interface 1 Data A2 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_3 ,Data byte 3"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_2 ,Data byte 2"
|
|
else
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_2 ,Data byte 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_3 ,Data byte 3"
|
|
endif
|
|
line.long 0x0C "CANIF1_DB1,Message Interface 1 Data B1 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_5 ,Data byte 5"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DATA_4 ,Data byte 4"
|
|
else
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_4 ,Data byte 4"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DATA_5 ,Data byte 5"
|
|
endif
|
|
line.long 0x10 "CANIF1_DB2,Message Interface 1 Data B2 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_7 ,Data byte 7"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_6 ,Data byte 6"
|
|
else
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_6 ,Data byte 6"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_7 ,Data byte 7"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CANIF2_CMDREQ,Message Interface 2 Command Request Register"
|
|
sif cpuis("LPC43*")||cpuis("LPC11C*")
|
|
rbitfld.long 0x00 15. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 15. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 0.--5. " MN ,Message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0x400A4000+0x80+0x04))&0x80)==0x80)
|
|
group.long (0x80+0x04)++0x3
|
|
line.long 0x00 "CANIF2_CMDMSK,Message Interface 2 Command Mask Register"
|
|
bitfld.long 0x00 7. " WR/RD ,Write/Read transfer" "Read,Write"
|
|
bitfld.long 0x00 6. " MASK ,Access mask bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " ARB ,Access arbitration bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " CTRL ,Access control bits" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRQST ,Access transmission request bit" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DATA_A ,Access data bytes 0-3" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " DATA_B ,Access data bytes 4-7" "Not transferred,Transferred"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CANIF2_CMDMSK,Message Interface 2 Command Mask"
|
|
bitfld.long 0x00 7. " WR/RD ,Write/Read transfer" "Read,Write"
|
|
bitfld.long 0x00 6. " MASK ,Access mask bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " ARB ,Access arbitration bits" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " CTRL ,Access control bits" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " NEWDAT ,Access new data bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " DATA_A ,Access data bytes 0-3" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " DATA_B ,Access data bytes 4-7" "Not transferred,Transferred"
|
|
endif
|
|
if (((per.l(ad:0x400A4000+0x80+0x14))&0x4000)==0x4000)
|
|
group.long (0x80+0x08)++0x0F
|
|
line.long 0x00 "CANIF2_MSK1,Message Interface 2 Mask Register 1"
|
|
bitfld.long 0x00 15. " MSK[15] ,Identifier mask bit 15" "Matched,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Identifier mask bit 14" "Matched,Masked"
|
|
bitfld.long 0x00 13. " [13] ,Identifier mask bit 13" "Matched,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Identifier mask bit 12" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Identifier mask bit 11" "Matched,Masked"
|
|
bitfld.long 0x00 10. " [10] ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Identifier mask bit 8" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Identifier mask bit 7" "Matched,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Identifier mask bit 4" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Identifier mask bit 3" "Matched,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x04 "CANIF2_MSK2,Message Interface 2 Mask Register 2"
|
|
bitfld.long 0x04 15. " MXTD ,Mask extend identifier" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MDIR ,Mask message direction" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x04 12. " MSK[28] ,Identifier mask bit 28" "Matched,Masked"
|
|
bitfld.long 0x04 11. " [27] ,Identifier mask bit 27" "Matched,Masked"
|
|
bitfld.long 0x04 10. " [26] ,Identifier mask bit 26" "Matched,Masked"
|
|
bitfld.long 0x04 9. " [25] ,Identifier mask bit 25" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 8. " [24] ,Identifier mask bit 24" "Matched,Masked"
|
|
bitfld.long 0x04 7. " [23] ,Identifier mask bit 23" "Matched,Masked"
|
|
bitfld.long 0x04 6. " [22] ,Identifier mask bit 22" "Matched,Masked"
|
|
bitfld.long 0x04 5. " [21] ,Identifier mask bit 21" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 4. " [20] ,Identifier mask bit 20" "Matched,Masked"
|
|
bitfld.long 0x04 3. " [19] ,Identifier mask bit 19" "Matched,Masked"
|
|
bitfld.long 0x04 2. " [18] ,Identifier mask bit 18" "Matched,Masked"
|
|
bitfld.long 0x04 1. " [17] ,Identifier mask bit 17" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x04 0. " [16] ,Identifier mask bit 16" "Matched,Masked"
|
|
line.long 0x08 "CANIF2_ARB1,Message Interface 2 Arbitration Register 1"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID[15:0] ,Message identifier"
|
|
line.long 0x0C "CANIF2_ARB2,Message Interface 2 Arbitration Register 2"
|
|
bitfld.long 0x0C 15. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 14. " XTD ,Extend identifier" "11-bit,29-bit"
|
|
newline
|
|
bitfld.long 0x0C 13. " DIR ,Message direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--12. 1. " ID[28:16] ,Message identifier"
|
|
else
|
|
group.long (0x80+0x08)++0x0F
|
|
line.long 0x00 "CANIF2_MSK1,Message Interface 2 Mask Register 1"
|
|
bitfld.long 0x00 10. " MSK[10] ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Identifier mask bit 8" "Matched,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Identifier mask bit 7" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Identifier mask bit 4" "Matched,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Identifier mask bit 3" "Matched,Masked"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x04 "CANIF2_MSK2,Message Interface 2 Mask Register 2"
|
|
bitfld.long 0x04 15. " MXTD ,Mask extend identifier" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MDIR ,Mask message direction" "Masked,Not masked"
|
|
newline
|
|
line.long 0x08 "CANIF2_ARB1,Message Interface 2 Arbitration Register 1"
|
|
hexmask.long.word 0x08 0.--10. 1. " ID[10:0] ,Message identifier"
|
|
line.long 0x0C "CANIF2_ARB2,Message Interface 2 Arbitration Register 2"
|
|
bitfld.long 0x0C 15. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 14. " XTD ,Extend identifier" "11-bit,29-bit"
|
|
newline
|
|
bitfld.long 0x0C 13. " DIR ,Message direction" "Receive,Transmit"
|
|
newline
|
|
endif
|
|
group.long (0x80+0x18)++0x13
|
|
line.long 0x00 "CANIF2_MCTRL,Message Interface 2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--3. " DLC[3:0] ,Data length code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "CANIF2_DA1,Message Interface 2 Data A1 Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA_1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA_0 ,Data byte 0"
|
|
line.long 0x08 "CANIF2_DA2,Message Interface 2 Data A2 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_3 ,Data byte 3"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_2 ,Data byte 2"
|
|
else
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_2 ,Data byte 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_3 ,Data byte 3"
|
|
endif
|
|
line.long 0x0C "CANIF2_DB1,Message Interface 2 Data B1 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_5 ,Data byte 5"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DATA_4 ,Data byte 4"
|
|
else
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DATA_4 ,Data byte 4"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DATA_5 ,Data byte 5"
|
|
endif
|
|
line.long 0x10 "CANIF2_DB2,Message Interface 2 Data B2 Register"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_7 ,Data byte 7"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_6 ,Data byte 6"
|
|
else
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_6 ,Data byte 6"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_7 ,Data byte 7"
|
|
endif
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "CANTXREQ1,Transmission Request Register 1"
|
|
bitfld.long 0x00 15. " TXRQST16 ,Transmission request bit of message object 16" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " TXRQST15 ,Transmission request bit of message object 15" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " TXRQST14 ,Transmission request bit of message object 14" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " TXRQST13 ,Transmission request bit of message object 13" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " TXRQST12 ,Transmission request bit of message object 12" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " TXRQST11 ,Transmission request bit of message object 11" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " TXRQST10 ,Transmission request bit of message object 10" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " TXRQST9 ,Transmission request bit of message object 9" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " TXRQST8 ,Transmission request bit of message object 8" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " TXRQST7 ,Transmission request bit of message object 7" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " TXRQST6 ,Transmission request bit of message object 6" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " TXRQST5 ,Transmission request bit of message object 5" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " TXRQST4 ,Transmission request bit of message object 4" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " TXRQST3 ,Transmission request bit of message object 3" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " TXRQST2 ,Transmission request bit of message object 2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " TXRQST1 ,Transmission request bit of message object 1" "Not requested,Requested"
|
|
line.long 0x04 "CANTXREQ2,Transmission Request Register 2"
|
|
bitfld.long 0x04 15. " TXRQST32 ,Transmission request bit of message object 32" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " TXRQST31 ,Transmission request bit of message object 31" "Not requested,Requested"
|
|
bitfld.long 0x04 13. " TXRQST30 ,Transmission request bit of message object 30" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " TXRQST29 ,Transmission request bit of message object 29" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " TXRQST28 ,Transmission request bit of message object 28" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " TXRQST27 ,Transmission request bit of message object 27" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " TXRQST26 ,Transmission request bit of message object 26" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " TXRQST25 ,Transmission request bit of message object 25" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " TXRQST24 ,Transmission request bit of message object 24" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " TXRQST23 ,Transmission request bit of message object 23" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " TXRQST22 ,Transmission request bit of message object 22" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " TXRQST21 ,Transmission request bit of message object 21" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " TXRQST20 ,Transmission request bit of message object 20" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " TXRQST19 ,Transmission request bit of message object 19" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " TXRQST18 ,Transmission request bit of message object 18" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " TXRQST17 ,Transmission request bit of message object 17" "Not requested,Requested"
|
|
rgroup.long 0x120++0x07
|
|
line.long 0x00 "CANND1,New Data Register 1"
|
|
bitfld.long 0x00 15. " NEWDAT16 ,New data bit of message object 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " NEWDAT15 ,New data bit of message object 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " NEWDAT14 ,New data bit of message object 14" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " NEWDAT13 ,New data bit of message object 13" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " NEWDAT12 ,New data bit of message object 12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " NEWDAT11 ,New data bit of message object 11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " NEWDAT10 ,New data bit of message object 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " NEWDAT9 ,New data bit of message object 9" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " NEWDAT8 ,New data bit of message object 8" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " NEWDAT7 ,New data bit of message object 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " NEWDAT6 ,New data bit of message object 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " NEWDAT5 ,New data bit of message object 5" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " NEWDAT4 ,New data bit of message object 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " NEWDAT3 ,New data bit of message object 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " NEWDAT2 ,New data bit of message object 2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " NEWDAT1 ,New data bit of message object 1" "Not occurred,Occurred"
|
|
line.long 0x04 "CANND2,New Data Register 2"
|
|
bitfld.long 0x04 15. " NEWDAT32 ,New data bit of message object 32" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " NEWDAT31 ,New data bit of message object 31" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " NEWDAT30 ,New data bit of message object 30" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " NEWDAT29 ,New data bit of message object 29" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 11. " NEWDAT28 ,New data bit of message object 28" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " NEWDAT27 ,New data bit of message object 27" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " NEWDAT26 ,New data bit of message object 26" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " NEWDAT25 ,New data bit of message object 25" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 7. " NEWDAT24 ,New data bit of message object 24" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " NEWDAT23 ,New data bit of message object 23" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " NEWDAT22 ,New data bit of message object 22" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " NEWDAT21 ,New data bit of message object 21" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 3. " NEWDAT20 ,New data bit of message object 20" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " NEWDAT19 ,New data bit of message object 19" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " NEWDAT18 ,New data bit of message object 18" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " NEWDAT17 ,New data bit of message object 17" "Not occurred,Occurred"
|
|
rgroup.long 0x140++0x07
|
|
line.long 0x00 "CANIR1,Interrupt Pending Register 1"
|
|
bitfld.long 0x00 15. " INTPND16 ,Interrupt pending bit of message object 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INTPND15 ,Interrupt pending bit of message object 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " INTPND14 ,Interrupt pending bit of message object 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INTPND13 ,Interrupt pending bit of message object 13" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " INTPND12 ,Interrupt pending bit of message object 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INTPND11 ,Interrupt pending bit of message object 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " INTPND10 ,Interrupt pending bit of message object 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INTPND9 ,Interrupt pending bit of message object 9" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " INTPND8 ,Interrupt pending bit of message object 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INTPND7 ,Interrupt pending bit of message object 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INTPND6 ,Interrupt pending bit of message object 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INTPND5 ,Interrupt pending bit of message object 5" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " INTPND4 ,Interrupt pending bit of message object 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTPND3 ,Interrupt pending bit of message object 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTPND2 ,Interrupt pending bit of message object 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTPND1 ,Interrupt pending bit of message object 1" "No interrupt,Interrupt"
|
|
line.long 0x04 "CANIR2,Interrupt pending 2"
|
|
bitfld.long 0x04 15. " INTPND32 ,Interrupt pending bit of message object 32" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTPND31 ,Interrupt pending bit of message object 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " INTPND30 ,Interrupt pending bit of message object 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTPND29 ,Interrupt pending bit of message object 29" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 11. " INTPND28 ,Interrupt pending bit of message object 28" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTPND27 ,Interrupt pending bit of message object 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " INTPND26 ,Interrupt pending bit of message object 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTPND25 ,Interrupt pending bit of message object 25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " INTPND24 ,Interrupt pending bit of message object 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTPND23 ,Interrupt pending bit of message object 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTPND22 ,Interrupt pending bit of message object 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTPND21 ,Interrupt pending bit of message object 21" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " INTPND20 ,Interrupt pending bit of message object 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTPND19 ,Interrupt pending bit of message object 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTPND18 ,Interrupt pending bit of message object 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTPND17 ,Interrupt pending bit of message object 17" "No interrupt,Interrupt"
|
|
rgroup.long 0x160++0x07
|
|
line.long 0x00 "CANMSGV1,Message Valid Register 1"
|
|
bitfld.long 0x00 15. " MSGVAL16 ,Message valid bit of message object 16" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " MSGVAL15 ,Message valid bit of message object 15" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " MSGVAL14 ,Message valid bit of message object 14" "Not valid,Valid"
|
|
bitfld.long 0x00 12. " MSGVAL13 ,Message valid bit of message object 13" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 11. " MSGVAL12 ,Message valid bit of message object 12" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " MSGVAL11 ,Message valid bit of message object 11" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " MSGVAL10 ,Message valid bit of message object 10" "Not valid,Valid"
|
|
bitfld.long 0x00 8. " MSGVAL9 ,Message valid bit of message object 9" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 7. " MSGVAL8 ,Message valid bit of message object 8" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " MSGVAL7 ,Message valid bit of message object 7" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " MSGVAL6 ,Message valid bit of message object 6" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " MSGVAL5 ,Message valid bit of message object 5" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 3. " MSGVAL4 ,Message valid bit of message object 4" "Not valid,Valid"
|
|
bitfld.long 0x00 2. " MSGVAL3 ,Message valid bit of message object 3" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " MSGVAL2 ,Message valid bit of message object 2" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " MSGVAL1 ,Message valid bit of message object 1" "Not valid,Valid"
|
|
line.long 0x04 "CANMSGV2,Message Valid Register 2"
|
|
bitfld.long 0x04 15. " MSGVAL32 ,Message valid bit of message object 32" "Not valid,Valid"
|
|
bitfld.long 0x04 14. " MSGVAL31 ,Message valid bit of message object 31" "Not valid,Valid"
|
|
bitfld.long 0x04 13. " MSGVAL30 ,Message valid bit of message object 30" "Not valid,Valid"
|
|
bitfld.long 0x04 12. " MSGVAL29 ,Message valid bit of message object 29" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x04 11. " MSGVAL28 ,Message valid bit of message object 28" "Not valid,Valid"
|
|
bitfld.long 0x04 10. " MSGVAL27 ,Message valid bit of message object 27" "Not valid,Valid"
|
|
bitfld.long 0x04 9. " MSGVAL26 ,Message valid bit of message object 26" "Not valid,Valid"
|
|
bitfld.long 0x04 8. " MSGVAL25 ,Message valid bit of message object 25" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x04 7. " MSGVAL24 ,Message valid bit of message object 24" "Not valid,Valid"
|
|
bitfld.long 0x04 6. " MSGVAL23 ,Message valid bit of message object 23" "Not valid,Valid"
|
|
bitfld.long 0x04 5. " MSGVAL22 ,Message valid bit of message object 22" "Not valid,Valid"
|
|
bitfld.long 0x04 4. " MSGVAL21 ,Message valid bit of message object 21" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x04 3. " MSGVAL20 ,Message valid bit of message object 20" "Not valid,Valid"
|
|
bitfld.long 0x04 2. " MSGVAL19 ,Message valid bit of message object 19" "Not valid,Valid"
|
|
bitfld.long 0x04 1. " MSGVAL18 ,Message valid bit of message object 18" "Not valid,Valid"
|
|
bitfld.long 0x04 0. " MSGVAL17 ,Message valid bit of message object 17" "Not valid,Valid"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CANCLKDIV,Can Clock Divider Register"
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 0.--3. " CLKDIVVAL ,Clock divider value" "/1,/2,/3,/5,/9,/17,/33,/65,/129,/257,/513,/1025,/2049,/4097,/8193,/16385"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CLKDIVVAL ,Clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "ADC"
|
|
tree "10-bit ADC0"
|
|
base ad:0x400E3000
|
|
width 9.
|
|
if ((per.long(ad:0x400E3000)&0x08000000)==0x08000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AD0CR,A/D Control Register"
|
|
bitfld.long 0x00 27. " EDGE ,Start Conversion Edge" "Rising,Falling"
|
|
textline " "
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC11D14"||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PPIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PPIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
elif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,,,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on P2.10,Falling edge on P1.27,Falling edge on MAT0.1,Falling edge on MAT0.3,Falling edge on MAT1.0,Falling edge on MAT1.1"
|
|
elif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on CTOUT_15,Falling edge on CTOUT_8,Falling edge on ADCTRIG0,Falling edge on ADCTRIG1,Falling edge on MCOA2,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
endif
|
|
sif (!cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDN ,A/D Power" "Power-down,Operational"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BURST ,Conversion Control Mode" "Software,Repeated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock Divider"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " AD.7 ,AD.7 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " AD.6 ,AD.6 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AD.5 ,AD.5 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " AD.3 ,AD.3 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " AD.2 ,AD.2 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AD.1 ,AD.1 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " AD.0 ,AD.0 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AD0CR,A/D Control Register"
|
|
bitfld.long 0x00 27. " EDGE ,Start Conversion Edge" "Rising,Falling"
|
|
textline " "
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PPIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PPIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
elif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,,,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 23.--26. " START ,Start Conversion Control" "No start,,Start,,ATRG0,Analog comparator output,ATRG1,,CT32B0_MAT0,,CT32B0_MAT1,,CT16B0_MAT0,,CT16B0_MAT1,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on P2.10,Rising edge on P1.27,Rising edge on MAT0.1,Rising edge on MAT0.3,Rising edge on MAT1.0,Rising edge on MAT1.1"
|
|
elif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on CTOUT_15,Rising edge on CTOUT_8,Rising edge on ADCTRIG0,Rising edge on ADCTRIG1,Rising edge on MCOA2,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
endif
|
|
sif !cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDN ,A/D Power" "Power-down,Operational"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BURST ,Conversion Control Mode" "Software,Repeated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock Divider"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " AD.7 ,AD.7 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " AD.6 ,AD.6 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AD.5 ,AD.5 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " AD.3 ,AD.3 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " AD.2 ,AD.2 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AD.1 ,AD.1 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " AD.0 ,AD.0 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "AD0GDR,A/D Global Data Register"
|
|
in
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SEL,A/D Select Register"
|
|
bitfld.long 0x00 14.--15. " AD7SEL ,This field selects the source signal for channel 7" "AD7,No signal,Temperature sensor,?..."
|
|
bitfld.long 0x00 12.--13. " AD6SEL ,This field selects the source signal for channel 6" "AD6,no signal,Internal voltage reference,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " AD5SEL ,This field selects the source signal for channel 5" "AD5,No signal,Core voltage regulator output,?..."
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "AD0INTEN,A/D Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " ADGINTEN ,Source of Generate Interrupt" "Individual,Global"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " ADINTEN7 ,Interrupt when Conversion on Channel 7 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ADINTEN6 ,Interrupt when Conversion on Channel 6 Completed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADINTEN5 ,Interrupt when Conversion on Channel 5 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ADINTEN4 ,Interrupt when Conversion on Channel 4 Completed" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADINTEN4 ,Interrupt when Conversion on Channel 4 Completed" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADINTEN3 ,Interrupt when Conversion on Channel 3 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ADINTEN2 ,Interrupt when Conversion on Channel 2 Completed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADINTEN1 ,Interrupt when Conversion on Channel 1 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ADINTEN0 ,Interrupt when Conversion on Channel 0 Completed" "No interrupt,Interrupt"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "AD0DR0,A/D Data Register"
|
|
in
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "AD0DR1,A/D Data Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "AD0DR2,A/D Data Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "AD0DR3,A/D Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "AD0DR4,A/D Data Register"
|
|
in
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "AD0DR5,A/D Data Register"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "AD0DR6,A/D Data Register"
|
|
in
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "AD0DR7,A/D Data Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "AD0STAT,A/D Status Register"
|
|
bitfld.long 0x00 16. " ADINT ,A/D Interrupt Flag" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 15. " OVERRUN7 ,Mirrors OVERRUN Status Flag for Channel 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " OVERRUN6 ,Mirrors OVERRUN Status Flag for Channel 6" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OVERRUN5 ,Mirrors OVERRUN Status Flag for Channel 5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " OVERRUN4 ,Mirrors OVERRUN Status Flag for Channel 4" "Not occurred,Occurred"
|
|
else
|
|
bitfld.long 0x00 12. " OVERRUN4 ,Mirrors OVERRUN Status Flag for Channel 4" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " OVERRUN3 ,Mirrors OVERRUN Status Flag for Channel 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " OVERRUN2 ,Mirrors OVERRUN Status Flag for Channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OVERRUN1 ,Mirrors OVERRUN Status Flag for Channel 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " OVERRUN0 ,Mirrors OVERRUN Status Flag for Channel 0" "Not occurred,Occurred"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " DONE7 ,Mirrors DONE Status Flag for Channel 7" "Not done,Done"
|
|
bitfld.long 0x00 6. " DONE6 ,Mirrors DONE Status Flag for Channel 6" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DONE5 ,Mirrors DONE Status Flag for Channel 5" "Not done,Done"
|
|
bitfld.long 0x00 4. " DONE4 ,Mirrors DONE Status Flag for Channel 4" "Not done,Done"
|
|
else
|
|
bitfld.long 0x00 4. " DONE4 ,Mirrors DONE Status Flag for Channel 4" "Not done,Done"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " DONE3 ,Mirrors DONE Status Flag for Channel 3" "Not done,Done"
|
|
bitfld.long 0x00 2. " DONE2 ,Mirrors DONE Status Flag for Channel 2" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DONE1 ,Mirrors DONE Status Flag for Channel 1" "Not done,Done"
|
|
bitfld.long 0x00 0. " DONE0 ,Mirrors DONE Status Flag for Channel 0" "Not done,Done"
|
|
sif (!cpuis("LPC11E*")&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ADTRIM,A/D Trim register"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 4.--7. " ADCOFFS ,Offset trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 8.--11. " TRIM ,Trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " ADCOFFS ,Offset trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "10-bit ADC1"
|
|
base ad:0x400E1000
|
|
width 9.
|
|
if ((per.long(ad:0x400E4000)&0x08000000)==0x08000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AD0CR,A/D Control Register"
|
|
bitfld.long 0x00 27. " EDGE ,Start Conversion Edge" "Rising,Falling"
|
|
textline " "
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC11D14"||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PPIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PPIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
elif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,,,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on P2.10,Falling edge on P1.27,Falling edge on MAT0.1,Falling edge on MAT0.3,Falling edge on MAT1.0,Falling edge on MAT1.1"
|
|
elif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on CTOUT_15,Falling edge on CTOUT_8,Falling edge on ADCTRIG0,Falling edge on ADCTRIG1,Falling edge on MCOA2,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
endif
|
|
sif (!cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDN ,A/D Power" "Power-down,Operational"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BURST ,Conversion Control Mode" "Software,Repeated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock Divider"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " AD.7 ,AD.7 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " AD.6 ,AD.6 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AD.5 ,AD.5 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " AD.3 ,AD.3 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " AD.2 ,AD.2 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AD.1 ,AD.1 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " AD.0 ,AD.0 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AD0CR,A/D Control Register"
|
|
bitfld.long 0x00 27. " EDGE ,Start Conversion Edge" "Rising,Falling"
|
|
textline " "
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PPIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PPIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
elif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,,,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 23.--26. " START ,Start Conversion Control" "No start,,Start,,ATRG0,Analog comparator output,ATRG1,,CT32B0_MAT0,,CT32B0_MAT1,,CT16B0_MAT0,,CT16B0_MAT1,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on P2.10,Rising edge on P1.27,Rising edge on MAT0.1,Rising edge on MAT0.3,Rising edge on MAT1.0,Rising edge on MAT1.1"
|
|
elif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on CTOUT_15,Rising edge on CTOUT_8,Rising edge on ADCTRIG0,Rising edge on ADCTRIG1,Rising edge on MCOA2,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
endif
|
|
sif !cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDN ,A/D Power" "Power-down,Operational"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BURST ,Conversion Control Mode" "Software,Repeated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock Divider"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " AD.7 ,AD.7 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " AD.6 ,AD.6 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AD.5 ,AD.5 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " AD.3 ,AD.3 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " AD.2 ,AD.2 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AD.1 ,AD.1 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " AD.0 ,AD.0 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "AD0GDR,A/D Global Data Register"
|
|
in
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SEL,A/D Select Register"
|
|
bitfld.long 0x00 14.--15. " AD7SEL ,This field selects the source signal for channel 7" "AD7,No signal,Temperature sensor,?..."
|
|
bitfld.long 0x00 12.--13. " AD6SEL ,This field selects the source signal for channel 6" "AD6,no signal,Internal voltage reference,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " AD5SEL ,This field selects the source signal for channel 5" "AD5,No signal,Core voltage regulator output,?..."
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "AD0INTEN,A/D Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " ADGINTEN ,Source of Generate Interrupt" "Individual,Global"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " ADINTEN7 ,Interrupt when Conversion on Channel 7 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ADINTEN6 ,Interrupt when Conversion on Channel 6 Completed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADINTEN5 ,Interrupt when Conversion on Channel 5 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ADINTEN4 ,Interrupt when Conversion on Channel 4 Completed" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADINTEN4 ,Interrupt when Conversion on Channel 4 Completed" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADINTEN3 ,Interrupt when Conversion on Channel 3 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ADINTEN2 ,Interrupt when Conversion on Channel 2 Completed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADINTEN1 ,Interrupt when Conversion on Channel 1 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ADINTEN0 ,Interrupt when Conversion on Channel 0 Completed" "No interrupt,Interrupt"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "AD0DR0,A/D Data Register"
|
|
in
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "AD0DR1,A/D Data Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "AD0DR2,A/D Data Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "AD0DR3,A/D Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "AD0DR4,A/D Data Register"
|
|
in
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "AD0DR5,A/D Data Register"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "AD0DR6,A/D Data Register"
|
|
in
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "AD0DR7,A/D Data Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "AD0STAT,A/D Status Register"
|
|
bitfld.long 0x00 16. " ADINT ,A/D Interrupt Flag" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 15. " OVERRUN7 ,Mirrors OVERRUN Status Flag for Channel 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " OVERRUN6 ,Mirrors OVERRUN Status Flag for Channel 6" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OVERRUN5 ,Mirrors OVERRUN Status Flag for Channel 5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " OVERRUN4 ,Mirrors OVERRUN Status Flag for Channel 4" "Not occurred,Occurred"
|
|
else
|
|
bitfld.long 0x00 12. " OVERRUN4 ,Mirrors OVERRUN Status Flag for Channel 4" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " OVERRUN3 ,Mirrors OVERRUN Status Flag for Channel 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " OVERRUN2 ,Mirrors OVERRUN Status Flag for Channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OVERRUN1 ,Mirrors OVERRUN Status Flag for Channel 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " OVERRUN0 ,Mirrors OVERRUN Status Flag for Channel 0" "Not occurred,Occurred"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " DONE7 ,Mirrors DONE Status Flag for Channel 7" "Not done,Done"
|
|
bitfld.long 0x00 6. " DONE6 ,Mirrors DONE Status Flag for Channel 6" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DONE5 ,Mirrors DONE Status Flag for Channel 5" "Not done,Done"
|
|
bitfld.long 0x00 4. " DONE4 ,Mirrors DONE Status Flag for Channel 4" "Not done,Done"
|
|
else
|
|
bitfld.long 0x00 4. " DONE4 ,Mirrors DONE Status Flag for Channel 4" "Not done,Done"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " DONE3 ,Mirrors DONE Status Flag for Channel 3" "Not done,Done"
|
|
bitfld.long 0x00 2. " DONE2 ,Mirrors DONE Status Flag for Channel 2" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DONE1 ,Mirrors DONE Status Flag for Channel 1" "Not done,Done"
|
|
bitfld.long 0x00 0. " DONE0 ,Mirrors DONE Status Flag for Channel 0" "Not done,Done"
|
|
sif (!cpuis("LPC11E*")&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ADTRIM,A/D Trim register"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 4.--7. " ADCOFFS ,Offset trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 8.--11. " TRIM ,Trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " ADCOFFS ,Offset trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DAC"
|
|
base ad:0x400E1000
|
|
width 11.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "DACR,D/A Converter Register"
|
|
bitfld.long 0x00 16. " BIAS ,Settling time\maximum current\maximum update rate" "1us/700uA/1MHz,2.5us/350uA/400kHz"
|
|
hexmask.long.word 0x00 6.--15. 1. " VALUE ,Value"
|
|
line.long 0x04 "DACCTRL,D/A Converter Control Register"
|
|
bitfld.long 0x04 3. " DMA_ENA ,DMA access enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CNT_ENA ,Time-out counter operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DBLBUF_ENA ,DACR double-buffering enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INT_DMA_REQ ,Interrupt DMA Request" "Not requested,Requested"
|
|
line.long 0x08 "DACCNTVAL,D/A Converter Counter Value Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,16-bit reload value for the DAC interrupt/DMA timer"
|
|
width 0xb
|
|
tree.end
|
|
sif !cpuis("LPC1810")&&!cpuis("LPC1820")&&!cpuis("LPC1830")&&!cpuis("LPC1850")
|
|
tree.open "FMC (Flash programming/ISP and IAP)"
|
|
tree "Flash bank A"
|
|
base ad:0x4000C000
|
|
width 11.
|
|
sif (cpuis("LPC11E*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "FLASHCFG,Flash Configuration Register"
|
|
bitfld.long 0x00 0.--1. " FLASHTIM ,Flash memory access time" "1 system clock,2 system clocks,3 system clocks,?..."
|
|
endif
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "FMSSTART,Flash Module Signature Start register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " START ,Signature generation start address"
|
|
line.long 0x04 "FMSSTOP,Flash Module Signature Stop register"
|
|
bitfld.long 0x04 17. " SIG_START ,Start control bit for signature generation" "Not started,Started"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " STOP ,BIST stop address divided by 16"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "FMSW0,FMSW0 register bit description (Word 0 of 128-bit signature)"
|
|
line.long 0x04 "FMSW1,FMSW1 register bit description (Word 1 of 128-bit signature)"
|
|
line.long 0x08 "FMSW2,FMSW2 register bit description (Word 2 of 128-bit signature)"
|
|
line.long 0x0c "FMSW3,FMSW3 register bit description (Word 3 of 128-bit signature)"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*"))
|
|
group.long 0x9C++0x07
|
|
line.long 0x00 "EEMSSTART,EEPROM BIST start address register"
|
|
hexmask.long.word 0x00 0.--13. 1. " STARTA ,BIST start address"
|
|
line.long 0x04 "EEMSSTOP,EEPROM BIST stop address register"
|
|
bitfld.long 0x04 31. " STRTBIST ,BIST start bit" "No action,Start"
|
|
textline " "
|
|
bitfld.long 0x04 30. " DEVSEL ,BIST device select bit" "Total memory,EEPROM"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--13. 1. " STOPA ,BIST stop address"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "EEMSSIG,EEPROM BIST signature register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PARITY_SIG ,BIST 16-bit signature calculated from only the parity bits of the data bytes"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_SIG ,16-bit signature calculated from only the data bytes"
|
|
endif
|
|
rgroup.long 0xfe0++0x03
|
|
line.long 0x00 "FMSTAT,Flash module Status register"
|
|
bitfld.long 0x00 2. " SIG_DONE ,Signature generation complete flag" "Not completed,Completed"
|
|
wgroup.long 0xfe8++0x03
|
|
line.long 0x00 "FMSTATCLR,Flash Module Status Clear register"
|
|
bitfld.long 0x00 2. " SIG_DONE_CLR ,Clear signature generation complete flag" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("LPC1812")&&!cpuis("LPC1822")
|
|
tree "Flash bank B"
|
|
base ad:0x4000D000
|
|
width 11.
|
|
sif (cpuis("LPC11E*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "FLASHCFG,Flash Configuration Register"
|
|
bitfld.long 0x00 0.--1. " FLASHTIM ,Flash memory access time" "1 system clock,2 system clocks,3 system clocks,?..."
|
|
endif
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "FMSSTART,Flash Module Signature Start register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " START ,Signature generation start address"
|
|
line.long 0x04 "FMSSTOP,Flash Module Signature Stop register"
|
|
bitfld.long 0x04 17. " SIG_START ,Start control bit for signature generation" "Not started,Started"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " STOP ,BIST stop address divided by 16"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "FMSW0,FMSW0 register bit description (Word 0 of 128-bit signature)"
|
|
line.long 0x04 "FMSW1,FMSW1 register bit description (Word 1 of 128-bit signature)"
|
|
line.long 0x08 "FMSW2,FMSW2 register bit description (Word 2 of 128-bit signature)"
|
|
line.long 0x0c "FMSW3,FMSW3 register bit description (Word 3 of 128-bit signature)"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*"))
|
|
group.long 0x9C++0x07
|
|
line.long 0x00 "EEMSSTART,EEPROM BIST start address register"
|
|
hexmask.long.word 0x00 0.--13. 1. " STARTA ,BIST start address"
|
|
line.long 0x04 "EEMSSTOP,EEPROM BIST stop address register"
|
|
bitfld.long 0x04 31. " STRTBIST ,BIST start bit" "No action,Start"
|
|
textline " "
|
|
bitfld.long 0x04 30. " DEVSEL ,BIST device select bit" "Total memory,EEPROM"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--13. 1. " STOPA ,BIST stop address"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "EEMSSIG,EEPROM BIST signature register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PARITY_SIG ,BIST 16-bit signature calculated from only the parity bits of the data bytes"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_SIG ,16-bit signature calculated from only the data bytes"
|
|
endif
|
|
rgroup.long 0xfe0++0x03
|
|
line.long 0x00 "FMSTAT,Flash module Status register"
|
|
bitfld.long 0x00 2. " SIG_DONE ,Signature generation complete flag" "Not completed,Completed"
|
|
wgroup.long 0xfe8++0x03
|
|
line.long 0x00 "FMSTATCLR,Flash Module Status Clear register"
|
|
bitfld.long 0x00 2. " SIG_DONE_CLR ,Clear signature generation complete flag" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("LPC1857")||cpuis("LPC1853")
|
|
tree "EEPROM memory"
|
|
base ad:0x4000E000
|
|
width 10.
|
|
group.long 0x0++0x3 "EEPROM registers"
|
|
line.long 0x00 "EECMD,EEPROM command register"
|
|
sif !cpuis("LPC1853")&&!cpuis("LPC1857")
|
|
bitfld.long 0x00 3. " RDPREFETCH ,Read data prefetch bit" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 0.--2. " CMD ,Command" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Erase/Program,?..."
|
|
sif !cpuis("LPC1853")&&!cpuis("LPC1857")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EEADDR,EEPROM address register"
|
|
hexmask.long.word 0x00 0.--11. 1. " ADDR ,Address"
|
|
endif
|
|
sif cpuis("LPC1853")||cpuis("LPC1857")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "RWSTATE,EEPROM read wait state register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RPHASE1 ,Wait states 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RPHASE2 ,Wait states 2"
|
|
line.long 0x04 "AUTOPROG,EEPROM auto programming register"
|
|
bitfld.long 0x04 0.--1. " AUTOPROG ,Auto programming mode" "Off,After 1 word,After a write to AHB,?..."
|
|
line.long 0x08 "WSTATE,EEPROM wait state register"
|
|
bitfld.long 0x08 31. " LCK_PARWEP ,Lock timing parameters for write, erase and program operation" "R/W,R"
|
|
hexmask.long.byte 0x08 16.--23. 1. " PHASE1 ,Wait states for phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " PHASE2 ,Wait states for phase 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PHASE3 ,Wait states for phase 3"
|
|
line.long 0x0C "CLKDIV,EEPROM clock divider register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CLKDIV ,Division factor"
|
|
line.long 0x10 "PWRDWN,EEPROM power down/DCM register"
|
|
bitfld.long 0x10 0. " PWRDWN ,Power down mode bit" "No,Yes"
|
|
endif
|
|
sif !cpuis("LPC1853")&&!cpuis("LPC1857")
|
|
if ((per.l(ad:0x4000E000+0x80)&0x07)==0x03)
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "EEWDATA,EEPROM write data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDATA ,Write data"
|
|
elif ((per.l(ad:0x4000E000+0x80)&0x07)==0x04)
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "EEWDATA,EEPROM write data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Write data"
|
|
elif ((per.l(ad:0x4000E000+0x80)&0x07)==0x05)
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "EEWDATA,EEPROM write data register"
|
|
else
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "EEWDATA,EEPROM write data register"
|
|
endif
|
|
if ((per.l(ad:0x4000E000+0x80)&0x07)==0x00)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "EERDATA,EEPROM read data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDATA ,Write data"
|
|
elif ((per.l(ad:0x4000E000+0x80)&0x07)==0x01)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "EERDATA,EEPROM read data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Write data"
|
|
elif ((per.l(ad:0x4000E000+0x80)&0x07)==0x02)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "EERDATA,EEPROM read data register"
|
|
else
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "EERDATA,EEPROM read data register"
|
|
endif
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "EEWSTATE,EEPROM wait state register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHASE1 ,Wait states 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PHASE2 ,Wait states 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PHASE3 ,Wait states 3"
|
|
line.long 0x04 "EECLKDIV,EEPROM clock divider register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CLKDIV ,Division factor (minus 1 encoded)"
|
|
line.long 0x08 "EEPWRDWN,EEPROM power down register"
|
|
bitfld.long 0x08 0. " PWRDWN ,Power down mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xFE0++0x07 "Interrupt registers"
|
|
line.long 0x04 "EEINTEN,Interrupt enable register"
|
|
sif !cpuis("LPC1853")&&!cpuis("LPC1857")
|
|
setclrfld.long 0x04 28. -0x04 28. -0x08 28. " EE_PROG_DONE_set/clr ,EEPROM program operation finished interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. -0x04 26. -0x08 26. " EE_RW_DONE_set/clr ,EEPROM read/write operation finished interrupt enable" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x04 2. -0x04 2. -0x08 2. " EE_PROG_DONE ,EEPROM program operation finished interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x00 "EEINTSTAT,Interrupt status register"
|
|
sif !cpuis("LPC1853")&&!cpuis("LPC1857")
|
|
setclrfld.long 0x00 28. 0x0C 28. 0x08 28. " END_OF_PROG1_set/clr ,EEPROM program operation finished interrupt status bit" "Not finished,Finished"
|
|
setclrfld.long 0x00 26. 0x0C 26. 0x08 26. " END_OF_RDWR_set/clr ,EEPROM read/write operation finished interrupt status bit" "Not finished,Finished"
|
|
else
|
|
setclrfld.long 0x00 2. 0x0c 2. 0x08 2. " END_OF_PROG ,EEPROM program operation finished interrupt status bit" "Not finished,Finished"
|
|
endif
|
|
tree.end
|
|
endif
|
|
textline ""
|