5002 lines
388 KiB
Plaintext
5002 lines
388 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: LPC1224/25/26/27 On-Chip Peripherals
|
|
; @Props: Released
|
|
; @Author: EMK, SLA
|
|
; @Changelog:
|
|
; 2011-06-13
|
|
; 2012-06-06
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Doc: lpc12xx_user_manual.pdf; UM10441.pdf Rev. 2 - 2011-09-19
|
|
; @Core: Cortex-M0
|
|
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: perlpc12xx.per 12528 2020-11-12 13:57:39Z bschroefel $
|
|
|
|
config 16. 8.
|
|
base ad:0x0
|
|
tree.close "Core Registers (Cortex-M0)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
|
|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "System Control"
|
|
base ad:0x40048000
|
|
width 17.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "SYSMEMREMAP,System memory remap register"
|
|
bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader Mode,User RAM Mode,User Flash Mode,?..."
|
|
line.long 0x04 "PRESETCTRL,Peripheral reset control register"
|
|
bitfld.long 0x04 15. " FLASH_OVERRIDE ,Flash read mode" "Multi-cycle,1-cycle"
|
|
bitfld.long 0x04 10. " DMA_RST_N ,Micro DMA reset control" "Reset,No reset"
|
|
bitfld.long 0x04 9. " CRC_RST_N ,CRC reset control" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CMP_RST_N ,Comparator reset control" "Reset,No reset"
|
|
bitfld.long 0x04 7. " CT32B1_RST_N ,32-bit counter/timer 1 reset control" "Reset,No reset"
|
|
bitfld.long 0x04 6. " CT32B0_RST_N ,32-bit counter/timer 0 reset control" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CT16B1_RST_N ,16-bit counter/timer 1 reset control" "Reset,No reset"
|
|
bitfld.long 0x04 4. " CT16B0_RST_N ,16-bit counter/timer 0 reset control" "Reset,No reset"
|
|
bitfld.long 0x04 3. " UART1_RST_N ,UART1 reset control" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " UART0_RST_N ,UART0 reset control" "Reset,No reset"
|
|
bitfld.long 0x04 1. " I2C_RST_N ,I2C reset control" "Reset,No reset"
|
|
bitfld.long 0x04 0. " SSP0_RST_N ,SSP reset control" "Reset,No reset"
|
|
line.long 0x08 "SYSPLLCTRL,System PLL control register"
|
|
bitfld.long 0x08 5.--6. " PSEL ,Post divider ratio" "1,2,4,8"
|
|
bitfld.long 0x08 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.long 0x0c++0x3
|
|
line.long 0x00 "SYSPLLSTAT,System PLL status register"
|
|
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked"
|
|
group.long 0x20++0xB
|
|
line.long 0x00 "SYSOSCCTRL,System oscillator control register"
|
|
bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator enable" "Disabled,Enabled"
|
|
line.long 0x04 "WDTOSCCTRL,Watchdog oscillator control register"
|
|
bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency(Fclkana)" "Reserved,0.5 MHz,0.8 MHz,1.1 MHz,1.4 MHz,1.6 MHz,1.8 MHz,2.0 MHz,2.2 MHz,2.4 MHz,2.6 MHz,2.7 MHz,2.9 MHz,3.1 MHz,3.2 MHz,3.4 MHz"
|
|
bitfld.long 0x04 0.--4. " DIVSEL ,Select divider for Fclkana." "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
line.long 0x08 "IRCCTRL,Internal resonant crystal control register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TRIM ,Trim value"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "SYSRSTSTAT,System reset status register"
|
|
eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset"
|
|
eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset"
|
|
eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "SYSPLLCLKSEL,System PLL clock source select register"
|
|
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,System oscillator,?..."
|
|
line.long 0x04 "SYSPLLUEN,System PLL clock source update enable register"
|
|
bitfld.long 0x04 0. " ENA ,System PLL clock source update enable" "Disabled,Enabled"
|
|
group.long 0x70++0xB
|
|
line.long 0x00 "MAINCLKSEL,Main clock source select register"
|
|
bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC oscillator,Input clock to system PLL,WDT oscillator,System PLL clock out"
|
|
line.long 0x04 "MAINCLKUEN,Main clock source update enable register"
|
|
bitfld.long 0x04 0. " ENA ,Enable main clock source update" "Disabled,Enabled"
|
|
line.long 0x08 "SYSAHBCLKDIV,System AHB clock divider register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "SYSAHBCLKCTRL,System AHB clock control register"
|
|
bitfld.long 0x00 31. " GPIO0 ,Clock for GPIO0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " GPIO1 ,Clock for GPIO1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GPIO2 ,Clock for GPIO2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CMP ,Clock for CMP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " RTC ,Clock for RTC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DMA ,Clock for DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WDT ,Clock for WDT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ADC ,Clock for ADC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " UART1 ,Clock for UART1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UART0 ,Clock for UART0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSP ,Clock for SPP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CT32B1 ,Clock for 32-bit counter/timer 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CT32B0 ,Clock for 32-bit counter/timer 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CT16B1 ,Clock for 16-bit counter/timer 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CT16B0 ,Clock for 16-bit counter/timer 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CRC ,Clock for CRC enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C ,Clock for I2C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FLASHARRAY ,Clock for flash array access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FLASHREG ,Clock for flash register interface enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RAM ,Clock for RAM enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ROM ,Clock for ROM enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SYS ,Clock for AHB to APB bridge enable" "Reserved,Enabled"
|
|
group.long 0x94++0xF
|
|
line.long 0x00 "SSPCLKDIV,SPP clock divider register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,SSP clock divider values"
|
|
line.long 0x04 "UART0CLKDIV,UART0 clock divider register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DIV ,UART0_PCLK clock divider values"
|
|
line.long 0x08 "UART1CLKDIV,UART1 clock divider register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,UART1_PCLK clock divider values"
|
|
line.long 0x0C "RTCCLKDIV,RTC clock divider register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DIV ,RTC_PCLK clock divider values"
|
|
group.long 0xe0++0xB
|
|
line.long 0x00 "CLKOUTCLKSEL,CLKOUT clock source select register"
|
|
bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC oscillator,System oscillator,Watchdog oscillator,Main clock"
|
|
line.long 0x04 "CLKOUTCLKUEN,CLKOUT clock source update enable register"
|
|
bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled"
|
|
line.long 0x08 "CLKOUTCLKDIV,CLKOUT clock divider register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values"
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x0 "PIOPORCAP0,POR captured PIO status register 0"
|
|
bitfld.long 0x0 31. " PIOSTAT[31] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 30. " PIOSTAT[30] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 29. " PIOSTAT[29] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 28. " PIOSTAT[28] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 27. " PIOSTAT[27] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 26. " PIOSTAT[26] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 25. " PIOSTAT[25] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 24. " PIOSTAT[24] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 23. " PIOSTAT[23] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 22. " PIOSTAT[22] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 21. " PIOSTAT[21] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 20. " PIOSTAT[20] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PIOSTAT[19] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 18. " PIOSTAT[18] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 17. " PIOSTAT[17] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 16. " PIOSTAT[16] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 15. " PIOSTAT[15] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 14. " PIOSTAT[14] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PIOSTAT[13] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 12. " PIOSTAT[12] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 11. " PIOSTAT[11] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 10. " PIOSTAT[10] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 9. " PIOSTAT[9] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 8. " PIOSTAT[8] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 7. " PIOSTAT[7] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 6. " PIOSTAT[6] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 5. " PIOSTAT[5] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PIOSTAT[4] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 3. " PIOSTAT[3] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 2. " PIOSTAT[2] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 1. " PIOSTAT[1] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x0 0. " PIOSTAT[0] ,Raw reset status input " "No reset,Reset"
|
|
line.long 0x4 "PIOPORCAP1,POR captured PIO status register 1"
|
|
bitfld.long 0x4 31. " PIOSTAT[31] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 30. " PIOSTAT[30] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 29. " PIOSTAT[29] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 28. " PIOSTAT[28] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 27. " PIOSTAT[27] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 26. " PIOSTAT[26] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 25. " PIOSTAT[25] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 24. " PIOSTAT[24] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 23. " PIOSTAT[23] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 22. " PIOSTAT[22] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 21. " PIOSTAT[21] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 20. " PIOSTAT[20] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PIOSTAT[19] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 18. " PIOSTAT[18] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 17. " PIOSTAT[17] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 16. " PIOSTAT[16] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 15. " PIOSTAT[15] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 14. " PIOSTAT[14] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 13. " PIOSTAT[13] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 12. " PIOSTAT[12] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 11. " PIOSTAT[11] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 10. " PIOSTAT[10] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 9. " PIOSTAT[9] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 8. " PIOSTAT[8] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 7. " PIOSTAT[7] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 6. " PIOSTAT[6] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 5. " PIOSTAT[5] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PIOSTAT[4] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 3. " PIOSTAT[3] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 2. " PIOSTAT[2] ,Raw reset status input " "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 1. " PIOSTAT[1] ,Raw reset status input " "No reset,Reset"
|
|
bitfld.long 0x4 0. " PIOSTAT[0] ,Raw reset status input " "No reset,Reset"
|
|
group.long 0x134++0x1B
|
|
line.long 0x0 "IOCONFIGCLKDIV0,IOCONFIG filter clock divider register 0"
|
|
hexmask.long.byte 0 0.--7. 1. " DIV ,IOCONFIG filter clock divider values"
|
|
line.long 0x4 "IOCONFIGCLKDIV1,IOCONFIG filter clock divider register 1"
|
|
hexmask.long.byte 1 0.--7. 1. " DIV ,IOCONFIG filter clock divider values"
|
|
line.long 0x8 "IOCONFIGCLKDIV2,IOCONFIG filter clock divider register 2"
|
|
hexmask.long.byte 2 0.--7. 1. " DIV ,IOCONFIG filter clock divider values"
|
|
line.long 0xC "IOCONFIGCLKDIV3,IOCONFIG filter clock divider register 3"
|
|
hexmask.long.byte 3 0.--7. 1. " DIV ,IOCONFIG filter clock divider values"
|
|
line.long 0x10 "IOCONFIGCLKDIV4,IOCONFIG filter clock divider register 4"
|
|
hexmask.long.byte 4 0.--7. 1. " DIV ,IOCONFIG filter clock divider values"
|
|
line.long 0x14 "IOCONFIGCLKDIV5,IOCONFIG filter clock divider register 5"
|
|
hexmask.long.byte 5 0.--7. 1. " DIV ,IOCONFIG filter clock divider values"
|
|
line.long 0x18 "IOCONFIGCLKDIV6,IOCONFIG filter clock divider register 6"
|
|
hexmask.long.byte 6 0.--7. 1. " DIV ,IOCONFIG filter clock divider values"
|
|
group.long 0x150++0xB
|
|
line.long 0x00 "BODCTRL,BOD control register"
|
|
bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" "No effect,2.248V/2.385V,2.541V/2.669V,2.828V/2.929V"
|
|
bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "No effect,2.038V/2.180V,2.336V/2.471V,2.624V/2.761V"
|
|
line.long 0x04 "SYSTCKCAL,System tick timer calibration register"
|
|
hexmask.long 0x04 0.--25. 1. " CAL ,System tick timer calibration value"
|
|
line.long 0x08 "AHBPRIO,AHB matrix master priority register"
|
|
bitfld.long 0x08 0.--1. " M0PRIO ,Priority of the ARM Cortex-M0 core" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " DMAPRIO ,Priority of the micro DMA controller" "0,1,2,3"
|
|
group.long 0x170++0x7
|
|
line.long 0x00 "IRQLATENCY,IRQ latency register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LATENCY ,8-bit latency value"
|
|
line.long 0x04 "INTNMI,NMI interrupt source configuration register"
|
|
bitfld.long 0x04 0.--5. " NMISRC ,NMI interrupt source select" "I2C,CT16B0,CT16B1,CT32B0,CT32B1,SSP,UART0,UART1,Comparator,ADC,Watchdog timer,I2C,Reserved,PIO0,PIO1,PIO2,PMU wake-up,DMA,RTC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Disabled"
|
|
group.long 0x200++0x7
|
|
line.long 0x00 "STARTAPRP0,Start logic edge control register 0"
|
|
bitfld.long 0x00 11. " APRPIO0_11 ,Edge select for start logic input PIO0_11" "Falling,Rising"
|
|
bitfld.long 0x00 10. " APRPIO0_10 ,Edge select for start logic input PIO0_10" "Falling,Rising"
|
|
bitfld.long 0x00 9. " APRPIO0_9 ,Edge select for start logic input PIO0_9" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 8. " APRPIO0_8 ,Edge select for start logic input PIO0_8" "Falling,Rising"
|
|
bitfld.long 0x00 7. " APRPIO0_7 ,Edge select for start logic input PIO0_7" "Falling,Rising"
|
|
bitfld.long 0x00 6. " APRPIO0_6 ,Edge select for start logic input PIO0_6" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 5. " APRPIO0_5 ,Edge select for start logic input PIO0_5" "Falling,Rising"
|
|
bitfld.long 0x00 4. " APRPIO0_4 ,Edge select for start logic input PIO0_4" "Falling,Rising"
|
|
bitfld.long 0x00 3. " APRPIO0_3 ,Edge select for start logic input PIO0_3" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 2. " APRPIO0_2 ,Edge select for start logic input PIO0_2" "Falling,Rising"
|
|
bitfld.long 0x00 1. " APRPIO0_1 ,Edge select for start logic input PIO0_1" "Falling,Rising"
|
|
bitfld.long 0x00 0. " APRPIO0_0 ,Edge select for start logic input PIO0_0" "Falling,Rising"
|
|
line.long 0x04 "STARTERP0,Start logic signal enable register 0"
|
|
bitfld.long 0x04 11. " ERPIO0_11 ,Start signal for start logic input PIO0_11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ERPIO0_10 ,Start signal for start logic input PIO0_10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ERPIO0_9 ,Start signal for start logic input PIO0_9 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " ERPIO0_8 ,Start signal for start logic input PIO0_8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " ERPIO0_7 ,Start signal for start logic input PIO0_7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ERPIO0_6 ,Start signal for start logic input PIO0_6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ERPIO0_5 ,Start signal for start logic input PIO0_5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ERPIO0_4 ,Start signal for start logic input PIO0_4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ERPIO0_3 ,Start signal for start logic input PIO0_3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ERPIO0_2 ,Start signal for start logic input PIO0_2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ERPIO0_1 ,Start signal for start logic input PIO0_1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ERPIO0_0 ,Start signal for start logic input PIO0_0 enable" "Disabled,Enabled"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x00 "STARTRSRP0CLR,Start logic reset register 0"
|
|
bitfld.long 0x00 11. " RSRPIO0_11 ,Start signal reset for start logic input PIO0_11" "-,Reset"
|
|
bitfld.long 0x00 10. " RSRPIO0_10 ,Start signal reset for start logic input PIO0_10" "-,Reset"
|
|
bitfld.long 0x00 9. " RSRPIO0_9 ,Start signal reset for start logic input PIO0_9" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSRPIO0_8 ,Start signal reset for start logic input PIO0_8" "-,Reset"
|
|
bitfld.long 0x00 7. " RSRPIO0_7 ,Start signal reset for start logic input PIO0_7" "-,Reset"
|
|
bitfld.long 0x00 6. " RSRPIO0_6 ,Start signal reset for start logic input PIO0_6" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RSRPIO0_5 ,Start signal reset for start logic input PIO0_5" "-,Reset"
|
|
bitfld.long 0x00 4. " RSRPIO0_4 ,Start signal reset for start logic input PIO0_4" "-,Reset"
|
|
bitfld.long 0x00 3. " RSRPIO0_3 ,Start signal reset for start logic input PIO0_3" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSRPIO0_2 ,Start signal reset for start logic input PIO0_2" "-,Reset"
|
|
bitfld.long 0x00 1. " RSRPIO0_1 ,Start signal reset for start logic input PIO0_1" "-,Reset"
|
|
bitfld.long 0x00 0. " RSRPIO0_0 ,Start signal reset for start logic input PIO0_0" "-,Reset"
|
|
rgroup.long 0x20c++0x3
|
|
line.long 0x00 "STARTSRP0,Start logic status register 0"
|
|
bitfld.long 0x00 11. " SRPIO0_11 ,Start signal status for start logic input PIO0_11" "Not started,Started"
|
|
bitfld.long 0x00 10. " SRPIO0_10 ,Start signal status for start logic input PIO0_10" "Not started,Started"
|
|
bitfld.long 0x00 9. " SRPIO0_9 ,Start signal status for start logic input PIO0_9" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SRPIO0_8 ,Start signal status for start logic input PIO0_8" "Not started,Started"
|
|
bitfld.long 0x00 7. " SRPIO0_7 ,Start signal status for start logic input PIO0_7" "Not started,Started"
|
|
bitfld.long 0x00 6. " SRPIO0_6 ,Start signal status for start logic input PIO0_6" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SRPIO0_5 ,Start signal status for start logic input PIO0_5" "Not started,Started"
|
|
bitfld.long 0x00 4. " SRPIO0_4 ,Start signal status for start logic input PIO0_4" "Not started,Started"
|
|
bitfld.long 0x00 3. " SRPIO0_3 ,Start signal status for start logic input PIO0_3" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRPIO0_2 ,Start signal status for start logic input PIO0_2" "Not started,Started"
|
|
bitfld.long 0x00 1. " SRPIO0_1 ,Start signal status for start logic input PIO0_1" "Not started,Started"
|
|
bitfld.long 0x00 0. " SRPIO0_0 ,Start signal status for start logic input PIO0_0" "Not started,Started"
|
|
group.long 0x210++0x7
|
|
line.long 0x00 "STARTAPRP1,Start logic edge control register 1"
|
|
bitfld.long 0x00 18. " APRRTC ,Edge select for start logic interrupt RTC" "Falling,Rising"
|
|
bitfld.long 0x00 17. " APRDMA ,Edge select for start logic interrupt DMA" "Falling,Rising"
|
|
bitfld.long 0x00 15. " APRGPIO2 ,Edge select for start logic interrupt GPIO2" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 14. " APRGPIO1 ,Edge select for start logic interrupt GPIO1" "Falling,Rising"
|
|
bitfld.long 0x00 13. " APRGPIO0 ,Edge select for start logic interrupt GPIO0" "Falling,Rising"
|
|
bitfld.long 0x00 11. " APRBOD ,Edge select for start logic interrupt BOD" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 10. " APRWDT ,Edge select for start logic interrupt WDT" "Falling,Rising"
|
|
bitfld.long 0x00 9. " APRCOMP ,Edge select for start logic interrupt COMP" "Falling,Rising"
|
|
bitfld.long 0x00 8. " APRPIOADC ,Edge select for start logic interrupt ADC" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 7. " APRUART1 ,Edge select for start logic interrupt UART1" "Falling,Rising"
|
|
bitfld.long 0x00 6. " APRUART0 ,Edge select for start logic interrupt UART0" "Falling,Rising"
|
|
bitfld.long 0x00 5. " APRSSP ,Edge select for start logic interrupt SSP" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 4. " APRCT32B1 ,Edge select for start logic interrupt CT32B1" "Falling,Rising"
|
|
bitfld.long 0x00 3. " APRCT32B0 ,Edge select for start logic interrupt CT32B0" "Falling,Rising"
|
|
bitfld.long 0x00 2. " APRCT16B1 ,Edge select for start logic interrupt CT16B1" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APRCT16B0 ,Edge select for start logic interrupt CT16B0" "Falling,Rising"
|
|
bitfld.long 0x00 0. " APRI2C ,Edge select for start logic interrupt I2C" "Falling,Rising"
|
|
line.long 0x04 "STARTERP1,Start logic signal enable register 1"
|
|
bitfld.long 0x04 18. " ERRTC ,Start signal for start logic input interrupt RTC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " ERDMA ,Start signal for start logic input interrupt DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " ERGPIO2 ,Start signal for start logic input interrupt GPIO2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " ERGPIO1 ,Start signal for start logic input interrupt GPIO1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " ERGPIO0 ,Start signal for start logic input interrupt GPIO0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ERBOD ,Start signal for start logic input interrupt BOD enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " ERWDT ,Start signal for start logic input interrupt WDT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ERCOMP ,Start signal for start logic input interrupt COMP enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " ERPADC ,Start signal for start logic input interrupt ADC enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ERUART1 ,Start signal for start logic input interrupt UART1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ERUART0 ,Start signal for start logic input interrupt UART0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ERSSP ,Start signal for start logic input interrupt SSP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ERCT32B1 ,Start signal for start logic input interrupt CT32B1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ERCT32B0 ,Start signal for start logic input interrupt CT32B0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ERCT16B1 ,Start signal for start logic input interrupt CT16B1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ERCT16B0 ,Start signal for start logic input interrupt CT16B0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ERI2C ,Start signal for start logic input interrupt I2C enable" "Disabled,Enabled"
|
|
wgroup.long 0x218++0x3
|
|
line.long 0x00 "STARTRSRP1CLR,Start logic reset register 1"
|
|
bitfld.long 0x00 18. " RSRRTC ,Start signal reset for start logic interrupt RTC" "-,Reset"
|
|
bitfld.long 0x00 17. " RSRDMA ,Start signal reset for start logic interrupt DMA" "-,Reset"
|
|
bitfld.long 0x00 15. " RSRGPIO2 ,Start signal reset for start logic interrupt GPIO2" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RSRGPIO1 ,Start signal reset for start logic interrupt GPIO1" "-,Reset"
|
|
bitfld.long 0x00 13. " RSRGPIO0 ,Start signal reset for start logic interrupt GPIO0" "-,Reset"
|
|
bitfld.long 0x00 11. " RSRBOD ,Start signal reset for start logic interrupt BOD" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RSRWDT ,Start signal reset for start logic interrupt WDT" "-,Reset"
|
|
bitfld.long 0x00 9. " RSRCOMP ,Start signal reset for start logic interrupt COMP" "-,Reset"
|
|
bitfld.long 0x00 8. " RSRADC ,Start signal reset for start logic interrupt ADC" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RSRUART1 ,Start signal reset for start logic interrupt UART1" "-,Reset"
|
|
bitfld.long 0x00 6. " RSRUART0 ,Start signal reset for start logic interrupt UART0" "-,Reset"
|
|
bitfld.long 0x00 5. " RSRSSP ,Start signal reset for start logic interrupt SSP" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RSRCT32B1 ,Start signal reset for start logic interrupt CT32B1" "-,Reset"
|
|
bitfld.long 0x00 3. " RSRCT32B0 ,Start signal reset for start logic interrupt CT32B0" "-,Reset"
|
|
bitfld.long 0x00 2. " RSRCT16B1 ,Start signal reset for start logic interrupt CT16B1" "-,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RSRCT16B0 ,Start signal reset for start logic interrupt CT16B0" "-,Reset"
|
|
bitfld.long 0x00 0. " RSRI2C ,Start signal reset for start logic interrupt I2C" "-,Reset"
|
|
rgroup.long 0x21c++0x3
|
|
line.long 0x00 "STARTSRP1,Start logic signal status register 1"
|
|
bitfld.long 0x00 18. " SRRTC ,Start signal status for start logic interrupt RTC" "Not started,Started"
|
|
bitfld.long 0x00 17. " SRDMA ,Start signal status for start logic interrupt DMA" "Not started,Started"
|
|
bitfld.long 0x00 15. " SRGPIO2 ,Start signal status for start logic interrupt GPIO2" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RSRGPIO1 ,Start signal status for start logic interrupt GPIO1" "Not started,Started"
|
|
bitfld.long 0x00 13. " SRGPIO0 ,Start signal status for start logic interrupt GPIO0" "Not started,Started"
|
|
bitfld.long 0x00 11. " SRBOD ,Start signal status for start logic interrupt BOD" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SRWDT ,Start signal status for start logic interrupt WDT" "Not started,Started"
|
|
bitfld.long 0x00 9. " SRCOMP ,Start signal status for start logic interrupt COMP" "Not started,Started"
|
|
bitfld.long 0x00 8. " SRADC ,Start signal status for start logic interrupt ADC" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SRUART1 ,Start signal status for start logic interrupt UART1" "Not started,Started"
|
|
bitfld.long 0x00 6. " SRUART0 ,Start signal status for start logic interrupt UART0" "Not started,Started"
|
|
bitfld.long 0x00 5. " SRSSP ,Start signal status for start logic interrupt SPP" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SRCT32B1 ,Start signal status for start logic interrupt CT32B1" "Not started,Started"
|
|
bitfld.long 0x00 3. " SRCT32B0 ,Start signal status for start logic interrupt CT32B0" "Not started,Started"
|
|
bitfld.long 0x00 2. " SRCT16B1 ,Start signal status for start logic interrupt CT16B1" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCT16B0 ,Start signal status for start logic interrupt CT16B0" "Not started,Started"
|
|
bitfld.long 0x00 0. " SRI2C ,Start signal status for start logic interrupt I2C" "Not started,Started"
|
|
group.long 0x230++0xb
|
|
line.long 0x00 "PDSLEEPCFG,Deep-sleep configuration register"
|
|
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down control" "Powered,Powered down"
|
|
bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down"
|
|
line.long 0x04 "PDAWAKECFG,Wake-up configuration register"
|
|
bitfld.long 0x04 15. " COMP_PD ,Comparator power-down wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SYSOSC_PD ,System oscillator wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 1. " IRC_PD ,IRC oscillator wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down"
|
|
line.long 0x08 "PDRUNCFG,Power-down configuration register"
|
|
bitfld.long 0x08 15. " COMP_PD ,Comparator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SYSOSC_PD ,System oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 4. " ADC_PD ,ADC power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 3. " BOD_PD ,BOD power-down" "Powered,Powered down"
|
|
textline " "
|
|
bitfld.long 0x08 2. " FLASH_PD ,Flash power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down"
|
|
rgroup.long 0x3f4++0x3
|
|
line.long 0x00 "DEVICE_ID,Device ID register"
|
|
hexmask.long 0x00 0.--31. 1. " DEVICEID ,Device ID for LPC122x parts"
|
|
tree.end
|
|
tree "Flash memory access"
|
|
base ad:0x50060028
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "FLASHCFG,Flash configuration register"
|
|
bitfld.long 0x00 0.--1. " RDCFG ,Flash memory read access time" "2 CPU clock,3 CPU clocks,4 CPU clocks,5 CPU clocks"
|
|
width 0xb
|
|
tree.end
|
|
tree "Power Management Unit (PMU)"
|
|
base ad:0x40038000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCON,Power Control Register"
|
|
eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not entered,Entered"
|
|
sif (cpu()=="EM773"||cpu()=="LPC11D14"||cpu()=="LPC1102LV"||cpu()=="LPC1102"||cpuis("LPC1111*")||cpu()=="LPC1110"||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpuis("LPC11U*")||cpuis("LPC11E*")||cpu()=="LPC1124"||cpu()=="LPC1125"||cpu()=="LPC1126"||cpu()=="LPC1127"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U3*")||cpuis("LPC11U6*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
|
|
eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not entered,Entered"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("LPC11U*")||cpuis("LPC11E*")||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
|
|
bitfld.long 0x00 3. " NODPD ,No Deep power-down mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " PM ,Power mode" "Default,Deep-sleep,Power-down,Deep-power down,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 1. " DPDEN ,Deep power-down mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPREG0,General Purpose Register 0"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPREG1,General Purpose Register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPREG2,General Purpose Register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPREG3,General Purpose Register 3"
|
|
sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DPDCTRL,Deep Power Down Control Register"
|
|
sif (cpuis("LPC82*"))
|
|
hexmask.long 0x00 6.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WAKECLKPAD_DISABLE ,Disable the external clock input for the self-wake-up time" "No,Yes"
|
|
bitfld.long 0x00 4. " WAKEUPCLKHYS ,External clock input for the self-wake-up timer WKTCLKIN hysteresis enable" "Disabled,Enabled"
|
|
else
|
|
hexmask.long 0x00 4.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " LPOSCDPDEN ,Deep power-down mode low-power oscillator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LPOSCEN ,10 kHz self wake-up timer low-power oscillator use enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes"
|
|
bitfld.long 0x00 0. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DPDCTRL,Deep Power Down Control Register"
|
|
sif (cpuis("LPC84*"))
|
|
bitfld.long 0x00 7. " RESET_DISABLE ,RESET pin disable" "No,Yes"
|
|
bitfld.long 0x00 6. " RESETHYS ,RESET pin hysteresis enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
|
|
bitfld.long 0x00 5. " WAKECLKPAD_DISABLE ,Disable the external clock input for the self-wake-up time" "No,Yes"
|
|
bitfld.long 0x00 4. " WAKEUPCLKHYS ,External clock input for the self-wake-up timer WKTCLKIN hysteresis enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " LPOSCDPDEN ,Deep power-down mode low-power oscillator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LPOSCEN ,10 kHz self wake-up timer low-power oscillator use enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes"
|
|
bitfld.long 0x00 0. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
else
|
|
sif cpuis("LPC11U6*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPREG4,General Purpose Register 4"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes"
|
|
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
elif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPREG4,General Purpose Register 4"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYSCFG,System Configuration Register"
|
|
bitfld.long 0x00 11.--14. " RTCCLK ,RTC clock source select" "1 Hz clock,delayed 1 Hz clock,,,RTC PCLK,RTC PCLK,RTC PCLK,RTC PCLK,,,1 kHz clock,1 kHz clock,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I/O configuration"
|
|
base ad:0x40044000
|
|
width 0xF
|
|
group.long 0x08++0x47
|
|
line.long 0x00 "PIO0_19,PIO0_19 register"
|
|
bitfld.long 0x00 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x00 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x00 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function" "PIO0_19,Reserved,ACMP0_I0,CT32B0_CAP1,CT32B0_MAT1,?..."
|
|
line.long 0x04 "PIO0_20,PIO0_20 register"
|
|
bitfld.long 0x04 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x04 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x04 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x04 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x04 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Pin function" "PIO0_20,Reserved,ACMP0_I1,CT32B0_CAP2,CT32B0_MAT2,?..."
|
|
line.long 0x08 "PIO0_21,PIO0_21 register"
|
|
bitfld.long 0x08 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x08 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x08 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x08 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x08 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x08 0.--2. " FUNC ,Pin function" "PIO0_21,Reserved,ACMP0_I2,CT32B0_CAP3,CT32B0_MAT3,?..."
|
|
line.long 0x0C "PIO0_22,PIO0_22 register"
|
|
bitfld.long 0x0C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x0C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x0C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x0C 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x0C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Pin function" "PIO0_22,Reserved,ACMP0_I3,?..."
|
|
line.long 0x10 "PIO0_23,PIO0_23 register"
|
|
bitfld.long 0x10 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x10 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x10 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x10 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x10 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x10 0.--2. " FUNC ,Pin function" "PIO0_23,Reserved,ACMP1_I0,CT32B1_CAP0,CT32B1_MAT0,?..."
|
|
line.long 0x14 "PIO0_24,PIO0_24 register"
|
|
bitfld.long 0x14 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x14 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x14 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x14 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x14 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x14 0.--2. " FUNC ,Pin function" "PIO0_24,Reserved,ACMP1_I1,CT32B1_CAP1,CT32B1_MAT1,?..."
|
|
line.long 0x18 "SWDIO_PIO0_25,SWDIO_PIO0_25 register"
|
|
bitfld.long 0x18 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x18 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x18 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x18 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x18 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x18 0.--2. " FUNC ,Pin function" "SWDIO,Reserved,ACMP1_I2,CT32B1_CAP2,CT32B1_MAT2,Reserved,PIO0_25,?..."
|
|
line.long 0x1C "SWCLK_PIO0_26,SWCLK_PIO0_26 register"
|
|
bitfld.long 0x1C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x1C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x1C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x1C 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x1C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x1C 0.--2. " FUNC ,Pin function" "SWCLK,Reserved,ACMP1_I3,CT32B1_CAP3,CT32B1_MAT3,Reserved,PIO0_26,?..."
|
|
line.long 0x20 "PIO0_27,PIO0_27 register"
|
|
bitfld.long 0x20 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x20 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x20 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x20 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x20 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " FUNC ,Pin function" "PIO0_26,Reserved,ACMP0_O,?..."
|
|
line.long 0x24 "PIO2_12,PIO2_12 register"
|
|
bitfld.long 0x24 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x24 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x24 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x24 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x24 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " FUNC ,Pin function" "PIO2_12,Reserved,Reserved,RXD1,?..."
|
|
line.long 0x28 "PIO2_13,PIO2_13 register"
|
|
bitfld.long 0x28 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x28 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x28 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x28 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x28 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " FUNC ,Pin function" "PIO2_13,Reserved,Reserved,TXD1,?..."
|
|
line.long 0x2C "PIO2_14,PIO2_14 register"
|
|
bitfld.long 0x2C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x2C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x2C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x2C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " FUNC ,Pin function" "PIO2_14,?..."
|
|
line.long 0x30 "PIO2_15,PIO2_15 register"
|
|
bitfld.long 0x30 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x30 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x30 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x30 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x30 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x30 0.--2. " FUNC ,Pin function" "PIO2_15,?..."
|
|
line.long 0x34 "PIO0_28,PIO0_28 register"
|
|
bitfld.long 0x34 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x34 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x34 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x34 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x34 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x34 0.--2. " FUNC ,Pin function" "PIO0_28,Reserved,ACMP1_O,CT16B0_CAP0,CT16B0_MAT0,?..."
|
|
line.long 0x38 "PIO0_29,PIO0_29 register"
|
|
bitfld.long 0x38 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x38 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x38 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x38 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x38 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " FUNC ,Pin function" "PIO0_29,Reserved,ROSC,CT16B0_CAP1,CT16B0_MAT1,?..."
|
|
line.long 0x3C "PIO0_0,PIO0_0 register"
|
|
bitfld.long 0x3C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x3C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x3C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " DRV ,Drive current mode" "2mA drive,High"
|
|
bitfld.long 0x3C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x3C 0.--2. " FUNC ,Pin function" "PIO0_0,Reserved,/RTS0,?..."
|
|
line.long 0x40 "PIO0_1,PIO0_1 register"
|
|
bitfld.long 0x40 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x40 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x40 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x40 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x40 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x40 0.--2. " FUNC ,Pin function" "PIO0_1,Reserved,RXD0,CT32B0_CAP0,CT32B0_MAT0,?..."
|
|
line.long 0x44 "PIO0_2,PIO0_2 register"
|
|
bitfld.long 0x44 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x44 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x44 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x44 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x44 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x44 0.--2. " FUNC ,Pin function" "PIO0_2,Reserved,TXD0,CT32B0_CAP1,CT32B0_MAT1,?..."
|
|
group.long 0x54++0x83
|
|
line.long 0x00 "PIO0_3,PIO0_3 register"
|
|
bitfld.long 0x00 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x00 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function" "PIO0_3,Reserved,/DTR0,CT32B0_CAP2,CT32B0_MAT2,?..."
|
|
line.long 0x04 "PIO0_4,PIO0_4 register"
|
|
bitfld.long 0x04 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x04 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x04 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x04 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " FUNC ,Pin function" "PIO0_4,Reserved,/DSR0,CT32B0_CAP3,CT32B0_MAT3,?..."
|
|
line.long 0x08 "PIO0_5,PIO0_5 register"
|
|
bitfld.long 0x08 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x08 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x08 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x08 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " FUNC ,Pin function" "PIO0_5,Reserved,/DCD0,?..."
|
|
line.long 0x0C "PIO0_6,PIO0_6 register"
|
|
bitfld.long 0x0C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x0C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x0C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x0C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Pin function" "PIO0_6,Reserved,/RI0,CT32B1_CAP0,CT32B1_MAT0,?..."
|
|
line.long 0x10 "PIO0_7,PIO0_7 register"
|
|
bitfld.long 0x10 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x10 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x10 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x10 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " FUNC ,Pin function" "PIO0_7,Reserved,/CTS0,CT32B1_CAP1,CT32B1_MAT1,?..."
|
|
line.long 0x14 "PIO0_8,PIO0_8 register"
|
|
bitfld.long 0x14 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x14 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x14 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x14 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " FUNC ,Pin function" "PIO0_8,Reserved,RXD1,CT32B1_CAP2,CT32B1_MAT2,?..."
|
|
line.long 0x18 "PIO0_9,PIO0_9 register"
|
|
bitfld.long 0x18 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x18 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x18 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x18 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " FUNC ,Pin function" "PIO0_9,Reserved,TXD1,CT32B1_CAP3,CT32B1_MAT3,?..."
|
|
line.long 0x1C "PIO2_0,PIO2_0 register"
|
|
bitfld.long 0x1C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x1C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x1C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x1C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " FUNC ,Pin function" "PIO2_0,Reserved,Reserved,CT16B0_CAP0,CT16B0_MAT0,/RTS0,?..."
|
|
line.long 0x20 "PIO2_1,PIO2_1 register"
|
|
bitfld.long 0x20 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x20 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x20 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x20 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x20 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " FUNC ,Pin function" "PIO2_1,Reserved,CT16B0_CAP1,CT16B0_MAT1,RXD0,?..."
|
|
line.long 0x24 "PIO2_2,PIO2_2 register"
|
|
bitfld.long 0x24 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x24 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x24 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x24 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x24 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " FUNC ,Pin function" "PIO2_2,Reserved,CT16B1_CAP0,CT16B1_MAT0,TXD0,?..."
|
|
line.long 0x28 "PIO2_3,PIO2_3 register"
|
|
bitfld.long 0x28 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x28 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x28 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x28 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x28 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " FUNC ,Pin function" "PIO2_3,Reserved,CT16B1_CAP1,CT16B1_MAT1,/DTR0,?..."
|
|
line.long 0x2C "PIO2_4,PIO2_4 register"
|
|
bitfld.long 0x2C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x2C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x2C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x2C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " FUNC ,Pin function" "PIO2_4,Reserved,CT32B0_CAP0,CT32B0_MAT0,/CTS0,?..."
|
|
line.long 0x30 "PIO2_5,PIO2_5 register"
|
|
bitfld.long 0x30 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x30 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x30 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x30 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x30 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x30 0.--2. " FUNC ,Pin function" "PIO2_5,Reserved,CT32B0_CAP1,CT32B0_MAT1,/RI0,?..."
|
|
line.long 0x34 "PIO2_6,PIO2_6 register"
|
|
bitfld.long 0x34 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x34 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x34 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x34 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x34 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x34 0.--2. " FUNC ,Pin function" "PIO2_6,Reserved,CT32B0_CAP2,CT32B0_MAT2,/DCD0,?..."
|
|
line.long 0x38 "PIO2_7,PIO2_7 register"
|
|
bitfld.long 0x38 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x38 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x38 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x38 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x38 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " FUNC ,Pin function" "PIO2_7,Reserved,CT32B0_CAP3,CT32B0_MAT3,/DSR0,?..."
|
|
line.long 0x3C "PIO0_10,PIO0_10 register"
|
|
bitfld.long 0x3C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x3C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x3C 10. " TOD ,True open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x3C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x3C 0.--2. " FUNC ,Pin function" "PIO0_10,Reserved,SCL,?..."
|
|
line.long 0x40 "PIO0_11,PIO0_11 register"
|
|
bitfld.long 0x40 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x40 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x40 10. " TOD ,True open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x40 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x40 0.--2. " FUNC ,Pin function" "PIO0_11,Reserved,SDA,CT16B0_CAP,CT16B0_MAT0,?..."
|
|
line.long 0x44 "PIO0_12,PIO0_12 register"
|
|
bitfld.long 0x44 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x44 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x44 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x44 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x44 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x44 0.--2. " FUNC ,Pin function" "PIO0_12,Reserved,CLKOUT,CT16B0_CAP1,CT16B0_MAT1,?..."
|
|
line.long 0x48 "RESET_PIO0_13,RESET_PIO0_13 register"
|
|
bitfld.long 0x48 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x48 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x48 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x48 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x48 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x48 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x48 0.--2. " FUNC ,Pin function" "/RESET,PIO0_13,?..."
|
|
line.long 0x4C "PIO0_14,PIO0_14 register"
|
|
bitfld.long 0x4C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x4C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x4C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x4C 9. " DRV ,Drive current mode" "2mA drive,High"
|
|
bitfld.long 0x4C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x4C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x4C 0.--2. " FUNC ,Pin function" "PIO0_14,Reserved,SCK,?..."
|
|
line.long 0x50 "PIO0_15,PIO0_15 register"
|
|
bitfld.long 0x50 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x50 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x50 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x50 9. " DRV ,Drive current mode" "2mA drive,High"
|
|
bitfld.long 0x50 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x50 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x50 0.--2. " FUNC ,Pin function" "PIO0_15,Reserved,SSEL,CT16B1_CAP0,CT16B1_MAT0,?..."
|
|
line.long 0x54 "PIO0_16,PIO0_16 register"
|
|
bitfld.long 0x54 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x54 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x54 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x54 9. " DRV ,Drive current mode" "2mA drive,High"
|
|
bitfld.long 0x54 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x54 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x54 0.--2. " FUNC ,Pin function" "PIO0_16,Reserved,MISO,CT16B1_CAP1,CT16B1_MAT1,?..."
|
|
line.long 0x58 "PIO0_17,PIO0_17 register"
|
|
bitfld.long 0x58 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x58 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x58 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x58 9. " DRV ,Drive current mode" "2mA drive,High"
|
|
bitfld.long 0x58 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x58 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x58 0.--2. " FUNC ,Pin function" "PIO0_17,Reserved,MOSI,?..."
|
|
line.long 0x5C "PIO0_18,PIO0_18 register"
|
|
bitfld.long 0x5C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x5C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x5C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x5C 9. " DRV ,Drive current mode" "2mA drive,High"
|
|
bitfld.long 0x5C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x5C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x5C 0.--2. " FUNC ,Pin function" "PIO0_18,SWCLK,Reserved,CT32B0_CAP0,CT32B0_MAT0,?..."
|
|
line.long 0x60 "R_PIO1_30,R_PIO1_30 register"
|
|
bitfld.long 0x60 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x60 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x60 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x60 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x60 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x60 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x60 0.--2. " FUNC ,Pin function" "Reserved,PIO1_30,Reserved,AD0,?..."
|
|
line.long 0x64 "R_PIO1_31,R_PIO1_31 register"
|
|
bitfld.long 0x64 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x64 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x64 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x64 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x64 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x64 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x64 0.--2. " FUNC ,Pin function" "Reserved,PIO1_31,Reserved,AD3,?..."
|
|
line.long 0x68 "R_PIO1_0,R_PIO1_0 register"
|
|
bitfld.long 0x68 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x68 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x68 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x68 9. " DRV ,Drive current mode" "2 mA drive,High"
|
|
bitfld.long 0x68 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x68 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x68 0.--2. " FUNC ,Pin function" "Reserved,PIO1_0,AD2,?..."
|
|
line.long 0x6C "R_PIO1_1,R_PIO1_1 register"
|
|
bitfld.long 0x6C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x6C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x6C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x6C 9. " DRV ,Drive current mode" "2 mA drive,High"
|
|
bitfld.long 0x6C 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x6C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x6C 0.--2. " FUNC ,Pin function" "Reserved,PIO1_0,AD3,?..."
|
|
line.long 0x70 "PIO1_2,PIO1_2 register"
|
|
bitfld.long 0x70 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x70 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x70 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x70 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x70 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x70 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x70 0.--2. " FUNC ,Pin function" "PIO1_2,SWDIO,AD4,?..."
|
|
line.long 0x74 "PIO1_3,PIO1_3 register"
|
|
bitfld.long 0x74 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x74 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x74 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x74 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x74 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x74 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x74 0.--2. " FUNC ,Pin function" "PIO1_3,AD5,?..."
|
|
line.long 0x78 "PIO1_4,PIO1_4 register"
|
|
bitfld.long 0x78 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x78 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x78 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x78 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x78 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x78 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x78 0.--2. " FUNC ,Pin function" "PIO1_4,AD6,?..."
|
|
line.long 0x7C "PIO1_5,PIO1_5 register"
|
|
bitfld.long 0x7C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x7C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x7C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x7C 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x7C 7. " ADMODE ,Analog/Digital mode" "Analog mode,Digital mode"
|
|
bitfld.long 0x7C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
bitfld.long 0x7C 0.--2. " FUNC ,Pin function" "PIO1_5,AD7,CT16B1_CAP0,CT16B1_MAT0,?..."
|
|
line.long 0x80 "PIO1_6,PIO1_6 register"
|
|
bitfld.long 0x80 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x80 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x80 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x80 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x80 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x80 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x80 0.--2. " FUNC ,Pin function" "PIO1_6,CT16B1_CAP1,CT16B1_MAT1,?..."
|
|
group.long 0xE0++0xF
|
|
line.long 0x00 "PIO2_8,PIO1_8 register"
|
|
bitfld.long 0x00 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x00 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " FUNC ,Pin function" "PIO2_8,Reserved,CT32B1_CAP0,CT32B1_MAT0,?..."
|
|
line.long 0x04 "PIO2_9,PIO2_9 register"
|
|
bitfld.long 0x04 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x04 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x04 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x04 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " FUNC ,Pin function" "PIO2_9,Reserved,CT32B1_CAP1,CT32B1_MAT1,?..."
|
|
line.long 0x08 "PIO2_10,PIO2_10 register"
|
|
bitfld.long 0x08 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x08 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x08 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x08 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " FUNC ,Pin function" "PIO2_10,Reserved,CT32B1_CAP2,CT32B1_MAT2,Reserved,TXD1,?..."
|
|
line.long 0x0C "PIO2_11,PIO2_11 register"
|
|
bitfld.long 0x0C 13.--15. " CLK_DIV ,Peripheral clock divider for input" "IOCONFIGCLKDIV0,IOCONFIGCLKDIV1,IOCONFIGCLKDIV2,IOCONFIGCLKDIV3,IOCONFIGCLKDIV4,IOCONFIGCLKDIV5,IOCONFIGCLKDIV6,?..."
|
|
bitfld.long 0x0C 11.--12. " S_MODE ,Sample mode" "No filter,One filter clock,Two filter clocks,Three filter clocks"
|
|
bitfld.long 0x0C 10. " OD ,Open-drain mode enable" "Disabled,Enbled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DRV ,Drive current mode" "Low,High"
|
|
bitfld.long 0x0C 6. " INV ,Invert input enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " MODE ,Function mode" "Inactive,Pull-up resistor"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Pin function" "PIO2_11,Reserved,CT32B1_CAP3,CT32B1_MAT3,Reserved,RXD1,?..."
|
|
tree.end
|
|
tree.open "GPIO (General Purpose Input/Output)"
|
|
tree "Port 0"
|
|
base ad:0x50000000
|
|
width 0x6
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MASK,GPIO mask register"
|
|
bitfld.long 0x00 31. " MASK0.31 ,PIO0_31 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " MASK0.30 ,PIO0_30 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " MASK0.29 ,PIO0_29 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MASK0.28 ,PIO0_28 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " MASK0.27 ,PIO0_27 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " MASK0.26 ,PIO0_26 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MASK0.25 ,PIO0_25 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " MASK0.24 ,PIO0_24 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MASK0.23 ,PIO0_23 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MASK0.22 ,PIO0_22 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " MASK0.21 ,PIO0_21 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " MASK0.20 ,PIO0_20 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MASK0.19 ,PIO0_19 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " MASK0.18 ,PIO0_18 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " MASK0.17 ,PIO0_17 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MASK0.16 ,PIO0_16 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MASK0.15 ,PIO0_15 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASK0.14 ,PIO0_14 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASK0.13 ,PIO0_13 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASK0.12 ,PIO0_12 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " MASK0.11 ,PIO0_11 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MASK0.10 ,PIO0_10 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " MASK0.9 ,PIO0_9 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASK0.8 ,PIO0_8 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASK0.7 ,PIO0_7 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASK0.6 ,PIO0_6 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MASK0.5 ,PIO0_5 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MASK0.4 ,PIO0_4 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " MASK0.3 ,PIO0_3 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASK0.2 ,PIO0_2 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASK0.1 ,PIO0_1 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASK0.0 ,PIO0_0 access control" "Not masked,Masked"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "PIN,GPIO pin value register"
|
|
bitfld.long 0x00 31. " PIN0.31 ,PIO0_31 value" "Low,High"
|
|
bitfld.long 0x00 30. " PIN0.30 ,PIO0_30 value" "Low,High"
|
|
bitfld.long 0x00 29. " PIN0.29 ,PIO0_29 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PIN0.28 ,PIO0_28 value" "Low,High"
|
|
bitfld.long 0x00 27. " PIN0.27 ,PIO0_27 value" "Low,High"
|
|
bitfld.long 0x00 26. " PIN0.26 ,PIO0_26 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PIN0.25 ,PIO0_25 value" "Low,High"
|
|
bitfld.long 0x00 24. " PIN0.24 ,PIO0_24 value" "Low,High"
|
|
bitfld.long 0x00 23. " PIN0.23 ,PIO0_23 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PIN0.22 ,PIO0_22 value" "Low,High"
|
|
bitfld.long 0x00 21. " PIN0.21 ,PIO0_21 value" "Low,High"
|
|
bitfld.long 0x00 20. " PIN0.20 ,PIO0_20 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PIN0.19 ,PIO0_19 value" "Low,High"
|
|
bitfld.long 0x00 18. " PIN0.18 ,PIO0_18 value" "Low,High"
|
|
bitfld.long 0x00 17. " PIN0.17 ,PIO0_17 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PIN0.16 ,PIO0_16 value" "Low,High"
|
|
bitfld.long 0x00 15. " PIN0.15 ,PIO0_15 value" "Low,High"
|
|
bitfld.long 0x00 14. " PIN0.14 ,PIO0_14 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PIN0.13 ,PIO0_13 value" "Low,High"
|
|
bitfld.long 0x00 12. " PIN0.12 ,PIO0_12 value" "Low,High"
|
|
bitfld.long 0x00 11. " PIN0.11 ,PIO0_11 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIN0.10 ,PIO0_10 value" "Low,High"
|
|
bitfld.long 0x00 9. " PIN0.9 ,PIO0_9 value" "Low,High"
|
|
bitfld.long 0x00 8. " PIN0.8 ,PIO0_8 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIN0.7 ,PIO0_7 value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN0.6 ,PIO0_6 value" "Low,High"
|
|
bitfld.long 0x00 5. " PIN0.5 ,PIO0_5 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIN0.4 ,PIO0_4 value" "Low,High"
|
|
bitfld.long 0x00 3. " PIN0.3 ,PIO0_3 value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN0.2 ,PIO0_2 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN0.1 ,PIO0_1 value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN0.0 ,PIO0_0 value" "Low,High"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "OUT,GPIO pin output register"
|
|
bitfld.long 0x00 31. " OUT0.31 ,PIO0_31 output value" "Low,High"
|
|
bitfld.long 0x00 30. " OUT0.30 ,PIO0_30 output value" "Low,High"
|
|
bitfld.long 0x00 29. " OUT0.29 ,PIO0_29 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OUT0.28 ,PIO0_28 output value" "Low,High"
|
|
bitfld.long 0x00 27. " OUT0.27 ,PIO0_27 output value" "Low,High"
|
|
bitfld.long 0x00 26. " OUT0.26 ,PIO0_26 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OUT0.25 ,PIO0_25 output value" "Low,High"
|
|
bitfld.long 0x00 24. " OUT0.24 ,PIO0_24 output value" "Low,High"
|
|
bitfld.long 0x00 23. " OUT0.23 ,PIO0_23 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OUT0.22 ,PIO0_22 output value" "Low,High"
|
|
bitfld.long 0x00 21. " OUT0.21 ,PIO0_21 output value" "Low,High"
|
|
bitfld.long 0x00 20. " OUT0.20 ,PIO0_20 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OUT0.19 ,PIO0_19 output value" "Low,High"
|
|
bitfld.long 0x00 18. " OUT0.18 ,PIO0_18 output value" "Low,High"
|
|
bitfld.long 0x00 17. " OUT0.17 ,PIO0_17 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OUT0.16 ,PIO0_16 output value" "Low,High"
|
|
bitfld.long 0x00 15. " OUT0.15 ,PIO0_15 output value" "Low,High"
|
|
bitfld.long 0x00 14. " OUT0.14 ,PIO0_14 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OUT0.13 ,PIO0_13 output value" "Low,High"
|
|
bitfld.long 0x00 12. " OUT0.12 ,PIO0_12 output value" "Low,High"
|
|
bitfld.long 0x00 11. " OUT0.11 ,PIO0_11 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OUT0.10 ,PIO0_10 output value" "Low,High"
|
|
bitfld.long 0x00 9. " OUT0.9 ,PIO0_9 output value" "Low,High"
|
|
bitfld.long 0x00 8. " OUT0.8 ,PIO0_8 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OUT0.7 ,PIO0_7 output value" "Low,High"
|
|
bitfld.long 0x00 6. " OUT0.6 ,PIO0_6 output value" "Low,High"
|
|
bitfld.long 0x00 5. " OUT0.5 ,PIO0_5 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OUT0.4 ,PIO0_4 output value" "Low,High"
|
|
bitfld.long 0x00 3. " OUT0.3 ,PIO0_3 output value" "Low,High"
|
|
bitfld.long 0x00 2. " OUT0.2 ,PIO0_2 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT0.1 ,PIO0_1 output value" "Low,High"
|
|
bitfld.long 0x00 0. " OUT0.0 ,PIO0_0 output value" "Low,High"
|
|
wgroup.long 0x0C++0x3
|
|
line.long 0x00 "SET,GPIO pin output set register"
|
|
bitfld.long 0x00 31. " SET0.31 ,PIO0_31 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 30. " SET0.30 ,PIO0_30 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 29. " SET0.29 ,PIO0_29 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SET0.28 ,PIO0_28 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 27. " SET0.27 ,PIO0_27 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 26. " SET0.26 ,PIO0_26 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SET0.25 ,PIO0_25 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 24. " SET0.24 ,PIO0_24 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 23. " SET0.23 ,PIO0_23 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SET0.22 ,PIO0_22 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 21. " SET0.21 ,PIO0_21 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 20. " SET0.20 ,PIO0_20 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SET0.19 ,PIO0_19 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 18. " SET0.18 ,PIO0_18 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 17. " SET0.17 ,PIO0_17 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SET0.16 ,PIO0_16 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 15. " SET0.15 ,PIO0_15 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET0.14 ,PIO0_14 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET0.13 ,PIO0_13 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET0.12 ,PIO0_12 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 11. " SET0.11 ,PIO0_11 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SET0.10 ,PIO0_10 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 9. " SET0.9 ,PIO0_9 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 8. " SET0.8 ,PIO0_8 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET0.7 ,PIO0_7 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 6. " SET0.6 ,PIO0_6 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 5. " SET0.5 ,PIO0_5 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SET0.4 ,PIO0_4 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 3. " SET0.3 ,PIO0_3 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 2. " SET0.2 ,PIO0_2 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET0.1 ,PIO0_1 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 0. " SET0.0 ,PIO0_0 output value set to high" "No effect,Set"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x00 "CLEAR,GPIO pin output clear register"
|
|
bitfld.long 0x00 31. " CLEAR0.31 ,PIO0_31 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 30. " CLEAR0.30 ,PIO0_30 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 29. " CLEAR0.29 ,PIO0_29 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CLEAR0.28 ,PIO0_28 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 27. " CLEAR0.27 ,PIO0_27 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CLEAR0.26 ,PIO0_26 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CLEAR0.25 ,PIO0_25 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CLEAR0.24 ,PIO0_24 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 23. " CLEAR0.23 ,PIO0_23 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CLEAR0.22 ,PIO0_22 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 21. " CLEAR0.21 ,PIO0_21 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CLEAR0.20 ,PIO0_20 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLEAR0.19 ,PIO0_19 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CLEAR0.18 ,PIO0_18 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CLEAR0.17 ,PIO0_17 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CLEAR0.16 ,PIO0_16 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 15. " CLEAR0.15 ,PIO0_15 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLEAR0.14 ,PIO0_14 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLEAR0.13 ,PIO0_13 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLEAR0.12 ,PIO0_12 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CLEAR0.11 ,PIO0_11 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CLEAR0.10 ,PIO0_10 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CLEAR0.9 ,PIO0_9 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLEAR0.8 ,PIO0_8 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLEAR0.7 ,PIO0_7 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLEAR0.14 ,PIO0_14 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLEAR0.13 ,PIO0_13 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLEAR0.12 ,PIO0_12 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CLEAR0.11 ,PIO0_11 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CLEAR0.10 ,PIO0_10 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CLEAR0.9 ,PIO0_9 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLEAR0.8 ,PIO0_8 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLEAR0.7 ,PIO0_7 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLEAR0.6 ,PIO0_6 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CLEAR0.5 ,PIO0_5 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLEAR0.4 ,PIO0_4 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CLEAR0.3 ,PIO0_3 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLEAR0.2 ,PIO0_2 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLEAR0.1 ,PIO0_1 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLEAR0.0 ,PIO0_0 output value clear to low" "No effect,Clear"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x00 "NOT,GPIO NOT register"
|
|
bitfld.long 0x00 31. " NOT0.31 ,PIO0_31 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 30. " NOT0.30 ,PIO0_30 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 29. " NOT0.29 ,PIO0_29 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 28. " NOT0.28 ,PIO0_28 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 27. " NOT0.27 ,PIO0_27 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 26. " NOT0.26 ,PIO0_26 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOT0.25 ,PIO0_25 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 24. " NOT0.24 ,PIO0_24 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 23. " NOT0.23 ,PIO0_23 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 22. " NOT0.22 ,PIO0_22 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 21. " NOT0.21 ,PIO0_21 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 20. " NOT0.20 ,PIO0_20 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOT0.19 ,PIO0_19 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 18. " NOT0.18 ,PIO0_18 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 17. " NOT0.17 ,PIO0_17 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOT0.16 ,PIO0_16 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 15. " NOT0.15 ,PIO0_15 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 14. " NOT0.14 ,PIO0_14 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOT0.13 ,PIO0_13 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 12. " NOT0.12 ,PIO0_12 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 11. " NOT0.11 ,PIO0_11 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOT0.10 ,PIO0_10 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 9. " NOT0.9 ,PIO0_9 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 8. " NOT0.8 ,PIO0_8 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOT0.7 ,PIO0_7 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 6. " NOT0.6 ,PIO0_6 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 5. " NOT0.5 ,PIO0_5 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOT0.4 ,PIO0_4 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 3. " NOT0.3 ,PIO0_3 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 2. " NOT0.2 ,PIO0_2 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOT0.1 ,PIO0_1 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 0. " NOT0.0 ,PIO0_0 output value invert" "No effect,Invert"
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "DIR,Data direction register"
|
|
bitfld.long 0x00 31. " IO0.31 ,PIO0_31 pin direction" "Input,Output"
|
|
bitfld.long 0x00 30. " IO0.30 ,PIO0_30 pin direction" "Input,Output"
|
|
bitfld.long 0x00 29. " IO0.29 ,PIO0_29 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IO0.28 ,PIO0_28 pin direction" "Input,Output"
|
|
bitfld.long 0x00 27. " IO0.27 ,PIO0_27 pin direction" "Input,Output"
|
|
bitfld.long 0x00 26. " IO0.26 ,PIO0_26 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IO0.25 ,PIO0_25 pin direction" "Input,Output"
|
|
bitfld.long 0x00 24. " IO0.24 ,PIO0_24 pin direction" "Input,Output"
|
|
bitfld.long 0x00 23. " IO0.23 ,PIO0_23 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IO0.22 ,PIO0_22 pin direction" "Input,Output"
|
|
bitfld.long 0x00 21. " IO0.21 ,PIO0_21 pin direction" "Input,Output"
|
|
bitfld.long 0x00 20. " IO0.20 ,PIO0_20 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IO0.19 ,PIO0_19 pin direction" "Input,Output"
|
|
bitfld.long 0x00 18. " IO0.18 ,PIO0_18 pin direction" "Input,Output"
|
|
bitfld.long 0x00 17. " IO0.17 ,PIO0_17 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IO0.16 ,PIO0_16 pin direction" "Input,Output"
|
|
bitfld.long 0x00 15. " IO0.15 ,PIO0_15 pin direction" "Input,Output"
|
|
bitfld.long 0x00 14. " IO0.14 ,PIO0_14 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IO0.13 ,PIO0_13 pin direction" "Input,Output"
|
|
bitfld.long 0x00 12. " IO0.12 ,PIO0_12 pin direction" "Input,Output"
|
|
bitfld.long 0x00 11. " IO0.11 ,PIO0_11 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IO0.10 ,PIO0_10 pin direction" "Input,Output"
|
|
bitfld.long 0x00 9. " IO0.9 ,PIO0_9 pin direction" "Input,Output"
|
|
bitfld.long 0x00 8. " IO0.8 ,PIO0_8 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IO0.7 ,PIO0_7 pin direction" "Input,Output"
|
|
bitfld.long 0x00 6. " IO0.6 ,PIO0_6 pin direction" "Input,Output"
|
|
bitfld.long 0x00 5. " IO0.5 ,PIO0_5 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IO0.4 ,PIO0_4 pin direction" "Input,Output"
|
|
bitfld.long 0x00 3. " IO0.3 ,PIO0_3 pin direction" "Input,Output"
|
|
bitfld.long 0x00 2. " IO0.2 ,PIO0_2 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IO0.1 ,PIO0_1 pin direction" "Input,Output"
|
|
bitfld.long 0x00 0. " IO0.0 ,PIO0_0 pin direction" "Input,Output"
|
|
line.long 0x04 "IS,Interrupt sense register"
|
|
bitfld.long 0x04 31. " ISENSE0.31 ,PIO0_31 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 30. " ISENSE0.30 ,PIO0_30 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 29. " ISENSE0.29 ,PIO0_29 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 28. " ISENSE0.28 ,PIO0_28 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 27. " ISENSE0.27 ,PIO0_27 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 26. " ISENSE0.26 ,PIO0_26 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ISENSE0.25 ,PIO0_25 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 24. " ISENSE0.24 ,PIO0_24 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 23. " ISENSE0.23 ,PIO0_23 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ISENSE0.22 ,PIO0_22 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 21. " ISENSE0.21 ,PIO0_21 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 20. " ISENSE0.20 ,PIO0_20 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ISENSE0.19 ,PIO0_19 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 18. " ISENSE0.18 ,PIO0_18 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 17. " ISENSE0.17 ,PIO0_17 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ISENSE0.16 ,PIO0_16 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 15. " ISENSE0.15 ,PIO0_15 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 14. " ISENSE0.14 ,PIO0_14 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ISENSE0.13 ,PIO0_13 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 12. " ISENSE0.12 ,PIO0_12 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 11. " ISENSE0.11 ,PIO0_11 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 10. " ISENSE0.10 ,PIO0_10 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 9. " ISENSE0.9 ,PIO0_9 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 8. " ISENSE0.8 ,PIO0_8 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ISENSE0.7 ,PIO0_7 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 6. " ISENSE0.6 ,PIO0_6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 5. " ISENSE0.5 ,PIO0_5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ISENSE0.4 ,PIO0_4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 3. " ISENSE0.3 ,PIO0_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 2. " ISENSE0.2 ,PIO0_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ISENSE0.1 ,PIO0_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 0. " ISENSE0.0 ,PIO0_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
line.long 0x08 "IBE,Interrupt both edges register"
|
|
bitfld.long 0x08 31. " IBE0.31 ,PIO0_31 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " IBE0.30 ,PIO0_30 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " IBE0.29 ,PIO0_29 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 28. " IBE0.28 ,PIO0_28 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " IBE0.27 ,PIO0_27 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " IBE0.26 ,PIO0_26 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IBE0.25 ,PIO0_25 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " IBE0.24 ,PIO0_24 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " IBE0.23 ,PIO0_23 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " IBE0.22 ,PIO0_22 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " IBE0.21 ,PIO0_21 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IBE0.20 ,PIO0_20 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IBE0.19 ,PIO0_19 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IBE0.18 ,PIO0_18 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " IBE0.17 ,PIO0_17 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " IBE0.16 ,PIO0_16 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " IBE0.15 ,PIO0_15 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " IBE0.14 ,PIO0_14 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IBE0.13 ,PIO0_13 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " IBE0.12 ,PIO0_12 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " IBE0.11 ,PIO0_11 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " IBE0.10 ,PIO0_10 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " IBE0.9 ,PIO0_9 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " IBE0.8 ,PIO0_8 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IBE0.7 ,PIO0_7 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IBE0.6 ,PIO0_6 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " IBE0.5 ,PIO0_5 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " IBE0.4 ,PIO0_4 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " IBE0.3 ,PIO0_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IBE0.2 ,PIO0_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IBE0.1 ,PIO0_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IBE0.0 ,PIO0_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
line.long 0x0C "IEV,Interrupt event register"
|
|
bitfld.long 0x0C 31. " IEV0.31 ,PIO0_31 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 30. " IEV0.30 ,PIO0_30 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 29. " IEV0.29 ,PIO0_29 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " IEV0.28 ,PIO0_28 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 27. " IEV0.27 ,PIO0_27 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 26. " IEV0.26 ,PIO0_26 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " IEV0.25 ,PIO0_25 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 24. " IEV0.24 ,PIO0_24 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 23. " IEV0.23 ,PIO0_23 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " IEV0.22 ,PIO0_22 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 21. " IEV0.21 ,PIO0_21 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 20. " IEV0.20 ,PIO0_20 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " IEV0.19 ,PIO0_19 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 18. " IEV0.18 ,PIO0_18 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 17. " IEV0.17 ,PIO0_17 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " IEV0.16 ,PIO0_16 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 15. " IEV0.15 ,PIO0_15 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 14. " IEV0.14 ,PIO0_14 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " IEV0.13 ,PIO0_13 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 12. " IEV0.12 ,PIO0_12 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 11. " IEV0.11 ,PIO0_11 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " IEV0.10 ,PIO0_10 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 9. " IEV0.9 ,PIO0_9 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 8. " IEV0.8 ,PIO0_8 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " IEV0.7 ,PIO0_7 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 6. " IEV0.6 ,PIO0_6 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 5. " IEV0.5 ,PIO0_5 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " IEV0.4 ,PIO0_4 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 3. " IEV0.3 ,PIO0_3 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 2. " IEV0.2 ,PIO0_2 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IEV0.1 ,PIO0_1 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 0. " IEV0.0 ,PIO0_0 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
line.long 0x10 "IE,Interrupt mask register"
|
|
bitfld.long 0x10 31. " MASK0.31 ,PIO0_31 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 30. " MASK0.30 ,PIO0_30 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 29. " MASK0.29 ,PIO0_29 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 28. " MASK0.28 ,PIO0_28 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 27. " MASK0.27 ,PIO0_27 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 26. " MASK0.26 ,PIO0_26 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 25. " MASK0.25 ,PIO0_25 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 24. " MASK0.24 ,PIO0_24 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 23. " MASK0.23 ,PIO0_23 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 22. " MASK0.22 ,PIO0_22 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 21. " MASK0.21 ,PIO0_21 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 20. " MASK0.20 ,PIO0_20 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 19. " MASK0.19 ,PIO0_19 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 18. " MASK0.18 ,PIO0_18 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 17. " MASK0.17 ,PIO0_17 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 16. " MASK0.16 ,PIO0_16 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 15. " MASK0.15 ,PIO0_15 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 14. " MASK0.14 ,PIO0_14 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 13. " MASK0.13 ,PIO0_13 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 12. " MASK0.12 ,PIO0_12 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 11. " MASK0.11 ,PIO0_11 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 10. " MASK0.10 ,PIO0_10 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 9. " MASK0.9 ,PIO0_9 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 8. " MASK0.8 ,PIO0_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 7. " MASK0.7 ,PIO0_7 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 6. " MASK0.6 ,PIO0_6 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 5. " MASK0.5 ,PIO0_5 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 4. " MASK0.4 ,PIO0_4 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 3. " MASK0.3 ,PIO0_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 2. " MASK0.2 ,PIO0_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 1. " MASK0.1 ,PIO0_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 0. " MASK0.0 ,PIO0_0 interrupt mask selection" "Masked,Not masked"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x00 "RIS,Raw interrupt status register"
|
|
bitfld.long 0x00 31. " RAWST0.31 ,PIO0_31 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " RAWST0.30 ,PIO0_30 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " RAWST0.29 ,PIO0_29 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RAWST0.28 ,PIO0_28 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " RAWST0.27 ,PIO0_27 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " RAWST0.26 ,PIO0_26 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RAWST0.25 ,PIO0_25 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " RAWST0.24 ,PIO0_24 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " RAWST0.23 ,PIO0_23 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RAWST0.22 ,PIO0_22 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " RAWST0.21 ,PIO0_21 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " RAWST0.20 ,PIO0_20 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAWST0.19 ,PIO0_19 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " RAWST0.18 ,PIO0_18 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " RAWST0.17 ,PIO0_17 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RAWST0.16 ,PIO0_16 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " RAWST0.15 ,PIO0_15 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " RAWST0.14 ,PIO0_14 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RAWST0.13 ,PIO0_13 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RAWST0.12 ,PIO0_12 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " RAWST0.11 ,PIO0_11 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RAWST0.10 ,PIO0_10 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " RAWST0.9 ,PIO0_9 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RAWST0.8 ,PIO0_8 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RAWST0.7 ,PIO0_7 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RAWST0.6 ,PIO0_6 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RAWST0.5 ,PIO0_5 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RAWST0.4 ,PIO0_4 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RAWST0.3 ,PIO0_3 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWST0.2 ,PIO0_2 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWST0.1 ,PIO0_1 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWST0.0 ,PIO0_0 raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "MIS,Masked interrupt status register"
|
|
bitfld.long 0x04 31. " MASKST0.31 ,PIO0_31 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 30. " MASKST0.30 ,PIO0_30 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 29. " MASKST0.29 ,PIO0_29 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 28. " MASKST0.28 ,PIO0_28 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 27. " MASKST0.27 ,PIO0_27 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 26. " MASKST0.26 ,PIO0_26 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " MASKST0.25 ,PIO0_25 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 24. " MASKST0.24 ,PIO0_24 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 23. " MASKST0.23 ,PIO0_23 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 22. " MASKST0.22 ,PIO0_22 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 21. " MASKST0.21 ,PIO0_21 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 20. " MASKST0.20 ,PIO0_20 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MASKST0.19 ,PIO0_19 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 18. " MASKST0.18 ,PIO0_18 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 17. " MASKST0.17 ,PIO0_17 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 16. " MASKST0.16 ,PIO0_16 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 15. " MASKST0.15 ,PIO0_15 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 14. " MASKST0.14 ,PIO0_14 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " MASKST0.13 ,PIO0_13 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 12. " MASKST0.12 ,PIO0_12 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 11. " MASKST0.11 ,PIO0_11 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MASKST0.10 ,PIO0_10 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 9. " MASKST0.9 ,PIO0_9 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 8. " MASKST0.8 ,PIO0_8 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MASKST0.7 ,PIO0_7 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 6. " MASKST0.6 ,PIO0_6 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 5. " MASKST0.5 ,PIO0_5 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " MASKST0.4 ,PIO0_4 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 3. " MASKST0.3 ,PIO0_3 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 2. " MASKST0.2 ,PIO0_2 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MASKST0.1 ,PIO0_1 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 0. " MASKST0.0 ,PIO0_0 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x00 "IC,GPIO interrupt clear register"
|
|
bitfld.long 0x00 31. " CLR0.31 ,PIO0_31 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " CLR0.30 ,PIO0_30 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " CLR0.29 ,PIO0_29 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CLR0.28 ,PIO0_28 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 27. " CLR0.27 ,PIO0_27 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CLR0.26 ,PIO0_26 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CLR0.25 ,PIO0_25 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CLR0.24 ,PIO0_24 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " CLR0.23 ,PIO0_23 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CLR0.22 ,PIO0_22 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " CLR0.21 ,PIO0_21 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CLR0.20 ,PIO0_20 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CLR0.19 ,PIO0_19 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CLR0.18 ,PIO0_18 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CLR0.17 ,PIO0_17 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CLR0.16 ,PIO0_16 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 15. " CLR0.15 ,PIO0_15 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CLR0.14 ,PIO0_14 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR0.13 ,PIO0_13 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLR0.12 ,PIO0_12 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CLR0.11 ,PIO0_11 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CLR0.10 ,PIO0_10 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CLR0.9 ,PIO0_9 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLR0.8 ,PIO0_8 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLR0.7 ,PIO0_7 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLR0.6 ,PIO0_6 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CLR0.5 ,PIO0_5 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLR0.4 ,PIO0_4 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CLR0.3 ,PIO0_3 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLR0.2 ,PIO0_2 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLR0.1 ,PIO0_1 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLR0.0 ,PIO0_0 interrupt clear" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "Port 1"
|
|
base ad:0x50010000
|
|
width 0x6
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MASK,GPIO mask register"
|
|
bitfld.long 0x00 6. " MASK1.6 ,PIO1_6 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MASK1.5 ,PIO1_5 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MASK1.4 ,PIO1_4 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " MASK1.3 ,PIO1_3 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASK1.2 ,PIO1_2 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASK1.1 ,PIO1_1 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASK1.0 ,PIO1_0 access control" "Not masked,Masked"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "PIN,GPIO pin value register"
|
|
bitfld.long 0x00 6. " PIN1.6 ,PIO1_6 value" "Low,High"
|
|
bitfld.long 0x00 5. " PIN1.5 ,PIO1_5 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIN1.4 ,PIO1_4 value" "Low,High"
|
|
bitfld.long 0x00 3. " PIN1.3 ,PIO1_3 value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN1.2 ,PIO1_2 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN1.1 ,PIO1_1 value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN1.0 ,PIO1_0 value" "Low,High"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "OUT,GPIO pin output register"
|
|
bitfld.long 0x00 6. " OUT1.6 ,PIO1_6 output value" "Low,High"
|
|
bitfld.long 0x00 5. " OUT1.5 ,PIO1_5 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OUT1.4 ,PIO1_4 output value" "Low,High"
|
|
bitfld.long 0x00 3. " OUT1.3 ,PIO1_3 output value" "Low,High"
|
|
bitfld.long 0x00 2. " OUT1.2 ,PIO1_2 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT1.1 ,PIO1_1 output value" "Low,High"
|
|
bitfld.long 0x00 0. " OUT1.0 ,PIO1_0 output value" "Low,High"
|
|
wgroup.long 0x0C++0x3
|
|
line.long 0x00 "SET,GPIO pin output set register"
|
|
bitfld.long 0x00 6. " SET1.6 ,PIO1_6 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 5. " SET1.5 ,PIO1_5 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SET1.4 ,PIO1_4 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 3. " SET1.3 ,PIO1_3 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 2. " SET1.2 ,PIO1_2 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET1.1 ,PIO1_1 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 0. " SET1.0 ,PIO1_0 output value set to high" "No effect,Set"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x00 "CLEAR,GPIO pin output clear register"
|
|
bitfld.long 0x00 6. " CLEAR1.6 ,PIO1_6 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CLEAR1.5 ,PIO1_5 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLEAR1.4 ,PIO1_4 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CLEAR1.3 ,PIO1_3 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLEAR1.2 ,PIO1_2 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLEAR1.1 ,PIO1_1 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLEAR1.0 ,PIO1_0 output value clear to low" "No effect,Clear"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x00 "NOT,GPIO NOT register"
|
|
bitfld.long 0x00 6. " NOT1.6 ,PIO1_6 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 5. " NOT1.5 ,PIO1_5 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOT1.4 ,PIO1_4 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 3. " NOT1.3 ,PIO1_3 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 2. " NOT1.2 ,PIO1_2 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOT1.1 ,PIO1_1 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 0. " NOT1.0 ,PIO1_0 output value invert" "No effect,Invert"
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "DIR,Data direction register"
|
|
bitfld.long 0x00 6. " IO1.6 ,PIO1_6 pin direction" "Input,Output"
|
|
bitfld.long 0x00 5. " IO1.5 ,PIO1_5 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IO1.4 ,PIO1_4 pin direction" "Input,Output"
|
|
bitfld.long 0x00 3. " IO1.3 ,PIO1_3 pin direction" "Input,Output"
|
|
bitfld.long 0x00 2. " IO1.2 ,PIO1_2 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IO1.1 ,PIO1_1 pin direction" "Input,Output"
|
|
bitfld.long 0x00 0. " IO1.0 ,PIO1_0 pin direction" "Input,Output"
|
|
line.long 0x04 "IS,Interrupt sense register"
|
|
bitfld.long 0x04 6. " ISENSE1.6 ,PIO1_6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 5. " ISENSE1.5 ,PIO1_5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ISENSE1.4 ,PIO1_4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 3. " ISENSE1.3 ,PIO1_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 2. " ISENSE1.2 ,PIO1_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ISENSE1.1 ,PIO1_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 0. " ISENSE1.0 ,PIO1_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
line.long 0x08 "IBE,Interrupt both edges register"
|
|
bitfld.long 0x08 6. " IBE1.6 ,PIO1_6 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " IBE1.5 ,PIO1_5 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " IBE1.4 ,PIO1_4 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " IBE1.3 ,PIO1_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IBE1.2 ,PIO1_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IBE1.1 ,PIO1_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IBE1.0 ,PIO1_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
line.long 0x0C "IEV,Interrupt event register"
|
|
bitfld.long 0x0C 6. " IEV1.6 ,PIO1_6 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 5. " IEV1.5 ,PIO1_5 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " IEV1.4 ,PIO1_4 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 3. " IEV1.3 ,PIO1_3 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 2. " IEV1.2 ,PIO1_2 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IEV1.1 ,PIO1_1 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 0. " IEV1.0 ,PIO1_0 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
line.long 0x10 "IE,Interrupt mask register"
|
|
bitfld.long 0x10 6. " MASK1.6 ,PIO1_6 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 5. " MASK1.5 ,PIO1_5 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 4. " MASK1.4 ,PIO1_4 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 3. " MASK1.3 ,PIO1_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 2. " MASK1.2 ,PIO1_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 1. " MASK1.1 ,PIO1_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 0. " MASK1.0 ,PIO1_0 interrupt mask selection" "Masked,Not masked"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x00 "RIS,Raw interrupt status register"
|
|
bitfld.long 0x00 6. " RAWST1.6 ,PIO1_6 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RAWST1.5 ,PIO1_5 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RAWST1.4 ,PIO1_4 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RAWST1.3 ,PIO1_3 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWST1.2 ,PIO1_2 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWST1.1 ,PIO1_1 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWST1.0 ,PIO1_0 raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "MIS,Masked interrupt status register"
|
|
bitfld.long 0x04 6. " MASKST1.6 ,PIO1_6 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 5. " MASKST1.5 ,PIO1_5 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " MASKST1.4 ,PIO1_4 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 3. " MASKST1.3 ,PIO1_3 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 2. " MASKST1.2 ,PIO1_2 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MASKST1.1 ,PIO1_1 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 0. " MASKST1.0 ,PIO1_0 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x00 "IC,GPIO interrupt clear register"
|
|
bitfld.long 0x00 6. " CLR1.6 ,PIO1_6 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CLR1.5 ,PIO1_5 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLR1.4 ,PIO1_4 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CLR1.3 ,PIO1_3 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLR1.2 ,PIO1_2 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLR1.1 ,PIO1_1 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLR1.0 ,PIO1_0 interrupt clear" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "Port 2"
|
|
base ad:0x50020000
|
|
width 0x6
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MASK,GPIO mask register"
|
|
bitfld.long 0x00 14. " MASK2.14 ,PIO2_14 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MASK2.13 ,PIO2_13 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASK2.12 ,PIO2_12 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " MASK2.11 ,PIO2_11 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MASK2.10 ,PIO2_10 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " MASK2.9 ,PIO2_9 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASK2.8 ,PIO2_8 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASK2.7 ,PIO2_7 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASK2.6 ,PIO2_6 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MASK2.5 ,PIO2_5 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MASK2.4 ,PIO2_4 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " MASK2.3 ,PIO2_3 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASK2.2 ,PIO2_2 access control" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MASK2.1 ,PIO2_1 access control" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASK2.0 ,PIO2_0 access control" "Not masked,Masked"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "PIN,GPIO pin value register"
|
|
bitfld.long 0x00 14. " PIN2.14 ,PIO2_14 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PIN2.13 ,PIO2_13 value" "Low,High"
|
|
bitfld.long 0x00 12. " PIN2.12 ,PIO2_12 value" "Low,High"
|
|
bitfld.long 0x00 11. " PIN2.11 ,PIO2_11 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PIN2.10 ,PIO2_10 value" "Low,High"
|
|
bitfld.long 0x00 9. " PIN2.9 ,PIO2_9 value" "Low,High"
|
|
bitfld.long 0x00 8. " PIN2.8 ,PIO2_8 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIN2.7 ,PIO2_7 value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN2.6 ,PIO2_6 value" "Low,High"
|
|
bitfld.long 0x00 5. " PIN2.5 ,PIO2_5 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIN2.4 ,PIO2_4 value" "Low,High"
|
|
bitfld.long 0x00 3. " PIN2.3 ,PIO2_3 value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN2.2 ,PIO2_2 value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN2.1 ,PIO2_1 value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN2.0 ,PIO2_0 value" "Low,High"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "OUT,GPIO pin output register"
|
|
bitfld.long 0x00 14. " OUT2.14 ,PIO2_14 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OUT2.13 ,PIO2_13 output value" "Low,High"
|
|
bitfld.long 0x00 12. " OUT2.12 ,PIO2_12 output value" "Low,High"
|
|
bitfld.long 0x00 11. " OUT2.11 ,PIO2_11 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OUT2.10 ,PIO2_10 output value" "Low,High"
|
|
bitfld.long 0x00 9. " OUT2.9 ,PIO2_9 output value" "Low,High"
|
|
bitfld.long 0x00 8. " OUT2.8 ,PIO2_8 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OUT2.7 ,PIO2_7 output value" "Low,High"
|
|
bitfld.long 0x00 6. " OUT2.6 ,PIO2_6 output value" "Low,High"
|
|
bitfld.long 0x00 5. " OUT2.5 ,PIO2_5 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OUT2.4 ,PIO2_4 output value" "Low,High"
|
|
bitfld.long 0x00 3. " OUT2.3 ,PIO2_3 output value" "Low,High"
|
|
bitfld.long 0x00 2. " OUT2.2 ,PIO2_2 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT2.1 ,PIO2_1 output value" "Low,High"
|
|
bitfld.long 0x00 0. " OUT2.0 ,PIO2_0 output value" "Low,High"
|
|
wgroup.long 0x0C++0x3
|
|
line.long 0x00 "SET,GPIO pin output set register"
|
|
bitfld.long 0x00 14. " SET2.14 ,PIO2_14 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET2.13 ,PIO2_13 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET2.12 ,PIO2_12 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 11. " SET2.11 ,PIO2_11 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SET2.10 ,PIO2_10 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 9. " SET2.9 ,PIO2_9 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 8. " SET2.8 ,PIO2_8 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET2.7 ,PIO2_7 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 6. " SET2.6 ,PIO2_6 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 5. " SET2.5 ,PIO2_5 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SET2.4 ,PIO2_4 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 3. " SET2.3 ,PIO2_3 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 2. " SET2.2 ,PIO2_2 output value set to high" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET2.1 ,PIO2_1 output value set to high" "No effect,Set"
|
|
bitfld.long 0x00 0. " SET2.0 ,PIO2_0 output value set to high" "No effect,Set"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x00 "CLEAR,GPIO pin output clear register"
|
|
bitfld.long 0x00 14. " CLEAR2.14 ,PIO2_14 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLEAR2.13 ,PIO2_13 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLEAR2.12 ,PIO2_12 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CLEAR2.11 ,PIO2_11 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CLEAR2.10 ,PIO2_10 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CLEAR2.9 ,PIO2_9 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLEAR2.8 ,PIO2_8 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLEAR2.7 ,PIO2_7 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLEAR2.6 ,PIO2_6 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CLEAR2.5 ,PIO2_5 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLEAR2.4 ,PIO2_4 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CLEAR2.3 ,PIO2_3 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLEAR2.2 ,PIO2_2 output value clear to low" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLEAR2.1 ,PIO2_1 output value clear to low" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLEAR2.0 ,PIO2_0 output value clear to low" "No effect,Clear"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x00 "NOT,GPIO NOT register"
|
|
bitfld.long 0x00 14. " NOT2.14 ,PIO2_14 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NOT2.13 ,PIO2_13 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 12. " NOT2.12 ,PIO2_12 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 11. " NOT2.11 ,PIO2_11 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOT2.10 ,PIO2_10 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 9. " NOT2.9 ,PIO2_9 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 8. " NOT2.8 ,PIO2_8 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOT2.7 ,PIO2_7 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 6. " NOT2.6 ,PIO2_6 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 5. " NOT2.5 ,PIO2_5 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOT2.4 ,PIO2_4 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 3. " NOT2.3 ,PIO2_3 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 2. " NOT2.2 ,PIO2_2 output value invert" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOT2.1 ,PIO2_1 output value invert" "No effect,Invert"
|
|
bitfld.long 0x00 0. " NOT2.0 ,PIO2_0 output value invert" "No effect,Invert"
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "DIR,Data direction register"
|
|
bitfld.long 0x00 14. " IO2.14 ,PIO2_14 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IO2.13 ,PIO2_13 pin direction" "Input,Output"
|
|
bitfld.long 0x00 12. " IO2.12 ,PIO2_12 pin direction" "Input,Output"
|
|
bitfld.long 0x00 11. " IO2.11 ,PIO2_11 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IO2.10 ,PIO2_10 pin direction" "Input,Output"
|
|
bitfld.long 0x00 9. " IO2.9 ,PIO2_9 pin direction" "Input,Output"
|
|
bitfld.long 0x00 8. " IO2.8 ,PIO2_8 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IO2.7 ,PIO2_7 pin direction" "Input,Output"
|
|
bitfld.long 0x00 6. " IO2.6 ,PIO2_6 pin direction" "Input,Output"
|
|
bitfld.long 0x00 5. " IO2.5 ,PIO2_5 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IO2.4 ,PIO2_4 pin direction" "Input,Output"
|
|
bitfld.long 0x00 3. " IO2.3 ,PIO2_3 pin direction" "Input,Output"
|
|
bitfld.long 0x00 2. " IO2.2 ,PIO2_2 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IO2.1 ,PIO2_1 pin direction" "Input,Output"
|
|
bitfld.long 0x00 0. " IO2.0 ,PIO2_0 pin direction" "Input,Output"
|
|
line.long 0x04 "IS,Interrupt sense register"
|
|
bitfld.long 0x04 14. " ISENSE2.14 ,PIO2_14 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ISENSE2.13 ,PIO2_13 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 12. " ISENSE2.12 ,PIO2_12 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 11. " ISENSE2.11 ,PIO2_11 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 10. " ISENSE2.10 ,PIO2_10 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 9. " ISENSE2.9 ,PIO2_9 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 8. " ISENSE2.8 ,PIO2_8 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ISENSE2.7 ,PIO2_7 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 6. " ISENSE2.6 ,PIO2_6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 5. " ISENSE2.5 ,PIO2_5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ISENSE2.4 ,PIO2_4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 3. " ISENSE2.3 ,PIO2_3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 2. " ISENSE2.2 ,PIO2_2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ISENSE2.1 ,PIO2_1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x04 0. " ISENSE2.0 ,PIO2_0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
line.long 0x08 "IBE,Interrupt both edges register"
|
|
bitfld.long 0x08 14. " IBE2.14 ,PIO2_14 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IBE2.13 ,PIO2_13 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " IBE2.12 ,PIO2_12 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " IBE2.11 ,PIO2_11 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " IBE2.10 ,PIO2_10 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " IBE2.9 ,PIO2_9 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " IBE2.8 ,PIO2_8 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IBE2.7 ,PIO2_7 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IBE2.6 ,PIO2_6 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " IBE2.5 ,PIO2_5 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " IBE2.4 ,PIO2_4 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " IBE2.3 ,PIO2_3 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IBE2.2 ,PIO2_2 interrupt on both edges enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IBE2.1 ,PIO2_1 interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IBE2.0 ,PIO2_0 interrupt on both edges enable" "Disabled,Enabled"
|
|
line.long 0x0C "IEV,Interrupt event register"
|
|
bitfld.long 0x0C 14. " IEV2.14 ,PIO2_14 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " IEV2.13 ,PIO2_13 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 12. " IEV2.12 ,PIO2_12 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 11. " IEV2.11 ,PIO2_11 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " IEV2.10 ,PIO2_10 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 9. " IEV2.9 ,PIO2_9 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 8. " IEV2.8 ,PIO2_8 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " IEV2.7 ,PIO2_7 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 6. " IEV2.6 ,PIO2_6 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 5. " IEV2.5 ,PIO2_5 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " IEV2.4 ,PIO2_4 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 3. " IEV2.3 ,PIO2_3 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 2. " IEV2.2 ,PIO2_2 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " IEV2.1 ,PIO2_1 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 0. " IEV2.0 ,PIO2_0 interrupt falling/rising edge selection" "Falling/Low,Rising/High"
|
|
line.long 0x10 "IE,Interrupt mask register"
|
|
bitfld.long 0x10 14. " MASK2.14 ,PIO2_14 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 13. " MASK2.13 ,PIO2_13 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 12. " MASK2.12 ,PIO2_12 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 11. " MASK2.11 ,PIO2_11 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 10. " MASK2.10 ,PIO2_10 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 9. " MASK2.9 ,PIO2_9 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 8. " MASK2.8 ,PIO2_8 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 7. " MASK2.7 ,PIO2_7 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 6. " MASK2.6 ,PIO2_6 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 5. " MASK2.5 ,PIO2_5 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 4. " MASK2.4 ,PIO2_4 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 3. " MASK2.3 ,PIO2_3 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 2. " MASK2.2 ,PIO2_2 interrupt mask selection" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 1. " MASK2.1 ,PIO2_1 interrupt mask selection" "Masked,Not masked"
|
|
bitfld.long 0x10 0. " MASK2.0 ,PIO2_0 interrupt mask selection" "Masked,Not masked"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x00 "RIS,Raw interrupt status register"
|
|
bitfld.long 0x00 14. " RAWST2.14 ,PIO2_14 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RAWST2.13 ,PIO2_13 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RAWST2.12 ,PIO2_12 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " RAWST2.11 ,PIO2_11 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RAWST2.10 ,PIO2_10 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " RAWST2.9 ,PIO2_9 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RAWST2.8 ,PIO2_8 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RAWST2.7 ,PIO2_7 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RAWST2.6 ,PIO2_6 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RAWST2.5 ,PIO2_5 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RAWST2.4 ,PIO2_4 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RAWST2.3 ,PIO2_3 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RAWST2.2 ,PIO2_2 raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAWST2.1 ,PIO2_1 raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RAWST2.0 ,PIO2_0 raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "MIS,Masked interrupt status register"
|
|
bitfld.long 0x04 14. " MASKST2.14 ,PIO2_14 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " MASKST2.13 ,PIO2_13 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 12. " MASKST2.12 ,PIO2_12 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 11. " MASKST2.11 ,PIO2_11 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MASKST2.10 ,PIO2_10 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 9. " MASKST2.9 ,PIO2_9 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 8. " MASKST2.8 ,PIO2_8 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MASKST2.7 ,PIO2_7 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 6. " MASKST2.6 ,PIO2_6 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 5. " MASKST2.5 ,PIO2_5 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " MASKST2.4 ,PIO2_4 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 3. " MASKST2.3 ,PIO2_3 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 2. " MASKST2.2 ,PIO2_2 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MASKST2.1 ,PIO2_1 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
bitfld.long 0x04 0. " MASKST2.0 ,PIO2_0 masked interrupt status" "No interrupt/Masked,Interrupt"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x00 "IC,GPIO interrupt clear register"
|
|
bitfld.long 0x00 14. " CLR2.14 ,PIO2_14 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR2.13 ,PIO2_13 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CLR2.12 ,PIO2_12 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CLR2.11 ,PIO2_11 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CLR2.10 ,PIO2_10 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CLR2.9 ,PIO2_9 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CLR2.8 ,PIO2_8 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLR2.7 ,PIO2_7 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CLR2.6 ,PIO2_6 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CLR2.5 ,PIO2_5 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLR2.4 ,PIO2_4 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CLR2.3 ,PIO2_3 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CLR2.2 ,PIO2_2 interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLR2.1 ,PIO2_1 interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLR2.0 ,PIO2_0 interrupt clear" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART0 with modem control"
|
|
base ad:0x40008000
|
|
width 11.
|
|
if (((per.l((ad:0x40008000+0xC)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "U0RBR/THR,Receiver/Transmit Buffer Register"
|
|
in
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U0IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud Time-out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of Auto-baud Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLSIE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THREIE ,THRE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RBRIE ,RBR Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "U0DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,UARTn Divisor Latch LSB"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U0DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLMSB ,UARTn Divisor Latch MSB"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "U0IIR,Interrupt ID"
|
|
in
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "U0FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTRIGLVL ,Rx Trigger Level Select" "Level 0(1 char.),Level 1(4 char.),Level 2(8 char.),Level 3(14 char.)"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC11D14"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x0 3. " DMAMODE ,DMA Mode Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 2. " TXFIFORES ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " RXFIFORES ,Receiver FIFO Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOENABLE ,FIFO Enable" "Disable,Enable"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "U0MCR,USART Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback Mode Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTSCON ,Source for modem output pin RTS" "Active,Inactive"
|
|
bitfld.long 0x00 0. " DTRCON ,Source for modem output pin DTR" "Active,Inactive"
|
|
endif
|
|
if ((per.l((ad:0x40008000+0xC))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U0LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U0LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC11D14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U0MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Low,High"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "U0LSR,Line Status Register"
|
|
in
|
|
sif (cpu()=="EM773"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U0MSR,Modem Status Register"
|
|
in
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "U0SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Pad ,A readable/writable byte"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "U0ACR,Auto-baud Control Register"
|
|
bitfld.long 0x00 9. " ABTOINTCLR ,Auto-baud Time-out Interrupt Clear Bit" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " ABEOINTCLR ,End of Auto-baud Interrupt Clear Bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTORESTART ,Auto Restart" "Not restarted,Restarted"
|
|
bitfld.long 0x00 1. " MODE ,Auto-baud Mode Select" "Mode 0,Mode 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Auto-baud Start" "Stopped,Started"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
elif (cpu()!="EM773"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
if (((per.l((ad:0x40008000+0x24)))&0x4)==0x4)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U0ICR,IrDA Control Register"
|
|
sif cpu()=="LPC11U12/201"||cpu()=="LPC11U13/x201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "3/(16 * baud rate),2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk"
|
|
else
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U0ICR,IrDA Control Register"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
endif
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "U0FDR,Fractional Divider Register"
|
|
bitfld.long 0x00 4.--7. " MULVAL , Pre-scaler Multiplier Value" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "No effect,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
endif
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times (ETUs)"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40008000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "U0OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U0HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
width 17.
|
|
if (((per.l((ad:0x40008000+0x48)))&0x04)==0x04)
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U0SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GUARDTIME ,Extra guard time"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("LPC176*")&&!cpuis("LPC175*")&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "U0FIFOLVL,FIFO Level Register"
|
|
bitfld.long 0x00 8.--11. " TXFIFOLVL ,Level of the UART transmitter FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
bitfld.long 0x00 0.--3. " RXFIFILVL ,Level of the UART receiver FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
width 17.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x04 "U0RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
line.long 0x08 "SYNCCTRL,Synchronous mode control register"
|
|
bitfld.long 0x08 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x08 5. " SSSDIS ,Start/stop bits" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x08 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x08 1. " CSRC ,Clock source select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SYNC ,Enables synchronous mode" "Disabled,Enabled"
|
|
line.long 0x0C "U0TER,Transmit Enable Register"
|
|
bitfld.long 0x0C 0. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
width 17.
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
sif (cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24")
|
|
textline " "
|
|
bitfld.long 0x00 3. " SEL ,Direction control pin select" "/RTS,/DTR"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "U0RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
sif (cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11D14"&&cpu()!="LPC1112LV"&&cpu()!="LPC1114LV")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNCCTRL,Synchronous mode control register"
|
|
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x00 5. " SSSDIS ,Start/stop bits" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC ,Enables synchronous mode" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
width 16.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U0RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "U0RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x4000C000
|
|
width 11.
|
|
if (((per.l((ad:0x4000C000+0xC)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "U1RBR/THR,Receiver/Transmit Buffer Register"
|
|
in
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U1IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud Time-out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of Auto-baud Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTSIE ,Modem status interrupt generation on a CTS1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXLSIE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THREIE ,THRE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RBRIE ,RBR Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "U1DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,UARTn Divisor Latch LSB"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "U1DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLMSB ,UARTn Divisor Latch MSB"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "U1IIR,Interrupt ID"
|
|
in
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "U1FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTRIGLVL ,Rx Trigger Level Select" "Level 0(1 char.),Level 1(4 char.),Level 2(8 char.),Level 3(14 char.)"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC11D14"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))
|
|
bitfld.long 0x0 3. " DMAMODE ,DMA Mode Enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 2. " TXFIFORES ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " RXFIFORES ,Receiver FIFO Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOENABLE ,FIFO Enable" "Disable,Enable"
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "U1MCR,USART Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback Mode Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTSCON ,Source for modem output pin RTS" "Active,Inactive"
|
|
bitfld.long 0x00 0. " DTRCON ,Source for modem output pin DTR" "Active,Inactive"
|
|
endif
|
|
if ((per.l((ad:0x4000C000+0xC))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U1LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "U1LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BREAKCONTROL ,Break Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PARITYSELECT ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PARITYENABLE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SBS ,Stop Bit Select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U1MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin, DTR" "Low,High"
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC11D14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "U1MCR,Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,Auto-cts flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,Auto-rts flow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPMODE ,Modem loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Low,High"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "U1LSR,Line Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U1MSR,Modem Status Register"
|
|
in
|
|
sif (cpu()=="EM773"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "U1MSR,Modem Status Register"
|
|
in
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "U1SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Pad ,A readable/writable byte"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "U1ACR,Auto-baud Control Register"
|
|
bitfld.long 0x00 9. " ABTOINTCLR ,Auto-baud Time-out Interrupt Clear Bit" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " ABEOINTCLR ,End of Auto-baud Interrupt Clear Bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTORESTART ,Auto Restart" "Not restarted,Restarted"
|
|
bitfld.long 0x00 1. " MODE ,Auto-baud Mode Select" "Mode 0,Mode 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Auto-baud Start" "Stopped,Started"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
elif (cpu()!="EM773"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227")
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
if (((per.l((ad:0x4000C000+0x24)))&0x4)==0x4)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U1ICR,IrDA Control Register"
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "U1ICR,IrDA Control Register"
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,IrDA Serial Input Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed-pulse-width mode" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "U1FDR,Fractional Divider Register"
|
|
bitfld.long 0x00 4.--7. " MULVAL , Pre-scaler Multiplier Value" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpu()=="EM773"||cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "No effect,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL , Pre-scaler Divisor Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
endif
|
|
sif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "U1OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" "Reserved,0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U1TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "U1HDEN,USART Half-duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "U1SCICCTRL,Smart Card Interface Control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times (ETUs)"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart Card Interface Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U1TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "U1TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
endif
|
|
sif (!cpuis("LPC176*")&&!cpuis("LPC175*")&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="EM773"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*")&&cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "U1FIFOLVL,FIFO Level Register"
|
|
bitfld.long 0x00 8.--11. " TXFIFOLVL ,Level of the UART transmitter FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
bitfld.long 0x00 0.--3. " RXFIFILVL ,Level of the UART receiver FIFO" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Full"
|
|
endif
|
|
sif (cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
width 17.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "U1RS485CTRL,RS485 Control register"
|
|
bitfld.long 0x00 5. " OINV ,Reverses the polarity of the direction control signal on the RTS (or DTR) pin" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto Direction Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SEL ,Direction control pin select" "/RTS,/DTR"
|
|
bitfld.long 0x00 2. " AADEN ,Auto Address Detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode" "Disabled,Enabled"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "U1RS485ADRMATCH,RS485 Address Match register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x04 "U1RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLY ,Direction control (RTS or DTR) delay value"
|
|
sif (cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*"))
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "U1TER,Transmit Enable Register"
|
|
bitfld.long 0x00 0. " TXEN ,Transmission Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()!="LPC4310FBD144"&&cpu()!="LPC4310FBD144-M0"&&cpu()!="LPC4310FET100"&&cpu()!="LPC4310FET100-M0"&&cpu()!="LPC4320FBD100"&&cpu()!="LPC4320FBD100-M0"&&cpu()!="LPC4320FBD144"&&cpu()!="LPC4320FBD144-M0"&&cpu()!="LPC4320FET100"&&cpu()!="LPC4320FET100-M0"&&cpu()!="LPC4330FBD144"&&cpu()!="LPC4330FBD144-M0"&&cpu()!="LPC4330FET100"&&cpu()!="LPC4330FET100-M0"&&cpu()!="LPC4330FET180"&&cpu()!="LPC4330FET180-M0"&&cpu()!="LPC4330FET256"&&cpu()!="LPC4330FET256-M0"&&cpu()!="LPC4350FBD208"&&cpu()!="LPC4350FBD208-M0"&&cpu()!="LPC4350FET180"&&cpu()!="LPC4350FET180-M0"&&cpu()!="LPC4350FET256"&&cpu()!="LPC4350FET256-M0"&&cpu()!="LPC4333FBD144"&&cpu()!="LPC4333FBD144-M0"&&cpu()!="LPC4333FET100"&&cpu()!="LPC4333FET100-M0"&&cpu()!="LPC4333FET180"&&cpu()!="LPC4333FET180-M0"&&cpu()!="LPC4333FET256"&&cpu()!="LPC4333FET256-M0"&&cpu()!="LPC4337FBD144"&&cpu()!="LPC4337FBD144-M0"&&cpu()!="LPC4337FET100"&&cpu()!="LPC4337FET100-M0"&&cpu()!="LPC4337FET180"&&cpu()!="LPC4337FET180-M0"&&cpu()!="LPC4337FET256"&&cpu()!="LPC4337FET256-M0"&&cpu()!="LPC4353FBD208"&&cpu()!="LPC4353FBD208-M0"&&cpu()!="LPC4353FET180"&&cpu()!="LPC4353FET180-M0"&&cpu()!="LPC4353FET256"&&cpu()!="LPC4353FET256-M0"&&cpu()!="LPC4357FBD208"&&cpu()!="LPC4357FBD208-M0"&&cpu()!="LPC4357FET256"&&cpu()!="LPC4357FET256-M0"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x40000000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CON,I2C0 Control Register"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_set/clr ,I2C interface enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_set/clr ,START flag" "Not started,Started"
|
|
bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stop"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_set/clr ,I2C interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_set/clr ,Assert acknowledge flag" "Not asserted,Asserted"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STAT,I2C0 Status Register"
|
|
bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "Bus error/undefined,START transmitted,Repeated START transmitted,SLA+W transmitted/ACK,SLA+W transmitted/NOT ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Arbitration lost SLA+R/W/Data/NOT ACK,SLA+R transmitted/ACK,SLA+R transmitted/NOT ACK,Data received/ACK,Data received/NOT ACK,Own SLA+W received/ACK,Arbitration lost SLA+R/W/Own SLA+W received/ACK,GCA (0x00) received/ACK,Arbitration lost SLA+R/W/GCA received/ACK,Own SLV/DATA received/ACK,Own SLA/DATA received/NOT ACK,General Call/DATA received/ACK,General Call/DATA received/NOT ACK,STOP/repeated START received SLV/REC/SLV/TRX,Own SLA+R received/ACK,Arbitration lost SLA+R/W/Own SLA+R received/ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Last I2DAT transmitted/ACK,,,,,,No information/SI = 0"
|
|
newline
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "DAT,I2C0 Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
line.long 0x04 "ADR0,I2C0 Slave Address Register 0"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Slave mode address"
|
|
bitfld.long 0x04 0. " GC ,General call enable bit" "Disabled,Enabled"
|
|
line.long 0x08 "SCLH,I2C0 SCL High Duty Cycle Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL HIGH time period selection"
|
|
line.long 0x0C "SCLL,I2C0 SCL Low Duty Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SCLL ,Count for SCL LOW time period selection"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MMCTRL,I2C0 Monitor Mode Control Register"
|
|
sif cpuis("LPC1311")||cpuis("LPC1313")||cpuis("LPC1342")||cpuis("LPC1343")||cpuis("EM773")||cpuis("LPC11A02")||cpuis("LPC11A04")||cpuis("LPC11A11")||cpuis("LPC11A12")||cpuis("LPC11A13")||cpuis("LPC11A14")
|
|
bitfld.long 0x00 3. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
else
|
|
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
endif
|
|
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADR1,I2C0 Slave Address Register 1"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADR2,I2C0 Slave Address Register 2"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADR3,I2C0 Slave Address Register 3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call bit enable" "Disabled,Enabled"
|
|
sif cpuis("LPC4072FBD80")||cpuis("LPC4072FET80")||cpuis("LPC4074FBD144")||cpuis("LPC4076FBD144")||cpuis("LPC4076FET180")||cpuis("LPC4078FBD100")||cpuis("LPC4078FBD144")||cpuis("LPC4078FBD208")||cpuis("LPC4078FBD80")||cpuis("LPC4078FET180")||cpuis("LPC4078FET208")||(cpu()=="LPC4088FBD144")||cpuis("LPC4088FBD208")||cpuis("LPC4088FET180")||cpuis("LPC4088FET208")||cpuis("LPC11E*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
elif cpuis("LPC111*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC112*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data"
|
|
else
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "DATA_BUFFER,I2C0 Data Buffer Register"
|
|
in
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MASK0,I2C0 Mask Register 0"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MASK1,I2C0 Mask Register 1"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MASK2,I2C0 Mask Register 2"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MASK3,I2C0 Mask Register 3"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSP (Synchronous Serial Port)"
|
|
base ad:0x40040000
|
|
width 11.
|
|
if ((per.l(ad:0x40040000)&0x30)==0x00)
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SSP0CR0,SSP0 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock Out Phase" "First clock,Second clock"
|
|
bitfld.long 0x00 6. " CPOL ,Clock Out Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP0CR0,SSP0 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x04)&0x4)==0x04)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave Output Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
endif
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSP0DR,SSP0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SSP0DR,SSP0 Data Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSP0SR,SSP0 Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO Not Empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO Not Full" "Full,Not Full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SSP0CPSR,SSP0 Clock Prescale Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CPSDVSR ,PCLK Divisor (even value between 2 and 254)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SSP0IMSC,SSP0 Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x00 3. " TXIM ,Tx FIFO Half Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIM ,Rx FIFO Half Full Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTIM ,Receive Timeout Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORIM ,Receive Overrun Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SSP0RIS,SSP0 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO Half Empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO Half Full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive Timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORRIS ,Frame Received When RxFIFO Full" "Not received,Received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SSP0MIS,SSP0 Masked Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXMIS ,Tx FIFO Half Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXMIS ,Rx FIFO Half Full Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RTMIS ,Receive Timeout Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RORMIS ,Frame Received When RxFIFO Full Interrupt" "No interrupt,Interrupt"
|
|
sif (cpu()=="EM773"||cpuis("LPC11E*")||cpu()=="LPC4310FBD144"||cpu()=="LPC4310FBD144-M0"||cpu()=="LPC4310FET100"||cpu()=="LPC4310FET100-M0"||cpu()=="LPC4320FBD100"||cpu()=="LPC4320FBD100-M0"||cpu()=="LPC4320FBD144"||cpu()=="LPC4320FBD144-M0"||cpu()=="LPC4320FET100"||cpu()=="LPC4320FET100-M0"||cpu()=="LPC4330FBD144"||cpu()=="LPC4330FBD144-M0"||cpu()=="LPC4330FET100"||cpu()=="LPC4330FET100-M0"||cpu()=="LPC4330FET180"||cpu()=="LPC4330FET180-M0"||cpu()=="LPC4330FET256"||cpu()=="LPC4330FET256-M0"||cpu()=="LPC4350FBD208"||cpu()=="LPC4350FBD208-M0"||cpu()=="LPC4350FET180"||cpu()=="LPC4350FET180-M0"||cpu()=="LPC4350FET256"||cpu()=="LPC4350FET256-M0"||cpu()=="LPC4333FBD144"||cpu()=="LPC4333FBD144-M0"||cpu()=="LPC4333FET100"||cpu()=="LPC4333FET100-M0"||cpu()=="LPC4333FET180"||cpu()=="LPC4333FET180-M0"||cpu()=="LPC4333FET256"||cpu()=="LPC4333FET256-M0"||cpu()=="LPC4337FBD144"||cpu()=="LPC4337FBD144-M0"||cpu()=="LPC4337FET100"||cpu()=="LPC4337FET100-M0"||cpu()=="LPC4337FET180"||cpu()=="LPC4337FET180-M0"||cpu()=="LPC4337FET256"||cpu()=="LPC4337FET256-M0"||cpu()=="LPC4353FBD208"||cpu()=="LPC4353FBD208-M0"||cpu()=="LPC4353FET180"||cpu()=="LPC4353FET180-M0"||cpu()=="LPC4353FET256"||cpu()=="LPC4353FET256-M0"||cpu()=="LPC4357FBD208"||cpu()=="LPC4357FBD208-M0"||cpu()=="LPC4357FET256"||cpu()=="LPC4357FET256-M0"||cpuis("LPC11U3*")||cpuis("LPC11U6*"))
|
|
wgroup.long 0x20++0x03
|
|
else
|
|
group.long 0x20++0x03
|
|
endif
|
|
line.long 0x00 "SSP0ICR,SSP0 Interrupt Clear Register"
|
|
bitfld.long 0x0 1. " RTIC ,Receive Timeout Clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " RORIC ,Clear Frame Received When RxFIFO Full" "No effect,Clear"
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&!cpuis("LPC11U24*")&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*"))||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SSP0DMACR,SSP0 DMA Control Register"
|
|
bitfld.long 0x0 1. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CT16B (16-bit counter/timer)"
|
|
tree "CT16B0"
|
|
base ad:0x40010000
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "TMR16B0IR,CT16B0 Interrupt Register"
|
|
sif (cpu()!="LPC1102LV"&&cpu()!="LPC1102"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif cpuis("LPC11E*")
|
|
eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TMR16B0TCR,CT16B0 Timer Control Register"
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 1. " CRST ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CEN ,Counter Enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR16B0TC,CT16B0 Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
|
|
line.long 0x04 "TMR16B0PR,CT16B0 Prescale Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PR ,Prescale max value"
|
|
line.long 0x08 "TMR16B0PC,CT16B0 Prescale Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value"
|
|
else
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR16B0TC,CT16B0 Timer Counter Register"
|
|
line.long 0x04 "TMR16B0PR,CT16B0 Prescale Register"
|
|
line.long 0x08 "TMR16B0PC,CT16B0 Prescale Counter Register"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TMR16B0MCR,CT16B0 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR16B0MR0,CT16B0 Match Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x04 "TMR16B0MR1,CT16B0 Match Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x08 "TMR16B0MR2,CT16B0 Match Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x0C "TMR16B0MR3,CT16B0 Match Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value"
|
|
else
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR16B0MR0,CT16B0 Match Register 0"
|
|
line.long 0x04 "TMR16B0MR1,CT16B0 Match Register 1"
|
|
line.long 0x08 "TMR16B0MR2,CT16B0 Match Register 2"
|
|
line.long 0x0C "TMR16B0MR3,CT16B0 Match Register 3"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR16B0CCR,CT16B0 Capture Control Register"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on comparator 0 edge output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on comparator 0 edge output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on comparator 0 edge output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on comparator 0 level output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on comparator 0 level output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on comparator 0 level output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT16B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT16B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT16B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("LPC11E*")
|
|
bitfld.long 0x00 8. " CAP1I ,Interrupt on CT16B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP1FE ,Capture on CT16B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP1RE ,Capture on CT16B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT16B0_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT16B0_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT16B0_CAP0 rising edge" "Disabled,Enable"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
rgroup.long 0x2C++0xF
|
|
line.long 0x00 "TMR16B0CR0,CT16B0 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14")
|
|
line.long 0x04 "TMR16B0CR1,CT16B0 Capture Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CAP ,Timer counter capture value"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
line.long 0x08 "TMR16B0CR2,CT16B0 Capture Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x0C "TMR16B0CR3,CT16B0 Capture Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CAP ,Timer counter capture value"
|
|
endif
|
|
endif
|
|
elif cpuis("LPC11E*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TMR16B0CR0,CT16B0 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TMR16B0CR1,CT16B0 Capture Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
else
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR16B0CR0,CT16B0 Capture Register 0"
|
|
endif
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TMR16B0EMR,CT16B0 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
if ((per.long(ad:0x40010000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Reserved,Reserved,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16B0_CAP0,CT16B0_CAP1,Comp 0 level output,Comp 0 edge output"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC1112LV"||cpuis("LPC1112*")||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16Bn_CAP0,CT16Bn_CAP1,?..."
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16B0_CAP0,Reserved,CT16B0_CAP1,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,?..."
|
|
endif
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Reserved,Reserved,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "TMR16B0PWMC,CT16B0 PWM Control register"
|
|
bitfld.long 0x00 3. " PWM_EN[3] ,PWM for match channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWM_EN[2] ,PWM for match channel 2 or CT16B0_MAT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWM_EN[1] ,PWM for CT16B0_MAT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN[0] ,PWM for CT16B0_MAT0 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "CT16B1"
|
|
base ad:0x40014000
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "TMR16B1IR,CT16B1 Interrupt Register"
|
|
sif (cpu()!="LPC1102LV"&&cpu()!="LPC1102"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif cpuis("LPC11E*")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TMR16B1TCR,CT16B1 Timer Control Register"
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 1. " CRST ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CEN ,Counter Enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR16B1TC,CT16B1 Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
|
|
line.long 0x04 "TMR16B1PR,CT16B1 Prescale Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PR ,Prescale max value"
|
|
line.long 0x08 "TMR16B1PC,CT16B1 Prescale Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value"
|
|
else
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR16B1TC,CT16B1 Timer Counter Register"
|
|
line.long 0x04 "TMR16B1PR,CT16B1 Prescale Register"
|
|
line.long 0x08 "TMR16B1PC,CT16B1 Prescale Counter Register"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TMR16B1MCR,CT16B1 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR16B1MR0,CT16B1 Match Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x04 "TMR16B1MR1,CT16B1 Match Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x08 "TMR16B1MR2,CT16B1 Match Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x0C "TMR16B1MR3,CT16B1 Match Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value"
|
|
else
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR16B1MR0,CT16B1 Match Register 0"
|
|
line.long 0x04 "TMR16B1MR1,CT16B1 Match Register 1"
|
|
line.long 0x08 "TMR16B1MR2,CT16B1 Match Register 2"
|
|
line.long 0x0C "TMR16B1MR3,CT16B1 Match Register 3"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR16B1CCR,CT16B1 Capture Control Register"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on comparator 1 edge output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on comparator 1 edge output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on comparator 1 edge output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on comparator 1 level output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on comparator 1 level output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on comparator 1 level output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT16B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT16B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT16B1_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("LPC11E*")
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT16B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT16B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT16B1_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT16B1_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT16B1_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT16B1_CAP0 rising edge" "Disabled,Enable"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
rgroup.long 0x2C++0xF
|
|
line.long 0x00 "TMR16B1CR0,CT16B1 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14")
|
|
line.long 0x04 "TMR16B1CR1,CT16B1 Capture Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CAP ,Timer counter capture value"
|
|
sif (cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
line.long 0x08 "TMR16B1CR2,CT16B1 Capture Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x0C "TMR16B1CR3,CT16B1 Capture Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CAP ,Timer counter capture value"
|
|
endif
|
|
endif
|
|
elif cpuis("LPC11E*")
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "TMR16B1CR0,CT16B1 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x04 "TMR16B1CR1,CT16B1 Capture Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CAP ,Timer counter capture value"
|
|
else
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR16B1CR0,CT16B1 Capture Register 0"
|
|
endif
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TMR16B1EMR,CT16B1 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
if ((per.long(ad:0x40014000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR16B1CTCR,CT16B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR16B1CTCR,CT16B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16B1_CAP0,CT16B1_CAP1,Comp 1 level output,Comp 1 edge output"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC1112LV"||cpuis("LPC1112*")||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16Bn_CAP0,CT16Bn_CAP1,?..."
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16B1_CAP0,CT16B1_CAP1,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP1.0,?..."
|
|
endif
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "TMR16B1PWMC,CT16B1 PWM Control register"
|
|
bitfld.long 0x00 3. " PWM_EN[3] ,PWM for match channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWM_EN[2] ,PWM for match channel 2 or CT16B1_MAT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWM_EN[1] ,PWM for CT16B1_MAT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN[0] ,PWM for CT16B1_MAT0 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "CT32B (32-bit counter/timer)"
|
|
tree "CT32B0"
|
|
base ad:0x40018000
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "TMR32B0IR,CT32B0 Interrupt Register"
|
|
sif (cpu()!="LPC1102LV"&&cpu()!="LPC1102"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif cpuis("LPC11E*")
|
|
eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TMR32B0TCR,CT32B0 Timer Control Register"
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 1. " CRST ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CEN ,Counter Enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR32B0TC,CT32B0 Timer Counter Register"
|
|
line.long 0x04 "TMR32B0PR,CT32B0 Prescale Register"
|
|
line.long 0x08 "TMR32B0PC,CT32B0 Prescale Counter Register"
|
|
else
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR32B0TC,CT32B0 Timer Counter Register"
|
|
line.long 0x04 "TMR32B0PR,CT32B0 Prescale Register"
|
|
line.long 0x08 "TMR32B0PC,CT32B0 Prescale Counter Register"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TMR32B0MCR,CT32B0 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR32B0MR0,CT32B0 Match Register 0"
|
|
line.long 0x04 "TMR32B0MR1,CT32B0 Match Register 1"
|
|
line.long 0x08 "TMR32B0MR2,CT32B0 Match Register 2"
|
|
line.long 0x0C "TMR32B0MR3,CT32B0 Match Register 3"
|
|
else
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR32B0MR0,CT32B0 Match Register 0"
|
|
line.long 0x04 "TMR32B0MR1,CT32B0 Match Register 1"
|
|
line.long 0x08 "TMR32B0MR2,CT32B0 Match Register 2"
|
|
line.long 0x0C "TMR32B0MR3,CT32B0 Match Register 3"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR32B0CCR,CT32B0 Capture Control Register"
|
|
sif (cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on comparator 0 edge output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on comparator 0 edge output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on comparator 0 edge output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on comparator 0 level output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on comparator 0 level output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on comparator 0 level output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("LPC11E*")
|
|
bitfld.long 0x00 8. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP1RE ,Capture on CT32B0_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B0_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B0_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B0_CAP0 rising edge" "Disabled,Enable"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B0CR0,CT32B0 Capture Register 0"
|
|
elif cpuis("LPC11E*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TMR32B0CR0,CT32B0 Capture Register 0"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TMR32B0CR1,CT32B0 Capture Register 1"
|
|
else
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B0CR0,CT32B0 Capture Register 0"
|
|
endif
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TMR32B0EMR,CT32B0 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
if ((per.long(ad:0x40018000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Reserved,Reserved,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT32B0_CAP0,CT32B0_CAP1,Comp 0 level output,Comp 0 edge output"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC1112LV"||cpuis("LPC1112*")||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16Bn_CAP0,CT16Bn_CAP1,?..."
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT32B0_CAP0,Reserved,CT32B0_CAP1,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,?..."
|
|
endif
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Reserved,Reserved,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
if ((per.long(ad:0x40018000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,?..."
|
|
endif
|
|
endif
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "TMR32B0PWMC,CT32B0 PWM Control register"
|
|
bitfld.long 0x00 3. " PWM_EN[3] ,PWM for match channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWM_EN[2] ,PWM for match channel 2 or CT32B0_MAT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWM_EN[1] ,PWM for CT32B0_MAT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN[0] ,PWM for CT32B0_MAT0 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "CT32B1"
|
|
base ad:0x4001C000
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "TMR32B1IR,CT32B1 Interrupt Register"
|
|
sif (cpu()!="LPC1102LV"&&cpu()!="LPC1102"&&cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227"&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&cpu()!="LPC11E14")
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif cpuis("LPC11E*")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TMR32B1TCR,CT32B1 Timer Control Register"
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 1. " CRST ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CEN ,Counter Enable" "Disabled,Enabled"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR32B1TC,CT32B1 Timer Counter Register"
|
|
line.long 0x04 "TMR32B1PR,CT32B1 Prescale Register"
|
|
line.long 0x08 "TMR32B1PC,CT32B1 Prescale Counter Register"
|
|
else
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "TMR32B1TC,CT32B1 Timer Counter Register"
|
|
line.long 0x04 "TMR32B1PR,CT32B1 Prescale Register"
|
|
line.long 0x08 "TMR32B1PC,CT32B1 Prescale Counter Register"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TMR32B1MCR,CT32B1 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*"))
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR32B1MR0,CT32B1 Match Register 0"
|
|
line.long 0x04 "TMR32B1MR1,CT32B1 Match Register 1"
|
|
line.long 0x08 "TMR32B1MR2,CT32B1 Match Register 2"
|
|
line.long 0x0C "TMR32B1MR3,CT32B1 Match Register 3"
|
|
else
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "TMR32B1MR0,CT32B1 Match Register 0"
|
|
line.long 0x04 "TMR32B1MR1,CT32B1 Match Register 1"
|
|
line.long 0x08 "TMR32B1MR2,CT32B1 Match Register 2"
|
|
line.long 0x0C "TMR32B1MR3,CT32B1 Match Register 3"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR32B1CCR,CT32B1 Capture Control Register"
|
|
sif (cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B1_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 11. " CAP3I ,Interrupt on comparator 1 edge output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Capture on comparator 1 edge output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Capture on comparator 1 edge output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CAP2I ,Interrupt on comparator 1 level output event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CAP2FE ,Capture on comparator 1 level output - falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Capture on comparator 1 level output - rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B1_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("LPC11E*")
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B1_CAP1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B1_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B1_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B1_CAP0 rising edge" "Disabled,Enable"
|
|
endif
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TMR32B1CCR,CT32B1 Capture Control Register"
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B1_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B1_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B1_CAP0 rising edge" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
endif
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
elif cpuis("LPC11E*")
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x04 "TMR32B1CR1,CT32B1 Capture Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CAP ,Timer counter capture value"
|
|
else
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
endif
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TMR32B1EMR,CT32B1 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
if ((per.long(ad:0x4001C000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT32B1_CAP0,CT32B1_CAP1,Comp 1 level output,Comp 1 edge output"
|
|
elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC1112LV"||cpuis("LPC1112*")||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT16Bn_CAP0,CT16Bn_CAP1,?..."
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CT32B1_CAP0,CT32B1_CAP1,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP1.0,?..."
|
|
endif
|
|
sif (cpu()!="LPC1110"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14")
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC11E11"||cpu()=="LPC11E12"||cpu()=="LPC11E13"||cpu()=="LPC11E14"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,Rising Edge of CAP2,Falling Edge of CAP2,Rising Edge of CAP3,Falling Edge of CAP3"
|
|
elif cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising Edge of CAP0,Falling Edge of CAP0,Rising Edge of CAP1,Falling Edge of CAP1,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
if ((per.long(ad:0x4001C000+0x70)&0x3)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter Input Select" "CAP1.0,?..."
|
|
endif
|
|
endif
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "TMR32B1PWMC,CT32B1 PWM Control register"
|
|
bitfld.long 0x00 3. " PWM_EN[3] ,PWM for match channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWM_EN[2] ,PWM for match channel 2 or CT32B1_MAT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWM_EN[1] ,PWM for CT32B1_MAT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWM_EN[0] ,PWM for CT32B1_MAT0 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "System Tick Timer"
|
|
base ad:0xe000e010
|
|
width 10.
|
|
sif (cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "STCTRL,System Timer Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,System Tick counter flag" "Low,High"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,System Tick clock source selection" "CPU clock,STCLK"
|
|
bitfld.long 0x00 1. " TICKINT ,System Tick interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,System Tick counter enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "STCTRL,System Timer Control and Status Register"
|
|
in
|
|
endif
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "STRELOAD,System Timer Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,System Tick counter reload value"
|
|
line.long 0x04 "STCURR,System Timer Current Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,System Tick counter value"
|
|
line.long 0x08 "STCALIB,System Timer Calibration Value Register"
|
|
bitfld.long 0x08 31. " NOREF ,External reference clock available" "Available,Not available"
|
|
bitfld.long 0x08 30. " SKEW ,TENMS value precise 10 millisecond time generation" "Precise,Not precise"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " TENMS ,Reload value to get a 10 millisecond System Tick underflow rate at 100 MHz"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40050000
|
|
width 6.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "DR,RTC data register"
|
|
group.long 0x04++0xF
|
|
line.long 0x00 "MR,RTC match register"
|
|
line.long 0x04 "LR,RTC load register"
|
|
line.long 0x08 "CR,RTC control register"
|
|
bitfld.long 0x08 0. " RTCSTART ,RTC enable" "Disabled,Enabled"
|
|
line.long 0x0C "ICSC,RTC interrupt mask register"
|
|
bitfld.long 0x0C 0. " RTCIC ,Interrupt control register" "Masked,Not masked"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x00 "RIS,RTC interrupt status register"
|
|
bitfld.long 0x00 0. " RTCRIS ,Raw interrupt event flag state" "No interrupt,Interrupt"
|
|
line.long 0x04 "MIS,RTC masked interrupt status register"
|
|
bitfld.long 0x04 0. " RTCMIS ,Masked interrupt register status" "No interrupt,Interrupt"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x00 "ICR,RTC interrupt clear register"
|
|
bitfld.long 0x00 0. " RTCICR ,Raw interrupt event flag clear register" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40004000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "WDMOD,Watchdog Mode Register"
|
|
sif cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC11E*")||cpuis("LPC11U6*"))
|
|
bitfld.long 0x00 5. " CSLOCK ,Clock source lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))
|
|
bitfld.long 0x00 5. " LOCK ,Watchdog oscillator lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 7. " WDLOCKEN ,Watchdog enable and reset lockout" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " WDLOCKDP ,Deep Power-down enable lock" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSLOCK ,Clock source lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected"
|
|
textline " "
|
|
endif
|
|
sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04")
|
|
eventfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "Not occurred,Occurred"
|
|
else
|
|
bitfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "Not occurred,Occurred"
|
|
endif
|
|
bitfld.long 0x00 2. " WDTOF ,Watchdog Time-out flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable" "Disabled,Enabled"
|
|
sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04")
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="EM773"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpu()=="LPC11U24"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC43S*")||cpuis("LPC11U6")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")||cpu()==("LPC8N04")||cpuis("LPC11D14"))
|
|
line.long 0x04 "WDTC,Watchdog Timer Constant Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out value"
|
|
else
|
|
line.long 0x04 "WDTC,Watchdog Timer Constant Register"
|
|
hexmask.long 0x04 0.--31. 1. " COUNT ,Watchdog time-out interval"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "WDFEED,Watchdog Feed Sequence Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value"
|
|
sif (cpu()=="EM773"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*"))||cpuis("LPC43S*")||cpuis("LPC11U6")||cpuis("LPC84*")||(cpu()=="LPC811M001JDH16")||(cpu()=="LPC832M101FDH20")||(cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))||cpu()=="LPC8N04"||cpuis("LPC11D14")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "WDTV,Watchdog Timer Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "WDTV,Watchdog Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " COUNT ,Counter timer value"
|
|
endif
|
|
sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&!cpuis("LPC1111*")&&cpu()!="LPC11D14"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850"&&cpu()!="LPC1853"&&cpu()!="LPC1857"&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC43*")&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&!cpuis("LPC43S*")&&!cpuis("LPC84*")&&cpu()!="LPC811M001JDH16"&&cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&cpu()!="LPC8N04"&&!cpuis("LPC802*")&&!cpuis("LPC804*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WDCLKSEL,Watchdog Timer Clock Source Selection Register"
|
|
bitfld.long 0x00 31. " WDLOCK ,Watchdog lock" "Not locked,Locked"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 0.--1. " WDSEL1 ,Select the clock source for the watchdog timer" "Internal RC,Watchdog,?..."
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11U6*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKSEL ,Selects source of WDT clock" "IRC,Watchdog oscillator"
|
|
else
|
|
bitfld.long 0x00 0.--1. " WDSEL2 ,Select the clock source for the watchdog timer" "RC,APB clock,RTC,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U6*")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "WDWARNINT,Watchdog Timer Warning Interrupt Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " WARNINT ,Watchdog warning interrupt compare value"
|
|
line.long 0x04 "WDWINDOW,Watchdog Timer Window Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " WINDOW ,Watchdog window value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Comparator"
|
|
base ad:0x40054000
|
|
width 6.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "CMP,Comparator control register"
|
|
bitfld.long 0x00 22. " CMP1STAT ,Comparator 1 status" "Low,High"
|
|
bitfld.long 0x00 21. " CMP0STAT ,Comparator 0 status" "Low,High"
|
|
bitfld.long 0x00 20. " INTCLR ,Interrupt clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " CMP1_VM_CTRL ,Comparator 1 negative voltage (VM) input channel" "Ladder output,ACMP0_I0,ACMP0_I1,ACMP0_I2,ACMP0_I3,ACMP1_I0,ACMP1_I1,BOD 0.9V band gap"
|
|
bitfld.long 0x00 14.--16. " CMP1_VP_CTRL ,Comparator 1 positive voltage (VP) input channel" "Ladder output,ACMP0_I0,ACMP0_I1,ACMP0_I2,ACMP0_I3,ACMP1_I0,ACMP1_I1,BOD 0.9V band gap"
|
|
bitfld.long 0x00 11.--13. " CMP0_VM_CTRL ,Comparator 0 negative voltage (VM) input channel" "Ladder output,ACMP0_I0,ACMP0_I1,ACMP0_I2,ACMP0_I3,ACMP1_I0,ACMP1_I1,BOD 0.9V band gap"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CMP0_VP_CTRL ,Comparator 0 positive voltage (VP) input channel" "Ladder output,ACMP0_I0,ACMP0_I1,ACMP0_I2,ACMP0_I3,ACMP1_I0,ACMP1_I1,BOD 0.9V band gap"
|
|
bitfld.long 0x00 7. " CMPSA1 ,Comparator 1 output sync enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMPSA0 ,Comparator 0 output sync enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CMPSR ,Orientation of the two comparators select" "Low,High"
|
|
bitfld.long 0x00 4. " CMPBE ,Edge triggered interrupt on both edges enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CMPIEV ,Edge triggered interrupt edge select" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMPIS ,Interrupt source select" "Edge,Level"
|
|
bitfld.long 0x00 1. " CMP1_EN ,Comparator 1 enable." "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CMP0_EN ,Comparator 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "VLAD,Voltage ladder register"
|
|
bitfld.long 0x04 6. " VLADREF ,Voltage reference pin select" "VREF_CMP,VDD(3V3)"
|
|
bitfld.long 0x04 1.--5. " VSEL ,Voltage ladder value" "Vss,1*Vref/31,2*Vref/31,3*Vref/31,4*Vref/31,5*Vref/31,6*Vref/31,7*Vref/31,8*Vref/31,9*Vref/31,10*Vref/31,11*Vref/31,12*Vref/31,13*Vref/31,14*Vref/31,15*Vref/31,16*Vref/31,17*Vref/31,18*Vref/31,19*Vref/31,20*Vref/31,21*Vref/31,22*Vref/31,23*Vref/31,24*Vref/31,25*Vref/31,26*Vref/31,27*Vref/31,28*Vref/31,29*Vref/31,30*Vref/31,Vref"
|
|
bitfld.long 0x04 0. " VLADEN ,Voltage ladder enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40020000
|
|
width 9.
|
|
if ((per.long(ad:0x40020000)&0x08000000)==0x08000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AD0CR,A/D Control Register"
|
|
bitfld.long 0x00 27. " EDGE ,Start Conversion Edge" "Rising,Falling"
|
|
textline " "
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpu()=="LPC11D14"||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PPIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PPIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
elif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,,,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on P2.10,Falling edge on P1.27,Falling edge on MAT0.1,Falling edge on MAT0.3,Falling edge on MAT1.0,Falling edge on MAT1.1"
|
|
elif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on CTOUT_15,Falling edge on CTOUT_8,Falling edge on ADCTRIG0,Falling edge on ADCTRIG1,Falling edge on MCOA2,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Falling edge on PIO0_2/SSEL/CT16B0_CAP0,Falling edge on PIO1_5/DIR/CT32B0_CAP0,Falling edge on CT32B0_MAT0,Falling edge on CT32B0_MAT1,Falling edge on CT16B0_MAT0,Falling edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
endif
|
|
sif (!cpuis("LPC11E*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDN ,A/D Power" "Power-down,Operational"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BURST ,Conversion Control Mode" "Software,Repeated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock Divider"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " AD.7 ,AD.7 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " AD.6 ,AD.6 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AD.5 ,AD.5 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " AD.3 ,AD.3 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " AD.2 ,AD.2 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AD.1 ,AD.1 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " AD.0 ,AD.0 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AD0CR,A/D Control Register"
|
|
bitfld.long 0x00 27. " EDGE ,Start Conversion Edge" "Rising,Falling"
|
|
textline " "
|
|
sif (cpu()=="LPC1311"||cpu()=="LPC1313"||cpu()=="LPC1342"||cpu()=="LPC1343"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U02"||cpu()=="LPC11U04"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*"))
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PPIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PPIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
elif (cpu()=="LPC1102"||cpu()=="LPC1102LV")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,,,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
bitfld.long 0x00 23.--26. " START ,Start Conversion Control" "No start,,Start,,ATRG0,Analog comparator output,ATRG1,,CT32B0_MAT0,,CT32B0_MAT1,,CT16B0_MAT0,,CT16B0_MAT1,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on P2.10,Rising edge on P1.27,Rising edge on MAT0.1,Rising edge on MAT0.3,Rising edge on MAT1.0,Rising edge on MAT1.1"
|
|
elif cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on CTOUT_15,Rising edge on CTOUT_8,Rising edge on ADCTRIG0,Rising edge on ADCTRIG1,Rising edge on MCOA2,?..."
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
else
|
|
bitfld.long 0x00 24.--26. " START ,Start Conversion Control" "No start,Start now,Rising edge on PIO0_2/SSEL/CT16B0_CAP0,Rising edge on PIO1_5/DIR/CT32B0_CAP0,Rising edge on CT32B0_MAT0,Rising edge on CT32B0_MAT1,Rising edge on CT16B0_MAT0,Rising edge on CT16B0_MAT1"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in Burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
endif
|
|
sif !cpuis("LPC11E*")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDN ,A/D Power" "Power-down,Operational"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BURST ,Conversion Control Mode" "Software,Repeated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock Divider"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " AD.7 ,AD.7 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " AD.6 ,AD.6 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AD.5 ,AD.5 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
else
|
|
bitfld.long 0x00 4. " AD.4 ,AD.4 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " AD.3 ,AD.3 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " AD.2 ,AD.2 Sampling and Conversion" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AD.1 ,AD.1 Sampling and Conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " AD.0 ,AD.0 Sampling and Conversion" "Not selected,Selected"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "AD0GDR,A/D Global Data Register"
|
|
in
|
|
sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14")
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SEL,A/D Select Register"
|
|
bitfld.long 0x00 14.--15. " AD7SEL ,This field selects the source signal for channel 7" "AD7,No signal,Temperature sensor,?..."
|
|
bitfld.long 0x00 12.--13. " AD6SEL ,This field selects the source signal for channel 6" "AD6,no signal,Internal voltage reference,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " AD5SEL ,This field selects the source signal for channel 5" "AD5,No signal,Core voltage regulator output,?..."
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "AD0INTEN,A/D Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " ADGINTEN ,Source of Generate Interrupt" "Individual,Global"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " ADINTEN7 ,Interrupt when Conversion on Channel 7 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ADINTEN6 ,Interrupt when Conversion on Channel 6 Completed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADINTEN5 ,Interrupt when Conversion on Channel 5 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ADINTEN4 ,Interrupt when Conversion on Channel 4 Completed" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADINTEN4 ,Interrupt when Conversion on Channel 4 Completed" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADINTEN3 ,Interrupt when Conversion on Channel 3 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ADINTEN2 ,Interrupt when Conversion on Channel 2 Completed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADINTEN1 ,Interrupt when Conversion on Channel 1 Completed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ADINTEN0 ,Interrupt when Conversion on Channel 0 Completed" "No interrupt,Interrupt"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "AD0DR0,A/D Data Register"
|
|
in
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "AD0DR1,A/D Data Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "AD0DR2,A/D Data Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "AD0DR3,A/D Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "AD0DR4,A/D Data Register"
|
|
in
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV")
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "AD0DR5,A/D Data Register"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "AD0DR6,A/D Data Register"
|
|
in
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "AD0DR7,A/D Data Register"
|
|
in
|
|
endif
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "AD0STAT,A/D Status Register"
|
|
bitfld.long 0x00 16. " ADINT ,A/D Interrupt Flag" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 15. " OVERRUN7 ,Mirrors OVERRUN Status Flag for Channel 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " OVERRUN6 ,Mirrors OVERRUN Status Flag for Channel 6" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OVERRUN5 ,Mirrors OVERRUN Status Flag for Channel 5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " OVERRUN4 ,Mirrors OVERRUN Status Flag for Channel 4" "Not occurred,Occurred"
|
|
else
|
|
bitfld.long 0x00 12. " OVERRUN4 ,Mirrors OVERRUN Status Flag for Channel 4" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " OVERRUN3 ,Mirrors OVERRUN Status Flag for Channel 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " OVERRUN2 ,Mirrors OVERRUN Status Flag for Channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OVERRUN1 ,Mirrors OVERRUN Status Flag for Channel 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " OVERRUN0 ,Mirrors OVERRUN Status Flag for Channel 0" "Not occurred,Occurred"
|
|
textline " "
|
|
sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1110")
|
|
bitfld.long 0x00 7. " DONE7 ,Mirrors DONE Status Flag for Channel 7" "Not done,Done"
|
|
bitfld.long 0x00 6. " DONE6 ,Mirrors DONE Status Flag for Channel 6" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DONE5 ,Mirrors DONE Status Flag for Channel 5" "Not done,Done"
|
|
bitfld.long 0x00 4. " DONE4 ,Mirrors DONE Status Flag for Channel 4" "Not done,Done"
|
|
else
|
|
bitfld.long 0x00 4. " DONE4 ,Mirrors DONE Status Flag for Channel 4" "Not done,Done"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " DONE3 ,Mirrors DONE Status Flag for Channel 3" "Not done,Done"
|
|
bitfld.long 0x00 2. " DONE2 ,Mirrors DONE Status Flag for Channel 2" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DONE1 ,Mirrors DONE Status Flag for Channel 1" "Not done,Done"
|
|
bitfld.long 0x00 0. " DONE0 ,Mirrors DONE Status Flag for Channel 0" "Not done,Done"
|
|
sif (!cpuis("LPC11E*")&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14"&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC11U12/201"&&cpu()!="LPC11U13/201"&&cpu()!="LPC11U14/201"&&cpu()!="LPC11U23/301"&&!cpuis("LPC11U24*")&&!cpuis("LPC11U3*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC181*")&&!cpuis("LPC182*")&&!cpuis("LPC183*")&&!cpuis("LPC185*"))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ADTRIM,A/D Trim register"
|
|
sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227")
|
|
bitfld.long 0x00 4.--7. " ADCOFFS ,Offset trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 8.--11. " TRIM ,Trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " ADCOFFS ,Offset trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA (General purpose micro DMA)"
|
|
base ad:0x4004C000
|
|
width 0x16
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "DMA_STATUS,DMA status register"
|
|
bitfld.long 0x00 16.--20. " CHNLS ,Number of micro DMA controller channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " STATE ,Current state of the control state machine" "Idle,Reading channel controller data,Reading source data end pointer,Reading destination data end pointer,Reading source data,Writing destination data,Waiting for DMA request to clear,Writing channel controller data,Stalled,Done,Peripheral scatter-gather transition,?..."
|
|
bitfld.long 0x00 0. " MASTER_EN ,Controller enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "DMA_CFG,DMA configuration register"
|
|
bitfld.long 0x00 6. " CHNL_PROT_CTRL2 ,Channel protection buffer control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CHNL_PROT_CTRL1 ,Channel protection access control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MASTER_EN ,Controller enable" "Disabled,Enabled"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "CTRL_BASE_PTR,Channel control base pointer register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " CTRL_BASE_PTR ,Pointer to the base address of the primary data structure"
|
|
rgroup.long 0x0C++0x7
|
|
line.long 0x00 "ATL_CTRL_BASE_PTR,Channel alternate control base pointer register"
|
|
line.long 0x04 "DMA_WAITONREQ_STATUS,Channel wait on request status register"
|
|
bitfld.long 0x04 20. " DMA_WAITONREQ_STATUS[20] ,Channel 20 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 19. " DMA_WAITONREQ_STATUS[19] ,Channel 19 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 18. " DMA_WAITONREQ_STATUS[18] ,Channel 18 wait-on-request status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DMA_WAITONREQ_STATUS[17] ,Channel 17 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 16. " DMA_WAITONREQ_STATUS[16] ,Channel 16 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 15. " DMA_WAITONREQ_STATUS[15] ,Channel 15 wait-on-request status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 14. " DMA_WAITONREQ_STATUS[14] ,Channel 14 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 13. " DMA_WAITONREQ_STATUS[13] ,Channel 13 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 12. " DMA_WAITONREQ_STATUS[12] ,Channel 12 wait-on-request status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DMA_WAITONREQ_STATUS[11] ,Channel 11 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 10. " DMA_WAITONREQ_STATUS[10] ,Channel 10 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 9. " DMA_WAITONREQ_STATUS[9] ,Channel 9 wait-on-request status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DMA_WAITONREQ_STATUS[8] ,Channel 8 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 7. " DMA_WAITONREQ_STATUS[7] ,Channel 7 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 6. " DMA_WAITONREQ_STATUS[6] ,Channel 6 wait-on-request status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DMA_WAITONREQ_STATUS[5] ,Channel 5 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 4. " DMA_WAITONREQ_STATUS[4] ,Channel 4 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 3. " DMA_WAITONREQ_STATUS[3] ,Channel 3 wait-on-request status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DMA_WAITONREQ_STATUS[2] ,Channel 2 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 1. " DMA_WAITONREQ_STATUS[1] ,Channel 1 wait-on-request status" "Low,High"
|
|
bitfld.long 0x04 0. " DMA_WAITONREQ_STATUS[0] ,Channel 0 wait-on-request status" "Low,High"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x00 "CHNL_SW_REQUEST,Channel software request register"
|
|
bitfld.long 0x00 20. " DMA_SW_REQUEST[20] ,DMA request for channel 20" "No request,Request"
|
|
bitfld.long 0x00 19. " DMA_SW_REQUEST[19] ,DMA request for channel 19" "No request,Request"
|
|
bitfld.long 0x00 18. " DMA_SW_REQUEST[18] ,DMA request for channel 18" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DMA_SW_REQUEST[17] ,DMA request for channel 17" "No request,Request"
|
|
bitfld.long 0x00 16. " DMA_SW_REQUEST[16] ,DMA request for channel 16" "No request,Request"
|
|
bitfld.long 0x00 15. " DMA_SW_REQUEST[15] ,DMA request for channel 15" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMA_SW_REQUEST[14] ,DMA request for channel 14" "No request,Request"
|
|
bitfld.long 0x00 13. " DMA_SW_REQUEST[13] ,DMA request for channel 13" "No request,Request"
|
|
bitfld.long 0x00 12. " DMA_SW_REQUEST[12] ,DMA request for channel 12" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DMA_SW_REQUEST[11] ,DMA request for channel 11" "No request,Request"
|
|
bitfld.long 0x00 10. " DMA_SW_REQUEST[10] ,DMA request for channel 10" "No request,Request"
|
|
bitfld.long 0x00 9. " DMA_SW_REQUEST[9] ,DMA request for channel 9" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA_SW_REQUEST[8] ,DMA request for channel 8" "No request,Request"
|
|
bitfld.long 0x00 7. " DMA_SW_REQUEST[7] ,DMA request for channel 7" "No request,Request"
|
|
bitfld.long 0x00 6. " DMA_SW_REQUEST[6] ,DMA request for channel 6" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DMA_SW_REQUEST[5] ,DMA request for channel 5" "No request,Request"
|
|
bitfld.long 0x00 4. " DMA_SW_REQUEST[4] ,DMA request for channel 4" "No request,Request"
|
|
bitfld.long 0x00 3. " DMA_SW_REQUEST[3] ,DMA request for channel 3" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMA_SW_REQUEST[2] ,DMA request for channel 2" "No request,Request"
|
|
bitfld.long 0x00 1. " DMA_SW_REQUEST[1] ,DMA request for channel 1" "No request,Request"
|
|
bitfld.long 0x00 0. " DMA_SW_REQUEST[0] ,DMA request for channel 0" "No request,Request"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CHNL_USEBURST_SET,Channel useburst set register"
|
|
bitfld.long 0x00 5. " DMA_USEBURST_SET[5] ,Useburst for channel 5 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DMA_USEBURST_SET[4] ,Useburst for channel 4 status" "Disabled,Enabled"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x00 "CHNL_USEBURST_CLR,Channel useburst clear register"
|
|
bitfld.long 0x00 5. " DMA_USEBURST_SET[5] ,Enable dma_sreq[5] to generate requests" "No effect,Enable"
|
|
bitfld.long 0x00 4. " DMA_USEBURST_SET[4] ,Enable dma_sreq[4] to generate requests" "No effect,Enable"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "CHNL_REQ_MASK_SET,Channel request mask set register"
|
|
bitfld.long 0x00 20. " CHNL_REQ_MASK_SET[20] ,Request mask status of dma_req[20] and dma_sreq[20]" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " CHNL_REQ_MASK_SET[19] ,Request mask status of dma_req[19] and dma_sreq[19]" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " CHNL_REQ_MASK_SET[18] ,Request mask status of dma_req[18] and dma_sreq[18]" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_REQ_MASK_SET[17] ,Request mask status of dma_req[17] and dma_sreq[17]" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " CHNL_REQ_MASK_SET[16] ,Request mask status of dma_req[16] and dma_sreq[16]" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " CHNL_REQ_MASK_SET[15] ,Request mask status of dma_req[15] and dma_sreq[15]" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_REQ_MASK_SET[14] ,Request mask status of dma_req[14] and dma_sreq[14]" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " CHNL_REQ_MASK_SET[13] ,Request mask status of dma_req[13] and dma_sreq[13]" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " CHNL_REQ_MASK_SET[12] ,Request mask status of dma_req[12] and dma_sreq[12]" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_REQ_MASK_SET[11] ,Request mask status of dma_req[11] and dma_sreq[11]" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " CHNL_REQ_MASK_SET[10] ,Request mask status of dma_req[10] and dma_sreq[10]" "Enabled,Disabled"
|
|
bitfld.long 0x00 9. " CHNL_REQ_MASK_SET[9] ,Request mask status of dma_req[9] and dma_sreq[9]" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_REQ_MASK_SET[8] ,Request mask status of dma_req[8] and dma_sreq[8]" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " CHNL_REQ_MASK_SET[7] ,Request mask status of dma_req[7] and dma_sreq[7]" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " CHNL_REQ_MASK_SET[6] ,Request mask status of dma_req[6] and dma_sreq[6]" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_REQ_MASK_SET[5] ,Request mask status of dma_req[5] and dma_sreq[5]" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " CHNL_REQ_MASK_SET[4] ,Request mask status of dma_req[4] and dma_sreq[4]" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " CHNL_REQ_MASK_SET[3] ,Request mask status of dma_req[3] and dma_sreq[3]" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_REQ_MASK_SET[2] ,Request mask status of dma_req[2] and dma_sreq[2]" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " CHNL_REQ_MASK_SET[1] ,Request mask status of dma_req[1] and dma_sreq[1]" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CHNL_REQ_MASK_SET[0] ,Request mask status of dma_req[0] and dma_sreq[0]" "Enabled,Disabled"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "CHNL_REQ_MASK_CLR,Channel request mask clear register"
|
|
bitfld.long 0x00 20. " CHNL_REQ_MASK_CLR[20] ,Enable dma_req[20] or dma_sreq[20] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 19. " CHNL_REQ_MASK_CLR[19] ,Enable dma_req[19] or dma_sreq[19] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 18. " CHNL_REQ_MASK_CLR[18] ,Enable dma_req[18] or dma_sreq[18] to generate DMA request" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_REQ_MASK_CLR[17] ,Enable dma_req[17] or dma_sreq[17] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 16. " CHNL_REQ_MASK_CLR[16] ,Enable dma_req[16] or dma_sreq[16] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 15. " CHNL_REQ_MASK_CLR[15] ,Enable dma_req[15] or dma_sreq[15] to generate DMA request" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_REQ_MASK_CLR[14] ,Enable dma_req[14] or dma_sreq[14] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 13. " CHNL_REQ_MASK_CLR[13] ,Enable dma_req[13] or dma_sreq[13] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 12. " CHNL_REQ_MASK_CLR[12] ,Enable dma_req[12] or dma_sreq[12] to generate DMA request" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_REQ_MASK_CLR[11] ,Enable dma_req[11] or dma_sreq[11] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 10. " CHNL_REQ_MASK_CLR[10] ,Enable dma_req[10] or dma_sreq[10] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 9. " CHNL_REQ_MASK_CLR[9] ,Enable dma_req[9] or dma_sreq[9] to generate DMA request" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_REQ_MASK_CLR[8] ,Enable dma_req[8] or dma_sreq[8] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 7. " CHNL_REQ_MASK_CLR[7] ,Enable dma_req[7] or dma_sreq[7] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 6. " CHNL_REQ_MASK_CLR[6] ,Enable dma_req[6] or dma_sreq[6] to generate DMA request" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_REQ_MASK_CLR[5] ,Enable dma_req[5] or dma_sreq[5] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 4. " CHNL_REQ_MASK_CLR[4] ,Enable dma_req[4] or dma_sreq[4] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 3. " CHNL_REQ_MASK_CLR[3] ,Enable dma_req[3] or dma_sreq[3] to generate DMA request" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_REQ_MASK_CLR[2] ,Enable dma_req[2] or dma_sreq[2] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 1. " CHNL_REQ_MASK_CLR[1] ,Enable dma_req[1] or dma_sreq[1] to generate DMA request" "No effect,Enable"
|
|
bitfld.long 0x00 1. " CHNL_REQ_MASK_CLR[0] ,Enable dma_req[0] or dma_sreq[0] to generate DMA request" "No effect,Enable"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CHNL_ENABLE_SET,Channel enable set register"
|
|
bitfld.long 0x00 20. " CHNL_ENABLE_SET[20] ,Channel 20 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CHNL_ENABLE_SET[19] ,Channel 19 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CHNL_ENABLE_SET[18] ,Channel 18 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_ENABLE_SET[17] ,Channel 17 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CHNL_ENABLE_SET[16] ,Channel 16 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CHNL_ENABLE_SET[15] ,Channel 15 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_ENABLE_SET[14] ,Channel 14 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CHNL_ENABLE_SET[13] ,Channel 13 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CHNL_ENABLE_SET[12] ,Channel 12 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_ENABLE_SET[11] ,Channel 11 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CHNL_ENABLE_SET[10] ,Channel 10 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CHNL_ENABLE_SET[9] ,Channel 9 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_ENABLE_SET[8] ,Channel 8 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CHNL_ENABLE_SET[7] ,Channel 7 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHNL_ENABLE_SET[6] ,Channel 6 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_ENABLE_SET[5] ,Channel 5 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CHNL_ENABLE_SET[4] ,Channel 4 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CHNL_ENABLE_SET[3] ,Channel 3 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_ENABLE_SET[2] ,Channel 2 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CHNL_ENABLE_SET[1] ,Channel 1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CHNL_ENABLE_SET[0] ,Channel 0 enable status" "Disabled,Enabled"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x00 "CHNL_ENABLE_CLR,Channel enable clear register"
|
|
bitfld.long 0x00 20. " CHNL_ENABLE_CLR[20] ,Channel 20 disable" "No effect,Disable"
|
|
bitfld.long 0x00 19. " CHNL_ENABLE_CLR[19] ,Channel 19 disable" "No effect,Disable"
|
|
bitfld.long 0x00 18. " CHNL_ENABLE_CLR[18] ,Channel 18 disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_ENABLE_CLR[17] ,Channel 17 disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " CHNL_ENABLE_CLR[16] ,Channel 16 disable" "No effect,Disable"
|
|
bitfld.long 0x00 15. " CHNL_ENABLE_CLR[15] ,Channel 15 disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_ENABLE_CLR[14] ,Channel 14 disable" "No effect,Disable"
|
|
bitfld.long 0x00 13. " CHNL_ENABLE_CLR[13] ,Channel 13 disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " CHNL_ENABLE_CLR[12] ,Channel 12 disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_ENABLE_CLR[11] ,Channel 11 disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " CHNL_ENABLE_CLR[10] ,Channel 10 disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " CHNL_ENABLE_CLR[9] ,Channel 9 disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_ENABLE_CLR[8] ,Channel 8 disable" "No effect,Disable"
|
|
bitfld.long 0x00 7. " CHNL_ENABLE_CLR[7] ,Channel 7 disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " CHNL_ENABLE_CLR[6] ,Channel 6 disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_ENABLE_CLR[5] ,Channel 5 disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " CHNL_ENABLE_CLR[4] ,Channel 4 disable" "No effect,Disable"
|
|
bitfld.long 0x00 3. " CHNL_ENABLE_CLR[3] ,Channel 3 disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_ENABLE_CLR[2] ,Channel 2 disable" "No effect,Disable"
|
|
bitfld.long 0x00 1. " CHNL_ENABLE_CLR[1] ,Channel 1 disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CHNL_ENABLE_CLR[0] ,Channel 0 disable" "No effect,Disable"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "CHNL_PRI_ALT_SET,Channel primary-alternate set register"
|
|
bitfld.long 0x00 20. " CHNL_PRI_ALT_SET[20] ,Channel 20 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 19. " CHNL_PRI_ALT_SET[19] ,Channel 19 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 18. " CHNL_PRI_ALT_SET[18] ,Channel 18 control data structure status selected" "Primary,Alternate"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_PRI_ALT_SET[17] ,Channel 17 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 16. " CHNL_PRI_ALT_SET[16] ,Channel 16 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 15. " CHNL_PRI_ALT_SET[15] ,Channel 15 control data structure status selected" "Primary,Alternate"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_PRI_ALT_SET[14] ,Channel 14 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 13. " CHNL_PRI_ALT_SET[13] ,Channel 13 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 12. " CHNL_PRI_ALT_SET[12] ,Channel 12 control data structure status selected" "Primary,Alternate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_PRI_ALT_SET[11] ,Channel 11 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 10. " CHNL_PRI_ALT_SET[10] ,Channel 10 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 9. " CHNL_PRI_ALT_SET[9] ,Channel 9 control data structure status selected" "Primary,Alternate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_PRI_ALT_SET[8] ,Channel 8 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 7. " CHNL_PRI_ALT_SET[7] ,Channel 7 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 6. " CHNL_PRI_ALT_SET[6] ,Channel 6 control data structure status selected" "Primary,Alternate"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_PRI_ALT_SET[5] ,Channel 5 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 4. " CHNL_PRI_ALT_SET[4] ,Channel 4 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 3. " CHNL_PRI_ALT_SET[3] ,Channel 3 control data structure status selected" "Primary,Alternate"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_PRI_ALT_SET[2] ,Channel 2 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 1. " CHNL_PRI_ALT_SET[1] ,Channel 1 control data structure status selected" "Primary,Alternate"
|
|
bitfld.long 0x00 0. " CHNL_PRI_ALT_SET[0] ,Channel 0 control data structure status selected" "Primary,Alternate"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "CHNL_PRI_ALT_CLR,Channel primary-alternate clear register"
|
|
bitfld.long 0x00 20. " CHNL_PRI_ALT_CLR[20] ,Channel 20 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 19. " CHNL_PRI_ALT_CLR[19] ,Channel 19 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 18. " CHNL_PRI_ALT_CLR[18] ,Channel 18 primary data structure set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_PRI_ALT_CLR[17] ,Channel 17 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 16. " CHNL_PRI_ALT_CLR[16] ,Channel 16 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 15. " CHNL_PRI_ALT_CLR[15] ,Channel 15 primary data structure set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_PRI_ALT_CLR[14] ,Channel 14 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 13. " CHNL_PRI_ALT_CLR[13] ,Channel 13 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 12. " CHNL_PRI_ALT_CLR[12] ,Channel 12 primary data structure set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_PRI_ALT_CLR[11] ,Channel 11 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 10. " CHNL_PRI_ALT_CLR[10] ,Channel 10 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 9. " CHNL_PRI_ALT_CLR[9] ,Channel 9 primary data structure set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_PRI_ALT_CLR[8] ,Channel 8 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 7. " CHNL_PRI_ALT_CLR[7] ,Channel 7 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 6. " CHNL_PRI_ALT_CLR[6] ,Channel 6 primary data structure set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_PRI_ALT_CLR[5] ,Channel 5 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 4. " CHNL_PRI_ALT_CLR[4] ,Channel 4 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 3. " CHNL_PRI_ALT_CLR[3] ,Channel 3 primary data structure set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_PRI_ALT_CLR[2] ,Channel 2 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 1. " CHNL_PRI_ALT_CLR[1] ,Channel 1 primary data structure set" "No effect,Set"
|
|
bitfld.long 0x00 0. " CHNL_PRI_ALT_CLR[0] ,Channel 0 primary data structure set" "No effect,Set"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "CHNL_PRIORITY_SET,Channel priority set register"
|
|
bitfld.long 0x00 20. " CHNL_PRIORITY_SET[20] ,Channel 20 priority selected" "Default,High"
|
|
bitfld.long 0x00 19. " CHNL_PRIORITY_SET[19] ,Channel 19 priority selected" "Default,High"
|
|
bitfld.long 0x00 18. " CHNL_PRIORITY_SET[18] ,Channel 18 priority selected" "Default,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_PRIORITY_SET[17] ,Channel 17 priority selected" "Default,High"
|
|
bitfld.long 0x00 16. " CHNL_PRIORITY_SET[16] ,Channel 16 priority selected" "Default,High"
|
|
bitfld.long 0x00 15. " CHNL_PRIORITY_SET[15] ,Channel 15 priority selected" "Default,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_PRIORITY_SET[14] ,Channel 14 priority selected" "Default,High"
|
|
bitfld.long 0x00 13. " CHNL_PRIORITY_SET[13] ,Channel 13 priority selected" "Default,High"
|
|
bitfld.long 0x00 12. " CHNL_PRIORITY_SET[12] ,Channel 12 priority selected" "Default,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_PRIORITY_SET[11] ,Channel 11 priority selected" "Default,High"
|
|
bitfld.long 0x00 10. " CHNL_PRIORITY_SET[10] ,Channel 10 priority selected" "Default,High"
|
|
bitfld.long 0x00 9. " CHNL_PRIORITY_SET[9] ,Channel 9 priority selected" "Default,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_PRIORITY_SET[8] ,Channel 8 priority selected" "Default,High"
|
|
bitfld.long 0x00 7. " CHNL_PRIORITY_SET[7] ,Channel 7 priority selected" "Default,High"
|
|
bitfld.long 0x00 6. " CHNL_PRIORITY_SET[6] ,Channel 6 priority selected" "Default,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_PRIORITY_SET[5] ,Channel 5 priority selected" "Default,High"
|
|
bitfld.long 0x00 4. " CHNL_PRIORITY_SET[4] ,Channel 4 priority selected" "Default,High"
|
|
bitfld.long 0x00 3. " CHNL_PRIORITY_SET[3] ,Channel 3 priority selected" "Default,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_PRIORITY_SET[2] ,Channel 2 priority selected" "Default,High"
|
|
bitfld.long 0x00 1. " CHNL_PRIORITY_SET[1] ,Channel 1 priority selected" "Default,High"
|
|
bitfld.long 0x00 0. " CHNL_PRIORITY_SET[0] ,Channel 0 priority selected" "Default,High"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x00 "CHNL_PRIORITY_CLR,Channel priority clear register"
|
|
bitfld.long 0x00 20. " CHNL_PRI_ALT_CLR[20] ,Channel 20 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 19. " CHNL_PRI_ALT_CLR[19] ,Channel 19 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 18. " CHNL_PRI_ALT_CLR[18] ,Channel 18 default priority set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_PRI_ALT_CLR[17] ,Channel 17 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 16. " CHNL_PRI_ALT_CLR[16] ,Channel 16 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 15. " CHNL_PRI_ALT_CLR[15] ,Channel 15 default priority set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_PRI_ALT_CLR[14] ,Channel 14 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 13. " CHNL_PRI_ALT_CLR[13] ,Channel 13 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 12. " CHNL_PRI_ALT_CLR[12] ,Channel 12 default priority set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_PRI_ALT_CLR[11] ,Channel 11 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 10. " CHNL_PRI_ALT_CLR[10] ,Channel 10 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 9. " CHNL_PRI_ALT_CLR[9] ,Channel 9 default priority set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_PRI_ALT_CLR[8] ,Channel 8 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 7. " CHNL_PRI_ALT_CLR[7] ,Channel 7 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 6. " CHNL_PRI_ALT_CLR[6] ,Channel 6 default priority set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_PRI_ALT_CLR[5] ,Channel 5 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 4. " CHNL_PRI_ALT_CLR[4] ,Channel 4 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 3. " CHNL_PRI_ALT_CLR[3] ,Channel 3 default priority set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_PRI_ALT_CLR[2] ,Channel 2 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 1. " CHNL_PRI_ALT_CLR[1] ,Channel 1 default priority set" "No effect,Set"
|
|
bitfld.long 0x00 0. " CHNL_PRI_ALT_CLR[0] ,Channel 0 default priority set" "No effect,Set"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "ERR_CLR,Bus error clear register"
|
|
bitfld.long 0x00 0. " ERR_CLR ,DMA_error status" "Low,High"
|
|
group.long 0x80++0xB
|
|
line.long 0x00 "CHNL_IRQ_STATUS,Channel DMA interrupt status register"
|
|
bitfld.long 0x00 20. " CHNL_IRQ_STAT[20] ,DMA done interrupt channel 20 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19. " CHNL_IRQ_STAT[19] ,DMA done interrupt channel 19 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " CHNL_IRQ_STAT[18] ,DMA done interrupt channel 18 status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_IRQ_STAT[17] ,DMA done interrupt channel 17 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " CHNL_IRQ_STAT[16] ,DMA done interrupt channel 16 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " CHNL_IRQ_STAT[15] ,DMA done interrupt channel 15 status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_IRQ_STAT[14] ,DMA done interrupt channel 14 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CHNL_IRQ_STAT[13] ,DMA done interrupt channel 13 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CHNL_IRQ_STAT[12] ,DMA done interrupt channel 12 status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_IRQ_STAT[11] ,DMA done interrupt channel 11 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CHNL_IRQ_STAT[10] ,DMA done interrupt channel 10 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CHNL_IRQ_STAT[9] ,DMA done interrupt channel 9 status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_IRQ_STAT[8] ,DMA done interrupt channel 8 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CHNL_IRQ_STAT[7] ,DMA done interrupt channel 7 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHNL_IRQ_STAT[6] ,DMA done interrupt channel 6 status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_IRQ_STAT[5] ,DMA done interrupt channel 5 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CHNL_IRQ_STAT[4] ,DMA done interrupt channel 4 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CHNL_IRQ_STAT[3] ,DMA done interrupt channel 3 status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_IRQ_STAT[2] ,DMA done interrupt channel 2 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CHNL_IRQ_STAT[1] ,DMA done interrupt channel 1 status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CHNL_IRQ_STAT[0] ,DMA done interrupt channel 0 status" "Not occurred,Occurred"
|
|
line.long 0x00 "IRQ_ERR_ENABLE,DMA error interrupt enable register"
|
|
bitfld.long 0x00 0. " IRQ_ERR_ENABLE ,DMA error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x00 "CHNL_IRQ_ENABLE,Channel DMA interrupt enable register"
|
|
bitfld.long 0x00 20. " CHNL_IRQ_ENABLE[20] ,DMA done interrupt channel 20 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CHNL_IRQ_ENABLE[19] ,DMA done interrupt channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CHNL_IRQ_ENABLE[18] ,DMA done interrupt channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CHNL_IRQ_ENABLE[17] ,DMA done interrupt channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CHNL_IRQ_ENABLE[16] ,DMA done interrupt channel 16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CHNL_IRQ_ENABLE[15] ,DMA done interrupt channel 15 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHNL_IRQ_ENABLE[14] ,DMA done interrupt channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CHNL_IRQ_ENABLE[13] ,DMA done interrupt channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CHNL_IRQ_ENABLE[12] ,DMA done interrupt channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHNL_IRQ_ENABLE[11] ,DMA done interrupt channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CHNL_IRQ_ENABLE[10] ,DMA done interrupt channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CHNL_IRQ_ENABLE[9] ,DMA done interrupt channel 9 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHNL_IRQ_ENABLE[8] ,DMA done interrupt channel 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CHNL_IRQ_ENABLE[7] ,DMA done interrupt channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHNL_IRQ_ENABLE[6] ,DMA done interrupt channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHNL_IRQ_ENABLE[5] ,DMA done interrupt channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CHNL_IRQ_ENABLE[4] ,DMA done interrupt channel 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CHNL_IRQ_ENABLE[3] ,DMA done interrupt channel 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHNL_IRQ_ENABLE[2] ,DMA done interrupt channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CHNL_IRQ_ENABLE[1] ,DMA done interrupt channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CHNL_IRQ_ENABLE[0] ,DMA done interrupt channel 0 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x50050000
|
|
width 9.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MODE,CRC Mode Register"
|
|
bitfld.long 0x00 5. " CMPL_SUM ,Data 1's complement enable for CRC_SUM" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_RVS_SUM ,Bit order for CRC_SUM" "Not reversed,Reversed"
|
|
bitfld.long 0x00 3. " CMPL_WR ,Data 1's complement enable for CRC_WR_DATA" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BIT_RVS_WR ,Bit order for CRC_WR_DATA" "Not reversed,Reversed"
|
|
bitfld.long 0x00 0.--1. " CRC_POLY ,CRC polynomial select" "CRC-CCITT,CRC-16,CRC-32,CRC-32"
|
|
line.long 0x04 "SEED,CRC Seed Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SUM,CRC Checksum Register"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "WR_DATA,CRC Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
textline ""
|