3424 lines
238 KiB
Plaintext
3424 lines
238 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: KRAIT On-Chip Peripherals
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; @Props: Released
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; @Author: BUJ, LEM
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; @Changelog:
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; 2011-11-28
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; 2013-05-14
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; 2013-07-19
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; @Manufacturer: QUALCOMM - Qualcomm
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; @Doc: 80-N3638-2_F_KraitCPRegistersP2.pdf (2011-11-10)
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; 80-N3638-5.pdf (80-N3638-5 Rev.A - 2013-01-30)
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; @Core: Krait
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; @Chip: KRAIT
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; @Chiplist: KRAIT
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; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perkrait.per 16305 2023-06-28 11:47:37Z pegold $
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config 16. 8.
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ASSERT VERSION.BUILD.BASE()>=80109.
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sif PER.isNOTIFICATION()
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base AVM:0x00000000
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wgroup AVM:0x00++0
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textline " Peripheral File Notification - "
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button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files:""+CONV.CHAR(0xa)+PER.NOTIFICATION.MISSINGFILES()"
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textline " ---------------------------------------------------------------"
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textline " The peripheral file for this SoC cannot be displayed. "
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textline " Possible reasons are: "
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textline " - it is missing in the local installation or under development "
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textline " - it is confidential "
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textline " "
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textline " As fallback only the core registers are shown. "
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textline " Please check www.lauterbach.com/scripts.html "
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textline " or contact support@lauterbach.com . "
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textline " "
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endif
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width 10.
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tree "ID Registers"
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rgroup.long c15:0x0000++0x00
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line.long 0x00 "MIDR,Main ID Register"
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hexmask.long.byte 0x00 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x00 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x00 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x00 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x0100++0x00
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line.long 0x00 "CTR,Cache Type Register"
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bitfld.long 0x00 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x00 24.--27. " MAXWB ,Maximum Write-Back Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x00 20.--23. " RGSIZE ,Reservation Granule Size" "Reserved,Reserved,Reserved,Reserved,Reserved,32 words,?..."
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textline " "
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bitfld.long 0x00 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x00 14.--15. " L1IPOLICY ,L1 Instruction Cache Policy" "Reserved,AVIVT,VIPT,PIPT"
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bitfld.long 0x00 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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rgroup.long c15:0x0400++0x00
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line.long 0x00 "MIDR1,Main ID Register"
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hexmask.long.byte 0x00 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x00 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x00 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x00 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x0600++0x00
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line.long 0x00 "MIDR2,Main ID Register"
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hexmask.long.byte 0x00 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x00 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x00 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x00 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x0700++0x00
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line.long 0x00 "MIDR3,Main ID Register"
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hexmask.long.byte 0x00 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x00 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x00 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x00 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x0200++0x00
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line.long 0x00 "TCMTR,Tightly Coupled Memory Type Register"
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bitfld.long 0x00 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,Implementation-defined,ARMv6,ARMv6,ARMv6"
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textline " "
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bitfld.long 0x00 28. " NEW ,Impl defined format" "Old,New"
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group.long c15:0x0300++0x00
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line.long 0x00 "TLBTR,TLB Type Register"
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bitfld.long 0x00 0. " S ,Separate" "Unified,Separated"
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rgroup.long c15:0x0500++0x00
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line.long 0x00 "MPIDR,Multiprocessor ID Register"
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bitfld.long 0x00 31. " FORMAT ,Format" "Old format,New format"
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bitfld.long 0x00 30. " U ,Uniprocessor" "Multiprocessor,Uniprocessor"
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bitfld.long 0x00 24. " MT ,Multi-Threading" "Single,Multi"
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textline " "
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bitfld.long 0x00 20.--23. " AFFL2[7:4] ,Affinity Level 2[7:4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " AFFL2[3:0] ,Affinity Level 2[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " AFFL1[7:4] ,Affinity Level 1[7:4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 8.--11. " AFFL1[3:0] ,Affinity Level 1[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " AFFL0[7:4] ,Affinity Level 0[7:4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " AFFL0[3:0] ,Affinity Level 0[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " ISH ,Inner-Shareable" "Non-cacheable,Coherent,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Non-coherent"
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Extension" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " AUX ,Auxiliary Registers" "Not supported,ACTRL,ACTRL/ADFSR/AIFSR,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCMDMA ,Tightly-Coupled Memory and DMA" "Not supported,Implementation-defined,ARMv6 TCM-only,ARMv6 TCM and DMA,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SHR ,Shareability realms" "Outer-shareable,Both,?..."
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bitfld.long 0x00 8.--11. " OSH ,Outer-Shareable" "Non-cacheable,Coherent,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Non-coherent"
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Protected Memory System Architecture" "Not supported,Implementation-defined,PMSAv6,PMSAv7,?..."
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textline " "
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture" "Not supported,Implementation-defined,VMSAv6,VMSAv7,VMSAv7 and PXN,VMSAv7 and PXN(64-bit),?..."
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BP ,Branch Predictor" "None,CONTEXTIDR[ASID] or FCSEIDR[PID],CONTEXTIDR[ASID],Underlying memory only,No flushing,?..."
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textline " "
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bitfld.long 0x00 24.--27. " L1TC ,L1 Test and Clean Ops" "Not supported,Legacy,Legacy,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCALL ,L1 Unified Cache Maintenance All" "Not supported,Legacy,Legacy,?..."
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bitfld.long 0x00 16.--19. " L1HCALL ,L1 Harvard Cache Maintenance All" "Not supported,Legacy,Legacy,Legacy,?..."
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bitfld.long 0x00 12.--15. " L1UCSW ,L1 Unified Cache Maintenance bySet/Way" "Not supported,Legacy,Legacy,Legacy,?..."
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textline " "
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bitfld.long 0x00 8.--11. " L1HCSW ,L1 Harvard Cache Maintenance by Set/Way" "Not supported,Legacy,Legacy,Legacy,?..."
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bitfld.long 0x00 4.--7. " L1UCMVA ,L1 Unified Cache Maintenance by MVA" "Not supported,Legacy,Legacy,?..."
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bitfld.long 0x00 0.--3. " L1HCMVA ,L1 Harvard Cache Maintenance by MVA" "Not supported,Legacy,Legacy,?..."
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " AFHU ,Access Flag Hardware Update" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait For Interrupt" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " BAR ,Barrier Operations" "Not supported,DSB,DSB/DMB/ISB,?..."
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textline " "
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bitfld.long 0x00 16.--19. " UTLB ,Unified TLB Maintenance" "Not supported,MVA/ALL,MVA/ALL/ASID,MVA/ALL/ASID/TLBIMVAA,MVA/ALL/ASID/TLBIMVAA/Virtualization extensions,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLB ,Harvard TLB Maintenance" "Not supported,MVA/ALL,MVA/ALL/ASID,?..."
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bitfld.long 0x00 8.--11. " L1HCRMVA ,L1 Harvard Cache Range Maintenance by MVA" "Not supported,Legacy,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1BPR ,L1 Background Prefetch Range" "Not supported,Legacy,?..."
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bitfld.long 0x00 0.--3. " L1FPR ,L1 Foreground Prefetch Range" "Not supported,Legacy,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersections" "Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported"
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bitfld.long 0x00 24.--27. " PMS ,Physical Memory Size Cache Support" "4GB,64GB,1TB,?..."
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bitfld.long 0x00 20.--23. " TTWC ,Translation Table Walk Coherency" "Disabled,Enabled,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MAINTBC ,Maintenance Broadcast" "Cache/TLB/branch predictor->local,Cache/branch predictor->local,Cache/TLB/branch predictor->defined,?..."
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textline " "
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bitfld.long 0x00 8.--11. " MLBPMVAALL ,Multi-Level Branch Predictor Maintenance by MVA/ALL" "Multi-level,All operation,Full support,?..."
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bitfld.long 0x00 4.--7. " MLCSW ,Multi-Level Cache Maintenance by Set/Way" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " MLCMVAALL ,Multi-Level Cache Maintenance by MVA/ALL" "Not supported,Supported,?..."
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIV ,Divide Instructions" "Not supported,SDIV/UDIV supported,SDIV/UDIV/ARM supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " DBG ,Debug Instructions" "Not supported,BKPT supported,?..."
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bitfld.long 0x00 16.--19. " CP ,Coprocessor Instructions" "Mandated support,Generic CDP/LDC/STC/MRC/MCR,Generic CDP/LDC/STC/MRC/MCR/generic CDP2/LDC2/STC2/MRC2/MCR2,Generic CDP/LDC/STC/MRC/MCR/generic CDP2/LDC2/STC2/MRC2/MCR2/generic MRRC/MCRR,Full support,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPB ,Compare-Branch Instructions" "Not supported,CBZ,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BITFIELD ,Bit Field Instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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textline " "
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bitfld.long 0x00 4.--7. " BITCOUNT ,Bit Count Instructions" "Not supported,CLZ,?..."
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bitfld.long 0x00 0.--3. " ATOMIC ,Atomic Instructions" "Not supported,SWP/SWPB,?..."
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rgroup.long c15:0x0120++0x00
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line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x00 28.--31. " JAZELLE ,Jazelle Instructions" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " INTERWORK ,Interworking Instructions" "Not supported,BX,BX/BLX/LDR,BX/BLX/LDR/ARM data,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMM ,Immediate Instructions" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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textline " "
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bitfld.long 0x00 16.--19. " IT ,If/Then Instructions" "Not supported,IT,?..."
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bitfld.long 0x00 12.--15. " SZEXT ,Sign/Zero Extend Instructions" "Not supported,SXTB/SXTH/UXTB/UXTH,Full support,?..."
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textline " "
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bitfld.long 0x00 8.--11. " EXCAR ,Exception Instructions(ARMv7A/R profiles)" "Not supported,CPS/RFE/SRS,?..."
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bitfld.long 0x00 4.--7. " EXC ,Exception Instructions" "Not supported,LDM(2)/LDM(3)/STM(2),?..."
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textline " "
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bitfld.long 0x00 0.--3. " ENDIAN ,Endian Instructions" "Not supported,SETEND,?..."
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rgroup.long c15:0x0220++0x00
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line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x00 28.--31. " REVERSAL ,Reversal Instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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textline " "
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bitfld.long 0x00 24.--27. " PSRAR ,Program Status Register Instructions" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " ADVUMULT ,Advanced Unsigned Multiply Instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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textline " "
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bitfld.long 0x00 16.--19. " ADVSMULT ,Advanced Signed Multiply Instructions" "Not supported,SMULL/SMLAL,Advanced support,Full support,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MULTIPLY ,Multiply Instructions" "MUL,MUL/MLA,MUL/MLA/MLS,?..."
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bitfld.long 0x00 8.--11. " MULTIPLE ,Load/Store Multiple Instructions" "Non-interruptible,Restartable,Continuable,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MEMHINT ,Memory Hint Instructions" "Not supported,PLD,Reserved,PLD/PLI,PLD/PLI/PLDW,?..."
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bitfld.long 0x00 0.--3. " LDST ,Load/Store Instructions" "Basic,LDRD/STRD,?..."
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rgroup.long c15:0x0320++0x00
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line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x00 28.--31. " THUMBEE ,Thumb Execution Environment" "Not supported,ENTERX/LEAVEX/null-check,?..."
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textline " "
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bitfld.long 0x00 24.--27. " TRUENOP ,True NOP Instructions" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " TCPY ,Thumb CPY Instructions" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TB ,Table Branch Instructions" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SYNCPRIM ,Synchronization Primitive Instructions" "Not supported,LDREX/STREX,Full support,?..."
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bitfld.long 0x00 8.--11. " SVC ,SVC Instruction" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMD ,SIMD Instructions" "Not supported,SSAT/USAT,Reserved,Full support,?..."
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bitfld.long 0x00 0.--3. " SAT ,Saturate Instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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rgroup.long c15:0x0420++0x00
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line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x00 28.--31. " SWPFRAC ,SWAP Fractional" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRM ,Program Status Register Instructions" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " SYNCPRIMFRAC ,Synchronization Primitive Fractional" "D_ISAR3[SYNCPRIM],Reserved,Reserved,Full support,?..."
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textline " "
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bitfld.long 0x00 16.--19. " BAR ,Barrier Instructions" "Not supported,DMB/DSB/ISB,?..."
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bitfld.long 0x00 12.--15. " SMI ,Secure Monitor Instruction" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BASEUPDATE ,Base Update Forms" "LDM/STM/PUSH/POP/RFE,Full support,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SHIFT ,Shift Forms" "MOV/Shift,MOV/Shift/LSL,Reserved,MOV/Shift/LS/IMM shift,MOV/Shift/LS/IMM shift/Reg shift,?..."
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textline " "
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bitfld.long 0x00 0.--3. " TFORM ,T-Form Instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHT/STRHT,?..."
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rgroup.long c15:0x0520++0x00
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line.long 0x00 "ID_ISAR5,Instruction Set Attributes Register 5"
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rgroup.long c15:0x0010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " THUMBEE ,ThumbEE State" "Not supported,Supported,?..."
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bitfld.long 0x00 8.--11. " JAZELLE ,Jazelle State" "Not supported,Supported/not cleared,Supported/cleared,?..."
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textline " "
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bitfld.long 0x00 4.--7. " THUMB ,Thumb State" "Not supported,16-bit Thumb,16-bit Thumb + 32-bit B/BL,All Thumb and Thumb-2,?..."
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textline " "
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bitfld.long 0x00 0.--3. " ARM ,ARM State" "Not supported,Supported,?..."
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rgroup.long c15:0x0110++0x00
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line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 16.--19. " GTS ,Generic Timer Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " VIRT ,Virtualization Extension" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " MPGM ,Micro-controller Programmer's Model" "Not supported,Reserved,2-stack,3-stack,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SEC ,Security Extension" "Not supported,Supported,Supported/NSACR[RFR],?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BPGM ,Base Programmer's Model" "Not supported,Supported,?..."
|
|
rgroup.long c15:0x0210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " PMM ,Performance Monitor Model" "Version 1/not supported,Version 1,Version 2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,No monitor"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MDMMM ,Micro-controller Debug Model - Memory-Mapped" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDMMM ,Trace Debug Model - Memory-Mapped" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDMCP ,Trace Debug Model - CP-based" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDMMM ,Core Debug Model - Memory-Mapped" "Not supported,Reserved,Reserved,Reserved,v7 MM,v7.1 MM,?..."
|
|
bitfld.long 0x00 4.--7. " SDMCP ,Security Debug Model - CP-based" "Not supported,Reserved,Reserved,v6.1,v7,v7.1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CDMCP ,Core Debug Model - CP-based" "Not supported,Reserved,v6,v6.1,v7 CP,v7.1 CP,?..."
|
|
group.long c10:0x7007++0x00
|
|
line.long 0x00 "MVFR0,Media Vector Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " VFPRM ,VFP Rounding Mode" "Round-to-nearest,All supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " VFPSV ,VFP Short Vectors" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 20.--23. " VFPSQRT ,VFP Square Root" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " VFPDIV ,VFP Divide" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " VFPTE ,VFP Trapped Exceptions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " VFPDP ,VFP Double Precision" "Not supported,VFPv2 supported,VFPv3 supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " VFPSP ,VFP Single Precision" "Not supported,VFPv2 supported,VFPv3 supported,?..."
|
|
bitfld.long 0x00 0.--3. " ASERF ,ASE Register File" "No ASE,16 x 64-bit,32 x 64-bit,?..."
|
|
group.long c10:0x7006++0x00
|
|
line.long 0x00 "MVFR1,Media Vector Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " ASEFMAC ,ASE Fused Multiply Accumulate" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " VFPHP ,VFP Half-Precision" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 20.--23. " ASEHP ,ASE Half-Precision" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " ASESP ,ASE Single-Precision" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " ASEINT ,ASE Integer" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " ASELDST ,ASE Load/Store" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " VFPDN ,VFP Default NaN" "NaN,IEEE handling,?..."
|
|
bitfld.long 0x00 0.--3. " VFPFZ ,VFP Flush-to-Zero" "Flush-to-zero,IEEE handling,?..."
|
|
rgroup.long c15:0x0310++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c14:0x7000++0x00
|
|
line.long 0x00 "JIDR,Jazelle ID Register"
|
|
rgroup.long c14:0x7002++0x00
|
|
line.long 0x00 "JMCR,Jazelle Main Configuration Register"
|
|
rgroup.long c14:0x7001++0x00
|
|
line.long 0x00 "JOSCR,Jazelle OS Control Register"
|
|
tree.end
|
|
width 10.
|
|
tree "System Control and Configuration"
|
|
group.long c15:0x0001++0x00
|
|
line.long 0x00 "SCTLR,System Control Register"
|
|
bitfld.long 0x00 30. " TE ,Thumb Exceptions" "ARM,Thumb"
|
|
bitfld.long 0x00 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TRE ,TEX-Remap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NMFI ,Non-Maskable Fast Interrupts" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " EE ,Exception Endianness" "Little,Big"
|
|
bitfld.long 0x00 21. " FI ,Fast Interrupts" "Normal,Fast"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HAF ,Hardware Access Flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RR ,Replacement Strategy" "Random,Predictable"
|
|
bitfld.long 0x00 13. " V ,High Vectors" "Base,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SWPE ,Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C ,Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " A ,Alignment Required" "Not required,Required"
|
|
bitfld.long 0x00 0. " M ,MMU Enable" "Disabled,Enabled"
|
|
group.long c15:0x0101++0x00
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " DCFID ,D-Cache Flash-Invalidate Disable" "No,Yes"
|
|
bitfld.long 0x00 30. " FFTLBIALL ,Force Flash TLBIALL" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IWPLIE ,Interworking PLI Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MMUDRE ,MMU-Disabled Remap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FNCL1I ,Force Non-Cacheable L1 I-cache" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " FNCL1D ,Force Non-Cacheable L1 D-cache" "Not forced,Forced"
|
|
group.long c15:0x0201++0x00
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 31. " ASED ,Advanced SIMD Extensions Disable" "No,Yes"
|
|
bitfld.long 0x00 30. " D32D ,D32 Disable" "No,Yes"
|
|
bitfld.long 0x00 28. " ETMD ,ETM Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CP13 ,Coprocessor 13" "0,?..."
|
|
bitfld.long 0x00 24.--25. " CP12 ,Coprocessor 12" "0,?..."
|
|
bitfld.long 0x00 22.--23. " CP11 ,Coprocessor 11" "No access,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " CP10 ,Coprocessor 10" "No access,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CP9 ,Coprocessor 9" "0,?..."
|
|
bitfld.long 0x00 16.--17. " CP8 ,Coprocessor 8" "0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CP7 ,Coprocessor 7" "0,?..."
|
|
bitfld.long 0x00 12.--13. " CP6 ,Coprocessor 6" "0,?..."
|
|
bitfld.long 0x00 10.--11. " CP5 ,Coprocessor 5" "0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CP4 ,Coprocessor 4" "0,?..."
|
|
bitfld.long 0x00 6.--7. " CP3 ,Coprocessor 3" "0,?..."
|
|
bitfld.long 0x00 4.--5. " CP2 ,Coprocessor 2" "0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CP1 ,Coprocessor 1" "0,?..."
|
|
bitfld.long 0x00 0.--1. " CP0 ,Coprocessor 0" "0,?..."
|
|
textline ""
|
|
group.long c15:0x0011++0x00
|
|
line.long 0x00 "SCR,Secure Configuration Register"
|
|
bitfld.long 0x00 6. " NET ,Not Early Terminate" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AW ,A-bit Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FW ,F-bit Write" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EF ,External Fault" "Abort mode,Secure Monitor mode"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIQ ,Fast Interrupt Request" "FIQ mode,Secure Monitor mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQ ,Interrupt Request" "IRQ mode,Secure Monitor mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NS ,Non-Secure" "Secure,Non-secure"
|
|
group.long c15:0x0111++0x00
|
|
line.long 0x00 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 20. " NSETMD ,Non-Secure ETM Disable" "No,Yes"
|
|
bitfld.long 0x00 19. " RFR ,Reserve FIQ Registers" "Permitted,Not Permitted"
|
|
bitfld.long 0x00 15. " NSASED ,Non-Secure Advanced SIMD Extensions Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NSD32D ,Non-Secure D32 Disable" "No,Yes"
|
|
bitfld.long 0x00 13. " CP13 ,CP13 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 12. " CP12 ,CP12 Access" "Not accessed,Accessed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,CP11 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 10. " CP10 ,CP10 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 9. " CP9 ,CP9 Access" "Not accessed,Accessed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CP8 ,CP8 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 7. " CP7 ,CP7 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 6. " CP6 ,CP6 Access" "Not accessed,Accessed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CP5 ,CP5 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 4. " CP4 ,CP4 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 3. " CP3 ,CP3 Access" "Not accessed,Accessed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CP2 ,CP2 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 1. " CP1 ,CP1 Access" "Not accessed,Accessed"
|
|
bitfld.long 0x00 0. " CP0 ,CP0 Access" "Not accessed,Accessed"
|
|
textline ""
|
|
group.long c15:0x000C++0x00
|
|
line.long 0x00 "VBAR,Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Vector Base Address"
|
|
group.long c15:0x010C++0x00
|
|
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Vector Base Address"
|
|
rgroup.long c15:0x001C++0x00
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 7. " IRQ ,IRQ" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " FIQ ,FIQ" "Not pending,Pending"
|
|
group.long c15:0x741F++0x00
|
|
line.long 0x00 "ACGCCNTR,Adaptive Clock Gating Clock Count Register"
|
|
group.long c15:0x721F++0x00
|
|
line.long 0x00 "ACGCSR,Adaptive Clock Gating Control and Status Register"
|
|
bitfld.long 0x00 18. " OVS ,Overflow Status" "Low,High"
|
|
bitfld.long 0x00 17. " HS ,High-limit Status" "Low,High"
|
|
bitfld.long 0x00 16. " LS ,Low-limit status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ROOE ,Ring Osc Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FCE ,Frequency Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " FCCS ,Frequency Counter Clk Select" "ACG Clock,Duplicate ACG Clock,Ring oscillator,Core clock"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CCNTLKE ,Cycle Count Lock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVINT ,Averaging Interval" "8 cycles,64 cycles,512 cycles,4K cycles,32K cycles,256K cycles,2M cycles,16M cycles"
|
|
bitfld.long 0x00 3. " HIRQE ,High-limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LIRQE ,Low-limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOSCE ,Duplicate Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OSCE ,Oscillator Enable" "Disabled,Enabled"
|
|
group.long c15:0x731F++0x00
|
|
line.long 0x00 "ACGFCR,Adaptive Clock Gating Frequency Control Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " FC ,Frequency Control"
|
|
group.long c15:0x761F++0x00
|
|
line.long 0x00 "ACGHLR,Adaptive Clock Gating High Limit Register"
|
|
group.long c15:0x751F++0x00
|
|
line.long 0x00 "ACGLLR,Adaptive Clock Gating Low Limit Register"
|
|
group.long c15:0x702F++0x00
|
|
line.long 0x00 "ACLCR,Adaptive Current Limiter Control Register"
|
|
bitfld.long 0x00 16.--17. " WFXINT ,WFI/WFE throttle interval" "4 cycles,8 cycles,16 cycles,32 cycles"
|
|
bitfld.long 0x00 15. " DCTE ,Duty Cycle Throttle Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WFXE ,WFI/WFE throttle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OSCFC ,Oscillator Frequency Control" "Fast,Slow"
|
|
bitfld.long 0x00 12. " OVINTE ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " DCTL ,Divide Control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MAXPRD ,Max Period" "8 TCXO,32 TCXO,128 TCXO,512 TCXO"
|
|
bitfld.long 0x00 7. " OVE ,Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHARMODE ,Characterization Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCE ,Throttle Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MAX1E ,Previous Max period delay count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MAX0E ,Current Max period delay count Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PREVE ,Previous sample period delay count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FIXE ,Fixed delay count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OSCE ,Oscillator Enable" "Disabled,Enabled"
|
|
group.long c15:0x732F++0x00
|
|
line.long 0x00 "ACLSR0,Adaptive Current Limiter Status Register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PREVCNT ,Previous Count"
|
|
bitfld.long 0x00 15. " OVS ,Overflow Sticky" "Low,High"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CURRCNT ,Current Count"
|
|
group.long c15:0x742F++0x00
|
|
line.long 0x00 "ACLSR1,Adaptive Current Limiter Status Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MAX1CNT ,Previous period Max delay Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MAX0CNT ,Current period Max delay Count"
|
|
group.long c15:0x752F++0x00
|
|
line.long 0x00 "ACLSR2,Adaptive Current Limiter Status Register 2"
|
|
group.long c15:0x712F++0x00
|
|
line.long 0x00 "ACLTR0,Adaptive Current Limiter Threshold Register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PREV ,Previous thresholds"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXED ,Fixed Delay Count"
|
|
group.long c15:0x722F++0x00
|
|
line.long 0x00 "ACLTR1,Adaptive Current Limiter Threshold Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MAX1 ,Previous Max threshold"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MAX0 ,Current Max threshold"
|
|
group.long c15:0x700F++0x00
|
|
line.long 0x00 "ANSACR,Auxiliary Non-Secure Access Control Register"
|
|
bitfld.long 0x00 24. " L2REMOTE ,L2 Remote" "Not allowed,Allowed"
|
|
bitfld.long 0x00 23. " L2VR ,L2 Verification Registers" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " L2PWR ,L2 Power Registers" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " L2DB ,L2 Debug" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " L2EH ,L2 Error Handling" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " L2LK ,L2 Locking" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " L2CR ,L2 Control Registers" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " CPUVR ,CPU Verification Registers" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " CPUPWR ,CPU Power Registers" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPUDB ,CPU Debug" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " CPUEH ,CPU Error Handling" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " CPULKTLB ,CPU Lock TLB" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPULKIC ,CPU Lock Instruction Cache" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " CPULKDC ,CPU Lock Data Cache" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " CPUCR ,CPU Control Registers" "Not allowed,Allowed"
|
|
group.long c15:0x771F++0x00
|
|
line.long 0x00 "AVSCSR,Adaptive Voltage Scaling Control and Status Register"
|
|
bitfld.long 0x00 29. " VAVSU ,VeNum AVS_Up" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " CPUAVSU ,CPU AVS_Up" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " VAVSD ,VeNum AVS_Down" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPUAVSD ,CPU AVS_Down" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " DSCRSEL ,DSCR Select" "L2CPUAVSDSCR,AVSDSCR"
|
|
bitfld.long 0x00 5. " VEN ,VeNum Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPUEN ,CPU Enable" "Disabled,Enabled"
|
|
group.long c15:0x760F++0x00
|
|
line.long 0x00 "AVSDSCR,Adaptive Voltage Scaling Delay Synthesizer Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " AVSDSDLY ,AVS Delay Synthesizer Delay"
|
|
group.long c15:0x720F++0x00
|
|
line.long 0x00 "BPCR,Branch Predictor Control Register"
|
|
bitfld.long 0x00 18. " BHTRRE ,BHT Re-Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " FL1BTACD ,Force L1 Branch Target Address Cache Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " FPLIAD ,Force PLI Allocation Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FBTICD ,Force BTIC Disable" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " BTICT ,BTIC Threshold" "1,2,3,?..."
|
|
bitfld.long 0x00 11. " FPLIHINTD ,Force PLI Hint Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FBHTD ,Force Branch History Table Disable" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " FBTACD ,Force Branch Target Address Cache Disable" "Not forced,Forced"
|
|
hexmask.long.word 0x00 0.--8. 1. " GHRM ,Global History Register Mask"
|
|
rgroup.long c15:0x1429++0x00
|
|
line.long 0x00 "BPDR0,Branch Predictor Data Register 0"
|
|
rgroup.long c15:0x1529++0x00
|
|
line.long 0x00 "BPDR1,Branch Predictor Data Register 1"
|
|
hexmask.long 0x00 0.--27. 1. " INST ,Instruction"
|
|
group.long c15:0x1029++0x00
|
|
line.long 0x00 "BPTR0,Branch Predictor Tag Register 0"
|
|
hexmask.long 0x00 1.--31. 0x2 " TVA ,Tag Virtual Address"
|
|
bitfld.long 0x00 0. " TV ,Tag Valid" "Disabled,Enabled"
|
|
group.long c15:0x1129++0x00
|
|
line.long 0x00 "BPTR1,Branch Predictor Tag Register 1"
|
|
hexmask.long 0x00 1.--31. 0x2 " BPTVA ,Branch Predictor Target Virtual Address"
|
|
bitfld.long 0x00 0. " BPTT ,Branch Predictor Target T-state" "Disabled,Enabled"
|
|
rgroup.long c15:0x1229++0x00
|
|
line.long 0x00 "BPTR2,Branch Predictor Tag Register 2"
|
|
bitfld.long 0x00 29. " BLC ,Branch Line Crossing instruction" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BTLC ,Branch Target Line Crossing instruction" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BTUX ,Branch Target User Execute" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " BTPX ,Branch Target Privileged Execute" "Not privileged,Privileged"
|
|
bitfld.long 0x00 25. " ATA ,Adjust Target Address" "Same cache line,Next cache line"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TT ,Tag T-state" "ARM,Thumb"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TJ ,Tag J-state" "ARM/Thumb,ThumbEE"
|
|
bitfld.long 0x00 22. " TNS ,Tag NS-state" "Secure,Non-secure"
|
|
bitfld.long 0x00 18.--20. " BTIVLD ,BTIC Instr Valid" "No instructions,One instruction,Reserved,Reserved,Two instructions,Reserved,Reserved,Three instructions"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CNTR ,Counter" "Weakly PLI,Strongly PLI,Weakly BTAC,Strongly BTAC"
|
|
bitfld.long 0x00 14.--15. " CCNTR[1:0] ,Confidence Counter" "Reserved,Not confident,Weakly confident,Strongly confident"
|
|
textline " "
|
|
bitfld.long 0x00 11.--13. " PLRU[2:0] ,Pseudo LRU" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BHTD3 ,Branch History Table Data 3" "Strongly not-taken,Weakly not-taken,Weakly taken,Strongly taken"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BHTD2 ,Branch History Table Data 2" "Strongly not-taken,Weakly not-taken,Weakly taken,Strongly taken"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " BHTD1 ,Branch History Table Data 1" "Strongly not-taken,Weakly not-taken,Weakly taken,Strongly taken"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " BHTD0 ,Branch History Table Data 0" "Strongly not-taken,Weakly not-taken,Weakly taken,Strongly taken"
|
|
group.long c15:0x1329++0x00
|
|
line.long 0x00 "BPVIC,Branch Predictor Victim Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " REPLVEC ,Replacement Vector"
|
|
group.long c15:0x703F++0x00
|
|
line.long 0x00 "MCTCNTR,Max Current Throttler Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Count"
|
|
group.long c15:0x762F++0x00
|
|
line.long 0x00 "MCTCR,Max Current Throttler Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ULIM ,Upper Limit"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DCNT ,Decrement Count"
|
|
bitfld.long 0x00 4.--7. " VAW ,VeNum Active Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MODE ,Mode" "Block instruction issue,Divide core clock by 2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DVI ,Disable when VeNum Idle" "No,Yes"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group.long c15:0x723F++0x00
|
|
line.long 0x00 "MCTVLSWR,Max Current Throttler Venum L/S-pipe Weight Register"
|
|
bitfld.long 0x00 28.--31. " IC7 ,Instruction Class 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " IC6 ,Instruction Class 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " IC5 ,Instruction Class 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " IC4 ,Instruction Class 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " IC3 ,Instruction Class 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " IC2 ,Instruction Class 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1 ,Instruction Class 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IC0 ,Instruction Class 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long c15:0x713F++0x00
|
|
line.long 0x00 "MCTVXWR,Max Current Throttler Venum X-pipe Weight Register"
|
|
bitfld.long 0x00 28.--31. " IC7 ,Instruction Class 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " IC6 ,Instruction Class 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " IC5 ,Instruction Class 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " IC4 ,Instruction Class 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " IC3 ,Instruction Class 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " IC2 ,Instruction Class 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1 ,Instruction Class 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IC0 ,Instruction Class 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long c15:0x772F++0x00
|
|
line.long 0x00 "MCTWR,Max Current Throttler Weight Register"
|
|
bitfld.long 0x00 28.--31. " IC7 ,Instruction Class 7 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " IC6 ,Instruction Class 6 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " IC5 ,Instruction Class 5 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " IC4 ,Instruction Class 4 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " IC3 ,Instruction Class 3 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " IC2 ,Instruction Class 2 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1 ,Instruction Class 1 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IC0 ,Instruction Class 0 weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long c15:0x701F++0x00
|
|
line.long 0x00 "ROCR,Ring Oscillator Control Register"
|
|
bitfld.long 0x00 4.--6. " ROSITE ,Ring Oscillator Site" "Reserved,CPU 1,CPU 2,CPU 3,CPU 4,CPU 5,Trace,?..."
|
|
bitfld.long 0x00 1.--3. " ROTYPE ,Ring Oscillator Type" "NVT/30nm/gate delay,NVT/40nm/gate delay,LVT/30nm/gate delay,LVT/40nm/gate delay,LVT/30nm/gate+wire delay,AVS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROE ,Ring Oscillator Enable" "Disabled,Enabled"
|
|
group.long c14:0x6000++0x00
|
|
line.long 0x00 "TEECR,Thumb Execution Environment Configuration Register"
|
|
bitfld.long 0x00 0. " XED ,Execution Environment Disable" "No,Yes"
|
|
group.long c14:0x6001++0x00
|
|
line.long 0x00 "TEEHBR,Thumb Execution Environment Handler Base Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " HBA ,Handler Base Address"
|
|
group.long c15:0x700B++0x00
|
|
line.long 0x00 "VPMRESR0,Venum Performance Monitor Region Event Selection Register 0"
|
|
bitfld.long 0x00 31. " EN ,EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " GRP3SEL ,Group 3 local event select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 16.--20. " GRP2SEL ,Group 2 local event select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " GRP1SEL ,Group 1 local event select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 0.--4. " GRP0SEL ,Group 0 local event select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long c15:0x740F++0x00
|
|
line.long 0x00 "CECR,CPU Error Control Register"
|
|
bitfld.long 0x00 8. " TLBMHIE ,TLB Multi-Hit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ICPEIE ,Instruction Cache Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DCPEIE ,Data Cache Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EICP ,Enable Instruction Cache Parity" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDCP ,Enable Data Cache Parity" "Disabled,Enabled"
|
|
group.long c15:0x710F++0x00
|
|
line.long 0x00 "CESR,CPU Error Status Register"
|
|
eventfld.long 0x00 16. " TLBMHE ,TLB Multi-Hit" "No error,Error"
|
|
eventfld.long 0x00 3. " ICDPE ,I-Cache Data Parity Error" "No error,Error"
|
|
eventfld.long 0x00 2. " ICTPE ,I-Cache Tag Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DCDPE ,D-Cache Data Parity Error" "No error,Error"
|
|
eventfld.long 0x00 0. " DCTPE ,D-Cache Tag Parity Error" "No error,Error"
|
|
group.long c15:0x770F++0x00
|
|
line.long 0x00 "CESRS,CPU Error Status Register Set"
|
|
bitfld.long 0x00 16. " TLBMHE ,TLB Multi-Hit" "No effect,Set"
|
|
bitfld.long 0x00 3. " ICDPE ,I-Cache Data Parity Error" "No effect,Set"
|
|
bitfld.long 0x00 2. " ICTPE ,I-Cache Tag Parity Error" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DCDPE ,D-Cache Data Parity Error" "No effect,Set"
|
|
bitfld.long 0x00 0. " DCTPE ,D-Cache Tag Parity Error" "No effect,Set"
|
|
if (((d.l(c15:0x710F))&0x10000)==0x10000)
|
|
rgroup.long c15:0x730F++0x00
|
|
line.long 0x00 "CESYNR,CPU Error Syndrome Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x1000 " DSVA ,Data-Side Virtual Address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,Address Space Identifier"
|
|
else
|
|
rgroup.long c15:0x730F++0x00
|
|
line.long 0x00 "CESYNR,CPU Error Syndrome Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " ERRPOSITION ,Error Position"
|
|
bitfld.long 0x00 12.--15. " WAY ,WAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--11. " SET ,SET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " QW ,QW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long c15:0x750F++0x00
|
|
line.long 0x00 "CPMR0,Clock and Power Management Register 0"
|
|
bitfld.long 0x00 17. " NOPWFI ,Nop WFI" "Normally,Nops"
|
|
bitfld.long 0x00 16. " NOPWFE ,Nop WFE" "Normally,Nops"
|
|
bitfld.long 0x00 8.--9. " VSLPDLY ,VeNum Sleep Delay" "0 cycles,64 cycles,Sleep,Never sleep"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CPUSLPDLY ,CPU Sleep Delay" "0 cycles,64 cycles"
|
|
bitfld.long 0x00 3. " ETMCLKEN ,ETM Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VCLKAGD ,VeNum Clock Auto-Gating Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPUCLKAGD ,CPU Clock Auto-Gating Disable" "No,Yes"
|
|
tree.end
|
|
width 12.
|
|
tree "Memory Management Unit"
|
|
group.long c15:0x0001++0x00
|
|
line.long 0x00 "SCTLR,System Control Register"
|
|
bitfld.long 0x00 30. " TE ,Thumb Exceptions" "ARM,Thumb"
|
|
bitfld.long 0x00 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TRE ,TEX-Remap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NMFI ,Non-Maskable Fast Interrupts" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " EE ,Exception Endianness" "Little,Big"
|
|
bitfld.long 0x00 21. " FI ,Fast Interrupts" "Normal,Fast"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HAF ,Hardware Access Flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RR ,Replacement Strategy" "Random,Predictable"
|
|
bitfld.long 0x00 13. " V ,High Vectors" "Base,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SWPE ,Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C ,Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " A ,Alignment Required" "Not required,Required"
|
|
bitfld.long 0x00 0. " M ,MMU Enable" "Disabled,Enabled"
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.quad c15:0x10020++0x01
|
|
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " ASID ,Application Space ID"
|
|
bitfld.quad 0x00 36.--39. " BADDR ,Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.quad.long 0x00 4.--35. 0x10 " BADDR ,Base Address"
|
|
group.quad c15:0x11020++0x01
|
|
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " ASID ,Application Space ID"
|
|
bitfld.quad 0x00 36.--39. " BADDR ,Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.quad.long 0x00 4.--35. 0x10 " BADDR ,Base Address"
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,64-bit"
|
|
bitfld.long 0x00 28.--29. " SH1 ,Shareability for TTBR1" "Not Shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.long 0x00 26.--27. " ORGN1 ,Outer Region Cache Policy for TTBR1" "Non-cacheable,Copy-back/write-allocate,Write-through,Copy-back/write-no-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IRGN1 ,Inner Region Cache Policy for TTBR1" "Non-cacheable,Copy-back/write-allocate,Write-through,Copy-back/write-no-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EPD1 ,Extended Page Disable 1" "No,Yes"
|
|
bitfld.long 0x00 22. " A1 ,ASID select" "TTBR0,TTBR1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " T1SZ ,TTBR1 region size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability for TTBR0" "Not Shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Region Cache Policy for TTBR0" "Non-cacheable,Copy-back/write-allocate,Write-through,Copy-back/write-no-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Region Cache Policy for TTBR0" "Non-cacheable,Copy-back/write-allocate,Write-through,Copy-back/write-no-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EPD0 ,Extended Page Disable 0" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " T0SZ ,TTBR0 region size" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PA ,Physical Address"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer-Shareable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " ORGN ,Outer Region Cache Policy" "Non-cacheable,Copy-back/write-allocate,Write-through,Copy-back/write-no-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SH ,Shareable" "Private,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner Region Cache Policy" "Non-cacheable,Copy-back/write-allocate,Write-through,Copy-back/write-no-allocate"
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " PA ,Physical Address"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer-Shareable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " ORGN ,Outer Region Cache Policy" "Non-cacheable,Copy-back/write-allocate,Write-through,Copy-back/write-no-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SH ,Shareable" "Private,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner Region Cache Policy" "Non-cacheable,Copy-back/write-allocate,Write-through,Copy-back/write-no-allocate"
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,64-bit"
|
|
bitfld.long 0x00 5. " PD1 ,Page Disable 1" "No,Yes"
|
|
bitfld.long 0x00 4. " PD0 ,Page Disable 0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " N ,Number" "TTBR0,TTBR1,TTBR1,TTBR1,TTBR1,TTBR1,TTBR1,TTBR1"
|
|
endif
|
|
group.long c15:0x0003++0x00
|
|
line.long 0x00 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x00 30.--31. " D15 ,Defines the access permissions for Domain 15" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 28.--29. " D14 ,Defines the access permissions for Domain 14" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 26.--27. " D13 ,Defines the access permissions for Domain 13" "No access,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " D12 ,Defines the access permissions for Domain12 " "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 22.--23. " D11 ,Defines the access permissions for Domain 11" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 20.--21. " D10 ,Defines the access permissions for Domain 10" "No access,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " D9 ,Defines the access permissions for Domain 9" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 16.--17. " D8 ,Defines the access permissions for Domain 8" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 14.--15. " D7 ,Defines the access permissions for Domain 7" "No access,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " D6 ,Defines the access permissions for Domain 6" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 10.--11. " D5 ,Defines the access permissions for Domain 5" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 8.--9. " D4 ,Defines the access permissions for Domain 4" "No access,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " D3 ,Defines the access permissions for Domain 3" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 4.--5. " D2 ,Defines the access permissions for Domain 2" "No access,Client,Reserved,Manager"
|
|
bitfld.long 0x00 2.--3. " D1 ,Defines the access permissions for Domain 1" "No access,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " D0 ,Defines the access permissions for Domain 0" "No access,Client,Reserved,Manager"
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache Maintenance" "No error,Error"
|
|
bitfld.long 0x00 11. " WNR ,Write/Not Read" "Read,Write"
|
|
bitfld.long 0x00 9. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " FS ,Fault Status" "No Data,Translation Fault at level 1,Translation Fault at level 2,Translation Fault at level 3,Reserved, Access Flag Fault at level 1, Access Flag Fault at level 2, Access Flag Fault at level 3,Reserved, Permission Fault at level 1, Permission Fault at level 2, Permission Fault at level 3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment Fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache Maintenance" "No error,Error"
|
|
bitfld.long 0x00 11. " WNR ,Write/Not Read" "Read,Write"
|
|
bitfld.long 0x00 9. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Fault Status" "No Data,Alignment,Watchpoint,Access Flag,Reserved,Translation,Access Flag(page),Translation(2nd level),Reserved,Domain(section),Reserved,Domain(page),Reserved,Permission(section),Reserved,Permission(page),Reserved,Permission Fault(section),Reserved, Permission Fault (page),TLB conflict,?..."
|
|
endif
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 9. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
bitfld.long 0x00 0.--5. " FS ,Fault Status" "No Prefetch,Reserved,Reserved,Reserved,Reserved,Translation Fault at level 1,Translation Fault at level 2,Translation Fault at level 3,Reserved,Access Flag Fault at level 1,Access Flag Fault at level 2,Access Flag Fault at level 3,Reserved,Permission Fault at level 1,Permission Fault at level 2,Permission Fault at level 3,Reserved,Reserved,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 9. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
bitfld.long 0x00 0.--5. 10. " FS ,Fault Status" "No Prefetch,Reserved,Debug Event,Access Flag (section),Reserved,Translation (1st-level),Access Flag (page),Translation (2nd-level),Reserved,Domain (section),Reserved,Domain (page),Reserved,Permission (section),Reserved,Permission (page),TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,..."
|
|
endif
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
hexmask.long 0x00 1.--31. 0x2 " VA ,Virtual Address"
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
if ((((d.l(c15:0x0047))&0x01)==0x01)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)&&(((d.l(c15:0x0047))&0x800)==0x000))
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
bitfld.long 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
bitfld.long 0x00 1.--6. " FS ,Fault Status" "No Data Abort,Reserved,Watchpoint Debug Event,Access Flag Fault (section),Reserved,Translation Fault (1st-level),Access Flag Fault (page),Translation Fault (2nd-level),Reserved,Domain Fault (section),Reserved,Domain Fault (page),Reserved,Permission Fault (section),Reserved,Permission Fault (page),TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
elif ((((d.l(c15:0x0047))&0x01)==0x01)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)&&(((d.l(c15:0x0047))&0x800)==0x800))
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
bitfld.long 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
bitfld.long 0x00 9. " FSTAGE ,Fault Stage" "Stage 1,Stage 2"
|
|
bitfld.long 0x00 8. " S2WLK ,Stage 2 Walk" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 1.--6. " FS ,Fault Status" "No Data,Translation Fault at level 1,Translation Fault at level 2,Translation Fault at level 3,Reserved,Access Flag Fault at level 1,Access Flag Fault at level 2,Access Flag Fault at level 3,Reserved,Permission Fault at level 1,Permission Fault at level 2,Permission Fault at level 3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
elif ((((d.l(c15:0x0047))&0x01)==0x00)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)&&(((d.l(c15:0x0047))&0x800)==0x000))
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " PA ,Physical Address"
|
|
bitfld.long 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
bitfld.long 0x00 10. " NOS ,Not Outer Shareable" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NS ,Non-Secure" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " IMP ,Implementation defined" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SH ,Shareable" "Not shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INNER ,Inner Cache Policy" "Non-cacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " OUTER ,Outer Cache Policy" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SS ,Supersection" "Section or page,Supersection"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
elif ((((d.l(c15:0x0047))&0x01)==0x00)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)&&(((d.l(c15:0x0047))&0x800)==0x800))
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
textline " Upper 32-bits of PAR are not accessible when"
|
|
textline " TTBCR[EAE] == 32-bit && PAR[LPAE] == 64-bit "
|
|
textline " "
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " PA ,Physical Address"
|
|
bitfld.long 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NS ,Non-Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 7.--8. " SH ,Shareability" "Non-shareable,Unpredictable,Outer shareable,Inner shareable"
|
|
bitfld.long 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
elif ((((d.q(c15:0x10070))&0x01)==0x01)&&(((d.l(c15:0x0202))&0x80000000)==0x80000000)&&(((d.q(c15:0x10070))&0x800)==0x000))
|
|
group.quad c15:0x10070++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
bitfld.quad 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
bitfld.quad 0x00 9. " FSTAGE ,Fault Stage" "Stage 1,Stage 2"
|
|
bitfld.quad 0x00 8. " S2WLK ,Stage 2 Walk" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.quad 0x00 1.--6. " FS ,Fault Status" "No Data Abort,Reserved,Watchpoint Debug Event,Access Flag Fault (section),Reserved,Translation Fault (1st-level),Access Flag Fault (page),Translation Fault (2nd-level),Reserved,Domain Fault (section),Reserved,Domain Fault (page),Reserved,Permission Fault (section),Reserved,Permission Fault (page),TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
elif ((((d.q(c15:0x10070))&0x01)==0x01)&&(((d.l(c15:0x0202))&0x80000000)==0x80000000)&&(((d.q(c15:0x10070))&0x800)==0x800))
|
|
group.quad c15:0x10070++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
bitfld.quad 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
bitfld.quad 0x00 9. " FSTAGE ,Fault Stage" "Stage 1,Stage 2"
|
|
bitfld.quad 0x00 8. " S2WLK ,Stage 2 Walk" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.quad 0x00 1.--6. " FS ,Fault Status" "No Data,Translation Fault at level 1,Translation Fault at level 2,Translation Fault at level 3,Reserved,Access Flag Fault at level 1,Access Flag Fault at level 2,Access Flag Fault at level 3,Reserved,Permission Fault at level 1,Permission Fault at level 2,Permission Fault at level 3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
elif ((((d.q(c15:0x10070))&0x01)==0x00)&&(((d.l(c15:0x0202))&0x80000000)==0x80000000)&&(((d.q(c15:0x10070))&0x800)==0x000))
|
|
group.quad c15:0x10070++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
hexmask.quad.tbyte 0x00 12.--31. 0x10 " PA ,Physical Address"
|
|
bitfld.quad 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
bitfld.quad 0x00 10. " NOS ,Not Outer Shareable" "Outer,Inner"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " NS ,Non-Secure" "Secure,Non-secure"
|
|
bitfld.quad 0x00 8. " IMP ,Implementation defined" "Disabled,Enabled"
|
|
bitfld.quad 0x00 7. " SH ,Shareable" "Not shareable,Shareable"
|
|
textline " "
|
|
bitfld.quad 0x00 4.--6. " INNER ,Inner Cache Policy" "Non-cacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.quad 0x00 2.--3. " OUTER ,Outer Cache Policy" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.quad 0x00 1. " SS ,Supersection" "Section or page,Supersection"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
elif ((((d.q(c15:0x10070))&0x01)==0x00)&&(((d.l(c15:0x0202))&0x80000000)==0x80000000)&&(((d.q(c15:0x10070))&0x800)==0x800)&&(((d.q(c15:0x10070))&0xF000000000000000)==0x0000000000000000))
|
|
group.quad c15:0x10070++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
bitfld.quad 0x00 60.--63. " ATTR[7:4] ,Attributes" "Non-normal,Normal/Write-through Transient,Normal/Write-through Transient,Normal/Write-through Transient,Normal/non-cacheable,Normal/Write-back Transient,Normal/Write-back Transient,Normal/Write-back Transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient"
|
|
textline " "
|
|
bitfld.quad 0x00 56.--59. " ATTR[3:0] ,Attributes - SO/DV differentiation" "Strongly Ordered,Unpredictable,Unpredictable,Unpredictable,Device,Unpredictable,Unpredictable,Unpredictable,Unpredictable,Unpredictable,Unpredictable,Unpredictable,Unpredictable,Unpredictable,Unpredictable,Unpredictable"
|
|
textline " "
|
|
hexmask.quad.long 0x00 12.--39. 0x1000 " PA ,Physical Address"
|
|
bitfld.quad 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " NS ,Non-Secure" "Secure,Non-Secure"
|
|
bitfld.quad 0x00 7.--8. " SH ,Shareability" "Non-shareable,Unpredictable,Outer shareable,Inner shareable"
|
|
bitfld.quad 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
else
|
|
group.quad c15:0x10070++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
bitfld.quad 0x00 60.--63. " ATTR[7:4] ,Attributes - outer region policy" "Non-normal,Normal/Write-through Transient,Normal/Write-through Transient,Normal/Write-through Transient,Normal/non-cacheable,Normal/Write-back Transient,Normal/Write-back Transient,Normal/Write-back Transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient"
|
|
textline " "
|
|
bitfld.quad 0x00 56.--59. " ATTR[3:0] ,Attributes - inner region policy" "Unpredictable,Normal/Write-through Transient,Normal/Write-through Transient,Normal/Write-through Transient,Normal/non-cacheable,Normal/Write-back Transient,Normal/Write-back Transient,Normal/Write-back Transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-through Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient,Normal/Write-back Non-transient"
|
|
textline " "
|
|
hexmask.quad.long 0x00 12.--39. 0x1000 " PA ,Physical Address"
|
|
bitfld.quad 0x00 11. " LPAE ,Large Physical Address Extension" "32-bit,64-bit"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " NS ,Non-Secure" "Secure,Non-Secure"
|
|
bitfld.quad 0x00 7.--8. " SH ,Shareability" "Non-shareable,Unpredictable,Outer shareable,Inner shareable"
|
|
bitfld.quad 0x00 0. " FAULT ,Fault" "No fault,Fault"
|
|
endif
|
|
group.long c15:0x000D++0x00
|
|
line.long 0x00 "FCSEIDR,Fast Context Switch Extension ID Register"
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x010D++0x00
|
|
line.long 0x00 "CONTEXTIDR,Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,Application Space ID"
|
|
else
|
|
group.long c15:0x010D++0x00
|
|
line.long 0x00 "CONTEXTIDR,Context ID Register"
|
|
endif
|
|
group.long c15:0x014A++0x00
|
|
line.long 0x00 "MMUDCPR,MMU Disabled Cache Policy Register"
|
|
bitfld.long 0x00 30.--31. " OCPR7 ,Outer Cache Policy Region 7" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 28.--29. " OCPR6 ,Outer Cache Policy Region 6" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OCPR5 ,Outer Cache Policy Region 5" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 24.--25. " OCPR4 ,Outer Cache Policy Region 4" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OCPR3 ,Outer Cache Policy Region 3" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 20.--21. " OCPR2 ,Outer Cache Policy Region 2" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OCPR1 ,Outer Cache Policy Region 1" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 16.--17. " OCPR0 ,Outer Cache Policy Region 0" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " ICPR7 ,Inner Cache Policy Region 7" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 12.--13. " ICPR6 ,Inner Cache Policy Region 6" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ICPR5 ,Inner Cache Policy Region 5" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 8.--9. " ICPR4 ,Inner Cache Policy Region 4" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICPR3 ,Inner Cache Policy Region 3" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 4.--5. " ICPR2 ,Inner Cache Policy Region 2" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ICPR1 ,Inner Cache Policy Region 1" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 0.--1. " ICPR0 ,Inner Cache Policy Region 0" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
group.long c15:0x004A++0x00
|
|
line.long 0x00 "MMUDMTR,MMU Disabled Memory Type Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NOS ,Not Outer-Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SHR7 ,Shareable Attribute for Region 7" "Not shareable,Shareable"
|
|
bitfld.long 0x00 22. " SHR6 ,Shareable Attribute for Region 6" "Not shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SHR5 ,Shareable Attribute for Region 5" "Not shareable,Shareable"
|
|
bitfld.long 0x00 20. " SHR4 ,Shareable Attribute for Region 4" "Not shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SHR3 ,Shareable Attribute for Region 3" "Not shareable,Shareable"
|
|
bitfld.long 0x00 18. " SHR2 ,Shareable Attribute for Region 2" "Not shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SHR1 ,Shareable Attribute for Region 1" "Not shareable,Shareable"
|
|
bitfld.long 0x00 16. " SHR0 ,Shareable Attribute for Region 0" "Not shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MTR7 ,Memory Type Region 7" "Strongly-ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 12.--13. " MTR6 ,Memory Type Region 6" "Strongly-ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MTR5 ,Memory Type Region 5" "Strongly-ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 8.--9. " MTR4 ,Memory Type Region 4" "Strongly-ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MTR3 ,Memory Type Region 3" "Strongly-ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 4.--5. " MTR2 ,Memory Type Region 2" "Strongly-ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MTR1 ,Memory Type Region 1" "Strongly-ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 0.--1. " MTR0 ,Memory Type Region 0" "Strongly-ordered,Device,Normal,?..."
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x002A++0x00
|
|
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NOS ,Not Outer-Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SHNS1 ,Shareable Attribute for Normal S=1 Classes" "Not shareable,Shareable"
|
|
bitfld.long 0x00 18. " SHNS0 ,Shareable Attribute for Normal S=0 Classes" "Not shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SHDS1 ,Shareable Attribute for Device S=1 Classes" "Not shareable,Shareable"
|
|
bitfld.long 0x00 16. " SHDS0 ,Shareable Attribute for Device S=0 Classes" "Not shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MTC7 ,Memory Type Class 7" "Strongly-ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 12.--13. " MTC6 ,Memory Type Class 6" "Strongly-ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MTC5 ,Memory Type Class 5" "Strongly-ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 8.--9. " MTC4 ,Memory Type Class 4" "Strongly-ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MTC3 ,Memory Type Class 3" "Strongly-ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 4.--5. " MTC2 ,Memory Type Class 2" "Strongly-ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MTC1 ,Memory Type Class 1" "Strongly-ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 0.--1. " MTC0 ,Memory Type Class 0" "Strongly-ordered,Device,Normal,?..."
|
|
group.long c15:0x012A++0x00
|
|
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x00 30.--31. " OCPC7 ,Outer Cache Policy Class 7" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 28.--29. " OCPC6 ,Outer Cache Policy Class 6" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OCPC5 ,Outer Cache Policy Class 5" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 24.--25. " OCPC4 ,Outer Cache Policy Class 4" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OCPC3 ,Outer Cache Policy Class 3" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 20.--21. " OCPC2 ,Outer Cache Policy Class 2" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OCPC1 ,Outer Cache Policy Class 1" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 16.--17. " OCPC0 ,Outer Cache Policy Class 0" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " ICPC7 ,Inner Cache Policy Class 7" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 12.--13. " ICPC6 ,Inner Cache Policy Class 6" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ICPC5 ,Inner Cache Policy Class 5" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 8.--9. " ICPC4 ,Inner Cache Policy Class 4" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICPC3 ,Inner Cache Policy Class 3" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 4.--5. " ICPC2 ,Inner Cache Policy Class 2" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ICPC1 ,Inner Cache Policy Class 1" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
bitfld.long 0x00 0.--1. " ICPC0 ,Inner Cache Policy Class 0" "Non-cacheable,Write-back/write-allocate,Write-through/no-write-allocate,Write-back/no-write-allocate"
|
|
else
|
|
group.long c15:0x002A++0x00
|
|
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
|
|
bitfld.long 0x00 28.--31. " ATTR3[7:4] ,Outer region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
bitfld.long 0x00 24.--27. " ATTR3[3:0] ,Inner region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ATTR2[7:4] ,Outer region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
bitfld.long 0x00 16.--19. " ATTR2[3:0] ,Inner region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ATTR1[7:4] ,Outer region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
bitfld.long 0x00 8.--11. " ATTR1[3:0] ,Inner region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ATTR0[7:4] ,Outer region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
bitfld.long 0x00 0.--3. " ATTR0[3:0] ,Inner region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
group.long c15:0x012A++0x00
|
|
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x00 28.--31. " ATTR7[7:4] ,Outer region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
bitfld.long 0x00 24.--27. " ATTR7[3:0] ,Inner region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ATTR6[7:4] ,Outer region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
bitfld.long 0x00 16.--19. " ATTR6[3:0] ,Inner region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ATTR5[7:4] ,Outer region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
bitfld.long 0x00 8.--11. " ATTR5[3:0] ,Inner region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ATTR4[7:4] ,Outer region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
bitfld.long 0x00 0.--3. " ATTR4[3:0] ,Inner region policy" "Reserved,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Write-through Transient,Normal memory/Non-cacheable,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-back Transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-through Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient,Normal memory/Write-back Non-transient"
|
|
endif
|
|
hgroup.long c15:0x003A++0x00
|
|
hide.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
|
|
hgroup.long c15:0x013A++0x00
|
|
hide.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
|
|
group.long c15:0x040D++0x00
|
|
line.long 0x00 "TPIDRPRW,Thread/Process ID Register - Privileged Read/Write"
|
|
group.long c15:0x030D++0x00
|
|
line.long 0x00 "TPIDRURO,Thread/Process ID Register - User Read-Only"
|
|
group.long c15:0x020D++0x00
|
|
line.long 0x00 "TPIDRURW,Thread/Process ID Register - User Read/Write"
|
|
tree.end
|
|
width 8.
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x00
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Coherency Inner Shareable" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 18.--20. " L7T ,L7 Type" "No cache,I-cache,D-cache,Separate I/D,Unified cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " L6T ,L6 Type" "No cache,I-cache,D-cache,Separate I/D,Unified cache,?..."
|
|
bitfld.long 0x00 12.--14. " L5T ,L5 Type" "No cache,I-cache,D-cache,Separate I/D,Unified cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " L4T ,L4 Type" "No cache,I-cache,D-cache,Separate I/D,Unified cache,?..."
|
|
bitfld.long 0x00 6.--8. " L3T ,L3 Type" "No cache,I-cache,D-cache,Separate I/D,Unified cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " L2T ,L2 Type" "No cache,I-cache,D-cache,Separate I/D,Unified cache,?..."
|
|
bitfld.long 0x00 0.--2. " L1T ,L1 Type" "No cache,I-cache,D-cache,Separate I/D,Unified cache,?..."
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Current Cache Size ID Registers"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " SETS ,Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000++0x00
|
|
line.long 0x00 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "1 cache,2 cache,?..."
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction"
|
|
group.long c15:0x3109++0x00
|
|
line.long 0x00 "ICCR,Instruction Cache Control Register"
|
|
bitfld.long 0x00 2.--3. " HPFQWT ,Hardware Prefetch Quadword Threshold" "Any QW,QW1 or higher,QW2 or higher,QW3"
|
|
bitfld.long 0x00 1. " DUSL1A ,Disable Unused" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DHPF ,Disable Hardware Prefetch" "No,Yes"
|
|
rgroup.long c15:0x1209++0x00
|
|
line.long 0x00 "ICRDR0,Instruction Cache Read Data Register 0"
|
|
rgroup.long c15:0x3009++0x00
|
|
line.long 0x00 "ICRDR1,Instruction Cache Read Data Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " HWX ,Half word X"
|
|
bitfld.long 0x00 12.--13. " DATAP ,Data Parity" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--11. 1. " PDCD ,Pre-decoded information"
|
|
bitfld.long 0x00 0.--3. " INST ,Instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c15:0x1009++0x00
|
|
line.long 0x00 "ICRTR0,Instruction Cache Read Tag Register 0"
|
|
bitfld.long 0x00 31. " TT ,Tag T-State" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TJ ,Tag J-State" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " NSTAG ,NS-Tag" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 8.--27. 1. " TVA ,Tag Virtual Address"
|
|
textline " "
|
|
bitfld.long 0x00 7. " UX ,User Execute permission" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PX ,Privilege Execute permission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " V ,Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " TAGP ,Tag Parity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PLRU ,PLRU" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x3309++0x00
|
|
line.long 0x00 "DCCR,Domain Cache Control Register"
|
|
bitfld.long 0x00 30.--31. " EHWPF ,Enable HW Prefetch" "Disabled,Address range based,PC based,Both"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " HWPFAC ,HW Prefetch Allocation Control" "L1 + L2,L2 and L1no RLD into L1,L2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " HWPFD ,Hardware Prefetch Distance" "Reserved,2 deltas,4 deltas,8 deltas"
|
|
bitfld.long 0x00 20. " EHWPFL1H ,Enable Hardware Prefetch on L1 Hits" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " HWPFRS ,Hardware Prefetch Range Size" "16KB,32KB,64KB,?..."
|
|
bitfld.long 0x00 16.--17. " EHWPFMST ,Enable Hardware Prefetch Minimum Stride Threshold" "Disabled,Reserved,16 bytes,32 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DL1ATM ,Disable L1 Allocation of Transient Memory" "No,Yes"
|
|
bitfld.long 0x00 12. " DSPLDR ,Disable Speculative PLD Requests" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSLDRNC ,Disable Speculative Load Requests for Non-Cacheable" "No,Yes"
|
|
bitfld.long 0x00 10. " DSLDRC ,Disable Speculative Load Requests for Cacheable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FBCTOC ,Fill Buffer Cleaning Time-Out Counter" "15 cycles,31 cycles,63 cycles,127 cycles"
|
|
bitfld.long 0x00 4.--7. " FBET ,Fill Buffer Eviction Threshold" "Normal,2 FBs,3 FBs,4 FBs,5 FBs,6 FBs,7 FBs,8 FBs,9 FBs,10 FBs,11 FBs,12 FBs,13 FBs,14 FBs,15 FBs,16 FBs"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NCBC ,Non-Cacheable Buffering Control" "Stores can gather/loads cannot gather,Both can gather,None can gather,None can gather"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PLDAC ,PLD Allocation Control" "L1 + L2,L2 and L1no RLD into L1,L2,No-op"
|
|
rgroup.long c15:0x1609++0x00
|
|
line.long 0x00 "DCRDR0,Data Cache Read Data Register 0"
|
|
rgroup.long c15:0x1409++0x00
|
|
line.long 0x00 "DCRTR0,Data Cache Read Tag Register 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " TPA ,Tag Physical Address"
|
|
bitfld.long 0x00 7. " V ,Valid" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NSTAG ,NS-Tag" "Low,High"
|
|
bitfld.long 0x00 5. " TAGP ,Tag Parity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PLRU ,PLRU" "Low,High"
|
|
bitfld.long 0x00 0.--3. " DATAP ,Data Parity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c15:0x071A++0x00
|
|
line.long 0x00 "TLBLKCR,TLB Lock Control Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TLBVIC ,TLB Victim"
|
|
hexmask.long.byte 0x00 8.--14. 1. " TLBFLOOR ,TLB Floor"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IULE ,Invalidate Unlock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BNA ,Block Normal Allocation" "Disabled,Enabled"
|
|
group.long c15:0x001A++0x00
|
|
line.long 0x00 "TLBTR0,TLB Tag Register 0 (UTLBxSW to UTLB)"
|
|
bitfld.long 0x00 27.--31. " DPSIZC ,Decoded Page Size - CAM copy" "4KB page,64KB page,Reserved,1MB section,Reserved,Reserved,Reserved,2MN section,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16MB supersection,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,1GB supersection"
|
|
textline " "
|
|
bitfld.long 0x00 22.--26. " DPSIZR ,Decoded Page Size - RAM copy" "4KB page,64KB page,Reserved,1MB section,Reserved,Reserved,Reserved,2MN section,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16MB supersection,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,1GB supersection"
|
|
textline " "
|
|
bitfld.long 0x00 21. " NG ,Not Global" "Global,Private"
|
|
bitfld.long 0x00 20. " LOCK ,Lock" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ISH ,Inner-Shareable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OSH ,Outer-Shareable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PXN ,Privileged Execute Never" "Permitted,Not permitted"
|
|
bitfld.long 0x00 16. " XN ,Execute Never" "Permitted,Not permitted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NSDESC ,NS-desc" "Secure,Non-secure"
|
|
bitfld.long 0x00 12.--14. " AP ,Access Permissions" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " WAL2 ,Write Allocate L2" "No allocate,Allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RAL2 ,Read Allocate L2" "No allocate,Allocate"
|
|
bitfld.long 0x00 5. " WTL2 ,Write-through L2" "Writeback,Write-through"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CL2 ,Cacheable L2" "Non-cacheable,Cacheable"
|
|
bitfld.long 0x00 3. " WAL1 ,Write Allocate L1" "No allocate,Allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RAL1 ,Read Allocate L1" "No allocate,Allocate"
|
|
bitfld.long 0x00 1. " WTL1 ,Write-through L1" "Writeback,Write-through"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CL1 ,Cacheable L1" "Non-cacheable,Cacheable"
|
|
group.long c15:0x011A++0x00
|
|
line.long 0x00 "TLBTR1,TLB Tag Register 1 (UTLBxSW to UTLB)"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " PA ,Physical Address"
|
|
bitfld.long 0x00 0.--3. " PA ,Physical Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long c15:0x021A++0x00
|
|
line.long 0x00 "TLBTR2,TLB Tag Register 2 (UTLBxSW to UTLB)"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " TVA ,Tag Virtual Address"
|
|
bitfld.long 0x00 10. " TNG ,Tag Not Global" "Ingored,Considereddd"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NSTID ,Non-Secure Tag ID" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " V ,Valid" "Invalid,Valid"
|
|
group.long c15:0x031A++0x00
|
|
line.long 0x00 "TLBTR3,TLB Tag Register 3 (UTLBxSW to UTLB / VA-to-PA)"
|
|
hexmask.long.byte 0x00 24.--30. 1. " V2PNDX ,VA-to-PA UTLB hit index"
|
|
bitfld.long 0x00 16. " V2PH ,VA-to-PA Hit" "Not hit,Hit"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TASID ,TASID"
|
|
group.long c15:0x024A++0x00
|
|
line.long 0x00 "CCPR,Cache Coherency Policy Register"
|
|
bitfld.long 0x00 2.--3. " L1OSHP ,L1 Outer-Shareable policy" "No forcing,Force write-through,Force non-cacheable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " L1ISHP ,L1 Inner-Shareable policy" "No forcing,Force write-through,Force non-cacheable,?..."
|
|
width 10.
|
|
tree "Level 0 memory system"
|
|
rgroup.long c15:0x2609++0x00
|
|
line.long 0x00 "L0DCRDR0,L0 Data Cache Read Data Register 0"
|
|
rgroup.long c15:0x2409++0x00
|
|
line.long 0x00 "L0DCRTR0,L0 Data Cache Read Tag Register 0"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " TVA ,Tag Virtual Address"
|
|
bitfld.long 0x00 7. " V ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 6. " NSTAG ,NS-Tag" "Disabled,Enabled"
|
|
rgroup.long c15:0x2209++0x00
|
|
line.long 0x00 "L0ICRDR0,L0 Instruction Cache Read Data Register 0"
|
|
rgroup.long c15:0x3409++0x00
|
|
line.long 0x00 "L0ICRDR1,L0 Instruction Cache Read Data Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " HWX ,HWX"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PDCD ,Pre-decoded information"
|
|
bitfld.long 0x00 0.--3. " INST ,Instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c15:0x2009++0x00
|
|
line.long 0x00 "L0ICRTR0,L0 Instruction Cache Read Tag Register 0"
|
|
bitfld.long 0x00 31. " TT ,Tag T-State" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TJ ,Tag J-State" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " NSTAG ,NS-Tag" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 8.--27. 1. " TVA ,Tag Virtual Address"
|
|
textline " "
|
|
bitfld.long 0x00 7. " UX ,User Execute permission" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PX ,Privilege Execute permission" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " V ,Valid" "Disabled,Enabled"
|
|
tree.end
|
|
width 13.
|
|
tree "Level 2 memory system"
|
|
group.long c15:0x360F++0x00
|
|
line.long 0x00 "L2CPUCPSELR,L2 CPU Coprocessor Select Register"
|
|
bitfld.long 0x00 12.--14. " CPUNDX ,CPU Index" "This CPU,Reserved,Reserved,Reserved,CPU0,CPU1,CPU2,CPU3"
|
|
bitfld.long 0x00 8.--10. " CLASSNDX ,Class Index" "L2 Control,L2 Locking,L2 Error Handling,L2 Debug,L2 Performance Monitors,L2 Power,Reserved,L2 Verification"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGNDX ,REGNDX"
|
|
group.long c15:0x370F++0x00
|
|
line.long 0x00 "L2CPUCPDR,L2 Coprocessor Data Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0508
|
|
line.long 0x00 "L2ACGCCNTR,L2 Adaptive Clock Gating Clock Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0509
|
|
line.long 0x00 "L2ACGCSR,L2 Adaptive Clock Gating Control and Status Register"
|
|
bitfld.long 0x00 18. " OVS ,Overflow Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " HS ,High-limit Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LS ,Low-limit status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ROOE ,Ring Osc Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FCE ,Frequency Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " FCCS ,Frequency Counter Clk Select" "ACG,Duplicate ACG,Core,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CCNTLKE ,Cycle Count Lock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVINT ,Averaging Interval" "8 cycles,64 cycles,512 cycles,4K cycles,32K cycles,256K cycles,2M cycles,16M cycles"
|
|
bitfld.long 0x00 3. " HIRQE ,High-limit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LIRQE ,Low-limit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOSCE ,Duplicate Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OSCE ,Oscillator Enable" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x050A
|
|
line.long 0x00 "L2ACGFCR,L2 Adaptive Clock Gating Frequency Control Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " FC ,Frequency Control"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x050B
|
|
line.long 0x00 "L2ACGHLR,L2 Adaptive Clock Gating High Limit Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x050C
|
|
line.long 0x00 "L2ACGLLR,L2 Adaptive Clock Gating Low Limit Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0500
|
|
line.long 0x00 "L2CPMR,L2 Clock and Power Management Register"
|
|
bitfld.long 0x00 21. " SSGE ,Soft Start Global Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " SSP ,Soft start period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " SSPE ,Soft Start Performance Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " L2SLPDLY ,L2 Sleep Delay" "16 cycles,64 cycles,1024 cycles,Never sleep"
|
|
bitfld.long 0x00 8.--9. " QSBSLPDLY ,QSB Port Sleep Delay" "16 cycles,64 cycles,256 cycles,Never sleep"
|
|
bitfld.long 0x00 6.--7. " PLLCLKDIV ,PLL Clock Divide" "/2,/4,/6,/8"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EL2SLPREQ ,Enable L2 Sleep Request" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SECCLKAGD ,Secondary Clock Auto Gate Disable" "No,Yes"
|
|
bitfld.long 0x00 2.--3. " SECCLKSRC ,Secondary Clock Source" "QSB,L2 PLL,L2 AUX,JTAG"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PRICLKSRC ,Primary Clock Source" "SEC,L2 PLL,L2 PLL divided,L2 ACG"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x450E
|
|
line.long 0x00 "L2CPUAVSDSCR0,L2 CPU Adaptive Voltage Scaling Delay Synthesizer Control Register 0"
|
|
hexmask.long 0x00 0.--30. 1. " AVSDSDLY ,AVS Delay Synthesizer Delay"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x550E
|
|
line.long 0x00 "L2CPUAVSDSCR1,L2 CPU Adaptive Voltage Scaling Delay Synthesizer Control Register 1"
|
|
hexmask.long 0x00 0.--30. 1. " AVSDSDLY ,AVS Delay Synthesizer Delay"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x650E
|
|
line.long 0x00 "L2CPUAVSDSCR2,L2 CPU Adaptive Voltage Scaling Delay Synthesizer Control Register 2"
|
|
hexmask.long 0x00 0.--30. 1. " AVSDSDLY ,AVS Delay Synthesizer Delay"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x750E
|
|
line.long 0x00 "L2CPUAVSDSCR3,L2 CPU Adaptive Voltage Scaling Delay Synthesizer Control Register 3"
|
|
hexmask.long 0x00 0.--30. 1. " AVSDSDLY ,AVS Delay Synthesizer Delay"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x4501
|
|
line.long 0x00 "L2CPUCPMR0,L2 CPU Clock and Power Management Register 0"
|
|
bitfld.long 0x00 21. " SSGE ,Soft Start Global Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " SSP ,Soft start period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " SSPE ,Soft Start Performance Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSHPE ,Soft Start High Performance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " LPLPLLCLKDIV ,Low Performance Level PLL Clock Divide" "/2,/4,/6,/8"
|
|
bitfld.long 0x00 10.--11. " LPLSECCLKSRC ,Low Performance Level Secondary Clock Source" "QSB,L2 PLL,APC AUX,REF"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LPLPRICLKSRC ,Low Performance Level Primary Clock Source" "SEC,APC PLL,APC PLL divided,APC ACG"
|
|
bitfld.long 0x00 6.--7. " PLLCLKDIV ,PLL Clock Divide" "/2,/4,/6,/8"
|
|
bitfld.long 0x00 2.--3. " SECCLKSRC ,Secondary Clock Source" "QSB,L2 PLL,APC AUX,JTAG"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PRICLKSRC ,Primary Clock Source" "SEC,APC PLL,APC PLL divided,APC ACG"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x5501
|
|
line.long 0x00 "L2CPUCPMR1,L2 CPU Clock and Power Management Register 1"
|
|
bitfld.long 0x00 21. " SSGE ,Soft Start Global Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " SSP ,Soft start period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " SSPE ,Soft Start Performance Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSHPE ,Soft Start High Performance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " LPLPLLCLKDIV ,Low Performance Level PLL Clock Divide" "/2,/4,/6,/8"
|
|
bitfld.long 0x00 10.--11. " LPLSECCLKSRC ,Low Performance Level Secondary Clock Source" "QSB,L2 PLL,APC AUX,REF"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LPLPRICLKSRC ,Low Performance Level Primary Clock Source" "SEC,APC PLL,APC PLL divided,APC ACG"
|
|
bitfld.long 0x00 6.--7. " PLLCLKDIV ,PLL Clock Divide" "/2,/4,/6,/8"
|
|
bitfld.long 0x00 2.--3. " SECCLKSRC ,Secondary Clock Source" "QSB,L2 PLL,APC AUX,JTAG"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PRICLKSRC ,Primary Clock Source" "SEC,APC PLL,APC PLL divided,APC ACG"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x6501
|
|
line.long 0x00 "L2CPUCPMR2,L2 CPU Clock and Power Management Register 2"
|
|
bitfld.long 0x00 21. " SSGE ,Soft Start Global Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " SSP ,Soft start period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " SSPE ,Soft Start Performance Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSHPE ,Soft Start High Performance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " LPLPLLCLKDIV ,Low Performance Level PLL Clock Divide" "/2,/4,/6,/8"
|
|
bitfld.long 0x00 10.--11. " LPLSECCLKSRC ,Low Performance Level Secondary Clock Source" "QSB,L2 PLL,APC AUX,REF"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LPLPRICLKSRC ,Low Performance Level Primary Clock Source" "SEC,APC PLL,APC PLL divided,APC ACG"
|
|
bitfld.long 0x00 6.--7. " PLLCLKDIV ,PLL Clock Divide" "/2,/4,/6,/8"
|
|
bitfld.long 0x00 2.--3. " SECCLKSRC ,Secondary Clock Source" "QSB,L2 PLL,APC AUX,JTAG"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PRICLKSRC ,Primary Clock Source" "SEC,APC PLL,APC PLL divided,APC ACG"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x7501
|
|
line.long 0x00 "L2CPUCPMR3,L2 CPU Clock and Power Management Register 3"
|
|
bitfld.long 0x00 21. " SSGE ,Soft Start Global Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " SSP ,Soft start period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " SSPE ,Soft Start Performance Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSHPE ,Soft Start High Performance Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 14.--15. " LPLPLLCLKDIV ,Low Performance Level PLL Clock Divide" "/2,/4,/6,/8"
|
|
bitfld.long 0x00 10.--11. " LPLSECCLKSRC ,Low Performance Level Secondary Clock Source" "QSB,L2 PLL,APC AUX,REF"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LPLPRICLKSRC ,Low Performance Level Primary Clock Source" "SEC,APC PLL,APC PLL divided,APC ACG"
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|
bitfld.long 0x00 6.--7. " PLLCLKDIV ,PLL Clock Divide" "/2,/4,/6,/8"
|
|
bitfld.long 0x00 2.--3. " SECCLKSRC ,Secondary Clock Source" "QSB,L2 PLL,APC AUX,JTAG"
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|
textline " "
|
|
bitfld.long 0x00 0.--1. " PRICLKSRC ,Primary Clock Source" "SEC,APC PLL,APC PLL divided,APC ACG"
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|
group.long c15:0x370F++0x00
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|
saveout c15:0x360F %l 0x0004
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|
line.long 0x00 "L2CPUCR,L2 CPU Control Register"
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|
bitfld.long 0x00 10. " ETRANSIENT ,Enable Transient Attribute CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FINCL ,Force I-side Non-cacheable Lookup" "Not forced,Forced"
|
|
bitfld.long 0x00 8. " DSF ,Disable Snoop Filtering" "No,Yes"
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|
textline " "
|
|
bitfld.long 0x00 6. " IPFECA ,I-side Prefetch Enable Cacheable Allocating" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DPFECA ,D-side Prefetch Enable Cacheable Allocating" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FWNAL2PG ,Force Write-No-Allocate L2 Partial Granule" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FWNAL2 ,Force Write No-allocate L2" "Not forced,Forced"
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|
bitfld.long 0x00 2. " FWAL2 ,Force Write-allocate L2" "Not forced,Forced"
|
|
bitfld.long 0x00 1. " FRNAL2D ,Force Read No-allocate L2 D-side" "Not forced,Forced"
|
|
textline " "
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bitfld.long 0x00 0. " FRNAL2I ,Force Read No-allocate L2 I-side" "Not forced,Forced"
|
|
group.long c15:0x370F++0x00
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saveout c15:0x360F %l 0x0000
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line.long 0x00 "L2CR0,L2 Control Register 0"
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bitfld.long 0x00 28. " ETRANSIENTSP ,Enable Transient Attribute from Slave Port" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " FWNAL2PGSP ,Force Write-No-Allocate L2 Partial Granule Slave Port" "Not forced,Forced"
|
|
bitfld.long 0x00 26. " FRNAL2SP ,Force Read No L2 Allocate Slave Port" "Not forced,Forced"
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|
textline " "
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bitfld.long 0x00 25. " FWNAL2SP ,Force Write No Allocate L2 Slave port" "Not forced,Forced"
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|
bitfld.long 0x00 24. " FWAL2SP ,Force Write Allocate L2 Slave Port" "Not forced,Forced"
|
|
bitfld.long 0x00 15. " CORSIZE ,Castout Request Size" "64 bytes,128 bytes"
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textline " "
|
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bitfld.long 0x00 13. " SPLDREXCFG ,Slave Port LDREX Config" "L2EM,Normal OK"
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bitfld.long 0x00 11. " FIOSODV ,Force In-Order SO/DV requests" "Not forced,Forced"
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bitfld.long 0x00 9. " L2PRRA ,L2 Pseudo Random Replacement Alogrithm" "Algorithm 0,Algorithm 1"
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textline " "
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bitfld.long 0x00 8. " L2LRP ,L2 Line Replacement Policy" "Round robin,Pseudo random"
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bitfld.long 0x00 6.--7. " L2DAC ,L2 Data Access Cycles" "2 cycles,3 cycles,4 cycles,?..."
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|
bitfld.long 0x00 4.--5. " L2TAC ,L2 Tag Access Cycles" "2 cycles,3 cycles,4 cycles,?..."
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textline " "
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bitfld.long 0x00 3. " WACO ,Write-Allocate for Castout" "Write-no-allocate,Write allocate"
|
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textline " "
|
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bitfld.long 0x00 2. " QSBMPRBNDXE ,QSB Master Port Read Beat Index Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 1. " QSBMPOOOWRE ,QSB Master Port OOO Write Response Enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " QSBMPOOORDE ,QSB Master Port OOO Read Data Enable" "Disabled,Enabled"
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rgroup.long c15:0x370F++0x00
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saveout c15:0x360F %l 0x0300
|
|
line.long 0x00 "L2DCRDR0,L2 D-Cache Read Data Register 0"
|
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rgroup.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0301
|
|
line.long 0x00 "L2DCRDR1,L2 D-Cache Read Data Register 1"
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rgroup.long c15:0x370F++0x00
|
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saveout c15:0x360F %l 0x0302
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line.long 0x00 "L2DCRTR0,L2 D-Cache Read Tag Register 0"
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bitfld.long 0x00 29.--31. " RR ,Round-Robin" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 28. " LK ,Lock" "Not locked,Locked"
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bitfld.long 0x00 14.--15. " V ,Valid" "0,1,2,3"
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|
textline " "
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bitfld.long 0x00 12.--13. " MODC ,Modified (copy C)" "No dirty granules,Least significant,Most significant,Both"
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|
textline " "
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bitfld.long 0x00 10.--11. " MODB ,Modified (copy B)" "No dirty granules,Least significant,Most significant,Both"
|
|
textline " "
|
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bitfld.long 0x00 8.--9. " MODA ,Modified (copy A)" "No dirty granules,Least significant,Most significant,Both"
|
|
textline " "
|
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hexmask.long.byte 0x00 0.--7. 1. " DECC ,Data Error Correction Code"
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rgroup.long c15:0x370F++0x00
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saveout c15:0x360F %l 0x0303
|
|
line.long 0x00 "L2DCRTR1,L2 D-Cache Read Tag Register 1"
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|
hexmask.long.tbyte 0x00 11.--31. 0x8 " TPA ,Tag Physical Address"
|
|
bitfld.long 0x00 10. " NS ,Non-Secure" "Secure,Non-secure"
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bitfld.long 0x00 4.--9. " TECC ,Tag Error Correction Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
textline " "
|
|
bitfld.long 0x00 0.--3. " TPA ,Tag Physical Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x020C
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|
line.long 0x00 "L2EAR0,L2 Error Address Register 0"
|
|
rgroup.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x020D
|
|
line.long 0x00 "L2EAR1,L2 Error Address Register 1"
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|
bitfld.long 0x00 0.--3. " PA ,Physical Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0200
|
|
line.long 0x00 "L2ECR,L2 Error Control Register"
|
|
bitfld.long 0x00 19. " DSEDBSPERE ,Data Soft Error Double Bit Slave Port Error Report Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 18. " TSEDBSPERE ,Tag Soft Error Double Bit Slave Port Error Report Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 17. " MPSLVSPERE ,Master Port Slave Error Slave Port Error Report Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MPDCDSPERE ,Master Port Decode Error Slave Port Error Report Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SPEMNAVRE ,Slave Port Exclusive Monitor Not Available Record Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 14. " SEDE ,Soft Error Detect Enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x00 13. " DCREADSECE ,DCREAD Soft Error Correct Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MPLDREXNOKIE ,Master Port LDREX Normal OK Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SPEMNAVIE ,Slave Port Exclusive Monitor Not Available Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MSEIE ,Modified Soft Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DSEDBIE ,Data Soft Error Double Bit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DSESBIE ,Data Soft Error Single Bit Interrupt Enable" "Disabled,Enabled"
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|
textline " "
|
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bitfld.long 0x00 3. " TSEDBIE ,Tag Soft Error Double Bit Interrupt Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 2. " TSESBIE ,Tag Soft Error Single Bit Interrupt Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 1. " MPSLVIE ,Master Port Slave Error Interrupt Enable" "Disabled,Enabled"
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|
textline " "
|
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bitfld.long 0x00 0. " MPDCDIE ,Master Port Decode Error Interrupt Enable" "Disabled,Enabled"
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group.long c15:0x370F++0x00
|
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saveout c15:0x360F %l 0x0204
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line.long 0x00 "L2ESR,L2 Error Status Register"
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eventfld.long 0x00 22. " CASTOUT ,Castout" "No error,Error"
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eventfld.long 0x00 20. " SP ,Slave Port" "No error,Error"
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eventfld.long 0x00 19. " CPU[3] ,CPU 3" "No error,Error"
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textline " "
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eventfld.long 0x00 18. " CPU[2] ,CPU 2" "No error,Error"
|
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eventfld.long 0x00 17. " CPU[1] ,CPU 1" "No error,Error"
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eventfld.long 0x00 16. " CPU[0] ,CPU 0" "No error,Error"
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textline " "
|
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eventfld.long 0x00 8. " MPLDREXNOK ,Master Port LDREX Normal OK" "No error,Error"
|
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eventfld.long 0x00 7. " SPEMNAV ,Slave Port Exclusive Monitor Not Available" "No error,Error"
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eventfld.long 0x00 6. " MSE ,Modified Soft Error" "No error,Error"
|
|
textline " "
|
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eventfld.long 0x00 5. " DSEDB ,Data Soft Error Double Bit" "No error,Error"
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eventfld.long 0x00 4. " DSESB ,Data Soft Error Single Bit" "No error,Error"
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eventfld.long 0x00 3. " TSEDB ,Tag Soft Error Double Bit" "No error,Error"
|
|
textline " "
|
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eventfld.long 0x00 2. " TSESB ,Tag Soft Error Single Bit" "No error,Error"
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eventfld.long 0x00 1. " MPSLV ,Master Port Slave Error" "No error,Error"
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eventfld.long 0x00 0. " MPDCD ,Master Port Decode Error" "No error,Error"
|
|
wgroup.long c15:0x370F++0x00
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saveout c15:0x360F %l 0x0205
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line.long 0x00 "L2ESRS,L2 Error Status Register Set"
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bitfld.long 0x00 22. " CASTOUT ,Castout" "No effect,Set"
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bitfld.long 0x00 20. " SP ,Slave Port" "No effect,Set"
|
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bitfld.long 0x00 19. " CPU[3] ,CPU 3" "No effect,Set"
|
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textline " "
|
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bitfld.long 0x00 18. " CPU[2] ,CPU 2" "No effect,Set"
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bitfld.long 0x00 17. " CPU[1] ,CPU 1" "No effect,Set"
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bitfld.long 0x00 16. " CPU[0] ,CPU 0" "No effect,Set"
|
|
textline " "
|
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bitfld.long 0x00 8. " MPLDREXNOK ,Master Port LDREX Normal OK" "No effect,Set"
|
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bitfld.long 0x00 7. " SPEMNAV ,Slave Port Exclusive Monitor Not Available" "No effect,Set"
|
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bitfld.long 0x00 6. " MSE ,Modified Soft Error" "No effect,Set"
|
|
textline " "
|
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bitfld.long 0x00 5. " DSEDB ,Data Soft Error Double Bit" "No effect,Set"
|
|
bitfld.long 0x00 4. " DSESB ,Data Soft Error Single Bit" "No effect,Set"
|
|
bitfld.long 0x00 3. " TSEDB ,Tag Soft Error Double Bit" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TSESB ,Tag Soft Error Single Bit" "No effect,Set"
|
|
bitfld.long 0x00 1. " MPSLV ,Master Port Slave Error" "No effect,Set"
|
|
bitfld.long 0x00 0. " MPDCD ,Master Port Decode Error" "No effect,Set"
|
|
rgroup.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0208
|
|
line.long 0x00 "L2ESYNR0,L2 Error Syndrome Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATID ,Address Channel Transaction ID"
|
|
bitfld.long 0x00 13.--15. " ABID ,Address Channel Bus ID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " APID ,Address Channel Port ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " AMID ,Address Channel Master ID"
|
|
rgroup.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0209
|
|
line.long 0x00 "L2ESYNR1,L2 Error Syndrome Register 1"
|
|
bitfld.long 0x00 28. " MWSE ,Multi-Way Soft Error" "No error,Error"
|
|
bitfld.long 0x00 25.--27. " SEWAYNDX ,Soft Error Way Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. " AFULL ,QSB AFULL attribute" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AOOORD ,Out-Of-Order Read attribute" "Low,High"
|
|
bitfld.long 0x00 22. " AOOOWR ,Out-Of-Order Write attribute" "Low,High"
|
|
bitfld.long 0x00 21. " AEXCLUSIVE ,QSB Exclusive attribute" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ARDBEATNDXEN ,QSB Rd Beat Index Enable attribute" "Low,High"
|
|
bitfld.long 0x00 16.--18. " ASIZE ,QSB Size attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. " ALEN ,QSB Length attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABURST ,QSB Burst attribute" "Low,High"
|
|
bitfld.long 0x00 9. " ANOALLOCATE ,ANOALLOCATE" "Low,High"
|
|
bitfld.long 0x00 8. " AWRITE ,QSB Write (not read) attribute" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AINST ,QSB Instruction attribute" "Low,High"
|
|
bitfld.long 0x00 6. " APROTNS ,QSB NS-prot attribute" "Low,High"
|
|
bitfld.long 0x00 5. " APRIV ,QSB Privileged attribute" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AINNERSHARED ,QSB Inner-Shareable attribute" "Low,High"
|
|
bitfld.long 0x00 3. " ASHARED ,QSB Shareable attribute" "Low,High"
|
|
bitfld.long 0x00 0.--2. " AMEMTYPE ,QSB Memory Type attribute" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0100
|
|
line.long 0x00 "L2LKCR,L2 Locking Control Register"
|
|
bitfld.long 0x00 4. " LKLCE ,Locked Line Clean Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " LKE[3] ,Lock Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LKE[2] ,Lock Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LKE[1] ,Lock Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LKE[0] ,Lock Enable 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0008
|
|
line.long 0x00 "L2MPCR,L2 Multi-Processing Control Register"
|
|
bitfld.long 0x00 25. " FWTL2NSH ,Force Write-Through L2 Non-Shareable" "Not forced,Forced"
|
|
bitfld.long 0x00 24. " FNCL2NSH ,Force Non-Cacheable L2 Non-Shareable" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " FWTL2ISH ,Force Write-Through L2 Inner-Shareable" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FNCL2ISH ,Force Non-Cacheable L2 Inner-Shareable" "Not forced,Forced"
|
|
bitfld.long 0x00 21. " FWTL2OSH ,Force Write-Through L2 Outer-Shareable" "Not forced,Forced"
|
|
bitfld.long 0x00 20. " FNCL2OSH ,Force Non-Cacheable L2 Outer-Shareable" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ISHBWWTW ,ISH Barriers Wait for Write-Through Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OSHBWWTW ,OSH Barriers Wait for Write-Through Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MISHSP ,Member Inner-Shareable Slave Port" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MOSHSP ,Member Outer-Shareable Slave Port" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MISHCPU[3] ,Member Inner-Sharable CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MISHCPU[2] ,Member Inner-Sharable CPU 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MISHCPU[1] ,Member Inner-Sharable CPU 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MISHCPU[0] ,Member Inner-Sharable CPU 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MOSHCPU[3] ,Member Outer-Shareable CPU 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MOSHCPU[2] ,Member Outer-Shareable CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MOSHCPU[1] ,Member Outer-Shareable CPU 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOSHCPU[0] ,Member Outer-Shareable CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0408
|
|
line.long 0x00 "L2PMCCNTCR,L2 Performance Monitor Cycle Count Control Register"
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0409
|
|
line.long 0x00 "L2PMCCNTR,L2 Performance Monitor Cycle Count Register"
|
|
rgroup.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x040A
|
|
line.long 0x00 "L2PMCCNTSR,L2 Performance Monitor Cycle Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Cycle counter state" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0402
|
|
line.long 0x00 "L2PMCNTENCLR,L2 Performance Monitor Count Enable Clear"
|
|
eventfld.long 0x00 31. " CCNT ,L2PMCCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " EVC7 ,L2PM7EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " EVC6 ,L2PM6EVCNTR enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 5. " EVC5 ,L2PM5EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " EVC4 ,L2PM4EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " EVC3 ,L2PM3EVCNTR enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EVC2 ,L2PM2EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " EVC1 ,L2PM1EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " EVC0 ,L2PM0EVCNTR enable" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0403
|
|
line.long 0x00 "L2PMCNTENSET,L2 Performance Monitor Count Enable Set"
|
|
bitfld.long 0x00 31. " CCNT ,L2PMCCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EVC7 ,L2PM7EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EVC6 ,L2PM6EVCNTR enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVC5 ,L2PM5EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EVC4 ,L2PM4EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EVC3 ,L2PM3EVCNTR enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EVC2 ,L2PM2EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EVC1 ,L2PM1EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EVC0 ,L2PM0EVCNTR enable" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0400
|
|
line.long 0x00 "L2PMCR,L2 Performance Monitor Control Register"
|
|
bitfld.long 0x00 11.--15. " NEVC ,Number of Event Counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DCCNTPR ,Disable PMCCNTR when prohibited" "No,Yes"
|
|
bitfld.long 0x00 4. " GTEVE ,Global Trace Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKDIV ,Clock Divider" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CCNTRST ,Cycle Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " EVCRST ,Event Counter Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GEN ,Global Enable" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x410
|
|
line.long 0x00 "L2PMRESR0,L2 Performance Monitor Region Event Select Register 0"
|
|
bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GRP3SEL ,Group 3 local event select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GRP2SEL ,Group 2 local event select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GRP1SEL ,Group 1 local event select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GRP0SEL ,Group 0 local event select"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x411
|
|
line.long 0x00 "L2PMRESR1,L2 Performance Monitor Region Event Select Register 1"
|
|
bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GRP3SEL ,Group 3 local event select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GRP2SEL ,Group 2 local event select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GRP1SEL ,Group 1 local event select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GRP0SEL ,Group 0 local event select"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x412
|
|
line.long 0x00 "L2PMRESR2,L2 Performance Monitor Region Event Select Register 2"
|
|
bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GRP3SEL ,Group 3 local event select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GRP2SEL ,Group 2 local event select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GRP1SEL ,Group 1 local event select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GRP0SEL ,Group 0 local event select"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x413
|
|
line.long 0x00 "L2PMRESR3,L2 Performance Monitor Region Event Select Register 3"
|
|
bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GRP3SEL ,Group 3 local event select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GRP2SEL ,Group 2 local event select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GRP1SEL ,Group 1 local event select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GRP0SEL ,Group 0 local event select"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x414
|
|
line.long 0x00 "L2PMRESR4,L2 Performance Monitor Region Event Select Register 4"
|
|
bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GRP3SEL ,Group 3 local event select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GRP2SEL ,Group 2 local event select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GRP1SEL ,Group 1 local event select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GRP0SEL ,Group 0 local event select"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0404
|
|
line.long 0x00 "L2PMINTENCLR,L2 Performance Monitor Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 31. " CCNT ,L2PMCCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EVC7 ,L2PM7EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EVC6 ,L2PM6EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVC5 ,L2PM5EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EVC4 ,L2PM4EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EVC3 ,L2PM3EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EVC2 ,L2PM2EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EVC1 ,L2PM1EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EVC0 ,L2PM0EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0405
|
|
line.long 0x00 "L2PMINTENSET,L2 Performance Monitor Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " CCNT ,L2PMCCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EVC7 ,L2PM7EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EVC6 ,L2PM6EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVC5 ,L2PM5EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EVC4 ,L2PM4EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EVC3 ,L2PM3EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EVC2 ,L2PM2EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EVC1 ,L2PM1EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EVC0 ,L2PM0EVCNTR interrupt request enable" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0407
|
|
line.long 0x00 "L2PMOVSSET,L2 Performance Monitor Overflow Status Set Register"
|
|
bitfld.long 0x00 31. " CCNT ,L2PMCCNTR overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 7. " EVC7 ,L2PM7EVCNTR overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " EVC6 ,L2PM6EVCNTR overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVC5 ,L2PM5EVCNTR overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 4. " EVC4 ,L2PM4EVCNTR overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " EVC3 ,L2PM3EVCNTR overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EVC2 ,L2PM2EVCNTR overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 1. " EVC1 ,L2PM1EVCNTR overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 0. " EVC0 ,L2PM0EVCNTR overflow" "No overflow,Overflow"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0406
|
|
line.long 0x00 "L2PMOVSR,L2 Performance Monitor Overflow Status Register"
|
|
eventfld.long 0x00 31. " CCNT ,L2PMCCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 7. " EVC7 ,L2PM7EVCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 6. " EVC6 ,L2PM6EVCNTR overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 5. " EVC5 ,L2PM5EVCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. " EVC4 ,L2PM4EVCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " EVC3 ,L2PM3EVCNTR overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EVC2 ,L2PM2EVCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " EVC1 ,L2PM1EVCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " EVC0 ,L2PM0EVCNTR overflow" "No overflow,Overflow"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x0401
|
|
line.long 0x00 "L2PMRLDR,L2 Performance Monitor Reload Register"
|
|
tree "Performance Monitor 0"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x420
|
|
line.long 0x00 "L2PM0EVCNTCR,L2 Performance Monitor 0 Event Count Control Register"
|
|
bitfld.long 0x00 30.--31. " TEVSEL ,Trace events select" "No events,L2PMXEVTYPER[EVTYPE],L2PMOVSR[EVx],L2PMOVSR[CCNT]"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x420+0x1)
|
|
line.long 0x00 "L2PM0EVCNTR,L2 Performance Monitor 0 Event Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x420+0x2)
|
|
line.long 0x00 "L2PM0EVCNTSR,L2 Performance Monitor 0 Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x420+0x3)
|
|
line.long 0x00 "L2PM0EVFILTER,L2 Performance Monitor 0 Event Filter"
|
|
bitfld.long 0x00 19. " SUFILTER3 ,Sub-Unit Filter 4 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SUFILTER2 ,Sub-Unit Filter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SUFILTER1 ,Sub-Unit Filter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUFILTER0 ,Sub-Unit Filter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ORGFILTER5 ,Origin Filter ID Independent Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ORGFILTER4 ,Origin Filter external master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORGFILTER3 ,Origin Filter CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ORGFILTER2 ,Origin Filter CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ORGFILTER1 ,Origin Filter CPU 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ORGFILTER0 ,Origin Filter CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x420+0x4)
|
|
line.long 0x00 "L2PM0EVTYPER,L2 Performance Monitor 0 Event Type Filter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event Number"
|
|
tree.end
|
|
tree "Performance Monitor 1"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x430
|
|
line.long 0x00 "L2PM1EVCNTCR,L2 Performance Monitor 1 Event Count Control Register"
|
|
bitfld.long 0x00 30.--31. " TEVSEL ,Trace events select" "No events,L2PMXEVTYPER[EVTYPE],L2PMOVSR[EVx],L2PMOVSR[CCNT]"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x430+0x1)
|
|
line.long 0x00 "L2PM1EVCNTR,L2 Performance Monitor 1 Event Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x430+0x2)
|
|
line.long 0x00 "L2PM1EVCNTSR,L2 Performance Monitor 1 Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x430+0x3)
|
|
line.long 0x00 "L2PM1EVFILTER,L2 Performance Monitor 1 Event Filter"
|
|
bitfld.long 0x00 19. " SUFILTER3 ,Sub-Unit Filter 4 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SUFILTER2 ,Sub-Unit Filter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SUFILTER1 ,Sub-Unit Filter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUFILTER0 ,Sub-Unit Filter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ORGFILTER5 ,Origin Filter ID Independent Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ORGFILTER4 ,Origin Filter external master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORGFILTER3 ,Origin Filter CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ORGFILTER2 ,Origin Filter CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ORGFILTER1 ,Origin Filter CPU 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ORGFILTER0 ,Origin Filter CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x430+0x4)
|
|
line.long 0x00 "L2PM1EVTYPER,L2 Performance Monitor 1 Event Type Filter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event Number"
|
|
tree.end
|
|
tree "Performance Monitor 2"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x440
|
|
line.long 0x00 "L2PM2EVCNTCR,L2 Performance Monitor 2 Event Count Control Register"
|
|
bitfld.long 0x00 30.--31. " TEVSEL ,Trace events select" "No events,L2PMXEVTYPER[EVTYPE],L2PMOVSR[EVx],L2PMOVSR[CCNT]"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x440+0x1)
|
|
line.long 0x00 "L2PM2EVCNTR,L2 Performance Monitor 2 Event Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x440+0x2)
|
|
line.long 0x00 "L2PM2EVCNTSR,L2 Performance Monitor 2 Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x440+0x3)
|
|
line.long 0x00 "L2PM2EVFILTER,L2 Performance Monitor 2 Event Filter"
|
|
bitfld.long 0x00 19. " SUFILTER3 ,Sub-Unit Filter 4 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SUFILTER2 ,Sub-Unit Filter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SUFILTER1 ,Sub-Unit Filter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUFILTER0 ,Sub-Unit Filter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ORGFILTER5 ,Origin Filter ID Independent Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ORGFILTER4 ,Origin Filter external master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORGFILTER3 ,Origin Filter CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ORGFILTER2 ,Origin Filter CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ORGFILTER1 ,Origin Filter CPU 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ORGFILTER0 ,Origin Filter CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x440+0x4)
|
|
line.long 0x00 "L2PM2EVTYPER,L2 Performance Monitor 2 Event Type Filter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event Number"
|
|
tree.end
|
|
tree "Performance Monitor 3"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x450
|
|
line.long 0x00 "L2PM3EVCNTCR,L2 Performance Monitor 3 Event Count Control Register"
|
|
bitfld.long 0x00 30.--31. " TEVSEL ,Trace events select" "No events,L2PMXEVTYPER[EVTYPE],L2PMOVSR[EVx],L2PMOVSR[CCNT]"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x450+0x1)
|
|
line.long 0x00 "L2PM3EVCNTR,L2 Performance Monitor 3 Event Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x450+0x2)
|
|
line.long 0x00 "L2PM3EVCNTSR,L2 Performance Monitor 3 Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x450+0x3)
|
|
line.long 0x00 "L2PM3EVFILTER,L2 Performance Monitor 3 Event Filter"
|
|
bitfld.long 0x00 19. " SUFILTER3 ,Sub-Unit Filter 4 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SUFILTER2 ,Sub-Unit Filter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SUFILTER1 ,Sub-Unit Filter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUFILTER0 ,Sub-Unit Filter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ORGFILTER5 ,Origin Filter ID Independent Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ORGFILTER4 ,Origin Filter external master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORGFILTER3 ,Origin Filter CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ORGFILTER2 ,Origin Filter CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ORGFILTER1 ,Origin Filter CPU 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ORGFILTER0 ,Origin Filter CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x450+0x4)
|
|
line.long 0x00 "L2PM3EVTYPER,L2 Performance Monitor 3 Event Type Filter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event Number"
|
|
tree.end
|
|
tree "Performance Monitor 4"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x460
|
|
line.long 0x00 "L2PM4EVCNTCR,L2 Performance Monitor 4 Event Count Control Register"
|
|
bitfld.long 0x00 30.--31. " TEVSEL ,Trace events select" "No events,L2PMXEVTYPER[EVTYPE],L2PMOVSR[EVx],L2PMOVSR[CCNT]"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x460+0x1)
|
|
line.long 0x00 "L2PM4EVCNTR,L2 Performance Monitor 4 Event Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x460+0x2)
|
|
line.long 0x00 "L2PM4EVCNTSR,L2 Performance Monitor 4 Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x460+0x3)
|
|
line.long 0x00 "L2PM4EVFILTER,L2 Performance Monitor 4 Event Filter"
|
|
bitfld.long 0x00 19. " SUFILTER3 ,Sub-Unit Filter 4 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SUFILTER2 ,Sub-Unit Filter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SUFILTER1 ,Sub-Unit Filter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUFILTER0 ,Sub-Unit Filter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ORGFILTER5 ,Origin Filter ID Independent Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ORGFILTER4 ,Origin Filter external master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORGFILTER3 ,Origin Filter CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ORGFILTER2 ,Origin Filter CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ORGFILTER1 ,Origin Filter CPU 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ORGFILTER0 ,Origin Filter CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x460+0x4)
|
|
line.long 0x00 "L2PM4EVTYPER,L2 Performance Monitor 4 Event Type Filter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event Number"
|
|
tree.end
|
|
tree "Performance Monitor 5"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x470
|
|
line.long 0x00 "L2PM5EVCNTCR,L2 Performance Monitor 5 Event Count Control Register"
|
|
bitfld.long 0x00 30.--31. " TEVSEL ,Trace events select" "No events,L2PMXEVTYPER[EVTYPE],L2PMOVSR[EVx],L2PMOVSR[CCNT]"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x470+0x1)
|
|
line.long 0x00 "L2PM5EVCNTR,L2 Performance Monitor 5 Event Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x470+0x2)
|
|
line.long 0x00 "L2PM5EVCNTSR,L2 Performance Monitor 5 Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x470+0x3)
|
|
line.long 0x00 "L2PM5EVFILTER,L2 Performance Monitor 5 Event Filter"
|
|
bitfld.long 0x00 19. " SUFILTER3 ,Sub-Unit Filter 4 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SUFILTER2 ,Sub-Unit Filter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SUFILTER1 ,Sub-Unit Filter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUFILTER0 ,Sub-Unit Filter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ORGFILTER5 ,Origin Filter ID Independent Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ORGFILTER4 ,Origin Filter external master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORGFILTER3 ,Origin Filter CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ORGFILTER2 ,Origin Filter CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ORGFILTER1 ,Origin Filter CPU 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ORGFILTER0 ,Origin Filter CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x470+0x4)
|
|
line.long 0x00 "L2PM5EVTYPER,L2 Performance Monitor 5 Event Type Filter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event Number"
|
|
tree.end
|
|
tree "Performance Monitor 6"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x480
|
|
line.long 0x00 "L2PM6EVCNTCR,L2 Performance Monitor 6 Event Count Control Register"
|
|
bitfld.long 0x00 30.--31. " TEVSEL ,Trace events select" "No events,L2PMXEVTYPER[EVTYPE],L2PMOVSR[EVx],L2PMOVSR[CCNT]"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x480+0x1)
|
|
line.long 0x00 "L2PM6EVCNTR,L2 Performance Monitor 6 Event Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x480+0x2)
|
|
line.long 0x00 "L2PM6EVCNTSR,L2 Performance Monitor 6 Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x480+0x3)
|
|
line.long 0x00 "L2PM6EVFILTER,L2 Performance Monitor 6 Event Filter"
|
|
bitfld.long 0x00 19. " SUFILTER3 ,Sub-Unit Filter 4 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SUFILTER2 ,Sub-Unit Filter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SUFILTER1 ,Sub-Unit Filter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUFILTER0 ,Sub-Unit Filter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ORGFILTER5 ,Origin Filter ID Independent Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ORGFILTER4 ,Origin Filter external master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORGFILTER3 ,Origin Filter CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ORGFILTER2 ,Origin Filter CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ORGFILTER1 ,Origin Filter CPU 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ORGFILTER0 ,Origin Filter CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x480+0x4)
|
|
line.long 0x00 "L2PM6EVTYPER,L2 Performance Monitor 6 Event Type Filter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event Number"
|
|
tree.end
|
|
tree "Performance Monitor 7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x490
|
|
line.long 0x00 "L2PM7EVCNTCR,L2 Performance Monitor 7 Event Count Control Register"
|
|
bitfld.long 0x00 30.--31. " TEVSEL ,Trace events select" "No events,L2PMXEVTYPER[EVTYPE],L2PMOVSR[EVx],L2PMOVSR[CCNT]"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
bitfld.long 0x00 15. " SAOV ,Stop All Counters on Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x490+0x1)
|
|
line.long 0x00 "L2PM7EVCNTR,L2 Performance Monitor 7 Event Count Register"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x490+0x2)
|
|
line.long 0x00 "L2PM7EVCNTSR,L2 Performance Monitor 7 Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x490+0x3)
|
|
line.long 0x00 "L2PM7EVFILTER,L2 Performance Monitor 7 Event Filter"
|
|
bitfld.long 0x00 19. " SUFILTER3 ,Sub-Unit Filter 4 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SUFILTER2 ,Sub-Unit Filter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SUFILTER1 ,Sub-Unit Filter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUFILTER0 ,Sub-Unit Filter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ORGFILTER5 ,Origin Filter ID Independent Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ORGFILTER4 ,Origin Filter external master" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORGFILTER3 ,Origin Filter CPU 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ORGFILTER2 ,Origin Filter CPU 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ORGFILTER1 ,Origin Filter CPU 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ORGFILTER0 ,Origin Filter CPU 0" "Disabled,Enabled"
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l (0x490+0x4)
|
|
line.long 0x00 "L2PM7EVTYPER,L2 Performance Monitor 7 Event Type Filter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event Number"
|
|
tree.end
|
|
group.long c15:0x370F++0x00
|
|
saveout c15:0x360F %l 0x050D
|
|
line.long 0x00 "L2ROCR,L2 Ring Oscillator Control Register"
|
|
bitfld.long 0x00 4.--6. " ROSITE ,Ring Oscillator Site" "CPU 0,CPU 1,CPU 2,CPU 3,L2 always-on domain,L2 head-switched domain site 0,L2 head-switched domain site 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " ROTYPE ,Ring Oscillator Type" "NVT/30nm/gate delay,NVT/40nm/gate delay,LVT/30nm/gate delay,LVT/40nm/gate delay,LVT/30nm/gate+wire delay,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROE ,Ring Oscillator Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree.end
|
|
width 11.
|
|
tree "System Timer Register"
|
|
group.long c15:0x000E++0x00
|
|
line.long 0x00 "CNTFRQ,Counter Frequency Register"
|
|
group.quad c15:0x100E0++0x01
|
|
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
|
|
group.long c15:0x001E++0x00
|
|
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
|
|
bitfld.long 0x00 9. " PL0PTEN ,PL0 mode Physical Timer access Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PL0VTEN ,PL0 mode Virtual Timer access Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " EVNTI ,Event Trigger" "0,1,2,3,4,5,6,7,..."
|
|
bitfld.long 0x00 3. " EVNTDIR ,Event Trigger Direction" "0 to 1,1 to 0"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EVNTEN ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PL0VCTEN ,PL0 Virtual Counter access Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PL0PCTEN ,PL0 Physical Counter access Enable" "Disabled,Enabled"
|
|
group.long c15:0x002E++0x00
|
|
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register"
|
|
group.long c15:0x012E++0x00
|
|
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable" "Disabled,Enabled"
|
|
group.long c15:0x003E++0x00
|
|
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
|
|
group.long c15:0x013E++0x00
|
|
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable" "Disabled,Enabled"
|
|
group.quad c15:0x110E0++0x01
|
|
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
|
|
group.quad c15:0x120E0++0x01
|
|
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
|
|
group.quad c15:0x130E0++0x01
|
|
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0x00C9++0x00
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " NEVC ,Number of Event Counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DCCNTPR ,Disable CCNT when prohibited" "No,Yes"
|
|
bitfld.long 0x00 4. " GEE ,Global Export Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CLKDIV ,Cycle Counter Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCNTRST ,Cycle Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " EVCRST ,Event Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " GEN ,Global Enable" "Disabled,Enabled"
|
|
group.long c15:0x01C9++0x00
|
|
line.long 0x00 "PMCNTENSET,Performance Monitor Count Enable Set Register"
|
|
bitfld.long 0x00 31. " CCNT ,PMCCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EVC3 ,PM3EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EVC2 ,PM2EVCNTR enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVC1 ,PM1EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EVC0 ,PM0EVCNTR enable" "Disabled,Enabled"
|
|
group.long c15:0x02C9++0x00
|
|
line.long 0x00 "PMCNTENCLR,Performance Monitor Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " CCNT ,PMCCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " EVC3 ,PM3EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " EVC2 ,PM2EVCNTR enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EVC1 ,PM1EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " EVC0 ,PM0EVCNTR enable" "Disabled,Enabled"
|
|
group.long c15:0x03C9++0x00
|
|
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
|
|
eventfld.long 0x00 31. " CCNT ,PMCCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " EVC3 ,PM3EVCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " EVC2 ,PM2EVCNTR overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EVC1 ,PM1EVCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " EVC0 ,PM0EVCNTR overflow" "No overflow,Overflow"
|
|
group.long c15:0x05C9++0x00
|
|
line.long 0x00 "PMSELR,Performance Monitor Select Register"
|
|
bitfld.long 0x00 0.--4. " PMXS ,Performance Monitor X Select" "PM0,PM1,PM2,PM3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,PMCCFILTR"
|
|
group.long c15:0x00D9++0x00
|
|
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
|
|
group.long c15:0x01D9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
|
|
bitfld.long 0x00 31. " P ,Privileged mode filtering" "Count,Not count"
|
|
bitfld.long 0x00 30. " U ,User mode filtering" "Count,Not count"
|
|
bitfld.long 0x00 29. " NSK ,Non-Secure Kernel mode filtering" "Count,Not count"
|
|
textline " "
|
|
bitfld.long 0x00 28. " NSU ,Non-secure User mode filtering" "Count,Not count"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTYPE ,Event number"
|
|
group.long c15:0x00E9++0x00
|
|
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
|
|
bitfld.long 0x00 0. " UEN ,User-mode Enable" "Disabled,Enabled"
|
|
group.long c15:0x01E9++0x00
|
|
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " CCNT ,PMCCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EVC3 ,PM3EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EVC2 ,PM2EVCNTR enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVC1 ,PM1EVCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EVC0 ,PM0EVCNTR enable" "Disabled,Enabled"
|
|
group.long c15:0x02E9++0x00
|
|
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " CCNT ,PMCCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " EVC3 ,PM3EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " EVC2 ,PM2EVCNTR enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EVC1 ,PM1EVCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " EVC0 ,PM0EVCNTR enable" "Disabled,Enabled"
|
|
group.long c15:0x05F9++0x00
|
|
line.long 0x00 "PMACTLR,Performance Monitor Auxiliary Control Register"
|
|
bitfld.long 0x00 30.--31. " CCNTOVA ,Cycle Counter Overflow Action" "No action,Halting Debug,Clock stop mfg test,Clock skip mfg test"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " EVC3OVA ,Event Counter 3 Overflow Action" "No action,Halting Debug,Clock stop mfg test,Clock skip mfg test"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " EVC2OVA ,Event Counter 2 Overflow Action" "No action,Halting Debug,Clock stop mfg test,Clock skip mfg test"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " EVC1OVA ,Event Counter 1 Overflow Action" "No action,Halting Debug,Clock stop mfg test,Clock skip mfg test"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EVC0OVA ,Event Counter 0 Overflow Action" "No action,Halting Debug,Clock stop mfg test,Clock skip mfg test"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UEN ,User-mode Enable" "Disabled,Enabled"
|
|
group.long c15:0x01D9++0x00
|
|
line.long 0x00 "PMCCFILTR,Performance Monitor Cycle Count Filter Control Register"
|
|
bitfld.long 0x00 31. " P ,Privileged mode filtering" "Count,Not count"
|
|
bitfld.long 0x00 30. " U ,User mode filtering" "Count,Not count"
|
|
bitfld.long 0x00 29. " NSK ,Non-Secure Kernel mode filtering" "Count,Not count"
|
|
textline " "
|
|
bitfld.long 0x00 28. " NSU ,Non-secure User mode filtering" "Count,Not count"
|
|
group.long c15:0x02F9++0x00
|
|
line.long 0x00 "PMCCNTCR,Performance Monitor Cycle Count Control Register"
|
|
bitfld.long 0x00 31. " OVEE ,Overflow Export Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SAOV ,Stop all counters on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,STOPCOND" "Not stopped,PMCCNTR,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR,PMxEVTYPER[EVTYPE]"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "No reload,PMCCNTR,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR,PMxEVTYPER[EVTYPE]"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "Reserved,Reserved,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR,PMxEVTYPER[EVTYPE]"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "No suspend,PMCCNTR,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR,PMxEVTYPER[EVTYPE]"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "Immediately,Reserved,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR,PMxEVTYPER[EVTYPE]"
|
|
rgroup.long c15:0x03F9++0x00
|
|
line.long 0x00 "PMCCNTSR,Performance Monitor Cycle Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Cycle counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
rgroup.long c15:0x06C9++0x00
|
|
line.long 0x00 "PMCEID0,Performance Monitor Common Event Identification 0"
|
|
rgroup.long c15:0x07C9++0x00
|
|
line.long 0x00 "PMCEID1,Performance Monitor Common Event Identification 1"
|
|
group.long c15:0x04F9++0x00
|
|
line.long 0x00 "PMRLDR,Performance Monitor Reload Register"
|
|
group.long c15:0x00F9++0x00
|
|
line.long 0x00 "PMXEVCNTCR,Performance Monitor Event Count Control Register"
|
|
bitfld.long 0x00 31. " OVEE ,Overflow Export Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EVEE ,Event Export Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ENL ,Edge/Not Level" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 26. " NEG ,Negative" "Positive,Negative"
|
|
bitfld.long 0x00 24.--25. " STOPNDX ,Stop Index" "PM0,PM1,PM2,PM3"
|
|
bitfld.long 0x00 22.--23. " RLDNDX ,Reload Index" "PM0,PM1,PM2,PM3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " RESNDX ,Resume Index" "PM0,PM1,PM2,PM3"
|
|
bitfld.long 0x00 18.--19. " SUSNDX ,Suspend Index" "PM0,PM1,PM2,PM3"
|
|
bitfld.long 0x00 16.--17. " STARTNDX ,Start Index" "PM0,PM1,PM2,PM3"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SAOV ,Stop all counters on overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " STOPCOND ,Stop Condition" "Not stopped,PMCCNTR overflow,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR overflow,PMxEVTYPER[EVTYPE]"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " RLDCOND ,Reload Condition" "Not reloaded,PMCCNTR overflow,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR overflow,PMxEVTYPER[EVTYPE]"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " RESCOND ,Resume Condition" "Reserved,PMCCNTR overflow,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR overflow,PMxEVTYPER[EVTYPE]"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SUSCOND ,Suspend Condition" "No suspend,PMCCNTR overflow,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR overflow,PMxEVTYPER[EVTYPE]"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STARTCOND ,Start Condition" "Immediately,PMCCNTR overflow,Reserved,Reserved,Reserved,Trace event,PMxEVCNTR overflow,PMxEVTYPER[EVTYPE]"
|
|
group.long c15:0x02D9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
|
|
group.long c15:0x01F9++0x00
|
|
line.long 0x00 "PMXEVCNTSR,Performance Monitor Event Count Status Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Event counter state" "Reserved,Stop,Count,Reserved,Suspend,?..."
|
|
group.long c15:0x10F9++0x00
|
|
line.long 0x00 "PMRESR0,Performance Monitor Region Event Selection Register 0"
|
|
bitfld.long 0x00 31. " EN ,EN" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GRP3SEL ,Group 3 local event select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GRP2SEL ,Group 2 local event select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GRP1SEL ,Group 1 local event select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GRP0SEL ,Group 0 local event select"
|
|
group.long c15:0x11F9++0x00
|
|
line.long 0x00 "PMRESR1,Performance Monitor Region Event Selection Register 1"
|
|
bitfld.long 0x00 31. " EN ,EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " GRP3SEL ,Group 3 local event select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 16.--20. " GRP2SEL ,Group 2 local event select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " GRP1SEL ,Group 1 local event select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 0.--4. " GRP0SEL ,Group 0 local event select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long c15:0x12F9++0x00
|
|
line.long 0x00 "PMRESR2,Performance Monitor Region Event Selection Register 2"
|
|
bitfld.long 0x00 31. " EN ,EN" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " GRP3SEL ,Group 3 local event select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GRP2SEL ,Group 2 local event select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GRP1SEL ,Group 1 local event select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GRP0SEL ,Group 0 local event select"
|
|
tree.end
|
|
width 0xb
|
|
width 15.
|
|
tree "Debug Registers"
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Not implemented,Implemented"
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
wgroup.long c14:6.++0x0
|
|
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
wgroup.long c14:5.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c14:195.))&0x1)==0x1)
|
|
group.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
rbitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
rbitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
else
|
|
rgroup.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
endif
|
|
wgroup.long c14:5.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)"
|
|
endif
|
|
group.long c14:0x7++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 31. " NSF ,FIQ vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " NSI ,IRG vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " NSD ,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NSP ,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NSS ,SVC vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " NSU ,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NSHF ,FIQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " NSHI ,IRQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " NSHE ,Hyp Trap or Hyp mode entry exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " NSHD ,Data Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " NSHP ,Prefetch Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " NSHC ,Hypervisor Call. from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NSHU ,Undefined Instruction, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MF ,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MI ,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MD ,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MP ,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MS ,SMC vector catch enable in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SF ,FIQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SI ,IRQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SD ,Data Abort vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SP ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SS ,SVC vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SU ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " R ,Reset vector catch enable" "Disabled,Enabled"
|
|
group.long c14:9.++0x0
|
|
line.long 0x00 "DBGECR,Debug Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group.long c14:32.++0x0
|
|
line.long 0x00 "DBGDTRRX,Debug Receive Register (External View)"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Debug Instruction Transfer Register"
|
|
rgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,Reserved,Thumb"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault Status" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c14:195.))&0x1)==0x1)
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
else
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
endif
|
|
endif
|
|
wgroup.long c14:35.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RRQ ,Restart request" "No effect,Restart"
|
|
bitfld.long 0x00 0. " HRQ ,Halt request" "No effect,Halt"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CBRRQ ,CBRRQ" "Low,High"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c14:37.++0x0
|
|
line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register"
|
|
bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset"
|
|
bitfld.long 0x00 2. " DECRR ,Debug extend core reset request" "No request,Request"
|
|
bitfld.long 0x00 1. " DPDO ,Debug power-down override" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DCSC ,Debug clock stop control" "Stopped,Running"
|
|
textline " "
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:37.++0x0
|
|
line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register"
|
|
bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset"
|
|
endif
|
|
rgroup.long c14:40.++0x0
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,?..."
|
|
rgroup.long c14:41.++0x0
|
|
line.long 0x00 "DBGCIDSR,DBGCIDSR"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c14:42.++0x0
|
|
line.long 0x00 "DBGVIDSR,Virtualization ID Sampling Register"
|
|
bitfld.long 0x00 31. " NS ,NS state sample" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " H ,Hyp mode sample" "Not associated,Associated"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID ,VMID sample"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:42.++0x0
|
|
line.long 0x00 "DBGVIDSR,DBGVIDSR"
|
|
endif
|
|
width 15.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
textline " "
|
|
wgroup.long c14:958.++0x0
|
|
line.long 0x00 "DBGITOCTRL,Debug Integration Output Control Register"
|
|
bitfld.long 0x00 3. " NPMUIRQ ,Drives the nPMUIRQ output" "Low,High"
|
|
bitfld.long 0x00 2. " CTI_PMUIRQ ,Drives the internal signal equivalent to PMUIRQ that goes from the Performance Monitor Unit (PMU) to the Cross Trigger Interface (CTI)" "Low,High"
|
|
bitfld.long 0x00 1. " CTI_DBGRESTARTED ,Drives the internal signal that goes from the Debug unit to the CTI to acknowledge success of a debug restart command" "Low,High"
|
|
bitfld.long 0x00 0. " CTI_DBGTRIGGER ,Drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unit to the CTI" "Low,High"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
textline " "
|
|
wgroup.long c14:958.++0x0
|
|
line.long 0x00 "DBGITMISCOUT,Integration Miscellaneous Signals Output Register"
|
|
bitfld.long 0x00 9. " DBGRESTARTED ,Value of the DBGRESTARTED output pin" "Low,High"
|
|
bitfld.long 0x00 4. " PMUIRQ ,Value of PMUIRQ output pin" "Low,High"
|
|
bitfld.long 0x00 0. " DBGACK ,Value of the DBGACK output pin" "Low,High"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c14:959.++0x0
|
|
line.long 0x00 "DBGITISR,Debug Integration Input Status Register"
|
|
bitfld.long 0x00 3. " DBGSWENABLE ,Reads the state of the DBGSWENABLE input" "Low,High"
|
|
bitfld.long 0x00 2. " CTI_DBGRESTART ,CTI debug restart" "Low,High"
|
|
bitfld.long 0x00 1. " CTI_EDBGRQ ,CTI debug request" "Low,High"
|
|
bitfld.long 0x00 0. " EDBGRQ ,Reads the state of the EDBGRQ input" "Low,High"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
textline " "
|
|
rgroup.long c14:959.++0x0
|
|
line.long 0x00 "DBGITMISCIN,Integration Miscellaneous Signals Input Register"
|
|
bitfld.long 0x00 2. " NFIQ ,Read value of nFIQ input pin" "Low,High"
|
|
bitfld.long 0x00 1. " NIRQ ,Read value of nIRQ input pin" "Low,High"
|
|
bitfld.long 0x00 0. " EDBGRQ ,Read value of EDBGRQ input pin" "Low,High"
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
rgroup.quad c14:128.++0x1
|
|
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.quad 0x0 12.--39. 0x1000 " ROMADDR ,ROM physical address"
|
|
bitfld.quad 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid"
|
|
rgroup.quad c14:256.++0x1
|
|
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hexmask.quad 0x0 12.--39. 0x1000 " SELFOFFSET ,Debug bus self-address offset value"
|
|
bitfld.quad 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid"
|
|
else
|
|
rgroup.long c14:128.++0x0
|
|
line.long 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " ROMADDR ,ROM physical address"
|
|
bitfld.long 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid"
|
|
rgroup.long c14:256.++0x0
|
|
line.long 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " SELFOFFSET ,Debug bus self-address offset value"
|
|
bitfld.long 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid"
|
|
endif
|
|
group.long c14:195.++0x00
|
|
line.long 0x00 "DBGOSDLR,OS Double Lock Register"
|
|
bitfld.long 0x00 0. " DLK ,OS Double Lock control bit" "Unlocked,Locked"
|
|
else
|
|
hgroup.quad c14:128.++0x1
|
|
hide.quad 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hgroup.quad c14:256.++0x1
|
|
hide.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hgroup.long c14:195.++0x00
|
|
hide.long 0x00 "DBGOSDLR,OS Double Lock Register"
|
|
endif
|
|
wgroup.long c14:192.++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup.long c14:193.++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " OSLK ,Status of the OS Lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. 3. " OSLM ,OS Lock Model implemented Bit" "Reserved,Reserved,W/o DBGOSSRR,?..."
|
|
group.long c14:196.++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 3. " COREPURQ ,Core Power Up Request" "Low,High"
|
|
bitfld.long 0x00 2. " HCWR ,Hold Core Warm Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " CWRR ,Core Warm Reset Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core No Power down Request" "Low,High"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 6. " DLK ,OS Double Lock status" "Low,High"
|
|
bitfld.long 0x00 5. " OSLK ,OS Lock status" "Low,High"
|
|
bitfld.long 0x00 4. " HALTED ,Halted" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Low,High"
|
|
bitfld.long 0x00 2. " RS ,Reset Status" "Low,High"
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Low,High"
|
|
tree "Processor ID registers"
|
|
rgroup.long c14:(832.+0.)++0x00
|
|
line.long 0x00 "PIDR0,Processor ID register 0"
|
|
rgroup.long c14:(832.+1.)++0x00
|
|
line.long 0x00 "PIDR1,Processor ID register 1"
|
|
rgroup.long c14:(832.+2.)++0x00
|
|
line.long 0x00 "PIDR2,Processor ID register 2"
|
|
rgroup.long c14:(832.+3.)++0x00
|
|
line.long 0x00 "PIDR3,Processor ID register 3"
|
|
rgroup.long c14:(832.+4.)++0x00
|
|
line.long 0x00 "PIDR4,Processor ID register 4"
|
|
rgroup.long c14:(832.+5.)++0x00
|
|
line.long 0x00 "PIDR5,Processor ID register 5"
|
|
rgroup.long c14:(832.+6.)++0x00
|
|
line.long 0x00 "PIDR6,Processor ID register 6"
|
|
rgroup.long c14:(832.+7.)++0x00
|
|
line.long 0x00 "PIDR7,Processor ID register 7"
|
|
rgroup.long c14:(832.+8.)++0x00
|
|
line.long 0x00 "PIDR8,Processor ID register 8"
|
|
rgroup.long c14:(832.+9.)++0x00
|
|
line.long 0x00 "PIDR9,Processor ID register 9"
|
|
rgroup.long c14:(832.+10.)++0x00
|
|
line.long 0x00 "PIDR10,Processor ID register 10"
|
|
rgroup.long c14:(832.+11.)++0x00
|
|
line.long 0x00 "PIDR11,Processor ID register 11"
|
|
rgroup.long c14:(832.+12.)++0x00
|
|
line.long 0x00 "PIDR12,Processor ID register 12"
|
|
rgroup.long c14:(832.+13.)++0x00
|
|
line.long 0x00 "PIDR13,Processor ID register 13"
|
|
rgroup.long c14:(832.+14.)++0x00
|
|
line.long 0x00 "PIDR14,Processor ID register 14"
|
|
rgroup.long c14:(832.+15.)++0x00
|
|
line.long 0x00 "PIDR15,Processor ID register 15"
|
|
rgroup.long c14:(832.+16.)++0x00
|
|
line.long 0x00 "PIDR16,Processor ID register 16"
|
|
rgroup.long c14:(832.+17.)++0x00
|
|
line.long 0x00 "PIDR17,Processor ID register 17"
|
|
rgroup.long c14:(832.+18.)++0x00
|
|
line.long 0x00 "PIDR18,Processor ID register 18"
|
|
rgroup.long c14:(832.+19.)++0x00
|
|
line.long 0x00 "PIDR19,Processor ID register 19"
|
|
rgroup.long c14:(832.+20.)++0x00
|
|
line.long 0x00 "PIDR20,Processor ID register 20"
|
|
rgroup.long c14:(832.+21.)++0x00
|
|
line.long 0x00 "PIDR21,Processor ID register 21"
|
|
rgroup.long c14:(832.+22.)++0x00
|
|
line.long 0x00 "PIDR22,Processor ID register 22"
|
|
rgroup.long c14:(832.+23.)++0x00
|
|
line.long 0x00 "PIDR23,Processor ID register 23"
|
|
rgroup.long c14:(832.+24.)++0x00
|
|
line.long 0x00 "PIDR24,Processor ID register 24"
|
|
rgroup.long c14:(832.+25.)++0x00
|
|
line.long 0x00 "PIDR25,Processor ID register 25"
|
|
rgroup.long c14:(832.+26.)++0x00
|
|
line.long 0x00 "PIDR26,Processor ID register 26"
|
|
rgroup.long c14:(832.+27.)++0x00
|
|
line.long 0x00 "PIDR27,Processor ID register 27"
|
|
rgroup.long c14:(832.+28.)++0x00
|
|
line.long 0x00 "PIDR28,Processor ID register 28"
|
|
rgroup.long c14:(832.+29.)++0x00
|
|
line.long 0x00 "PIDR29,Processor ID register 29"
|
|
rgroup.long c14:(832.+30.)++0x00
|
|
line.long 0x00 "PIDR30,Processor ID register 30"
|
|
rgroup.long c14:(832.+31.)++0x00
|
|
line.long 0x00 "PIDR31,Processor ID register 31"
|
|
rgroup.long c14:(832.+32.)++0x00
|
|
line.long 0x00 "PIDR32,Processor ID register 32"
|
|
rgroup.long c14:(832.+33.)++0x00
|
|
line.long 0x00 "PIDR33,Processor ID register 33"
|
|
rgroup.long c14:(832.+34.)++0x00
|
|
line.long 0x00 "PIDR34,Processor ID register 34"
|
|
rgroup.long c14:(832.+35.)++0x00
|
|
line.long 0x00 "PIDR35,Processor ID register 35"
|
|
rgroup.long c14:(832.+36.)++0x00
|
|
line.long 0x00 "PIDR36,Processor ID register 36"
|
|
rgroup.long c14:(832.+37.)++0x00
|
|
line.long 0x00 "PIDR37,Processor ID register 37"
|
|
rgroup.long c14:(832.+38.)++0x00
|
|
line.long 0x00 "PIDR38,Processor ID register 38"
|
|
rgroup.long c14:(832.+39.)++0x00
|
|
line.long 0x00 "PIDR39,Processor ID register 39"
|
|
rgroup.long c14:(832.+40.)++0x00
|
|
line.long 0x00 "PIDR40,Processor ID register 40"
|
|
rgroup.long c14:(832.+41.)++0x00
|
|
line.long 0x00 "PIDR41,Processor ID register 41"
|
|
rgroup.long c14:(832.+42.)++0x00
|
|
line.long 0x00 "PIDR42,Processor ID register 42"
|
|
rgroup.long c14:(832.+43.)++0x00
|
|
line.long 0x00 "PIDR43,Processor ID register 43"
|
|
rgroup.long c14:(832.+44.)++0x00
|
|
line.long 0x00 "PIDR44,Processor ID register 44"
|
|
rgroup.long c14:(832.+45.)++0x00
|
|
line.long 0x00 "PIDR45,Processor ID register 45"
|
|
rgroup.long c14:(832.+46.)++0x00
|
|
line.long 0x00 "PIDR46,Processor ID register 46"
|
|
rgroup.long c14:(832.+47.)++0x00
|
|
line.long 0x00 "PIDR47,Processor ID register 47"
|
|
rgroup.long c14:(832.+48.)++0x00
|
|
line.long 0x00 "PIDR48,Processor ID register 48"
|
|
rgroup.long c14:(832.+49.)++0x00
|
|
line.long 0x00 "PIDR49,Processor ID register 49"
|
|
rgroup.long c14:(832.+50.)++0x00
|
|
line.long 0x00 "PIDR50,Processor ID register 50"
|
|
rgroup.long c14:(832.+51.)++0x00
|
|
line.long 0x00 "PIDR51,Processor ID register 51"
|
|
rgroup.long c14:(832.+52.)++0x00
|
|
line.long 0x00 "PIDR52,Processor ID register 52"
|
|
rgroup.long c14:(832.+53.)++0x00
|
|
line.long 0x00 "PIDR53,Processor ID register 53"
|
|
rgroup.long c14:(832.+54.)++0x00
|
|
line.long 0x00 "PIDR54,Processor ID register 54"
|
|
rgroup.long c14:(832.+55.)++0x00
|
|
line.long 0x00 "PIDR55,Processor ID register 55"
|
|
rgroup.long c14:(832.+56.)++0x00
|
|
line.long 0x00 "PIDR56,Processor ID register 56"
|
|
rgroup.long c14:(832.+57.)++0x00
|
|
line.long 0x00 "PIDR57,Processor ID register 57"
|
|
rgroup.long c14:(832.+58.)++0x00
|
|
line.long 0x00 "PIDR58,Processor ID register 58"
|
|
rgroup.long c14:(832.+59.)++0x00
|
|
line.long 0x00 "PIDR59,Processor ID register 59"
|
|
rgroup.long c14:(832.+60.)++0x00
|
|
line.long 0x00 "PIDR60,Processor ID register 60"
|
|
rgroup.long c14:(832.+61.)++0x00
|
|
line.long 0x00 "PIDR61,Processor ID register 61"
|
|
rgroup.long c14:(832.+62.)++0x00
|
|
line.long 0x00 "PIDR62,Processor ID register 62"
|
|
rgroup.long c14:(832.+63.)++0x00
|
|
line.long 0x00 "PIDR63,Processor ID register 63"
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x0
|
|
line.long 0x00 "DBGITCTRL,Debug Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group.long c14:1000.++0x0
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Set" "Not set,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Set" "Not set,Set"
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Set" "Not set,Set"
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Set" "Not set,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Set" "Not set,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Set" "Not set,Set"
|
|
group.long c14:1001.++0x0
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Clear" "Not cleared,Cleared"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
rgroup.long c14:1006.++0x0
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c14:1009.++0x0
|
|
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Depends on instr set state,No offset,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:1009.++0x0
|
|
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Reserved,No offset,?..."
|
|
endif
|
|
textline " "
|
|
rgroup.long c14:1010.++0x0
|
|
line.long 0x0 "DBGDEVID0,Debug Device ID Register 0"
|
|
bitfld.long 0x0 24.--27. " AR ,Debug External Auxiliary Control Register support status" "Reserved,Supported,?..."
|
|
bitfld.long 0x0 20.--23. " DL ,Support for Debug OS Double Lock Register" "Reserved,Supported,?..."
|
|
bitfld.long 0x0 16.--19. " VE ,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " VC ,Form of the vector catch event implemented" "Implemented,?..."
|
|
bitfld.long 0x0 8.--11. " BPAM ,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
|
|
bitfld.long 0x0 4.--7. " WPAM ,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " PCS ,Level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
|
|
textline " "
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Debug Device Type Register"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c14:1016.++0x00
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup.long c14:1017.++0x00
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup.long c14:1018.++0x00
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup.long c14:1019.++0x00
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup.long c14:1012.++0x00
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup.long c14:1020.++0x00
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup.long c14:1021.++0x00
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup.long c14:1022.++0x00
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup.long c14:1023.++0x00
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 10.
|
|
tree "Breakpoint Registers"
|
|
if ((d.l(c14:80.+0.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+0.)++0x0
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+0.)++0x0
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+0.)++0x0
|
|
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+1.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+1.)++0x0
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+1.)++0x0
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+1.)++0x0
|
|
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+2.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+2.)++0x0
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+2.)++0x0
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+2.)++0x0
|
|
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+3.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+3.)++0x0
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+3.)++0x0
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+3.)++0x0
|
|
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+4.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+4.)++0x0
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+4.)++0x0
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+4.)++0x0
|
|
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+5.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+5.)++0x0
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+5.)++0x0
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+5.)++0x0
|
|
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
group.long c14:148.++0x0
|
|
line.long 0x00 "DBGBXVR0,Debug Breakpoint Extended Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value"
|
|
group.long c14:149.++0x0
|
|
line.long 0x00 "DBGBXVR1,Debug Breakpoint Extended Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value"
|
|
tree.end
|
|
width 10.
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:(96.+0.)++0x00
|
|
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+0.)++0x00
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+0.)++0x00
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+1.)++0x00
|
|
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+1.)++0x00
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+1.)++0x00
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+2.)++0x00
|
|
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+2.)++0x00
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+2.)++0x00
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+3.)++0x00
|
|
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+3.)++0x00
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+3.)++0x00
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
textline ""
|