40654 lines
2.8 MiB
40654 lines
2.8 MiB
; --------------------------------------------------------------------------------
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; @Title: KinetisW Family On-Chip Peripherals
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; @Props: Released
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; @Author: SZM, BFG, FSZ
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; @Changelog: 2017-08-07 BFG
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; 2018-02-26 STR
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; 2018-03-08 FSZ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: MKW2xDxxxRM.pdf (Rev. 1, 2013-11)
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; MKW01xxRM.pdf (Rev. 3, 2016-04)
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; MKW40Z160RM.pdf (Rev. 1.2, 2015-10)
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; MKW41Z512RM.pdf (Rev. 1, 2016-10)
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; MKW2xDxxxRM.pdf (Rev. 3, 2016-05)
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; MKW41Z512RM.pdf (Rev. 2, 2017-07)
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; @Chip: MKW21D256VHA5, MKW21D512VHA5, MKW22D512VHA5, MKW24D512VHA5,
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; MKW01Z128CHNR, MKW20Z160VHT4, MKW21Z256VHT4, MKW21Z512VHT4,
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; MKW30Z160VHM4, MKW30Z160VHM4R, MKW31Z256VHT4, MKW31Z512VHT4,
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; MKW40Z160VHT4, MKW40Z160VHT4R, MKW41Z256VHT4, MKW41Z512VHT4,
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; MKW01Z128CHN, MKW21D256VHA5R, MKW41Z512VHT4R
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; @Core: Cortex-M4, Cortex-M0P
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perkinetisw.per 17736 2024-04-08 09:26:07Z kwisniewski $
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; Known Problems:
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; MODULE REGISTER DESCRIPTION
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;-------------------------------------------------------------------------------------
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; SIM for MKW40Z SDID bitfld 16.--19. SRAMSIZE no specified state
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; for 20kB value
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; SIM for MKW40Z FCFG1 bitfld 24.--27. PFSIZE no specified state
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; for 160KB value
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; MCG for MKW2xDxxx C1 bitfld 6.--7. CLKS no description for state
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; 00b
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; VREF DTEST_CTRL bitfld 0.--5. Link provided in reference manual
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; is not working, meaning no states
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; BLE Link Layer Registers registers offsets not provided in clear way
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sif (corename()=="CORTEXM4")
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
elif (corename()=="CORTEXM0+")
|
|
tree.close "Core Registers (Cortex-M0+)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
|
|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
config 16. 8.
|
|
tree.open "PORT (Port control and interrupts)"
|
|
tree "PORTA"
|
|
base ad:0x40049000
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "PORTA_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,UART0_CTS_b/UART0_COL_b,FTM0_CH5,,,,JTAG_TCLK/SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,,,,,,NMI_b"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH8,PTA0,SPI0_PCS1,,,TPM1_CH0,,SWD_DIO"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTA_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,UART0_RX,FTM0_CH6,,,,JTAG_TDI"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1/LLWU_P0/RF_ANT_B,LPUART0_CTS,LPI2C0_SDAS,LPUART1_CTS,,,JTAG_TCLK/SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTA1,SPI1_PCS0,,,TPM1_CH1,,SWD_CLK"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTA1,,,,TPM1_CH1,,SWD_CLK"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTA_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,UART0_TX,FTM0_CH7,,,,JTAG_TDO/TRACE_SWO"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2/LLWU_P1/RF_ANT_A,LPUART0_RX,LPI2C0_SDA,LPUART1_RX,,,JTAG_TDI"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,,,,TPM0_CH3,,RESET_b"
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
sif (cpuis("MKW2?D*")||cpuis("MKW01Z128*")||cpuis("K32W0?2S1M*"))
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "PORTA_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA3,UART0_RTS_b,FTM0_CH0,,,,JTAG_TMS/SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA3/RF0_TX_SWITCH,LPUART0_TX,FLPI2C0_SCL,LPUART1_TX,,TPM0_CLKIN,JTAG_TDO/SWD_SWO"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTA_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA4/LLWU_P3,,FTM0_CH1,,,,NMI_b"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,NMI_b"
|
|
textline " "
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA4/RF0_RX_SWITCH,LPUART0_RTS,LPI2C0_SCLS,LPUART1_RTS,,LPCMP0_OUT,JTAG_TMS/SWD_DIO"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "PORTA_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA9,LPI2C2_SDAS,LPSPI3_SCK,,FB_A23,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTA_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA10,LPI2C2_SCLS,LPSPI3_SOUT,,FB_A22,?..."
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "PORTA_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA14,LPI2C2_SDA,,,FB_AD23,LPCMP0_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTA_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA15,LPI2C2_SCL,,,FB_AD22,?..."
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW31Z*")||cpuis("MKW2?Z*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PORTA_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTA16/LLWU_P4,SPI1_SOUT,,,TPM0_CH0,?..."
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*")||cpuis("MKW4?Z*")||cpuis("MKW31Z*")||cpuis("MKW2?Z*"))
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTA_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA17,LPI2C2_HREQ,LPSPI3_PCS1,EMVSIM0_CLK,FB_AD21,?..."
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTA17/LLWU_P5/RF_RESET,SPI1_SIN,,,TPM_CLKIN1,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "PORTA_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,FTM0_FLT2,FTM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA18,LPSPI2_PCS1,LPSPI3_PCS3,EMVSIM_RST,FB_AD20,?..."
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTA18/LLWU_P6,SPI1_SCK,,,TPM2_CH0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTA18/LLWU_P6,SPI1_SCK,,,TPM2_CH0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTA_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,FTM1_FLT0,FTM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA19,LPSPI2_PCS3,LPSPI3_SCK,EMVSIM0_VCCEN,FB_AD19,TPM2_CH5,?..."
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH13/ADC0_SE5,PTA19/LLWU_P7,SPI1_PCS0,,,TPM2_CH1,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW20Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH13,PTA19/LLWU_P7,SPI1_PCS0,,,TPM2_CH1,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("MKW01Z128*")||(cpuis("K32W0?2S1M*")))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PORTA_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA20,LPSPI2_SCK,LPSPI1_PCS1,EMVSIM0_IO,FB_AD18,TPM2_CH4,?..."
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA20,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x54++0x1F
|
|
line.long 0x00 "PORTA_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA21,LPSPI2_SOUT,,EMVSIM0_PD,FB_AD17,TPM2_CH3,?..."
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTA_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA22/LLWU_P2,LPSPI2_PCS2,,LPI2C2_HREQ,FB_AD16,TPM2_CH2,?..."
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTA_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA23,LPSPI2_SIN,LPSPI1_PCS3,LPI2C2_SDA,FB_AD15,TPM2_CH1,?..."
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTA_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA24,LPSPI2_PCS0,LPSPI1_SCK,LPI2C2_SCL,FB_OE_b,TPM2_CH0,?..."
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x10 "PORTA_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA25,LPUART1_RX,LPSPI3_SOUT,LPI2C2_SDAS,FB_AD31,?..."
|
|
bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x14 "PORTA_PCR26,Pin Control Register 26"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTA26,LPUART1_TX,LPSPI3_PCS2,LPI2C2_SCLS,FB_AD30,?..."
|
|
bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x18 "PORTA_PCR27,Pin Control Register 27"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" ",PTA27,LPUART1_CTS,LPSPI3_SIN,,FB_AD29,?..."
|
|
bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x1C "PORTA_PCR28,Pin Control Register 28"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" ",PTA28,LPUART1_RTS,LPSPI3_PCS0,,FB_AD28,?..."
|
|
bitfld.long 0x1C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "PORTA_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA3/RF0_TX_SWITCH,LPUART0_TX,FLPI2C0_SCL,LPUART1_TX,,TPM0_CLKIN,JTAG_TDO/SWD_SWO"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTA_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA3/RF0_TX_SWITCH,LPUART0_TX,FLPI2C0_SCL,LPUART1_TX,,TPM0_CLKIN,JTAG_TDO/SWD_SWO"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
wgroup.long 0x80++0x0F
|
|
line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE[15] ,Global pin write enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Global pin write enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Global pin write enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [9] ,Global pin write enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Global pin write enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [3] ,Global pin write enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " [2] ,Global pin write enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Global pin write enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORTA_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE[31] ,Global pin write enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [30] ,Global pin write enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [28] ,Global pin write enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [27] ,Global pin write enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [26] ,Global pin write enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [25] ,Global pin write enable 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " [24] ,Global pin write enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [23] ,Global pin write enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [22] ,Global pin write enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " [21] ,Global pin write enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,Global pin write enable 20" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [19] ,Global pin write enable 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " [18] ,Global pin write enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Global pin write enable 17" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x08 "PORTA_GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write data"
|
|
bitfld.long 0x08 15. " [15] ,Global interrupt write enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Global interrupt write enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " [10] ,Global interrupt write enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Global interrupt write enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Global interrupt write enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Global interrupt write enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Global interrupt write enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Global interrupt write enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " [0] ,Global interrupt write enable 0" "Disabled,Enabled"
|
|
line.long 0x0C "PORTA_GICHR, Global Interrupt Control High Register"
|
|
bitfld.long 0x0C 15. " GIWE[31] ,Global interrupt write enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [30] ,Global interrupt write enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [28] ,Global interrupt write enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [27] ,Global interrupt write enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [26] ,Global interrupt write enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [25] ,Global interrupt write enable 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " [24] ,Global interrupt write enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [23] ,Global interrupt write enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [22] ,Global interrupt write enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " [21] ,Global interrupt write enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [20] ,Global interrupt write enable 20" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [19] ,Global interrupt write enable 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " [18] ,Global interrupt write enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [17] ,Global interrupt write enable 17" "Disabled,Enabled"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTA_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " [31] ,Interrupt status flag 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,Interrupt status flag 30" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,Interrupt status flag 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Interrupt status flag 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,Interrupt status flag 26" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [25] ,Interrupt status flag 25" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 24. " [24] ,Interrupt status flag 24" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " [23] ,Interrupt status flag 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,Interrupt status flag 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " [21] ,Interrupt status flag 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,Interrupt status flag 20" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " [19] ,Interrupt status flag 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 18. " [18] ,Interrupt status flag 18" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,Interrupt status flag 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " [15] ,Interrupt status flag 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " [14] ,Interrupt status flag 14" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt status flag 10" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt status flag 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " [4] ,Interrupt status flag 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt status flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt status flag 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,Interrupt status flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt status flag 0" "No interrupt,Interrupt"
|
|
else
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register"
|
|
sif (cpuis("MKW2?D*")||cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "No effect,Update"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "No effect,Update"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "No effect,Update"
|
|
else
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "No effect,Update"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "No effect,Update"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
sif (!cpuis("MKW30Z*"))
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "PORTA_GPCHR,Global Pin Control High Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 20. " GPWE20 ,Global pin 20 write enable" "No effect,Update"
|
|
bitfld.long 0x00 19. " GPWE19 ,Global pin 19 write enable" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No effect,Update"
|
|
else
|
|
bitfld.long 0x00 19. " GPWE19 ,Global pin 19 write enable" "No effect,Update"
|
|
bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No effect,Update"
|
|
endif
|
|
sif (cpuis("MKW4?Z")||cpuis("MKW31Z*")||cpuis("MKW2?Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE17 ,Global pin 17 write enable" "No effect,Update"
|
|
bitfld.long 0x00 16. " GPWE16 ,Global pin 16 write enable" "No effect,Update"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTA_ISFR,Interrupt Status Flag Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW31Z*")||cpuis("MKW2?Z*"))
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW2?D*")||cpuis("MKW01Z128*"))
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
sif (cpuis("MKW2?D*"))
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "PORTA_DFER,Digital Filter Enable Register"
|
|
bitfld.long 0x00 19. " DFE19 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DFE18 ,Digital filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTA_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO Clock(1kHz)"
|
|
line.long 0x08 "PORTA_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
tree "PORTB"
|
|
base ad:0x4004A000
|
|
width 13.
|
|
sif (!cpuis("MKW30Z*"))
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "PORTB_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,,?..."
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB0/LLWU_P8/XTAL_OUT_EN,,I2C0_SCL,CMP0_OUT,TPM0_CH1,,CLKOUT"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB0,LPUART2_TX,LPSPI1_SIN,USB0_SOF_OUT,CLKOUT,TPM1_CLKIN,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB0/LLWU_P8,,I2C0_SCL,CMP0_OUT,TPM0_CH1,,CLKOUT"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Low,High"
|
|
else
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTB_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN5,PTB1,DTM_RX,I2C0_SDA,LPTMR0_ALT1,TPM0_CH2,,CMT_IRO"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB1/LLWU_P4,LPUART2_RX,LPSPI1_PCS0,I2S0_TXD1,FB_AD12,,LPTMR1_ALT3"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN5,PTB1,,I2C0_SDA,LPTMR0_ALT1,TPM0_CH2,,CMT_IRO"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Low,High"
|
|
else
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTB_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE3/CMP0_IN3,PTB2,RF_NOT_ALLOWED,DTM_TX,,TPM1_CH0,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB2/LLWU_P5/RF0_RFOSC_EN,LPSPI0_PCS1,LPUART1_RX,I2S0_TXD0,FB_AD11,TPM0_CH0,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE3/CMP0_IN3,PTB2,,,,TPM1_CH0,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Low,High"
|
|
else
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PORTB_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTB3,LPSPI0_PCS3,LPUART1_TX,I2S0_TX_FS,FB_AD10,TPM0_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE2/CMP0_IN4,PTB3,,,CLKOUT,TPM1_CH1,,RTC_CLKOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "PORTB_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE1,PTB4,LPSPI0_SCK,LPUART1_CTS,I2S0_TX_BCLK,FB_AD9,TPM0_CH2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTB_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB5,LPSPI0_SOUT,LPUART1_RTS,I2S0_MCLK,FB_AD8,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTB_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB6,LPSPI0_PCS2,LPUART1_SDA,I2S0_RX_BCLK,FB_AD7,TPM0_CH4,RF0_BSM_FRAME"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTB_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTB7,LPSPI0_SIN,LPUART1_SDAS,I2S0_RX_FS,FB_AD6,TPM0_CH5,RF0_BSM_DATA"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x10 "PORTB_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTB8,LPSPI0_PCS0,LPUART1_SCLS,I2S0_RXD0,FB_AD5,,PTMR0_ALT1"
|
|
textline " "
|
|
bitfld.long 0x10 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x14 "PORTB_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTB9,LPSPI0_PCS1,LPUART1_SCL,I2S0_RXD1,FB_RW_b,,FXIO0_D0"
|
|
textline " "
|
|
bitfld.long 0x14 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
group.long 0x2C++0x13
|
|
line.long 0x00 "PORTB_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB11,LPUART2_RX,LPI2C1_SDAS,LPI2C0_SDA,FB_AD27,,FXIO0_D1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTB_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB12,LPUART2_TX,LPI2C1_SCLS,LPI2C0_SCL,FB_AD26,TPM3_CLKIN,FXIO0_D2"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTB_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB13,LPUART2_CTS,LPI2C1_SDA,LPI2C0_SDAS,FB_AD25,TPM3_CH0,FXIO0_D3"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTB_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTB14,LPUART2_RTS,LPI2C1_SCL,LPI2C0_SCLS,FB_AD24,TPM3_CH1,FXIO0_D4"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x10 "PORTB_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTB15,,LPI2C1_HREQ,LPI2C3_SCL,FB_CS5_b,TPM0_CLKIN,FXIO0_D5"
|
|
textline " "
|
|
bitfld.long 0x10 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "PORTB_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB16,,LPUART3_CTS,LPI2C3_SDA,FB_CS4_B,,FXIO0_D6"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL32K,PTB16,,I2C1_SCL,,TPM2_CH0,?..."
|
|
endif
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Low,High"
|
|
else
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTB_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL32K,PTB17,,I2C1_SDA,,TPM2_CH1,,BSM_CLK"
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB17,,LPUART3_RTS,LPI2C3_SCLS,FB_TBST_B,,FXIO0_D7"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL32K,PTB17,,I2C1_SDA,,TPM2_CH0,?..."
|
|
endif
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Low,High"
|
|
else
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTB_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE4/CMP0_IN2,PTB18,,I2C1_SCL,TPM_CLKIN0,TPM0_CH0,,NMI_b"
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB18,LPSPI1_PCS1,LPUART2_RX,LPI2C3_SDAS,FB_CS3_b,FB_TA_b,FXIO0_D8"
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE4/CMP0_IN2,PTB18,,I2C1_SCL,TPM_CLKIN0,TPM0_CH0,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Low,High"
|
|
else
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTB_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x4C++0x0F
|
|
line.long 0x00 "PORTB_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB19,LPSPI1_PCS3,LPUART2_TX,,FB_ALE/FB_CS1_b/FB_TS_b,TPM1_CLKIN,FXIO0_D9"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTB_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB20/LLWU_P11,LPSPI1_SCK,LPUART2_CTS,,FB_CS0_b,TPM1_CH0,FXIO0_D10"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTB_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB21,LPSPI1_SOUT,LPUART2_RTS,LPI2C2_HREQ,FB_AD4,TPM1_CH1,FXIO0_D11"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTB_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTB22/LLWU_12,LPSPI1_PCS2,LPUART0_CTS,LPI2C2_SDA,FB_AD3,TPM2_CLKIN,FXIO0_D12"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
group.long 0x60++0x0B
|
|
line.long 0x00 "PORTB_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB24,LPSPI1_SIN,LPUART0_RTS,LPI2C2_SCL,FB_AD2,EWM_IN,FXIO0_D13"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTB_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB25/LLWU_P13,LPSPI1_PCS0,LPUART0_RX,LPI2C2_SDAS,FB_AD1,EWM_OUT_b,FXIO0_D14"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTB_PCR26,Pin Control Register 26"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB26,USB0_SOF_OUT,LPUART0_TX,LPI2C2_SCLS,FB_AD0,LPCMP0_OUT,RF0_BSM_CLK"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
group.long 0x70++0x0F
|
|
line.long 0x00 "PORTB_PCR28,Pin Control Register 28"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB28/LLWU_P14,,LPUART3_RX,I2S0_TXD0,FB_A16,,FXIO0_D15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTB_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB29,,LPUART3_TX,I2S0_TX_FS,FB_A17,,FXIO0_D16"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTB_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB30,,,I2S0_TX_BCLD,FB_A18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTB_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTB31,,,I2S0_RX_D0,FB_A19,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Low,High"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register"
|
|
sif (!cpuis("MKW01Z128*")&&!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "No effect,Update"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "No effect,Update"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "No effect,Update"
|
|
textline " "
|
|
elif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 31. " GPWE[15] ,Global pin write enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Global pin write enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,Global pin write enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " [12] ,Global pin write enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [11] ,Global pin write enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [9] ,Global pin write enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,Global pin write enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [7] ,Global pin write enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [6] ,Global pin write enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Global pin write enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Global pin write enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [3] ,Global pin write enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Global pin write enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Global pin write enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [0] ,Global pin write enable 16" "Disabled,Enabled"
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORTB_GPCHR,Global Pin Control High Register"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "No effect,Update"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "No effect,Update"
|
|
elif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x04 31. " GPWE[31] ,Global pin write enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [30] ,Global pin write enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [29] ,Global pin write enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " [28] ,Global pin write enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [26] ,Global pin write enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " [25] ,Global pin write enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [24] ,Global pin write enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " [22] ,Global pin write enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [21] ,Global pin write enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,Global pin write enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [19] ,Global pin write enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,Global pin write enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Global pin write enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " [16] ,Global pin write enable 16" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "No effect,Update"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
sif cpuis("K32W0?2S1M*")
|
|
wgroup.long 0x84++0x0B
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 31. " GPWE[31] ,Global pin write enable 31 ""Disabled,Enable"
|
|
bitfld.long 0x00 30. " [30] ,Global pin write enable 30 ""Disabled,Enable"
|
|
bitfld.long 0x00 29. " [29] ,Global pin write enable 29 ""Disabled,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " [28] ,Global pin write enable 28 ""Disabled,Enable"
|
|
bitfld.long 0x00 26. " [26] ,Global pin write enable 26 ""Disabled,Enable"
|
|
bitfld.long 0x00 25. " [25] ,Global pin write enable 25 ""Disabled,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,Global pin write enable 24 ""Disabled,Enable"
|
|
bitfld.long 0x00 22. " [22] ,Global pin write enable 22 ""Disabled,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Global pin write enable 21 ""Disabled,Enable"
|
|
bitfld.long 0x00 20. " [20] ,Global pin write enable 20 ""Disabled,Enable"
|
|
bitfld.long 0x00 19. " [19] ,Global pin write enable 19 ""Disabled,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " [18] ,Global pin write enable 18 ""Disabled,Enable"
|
|
bitfld.long 0x00 17. " [17] ,Global pin write enable 17 ""Disabled,Enable"
|
|
bitfld.long 0x00 16. " [16] ,Global pin write enable 16 ""Disabled,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " GIWD ,Global interrupt write data"
|
|
bitfld.long 0x04 15. " GPWD[15] ,Global interrupt write enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [14] ,Global interrupt write enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [13] ,Global interrupt write enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [12] ,Global interrupt write enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [11] ,Global interrupt write enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Global interrupt write enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [8] ,Global interrupt write enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Global interrupt write enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Global interrupt write enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Global interrupt write enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " [4] ,Global interrupt write enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [3] ,Global interrupt write enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Global interrupt write enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [1] ,Global interrupt write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Global interrupt write enable 0" "Disabled,Enabled"
|
|
line.long 0x08 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write data"
|
|
bitfld.long 0x08 15. " GIWE[31] ,Global interrupt write enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [30] ,Global interrupt write enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " [29] ,Global interrupt write enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [28] ,Global interrupt write enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " [26] ,Global interrupt write enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [25] ,Global interrupt write enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [24] ,Global interrupt write enable 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " [22] ,Global interrupt write enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [21] ,Global interrupt write enable 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " [20] ,Global interrupt write enable 20" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [19] ,Global interrupt write enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [18] ,Global interrupt write enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " [17] ,Global interrupt write enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [16] ,Global interrupt write enable 16" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("K32W0?2S1M*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF[31] ,Interrupt status flag 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,Interrupt status flag 30" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,Interrupt status flag 29" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 28. " [28] ,Interrupt status flag 28" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,Interrupt status flag 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " [25] ,Interrupt status flag 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,Interrupt status flag 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " [22] ,Interrupt status flag 22" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [21] ,Interrupt status flag 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,Interrupt status flag 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Interrupt status flag 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,Interrupt status flag 18" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,Interrupt status flag 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " [16] ,Interrupt status flag 16" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " [15] ,Interrupt status flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt status flag 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " [13] ,Interrupt status flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt status flag 12" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " [11] ,Interrupt status flag 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " [9] ,Interrupt status flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt status flag 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,Interrupt status flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt status flag 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt status flag 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " [4] ,Interrupt status flag 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt status flag 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt status flag 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Interrupt status flag 0" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
elif (cpuis("MKW30Z*"))
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "PORTC"
|
|
base ad:0x4004B000
|
|
width 13.
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*")||cpuis("K32W0?2S1M*"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTC_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC0,,I2S0_RX_FS,FB_A20,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC0/LLWU_P9,ANT_A,I2C0_SCL,LPUART0_CTS_b,TPM0_CH1,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z")||cpuis("MKW01Z128*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORTC_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC1,ANT_B,I2C0_SDA,LPUART0_RTS_b,TPM0_CH2,,BLE_RF_ACTIVE"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC1,,I2S0_BCLK_FS,FB_A21,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC1,ANT_B,I2C0_SDA,UART0_RTS_b,TPM0_CH2,,BLE_ACTIVE"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif !cpuis("K32W0?2S1M*")
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "PORTC_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH14/DIAG1,PTC2/LLWU_P10,TX_SWITCH,I2C1_SCL,LPUART0_RX,CMT_IRO,,DTM_RX"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH14,PTC2/LLWU_P10,TX_SWITCH,I2C1_SCL,UART0_RX,CMT_IRO,,DTM_RX"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTC_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH15/DIAG2,PTC3/LLWU_P11,RX_SWITCH,I2C1_SDA,LPUART0_TX,TPM0_CH1,,DTM_TX"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH15,PTC3/LLWU_P11,RX_SWITCH,I2C1_SDA,UART0_TX,,,DTM_TX"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (!cpuis("MKW30Z*")&&!cpuis("K32W0?2S1M*"))
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "PORTC_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,FTM0_CH3,,CMP1_OUT,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH0/DIAG3,PTC4/LLWU_P12,ANT_A,EXTRG_IN,LPUART0_CTS_b,TPM1_CH0,,BSM_DATA"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW20Z"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH0,PTC4/LLWU_P12,,EXTRG_IN,UART0_CTS_b,TPM1_CH0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTC_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTC5/LLWU_P9,SPI0_SCK,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH1/DIAG4,PTC5/LLWU_P13,RF_NOT_ALLOWED,LPTMR0_ALT2,LPUART0_RTS_b,TPM1_CH1,,BSM_CLK"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW20Z"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTC5/LLWU_P13,,LPTMR0_ALT2,UART0_RTS_b,TPM1_CH1,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTC_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMPO_IN0,PTC6/LLWU_P10,SPI0_SOUT,PDB0_EXTRG,I2S0_RX_BCLK,,I2S0_MCLK,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMPO_IN0,PTC6/LLWU_P10,SPI0_MOSI,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTC6/LLWU_P14/XTAL_OUT_EN,,I2C1_SCL,LPUART0_RX,TPM2_CH0,,BSM_FRAME"
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW20Z"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTC6/LLWU_P14,,I2C1_SCL,UART0_RX,TPM2_CH0,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PORTC_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_SIN,USB_SOF_OUT,I2S0_RX_FS,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0_IN1,,SPI0_MISO,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LPCMP0_IN0,PTC7/LLWU_P15,LPSPI0_PCS3,LPUART0_RX,LPI2C1_HREQ,,TPM0_CH0,LPTMR1_ALT1"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTC7/LLWU_P15,SPI0_PCS2,I2C1_SDA,LPUART0_TX,TPM2_CH1,,BSM_DATA"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW20Z"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTC7/LLWU_P15,SPI0_PCS2,I2C1_SDA,UART0_TX,TPM2_CH1,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "PORTC_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LPCMP0_IN1,PTC8,LPSPI0_SCK,LPUART0_TX,LPI2C2_HREQ,,TPM0_CH1,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTC_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE4/LPCMP0_IN2,PTC9/LLWU_P16,LPSPI0_SOUT,LPUART0_CTS,LPI2C0_SDA,,TPM0_CH2,LPTMR0_ALT2"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTC_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE5,PTC10,LPSPI0_PCS2,LPUART0_RTS,LPI2C0_SCL,,TPM0_CH3,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTC_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTC11/LLWU_P17,LPSPI0_SIN,LPI2C1_SDA,LPI2C0_SDAS,,TPM0_CH4,EWM_IN"
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x0c 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x10 "PORTC_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTC12/LLWU_P18,LPSPI0_PCS0,LPI2C1_SCL,LPI2C0_SCLS,,TPM0_CH5,EWM_OUT_b"
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "PORTC_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTC16/LLWU_P0,SPI0_SCK,I2C0_SDA,LPUART0_RTS_b,TPM0_CH3,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTC16/LLWU_P0,SPI0_SCK,I2C0_SDA,UART0_RTS_b,TPM0_CH3,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTC_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTC17/LLWU_P1,SPI0_SOUT,I2C1_SCL,LPUART0_RX,BSM_FRAME,,DTM_RX"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTC17/LLWU_P1,SPI0_SOUT,,UART0_RX,,,DTM_RX"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTC_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH6,PTC18/LLWU_P2,SPI0_SIN,I2C1_SDA,LPUART0_TX,BSM_DATA,,DTM_TX"
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH6,PTC18/LLWU_P2,SPI0_SIN,,UART0_TX,,,DTM_TX"
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTC_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH7,PTC19/LLWU_P3,SPI0_PCS0,I2C0_SCL,LPUART0_CTS_b,BSM_CLK,,BLE_RF_ACTIVE"
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH7,PTC19/LLWU_P3,SPI0_PCS0,I2C0_SCL,UART0_CTS_b,,,BLE_ACTIVE"
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x68++0x17
|
|
line.long 0x00 "PORTC_PCR26,Pin Control Register 26"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC26,,,,,TPM0_CH5,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTC_PCR27,Pin Control Register 27"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTC27,,,,,TPM0_CH4,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTC_PCR28,Pin Control Register 28"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTC28,,LPSPI0_PCS1,,,TPM0_CH3,FXIO0_D17"
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTC_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTC29,LPUART1_RX,LPSPI0_PCS3,,,TPM0_CH4,FXIO0_D18"
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x10 "PORTC_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTC29,LPUART1_RX,LPSPI0_SCK,,,TPM0_CH2,FXIO0_D18"
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x14 "PORTC_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTC30,LPUART1_TX,LPSPI0_SCK,,,TPM0_CH1,FXIO0_D19"
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
wgroup.long 0x80++0x0F
|
|
line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE[15] ,Global pin write enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,Global pin write enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [11] ,Global pin write enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Global pin write enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [9] ,Global pin write enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,Global pin write enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [7] ,Global pin write enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [1] ,Global pin write enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORTC_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE[31] ,Global pin write enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [30] ,Global pin write enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [29] ,Global pin write enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " [28] ,Global pin write enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [27] ,Global pin write enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [26] ,Global pin write enable 26" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x08 "PORTC_GICLR, Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write"
|
|
textline " "
|
|
bitfld.long 0x08 12. " GIWE[12] ,Global interrupt write enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [11] ,Global interrupt write enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " [10] ,Global interrupt write enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Global interrupt write enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Global interrupt write enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Global interrupt write enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " [1] ,Global interrupt write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Global interrupt write enable 0" "Disabled,Enabled"
|
|
line.long 0x0C "PORTC_GICHR ,Global Interrupt Control High Register GICHR"
|
|
hexmask.long.word 0x0C 16.--31. 1. " GIWD ,Global interrupt write"
|
|
bitfld.long 0x0C 15. " GIWE[31] ,Global interrupt write enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [30] ,Global interrupt write enable 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " [29] ,Global interrupt write enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [28] ,Global interrupt write enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [27] ,Global interrupt write enable 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " [26] ,Global interrupt write enable 26" "Disabled,Enabled"
|
|
else
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register"
|
|
sif (!cpuis("MKW30Z*"))
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "No effect,Update"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "No effect,Update"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "No effect,Update"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "No effect,Update"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "No effect,Update"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 1 write enable" "No effect,Update"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "No effect,Update"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "No effect,Update"
|
|
endif
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "PORTC_GPHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 19. " GPWE19 ,Global pin 19 write enable" "No effect,Update"
|
|
bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No effect,Update"
|
|
bitfld.long 0x00 17. " GPWE17 ,Global pin 17 write enable" "No effect,Update"
|
|
bitfld.long 0x00 16. " GPWE16 ,Global pin 16 write enable" "No effect,Update"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF[30] ,Interrupt status flag 30" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,Interrupt status flag 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,Interrupt status flag 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,Interrupt status flag 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,Interrupt status flag 26" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt status flag 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Interrupt status flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt status flag 10" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt status flag 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " [8] ,Interrupt status flag 8" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Interrupt status flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt status flag 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Interrupt status flag 0" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*"))
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "PORTC_DFER,Digital Filter Enable Register"
|
|
bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTC_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO Clock(1kHz)"
|
|
line.long 0x08 "PORTC_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW2?D*"))
|
|
tree "PORTD"
|
|
base ad:0x4004C000
|
|
width 13.
|
|
sif (cpuis("MKW01Z128*")||(cpuis("K32W0?2S1M*")))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTD_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0,LPUART1_CTS,LPSPI0_SOUT,,,TPM0_CH0,FXIO0_D19"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0,SPI0_PCS0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "PORTD_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD1,LPUART1_RTS,LPSPI0_PCS2,,,EWM_IN,FXIO0_D21"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE5b,PTD1,SPI0_SCK,UART2_CTS_b,?..."
|
|
else
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTD_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTD2,SDHC0_D7,LPSPI0_SIN,,,EWM_OUT_b,FXIO0_D22"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTD2/LLWU_P13,SPI0_SOUT,UART2_RX,I2C0_SCL,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTD_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD3,SDHC0_D6,LPSPI0_PCS0,EMVSIM0_CLK,,TPM2_CLKIN,FXIO0_D23"
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD3,SPI0_SIN,UART2_TX,I2C0_SDA,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "PORTD_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD4,SDHC0_D5,LPSPI2_PCS1,EMVSIM0_RST,,,FXIO0_D24"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE21,PTD4/LLWU_P14,SPI0_PCS1,UART0_RTS_b,FTM0_CH4,,EWM_IN,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTD_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTD5,SDHC0_D4,LPSPI2_PCS3,EMVSIM0_VCCEN,,,FXIO0_D25"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE6b,PTD5,SPI0_PCS2,UART0_CTS_b/UART0_COL_b,FTM0_CH5,,EWM_OUT_b,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTD_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTD6,SDHC0_D1,LPSPI2_SCK,EMVSIM0_IO,TRACE_D3,TPM2_CH5,FXIO0_D26"
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE7b,PTD6/LLWU_P15,SPI0_PCS3,UART0_RX,FTM0_CH6,,FTM0_FLT0,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTD_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE10,PTD7,SDHC0_D0,LPSPI2_SOUT,EMVSIM0_PD,TRACE_D2,TPM2_CH4,FXIO0_D27"
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE22,PTD7,CMT_IRO,UART0_TX,FTM0_CH7,,FTM0_FLT1,?..."
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PORTD_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTD8/LLWU_P19,SDHC0_DCLK,LPSPI2_PCS2,LPI2C1_SDAS,TRACE_D1,TPM2_CH3,FXIO0_D28"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTD_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTD9,SDHC0_CMD,LPSPI2_SIN,LPI2C1_SCLS,TRACE_D0,TPM2_CH2,FXIO0_D29"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTD_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTD10/LLWU_P20,SDHC0_D3,LPSPI2_PCS0,LPI2C1_SDA,TRACE_CLKOUT,TPM2_CH1,FXIO0_D30"
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTD_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt Configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 15. " LK ,Lock Register" "Not locked,Locked"
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTD11,SDHC0_D2,USB0_SOF_OUT,LPI2C1_SCL,CLKOUT,TPM2_CH0,FXIO0_D31"
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
wgroup.long 0x80++0x0F
|
|
line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE[11] ,Global pin write enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Global pin write enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,Global pin write enable 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [8] ,Global pin write enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [7] ,Global pin write enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Global pin write enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [5] ,Global pin write enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Global pin write enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [3] ,Global pin write enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " [2] ,Global pin write enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Global pin write enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Global pin write enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
line.long 0x04 "PORTD_GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
line.long 0x08 "GICLR, Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global Interrupt Write"
|
|
bitfld.long 0x08 11. " GIWE[11] ,Global interrupt write enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Global interrupt write enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " [9] ,Global interrupt write enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Global interrupt write enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [7] ,Global interrupt write enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " [6] ,Global interrupt write enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Global interrupt write enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Global interrupt write enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Global interrupt write enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Global interrupt write enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Global interrupt write enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " [0] ,Global interrupt write enable 0" "Disabled,Enabled"
|
|
line.long 0x0C "GICHR ,Global Interrupt Control High Register GICHR"
|
|
hexmask.long.word 0x0C 16.--31. 1. " GIWD ,Global Interrupt Write"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTD_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 11. " ISF[11] ,Interrupt status register 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt status register 10" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt status register 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " [8] ,Interrupt status register 8" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Interrupt status register 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt status register 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " [5] ,Interrupt status register 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt status register 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt status register 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " [2] ,Interrupt status register 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt status register 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt status register 0" "No interrupt,Interrupt"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "DFER, Digital Filter Enable Register"
|
|
bitfld.long 0x00 11. " DFE[11] ,Digital filter enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Digital filter enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Digital filter enable 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Digital filter enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Digital filter enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Digital filter enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Digital filter enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Digital filter enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Digital filter enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Digital filter enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Digital filter enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Digital filter enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "DFCR, Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock Source" "Bus Clock,8 Clock"
|
|
line.long 0x08 "DFWR, Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "No effect,Update"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "No effect,Update"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "No effect,Update"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "No effect,Update"
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "No effect,Update"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "No effect,Update"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "No effect,Update"
|
|
else
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "No effect,Update"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTD_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "PORTD_DFER,Digital Filter Enable Register"
|
|
bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTD_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO Clock(1kHz)"
|
|
line.long 0x08 "PORTD_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORTE"
|
|
base ad:0x4004D000
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "PORTE_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LPCMP1_IN4,PTE0,,,,,EWM_IN,?..."
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE10,PTE0,SPI1_PCS1,UART1_TX,,TRACE_CLKOUT,I2C1_SDA,RTC_CLKOUT"
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTE_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE18,PTE1/LLWU_P21,SDHC0_D1,LPI2C0_SDAS,LPSPI3_PCS1,,EWM_OUT_b,LPTMR_ALT2"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTE1/LLWU_P0,SPI1_SOUT,UART1_RX,,TRACE_D3,I2C1_SCL,SPI1_SIN"
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTE_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE19,PTE2,SDHC0_D0,LPI2C0_SCSL,LPSPI3_PCS3,,LPCMP1_OUT,?..."
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP1,PTE2/LLWU_P1,SPI1_SCK,UART1_CTS_b,,TRACE_D2,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTE2,SPI1_SCK,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTE_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE20/LPCMP1_IN0,PTE3/LLWU_P22,SDHC0_D7,LPI2C0_SDA,LPSPI3_SCK,,LPM0_CLKIN,LPTMR0_ALT3"
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_DM1,PTE3,SPI1_SIN,UART1_RTS_b,,TRACE_D1,,SPI1_SOUT"
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTE3,SPI1_MISO,,,SPI1_MOSI,?..."
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PORTE_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE21/LPCMP1_IN1,PTE4,SDHC0_D6,LPI2C0_SCL,LPSPI3_SOUT,CLKOUT,TPM1_CLKIN,RF0_DTM_RX"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE4/LLWU_P2,SPI1_PCS0,,,TRACE_D0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PORTE_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LPCMP1_IN1,PTE5,SDHC0_DCLK,LPI2C0_HREQ,LPSPI3_PCS2,,LPCMP1_OUT,RF0_DTM_TX"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
group.long 0x20++0x1F
|
|
line.long 0x00 "PORTE_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE22,PTE8/LLWU_P23,SDHC0_D5,LPUART3_RX,LPSPI3_SIN,,TPM1_CH0,LPTMR2_ALT1"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTE_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23,PTE9/LLWU_P24,SDHC0_CMD,LPUART3_TX,LPSPI3_PCS0,,TPM1_CH1,FXIO0_D0"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTE_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTE10/LWU_P25,SDHC0_D4,LPUART3_CTS,LPI2C3_SDA,,TPM3_CH0,LPTMR2_ALT3"
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTE_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTE11,SDHC0_D3,LPUART3_RTS,LPI2C3_SCL,,TPM3_CH1,FXIO0_D1"
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x10 "PORTE_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTE12/LLWU_P26,SDHC0_D2,LPUART3_RTS,LPI2C3_SDAS,,TPM3_CLKIN,FXIO0_D2"
|
|
bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x14 "PORTE_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTE13,I2S0_TX_BCLK,,LPI2C3_SCLS,,TPM3_CH0,FXIO0_D3"
|
|
bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x18 "PORTE_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x18 15. " LK ,Lock Register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" ",PTE14,I2S0_TX_FS,,LPI2C3_HREQ,,TPM3_CH1,FXIO0_D4"
|
|
bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x1C "PORTE_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" ",PTE15,I2S0_TX_D0,,,,TPM3_CLKIN,FXIO0_D5"
|
|
bitfld.long 0x1C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW01Z128*")||cpuis("K32W0?2S1M*"))
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "PORTE_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE16,I2S0_RX_BCLK,,,,TPM2_CH0,FXIO0_D6"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE4a,PTE16,SPI0_PCS0,UART2_TX,FTM_CLKIN0,,FTM0_FLT3,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTE_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE17,I2S0_RX_FS,,,,TPM2_CH1,FXIO0_D7"
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5a,PTE17,SPI0_SCK,UART2_RX,FTM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_DM1/ADC0_SE5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTE_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTE1,I2S0_RX_D0,,,,TPM2_CH2,FXIO0_D8"
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE6a,PTE18,SPI0_SOUT,UART2_CTS_b,I2C0_SDA,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
textline " "
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x0C "PORTE_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTE19,I2S0_MCLK,,,,TPM2_CH3,FXIO0_D9"
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE7a,PTE19,SPI0_SIN,UART2_RTS_b,I2C0_SCL,?..."
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_DM2/ADC0_SE6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "PORTE_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE21,I2S0_TXD1,USB0_SOF_OUT,,,TPM2_CH4,FXIO0_D10"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTE_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE22,I2S0_RXD1,LPI2C3_HREQ,,,TPM2_CH5,FXIO0_D11"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
group.long 0x6C++0x0B
|
|
line.long 0x00 "PORTE_PCR27,Pin Control Register 27"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE27,LPUART3_CTS,LPI2C3_SDAS,,,,FXIO0_D28"
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x04 "PORTE_PCR28,Pin Control Register 28"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE28,LPUART3_RTS,LPI2C3_SCLS,,,,FXIO0_D29"
|
|
bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
line.long 0x08 "PORTE_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTE29,LPUART3_RX,LPI2C3_SDA,,,,FXIO0_D30"
|
|
bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("MKW01Z128*")||(cpuis("K32W0?2S1M*")))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PORTE_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..."
|
|
textline " "
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE30,LPUART3_TX,LPI2C3_SCL,,,TPM2_CLKIN,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow"
|
|
bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
wgroup.long 0x80++0x0F
|
|
line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE[15] ,Global pin 15 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Global pin 14 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,Global pin 13 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " [12] ,Global pin 12 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [11] ,Global pin 11 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORTC_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE[30] ,Global pin 30 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [29] ,Global pin 29 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " [28] ,Global pin 28 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [27] ,Global pin 27 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " [22] ,Global pin 22 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [21] ,Global pin 21 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [19] ,Global pin 19 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x08 "GICLR, Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write data"
|
|
textline " "
|
|
bitfld.long 0x08 15. " GIWE[15] ,Global interrupt 15 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Global interrupt 14 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [13] ,Global interrupt 13 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " [12] ,Global interrupt 12 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [11] ,Global interrupt 11 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Global interrupt 10 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " [9] ,Global interrupt 9 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Global interrupt 8 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " [5] ,Global interrupt 5 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Global interrupt 4 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Global interrupt 3 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Global interrupt 2 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Global interrupt 1 write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " [0] ,Global interrupt 0 write enable" "Disabled,Enabled"
|
|
line.long 0x0C "GICHR ,Global Interrupt Control High Register GICHR"
|
|
hexmask.long.word 0x0C 16.--31. 1. " GIWD ,Global interrupt write data"
|
|
bitfld.long 0x0C 14. " GIWE[30] ,Global interrupt write enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [29] ,Global interrupt write enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " [28] ,Global interrupt write enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [27] ,Global interrupt write enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [22] ,Global interrupt write enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " [21] ,Global interrupt write enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [19] ,Global interrupt write enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [18] ,Global interrupt write enable 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " [17] ,Global interrupt write enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [16] ,Global interrupt write enable 16" "Disabled,Enabled"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF[30] ,Interrupt status flag 30" "Not detected,Detected"
|
|
eventfld.long 0x00 29. " [29] ,Interrupt status flag 29" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 28. " [28] ,Interrupt status flag 28" "Not detected,Detected"
|
|
eventfld.long 0x00 27. " [27] ,Interrupt status flag 27" "Not detected,Detected"
|
|
textline " "
|
|
textline " "
|
|
eventfld.long 0x00 22. " [22] ,Interrupt status flag 22" "Not detected,Detected"
|
|
eventfld.long 0x00 21. " [21] ,Interrupt status flag 21" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,Interrupt status flag 19" "Not detected,Detected"
|
|
eventfld.long 0x00 18. " [18] ,Interrupt status flag 18" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " [17] ,Interrupt status flag 17" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 16. " [16] ,Interrupt status flag 16" "Not detected,Detected"
|
|
eventfld.long 0x00 15. " [15] ,Interrupt status flag 15" "Not detected,Detected"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt status flag 14" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 13. " [13] ,Interrupt status flag 13" "Not detected,Detected"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt status flag 12" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " [11] ,Interrupt status flag 11" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " [10] ,Interrupt status flag 10" "Not detected,Detected"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt status flag 9" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt status flag 8" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 5. " [5] ,Interrupt status flag 5" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 4. " [4] ,Interrupt status flag 4" "Not detected,Detected"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt status flag 3" "Not detected,Detected"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt status flag 2" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,Interrupt status flag 1" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt status flag 0" "Not detected,Detected"
|
|
else
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "No effect,Update"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "No effect,Update"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "No effect,Update"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "No effect,Update"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "No effect,Update"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW01Z128*"))
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "PORTE_GPCHR,Global Pin Control High Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 30. " GPWE30 ,Global pin 30 write enable" "No effect,Update"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " GPWE19 ,Global pin 19 write enable" "No effect,Update"
|
|
bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No effect,Update"
|
|
bitfld.long 0x00 17. " GPWE17 ,Global pin 17 write enable" "No effect,Update"
|
|
bitfld.long 0x00 16. " GPWE16 ,Global pin 16 write enable" "No effect,Update"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW01Z128*"))
|
|
sif (cpuis("MKW01Z128*"))
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "No interrupt,Interrupt"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "PORTE_DFER,Digital Filter Enable Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5"))
|
|
bitfld.long 0x00 19. " DFE19 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DFE18 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DFE17 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DFE16 ,Digital filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORTE_DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO Clock(1kHz)"
|
|
line.long 0x08 "PORTE_DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SIM (System Integration Module)"
|
|
base ad:0x40047000
|
|
width 10.
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SOPT1,System Options Register 1"
|
|
sif (cpuis("MKW2?D*"))
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop/VLPS/LLS/VLLS modes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC 32.768kHz,LPO 1kHz"
|
|
rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" ",8KB,,16KB,24KB,32KB,48KB,64KB,96KB,128KB,,256KB,?..."
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC_CLKIN,LPO 1kHz"
|
|
bitfld.long 0x00 16.--17. " OSC32KOUT ,32K oscillator clock output" "No output,PTB3,?..."
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC_CLKIN,LPO 1kHz"
|
|
endif
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHIPCTRL,Chip Control Register"
|
|
bitfld.long 0x00 8.--9. " FBSEL ,FLEXBUS security level [instruction/data]" "Disallowed/Disallowed,Disallowed/Disallowed,Disallowed/Allowed,Allowed/Allowed"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 " SDID ,System Device Identification Register"
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" "K32W0,?..."
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,02,03,04,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SERIESID ,Kinetis series ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " PINID ,Pin count identification " ",,,,,,,,176-pin,,,,,191-pin,,?..."
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOPT1CFG,SOPT1 Configuration Register"
|
|
bitfld.long 0x00 26. " USSWE ,USB voltage regulator stop standby write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " UVSWE ,USB voltage regulator VLP standby write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " URWE ,USB voltage regulator enable write enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SOPT1CFG,SOPT1 Configuration Register"
|
|
endif
|
|
endif
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
group.long 0x1004++0x03
|
|
line.long 0x00 "SOPT2,System Options Register 2"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK/2"
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock 1kHz,MCGIRCLK,,OSCERCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1Hz,OSCERCLK"
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 26.--27. " LPUART0SRC ,LPUART0 clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" "OSCERCLK/2,OSCERCLK/4,Bus clock,LPO clock 1kHz,MCGIRCLK,OSCERCLK DIV8,OSCERCLK,?..."
|
|
elif (cpuis("MKW2?D*"))
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGFLLCLK or MCGPLLCLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK"
|
|
bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/System clock"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PTD7PAD ,PTD7 pad drive strength" "Single-pad,Double pad"
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Flash clock,LPO clock(1kHz),MCGIRCLK,RTC 32.768kHz clock,OSCERCLK0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1Hz,RTC 32.768kHz"
|
|
endif
|
|
endif
|
|
sif (!cpuis("K32W0?2S1M*"))
|
|
group.long 0x100C++0x07
|
|
line.long 0x00 "SOPT4,System Options Register 4"
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 29. " FTM0TRG1SRC ,FlexTimer 0 hardware trigger 1 source select" "PDB output trigger 1,FTM2 channel match"
|
|
bitfld.long 0x00 28. " FTM0TRG0SRC ,FlexTimer 0 hardware trigger 0 source select" "HSCMP0 output,FTM1 channel match"
|
|
textline " "
|
|
bitfld.long 0x00 26. " FTM2CLKSEL ,FlexTimer 2 external clock pin select" "FTM_CLK0,FTM_CLK1"
|
|
bitfld.long 0x00 25. " FTM1CLKSEL ,FlexTimer 1 external clock pin select" "FTM_CLK0,FTM_CLK1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FTM0CLKSEL ,FlexTimer 0 external clock pin select" "FTM_CLK0,FTM_CLK1"
|
|
bitfld.long 0x00 20.--21. " FTM2CH0SRC ,FTM2 channel 0 input capture source select" "FTM2_CH0 signal,CMP0 output,CMP1 output,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " FTM1CH0SRC ,FTM1 channel 0 input capture source select" "FTM1_CH0 signal,CMP0 output,CMP1 output,USB start of frame pulse"
|
|
bitfld.long 0x00 8. " FTM2FLT0 ,FTM2 fault 0 select" "FTM2_FLT0 pin,CMP0 out"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FTM1FLT0 ,FTM1 fault 0 select" "FTM1_FLT0 pin,CMP0 out"
|
|
bitfld.long 0x00 1. " FTM0FLT1 ,FTM2 fault 0 select" "FTM0_FLT1 pin,CMP1 out"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FTM0FLT0 ,FTM1 fault 0 select" "FTM0_FLT0 pin,CMP0 out"
|
|
else
|
|
bitfld.long 0x00 26. " TPM2CLKSEL ,TPM2 external clock pin select" "TPM_CLKIN0,TPM_CLKIN1"
|
|
bitfld.long 0x00 25. " TPM1CLKSEL ,TPM1 external clock pin select" "TPM_CLKIN0,TPM_CLKIN1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPM0CLKSEL ,TPM0 external clock pin select" "TPM_CLKIN0,TPM_CLKIN1"
|
|
bitfld.long 0x00 20. " TPM2CH0SRC ,TPM2 channel 0 input capture source select" "TMP2_CH0 signal,CMP0 output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output"
|
|
endif
|
|
line.long 0x04 "SOPT5,System Options Register 5"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x04 18. " UART2ODE ,UART2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " UART1ODE ,UART1 open drain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " UART0ODE ,UART0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " UART1RXSRC ,UART1 receive data source select" "UART1_RX pin,CMP0 output"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " UART1TXSRC ,UART1 transmit data source select" "UART1_TX pin,UART1_TX pin - TPM1,UART1_TX pin - TPM2,?..."
|
|
bitfld.long 0x04 2. " UART0RXSRC ,UART0 receive data source select" "UART0_RX pin,CMP0 output"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " UART0TXSRC ,UART 0 transmit data source select" "UART0_TX pin,UART0_TX pin modulated - TPM1 CH0 out,UART0_TX pin modulated - TPM2 CH0 out,?..."
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x04 6.--7. " UART1RXSRC ,UART 1 receive data source select" "UART1_RX,CMP0,CMP1,?..."
|
|
bitfld.long 0x04 4.--5. " UART1TXSRC ,UART 1 transmit data source select" "UART1_TX,UART1_TX pin modulated - FTM1 CH0 out,UART1_TX pin modulated - FTM2 CH0 out,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " UART0RXSRC ,UART 0 receive data source select" "UART0_RX pin,CMP0,CMP1,?..."
|
|
bitfld.long 0x04 0.--1. " UART0TXSRC ,UART0 transmit data source select" "UART0_TX,UART0_TX pin modulated - FTM1 CH0 out,UART0_TX pin modulated - FTM2 CH0 out,?..."
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x04 16. " LPUART0ODE ,LPUART0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LPUART0RXSRC ,LPUART0 receive data source select" "LPUART_RX pin,CMP0 output"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " LPUART0TXSRC ,LPUART0 transmit data source select" "LPUART0_TX pin,LPUART0_TX pin - TPM1,LPUART0_TX pin - TPM2,?..."
|
|
endif
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "SOPT7,System Options Register 7"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pretrigger select" "ADHWTSA,ADHWTSB"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR0 trigger,?..."
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pretrigger select" "ADHDWTSA,ADHDWTSB"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR0 trigger,Radio TSM"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pretrigger select" "A,B"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "PDB0_EXTRG,High speed comparator 0 output,High speed comparator 1 output,,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
endif
|
|
textline " "
|
|
rgroup.long 0x1024++0x03
|
|
line.long 0x00 "SDID,System Device Identification Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" "KL0x,KL1x,KL2x,KL3x,KL4x,?..."
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,KLx2,KLx3,KLx4,KLx5,KLx6,KLx7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SERIESID ,Kinetis series ID" ",KL,?..."
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System RAM size" "0.5KB,1KB,2KB,4KB,8KB,16KB,32KB,64KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" "16-pin,24-pin,32-pin,36-pin,48-pin,64-pin,80-pin,,100-pin,,,Custom pinout,?..."
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" ",,KW20Z,KW30Z,KW40Z,?..."
|
|
bitfld.long 0x00 24.--25. " SUBFAMID ,Kinetis sub-family ID" "KWx0,KWx1,KWx2,KWx3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SERIESID ,Kinetis series ID" ",,,,,KW,?..."
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System RAM size" "20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB,20KB"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,,,,,,,CSP,?..."
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" ",,KW2x,KW3x,KW4x,?..."
|
|
bitfld.long 0x00 24.--25. " SUBFAMID ,Kinetis sub-family ID" "KWx0,KWx1,KWx2,KWx3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SERIESID ,Kinetis series ID" ",,,,,KW,?..."
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System RAM size" ",,,,,,,64KB,,128KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,48-pin,?..."
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " FAMID ,Kinetis family identification" "K10/K12,K20/K22,K30/K11/K61,K40/K21,K60/K62,K70,KW24,?..."
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,64-pin,80-pin,81-pin/121-pin,100-pin,121-pin,144-pin,Custom pinout,,,256-pin,?..."
|
|
endif
|
|
textline " "
|
|
group.long 0x1034++0x0F
|
|
line.long 0x00 "SCGC4,System Clock Gating Control Register 4"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 23. " SPI1 ,SPI1 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SPI0 ,SPI0 clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW2?D*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 20. " VREF ,VREF clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " CMP ,Comparator clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
bitfld.long 0x00 18. " USBOTG ,USB clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 12. " UART2 ,UART2 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UART1 ,UART1 clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UART0 ,UART0 clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " I2C1 ,I2C1 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " I2C0 ,I2C0 clock gate control" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 2. " CMT ,CMT clock gate control" "Disabled,Enabled"
|
|
sif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.long 0x00 1. " EWM ,EWM clock gate control" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
line.long 0x04 "SCGC5,System Clock Gating Control Register 5"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z")||cpuis("MKW2?Z*"))
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z"))
|
|
bitfld.long 0x04 31. " GEN_FSK ,Generic FSK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW2?Z*")||cpuis("MKW4?Z*"))
|
|
bitfld.long 0x04 29. " ZIGBEE ,802.15.4 clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 28. " PHYDIG ,PHY digital clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z"))
|
|
bitfld.long 0x04 27. " BTLL ,BTLL system clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 26. " DCDC ,DCDC clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " RSIM ,RSIM clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " LTC ,LTC clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LPUART0 ,LPUART0 clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW2?D*"))
|
|
bitfld.long 0x04 13. " PORTE ,Port E clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " PORTD ,Port D clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " PORTC ,Port C clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PORTB ,Port B clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PORTA ,Port A clock gate control" "Disabled,Enabled"
|
|
sif (!cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.long 0x04 5. " TSI ,TSI access control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 0. " LPTMR ,Low power timer access control" "Disabled,Enabled"
|
|
line.long 0x08 "SCGC6,System Clock Gating Control Register 6"
|
|
bitfld.long 0x08 31. " DAC0 ,DAC0 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " RTC ,RTC access control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ADC0 ,ADC0 clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x08 26. " FTM2 ,FTM2 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " FTM1 ,FTM1 clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " FTM0 ,FTM0 clock gate control" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 26. " TPM2 ,TPM2 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " TPM1 ,TPM1 clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TPM0 ,TPM0 clock gate control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 23. " PIT ,PIT clock gate control" "Disabled,Enabled"
|
|
sif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.long 0x08 22. " PDB ,PDB clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
bitfld.long 0x08 21. " USBDCD ,USB DCD clock gate control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18. " CRC ,CRC clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " I2S ,I2S clock gate control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x08 13. " SPI1 ,SPI1 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SPI0 ,SPI0 clock gate control" "Disabled,Enabled"
|
|
sif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.long 0x08 9. " RNGA ,RNGA clock gate control" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x08 9. " TRNG ,TRNG clock gate control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 1. " DMAMUX ,DMA Mux clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " FTF ,Flash memory clock gate control" "Disabled,Enabled"
|
|
line.long 0x0C "SCGC7,System Clock Gating Control Register 7"
|
|
sif (!cpuis("MKW2?D*"))
|
|
bitfld.long 0x0C 8. " DMA ,DMA clock gate control" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x0C 1. " DMA ,DMA clock gate control" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x4007E000+0x01))&0x60)==0x40)
|
|
rgroup.long 0x1044++0x03
|
|
line.long 0x00 "CLKDIV1,System Clock Divider Register 1"
|
|
bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
endif
|
|
else
|
|
group.long 0x1044++0x03
|
|
line.long 0x00 "CLKDIV1,System Clock Divider Register 1"
|
|
bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "CLKDIV2,System Clock Divider Register 2"
|
|
bitfld.long 0x00 1.--3. " USBDIV ,USB clock divider divisor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " USBFRAC ,USB clock divider fraction" "0,1"
|
|
elif (cpuis("MKW21D*"))
|
|
hgroup.long 0x1048++0x03
|
|
hide.long 0x00 "CLKDIV2,System Clock Divider Register 2"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
if (((per.l(ad:0x40047000+0x1050))&0x800000)==0x000000)
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
rbitfld.long 0x00 28.--31. " NVMSIZE ,FlexNVM size" "0KB,,,32KB,,64KB,,128KB,,256KB,,512KB,,,,256KB/32KB protect"
|
|
rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,32KB,,64KB,,128KB,,256KB,,512KB,,1024KB,,512KB"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--19. " EESIZE ,EEPROM size" "16KB,8KB,4KB,2KB,1KB,512B,256B,128B,64B,32B,,,,,,0B"
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Enabled during Wait mode,Disabled during Wait mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes"
|
|
else
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
rbitfld.long 0x00 28.--31. " NVMSIZE ,FlexNVM size" "0KB,,,32KB,,64KB,,128KB,,256KB,,512KB,,,,0KB"
|
|
rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,32KB,,64KB,,128KB,,256KB,,512KB,,1024KB,,512KB"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--19. " EESIZE ,EEPROM size" "16KB,8KB,4KB,2KB,1KB,512B,256B,128B,64B,32B,,,,,,0B"
|
|
rbitfld.long 0x00 8.--11. " DEPART ,FlexNVM partition" "64KB/0KB,,,32KB/32KB,0KB/64KB,,,,0KB/64KB,,,32KB/32KB,64KB/0KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Enabled during Wait mode,Disabled during Wait mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes"
|
|
endif
|
|
else
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" "8KB,16KB,,32KB,,64KB,,128KB,,256KB,,,,,,128KB"
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Enabled during Doze mode,Disabled during Doze mode"
|
|
textline " "
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" "?..."
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Enabled during Doze mode,Disabled during Doze mode"
|
|
textline " "
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,,,,,,,256KB,,512KB,,,,512KB"
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Enabled during Doze mode,Disabled during Doze mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
rbitfld.long 0x00 28.--31. " CORE0_PFSIZE ,The flash size for core0 (CM4)" ",,,,,,,,,,,,1MB,?..."
|
|
rbitfld.long 0x00 24.--27. " CORE1_PFSIZE ,The flash size for core1 (CM0+)" ",,,,,,,,,,256KB,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 20.--23. " CORE0_SRAMSIZE ,The SRAM size for core0 (CM4)" ",,,,,,,,,,256KB,?..."
|
|
rbitfld.long 0x00 16.--19. " CORE1_SRAMSIZE ,The SRAM size for core1 (CM0+)" ",,,,,,,,,128KB,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 3.--13. 1. " FLSAUTODISWD ,The clock counter for time period of flash auto disable"
|
|
bitfld.long 0x00 2. " FLSAUTODISEN ,Flash auto disable enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "Yes,No"
|
|
line.long 0x04 "FCFG2,Flash Configuration Register 2"
|
|
bitfld.long 0x04 31. " SWAP ,SWAP bit from flash FCNFG register" "Block0,Block1"
|
|
hexmask.long.byte 0x04 24.--30. 1. " MAXADDR01 ,Max address lock"
|
|
textline " "
|
|
bitfld.long 0x04 16.--21. " MAXADDR2 ,Max address lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x58++0x07
|
|
line.long 0x00 " UIDH ,Unique Identification Register High"
|
|
hexmask.long.word 0x00 0.--15. 1. " UID ,Unique Identification"
|
|
line.long 0x04 " UIDM ,Unique Identification Register Mid Middle"
|
|
else
|
|
rgroup.long 0x1050++0x03
|
|
line.long 0x00 "FCFG2,Flash Configuration Register 2"
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 31. " SWAPPFLSH ,Swap program flash" "Not active,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " MAXADDR0 ,Max address block 0"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFLASH ,Program flash only" "FlexNVM supported,FlexNVM not supported"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MAXADDR1 ,Max address block 1"
|
|
else
|
|
hexmask.long.byte 0x00 24.--30. 1. " MAXADDR0 ,Max address lock 0"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MAXADDR1 ,Max address lock 1"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
rgroup.long 0x1054++0x03
|
|
line.long 0x00 "UIDH,Unique Identification Register High"
|
|
endif
|
|
sif !cpuis("K32W0?2S1M*")
|
|
rgroup.long 0x1058++0x0B
|
|
line.long 0x00 "UIDMH,Unique Identification Register Mid-High"
|
|
sif (!cpuis("MKW2?D*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " UID ,Unique identification"
|
|
endif
|
|
line.long 0x04 "UIDML,Unique Identification Register Mid Low"
|
|
line.long 0x08 "UIDL,Unique Identification Register Low"
|
|
endif
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "COPC,COP Control Register"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 6.--7. " COPCLKSEL ,COP clock select" "LPO,MCGIRCLK,OSCERCLK,Bus clock"
|
|
bitfld.long 0x00 5. " COPDBGEN ,COP debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " COPSTPEN ,COP stop enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " COPT ,COP watchdog timeout" "Disabled,After 2^5 LPO cycles or 2^13 bus clock cycles,After 2^8 LPO cycles or 2^16 bus clock cycles,After 2^10 LPO cycles or 2^18 bus clock cycles"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COPCLKS ,COP clock select" "Short timeout,Long timeout"
|
|
bitfld.long 0x00 0. " COPW ,COP windowed mode" "Normal,Windowed"
|
|
else
|
|
bitfld.long 0x00 2.--3. " COPT ,COP watchdog timeout" "Disabled,After 2^5 LPO cycles or 2^13 bus clock cycles,After 2^8 LPO cycles or 2^16 bus clock cycles,After 2^10 LPO cycles or 2^18 bus clock cycles"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COPCLKS ,COP clock select" "Internal 1kHz clock,Bus clock"
|
|
bitfld.long 0x00 0. " COPW ,COP windowed mode" "Normal,Windowed"
|
|
endif
|
|
wgroup.long 0x1104++0x03
|
|
line.long 0x00 "SRVCOP,Service COP"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SRVCOP ,Service COP"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
rgroup.long 0x60++0x0B
|
|
line.long 0x00 "UIDL,Unique Identification Register Mid Low"
|
|
line.long 0x04 "RFADDRL,RF Mac Address Low"
|
|
hexmask.long.byte 0x04 24.--31. 0x01 " MACADDR3 ,RF address - loaded from IFR"
|
|
hexmask.long.byte 0x04 16.--23. 0x01 " MACADDR2 ,RF address - loaded from IFR"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 0x01 " MACADDR1 ,RF address - loaded from IFR"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " MACADDR0 ,RF address - loaded from IFR"
|
|
line.long 0x08 "RFADDRH,RF Mac Address Low"
|
|
hexmask.long.byte 0x08 0.--7. 0x01 " MACADDR4 ,RF address - loaded from IFR"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MISC2,MISC2 Register"
|
|
bitfld.long 0x00 0. " SYSTICK_CLK_EN ,Systick clock enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMC (System Mode Controller)"
|
|
base ad:0x4007E000
|
|
width 10.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "PMPROT,Power Mode Protection Register"
|
|
bitfld.byte 0x00 5. " AVLP ,Allow very-low-power modes" "VLPR/VLPW/VLPS not allowed,VLPR/VLPW/VLPS allowed"
|
|
bitfld.byte 0x00 3. " ALLS ,Allow low-leakage stop mode" "LLSx not allowed,LLSx allowed"
|
|
bitfld.byte 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "VLLSx not allowed,VLLSx allowed"
|
|
line.byte 0x01 "PMCTRL,Power Mode Control Register"
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x01 7. " LPWUI ,Low-power wake up on interrupt" "Remain in VLP,Exit to RUN"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "RUN,,VLPR,"
|
|
textline " "
|
|
rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted"
|
|
bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "STOP,,VLPS,LLS,VLLSx,?..."
|
|
sif (cpuis("MKW2?D*"))
|
|
if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "VLLSCTRL,VLLS Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered"
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,,,,"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "VLLSCTRL,VLLS Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered"
|
|
endif
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04)
|
|
if (((per.b(ad:0x4007E000+0x02))&0x07)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled in VLLS0,Disabled in VLLS0"
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled in VLLS0,Disabled in VLLS0"
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..."
|
|
endif
|
|
elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x03)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled in VLLS0,Disabled in VLLS0"
|
|
bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..."
|
|
elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..."
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled in VLLS0,Disabled in VLLS0"
|
|
endif
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered"
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,,,,"
|
|
elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x03)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled in VLLS0,Disabled in VLLS0"
|
|
bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered"
|
|
bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..."
|
|
elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..."
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled in VLLS0,Disabled in VLLS0"
|
|
endif
|
|
elif (cpuis("MKW01Z128*"))
|
|
if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..."
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,,VLLS3,?..."
|
|
elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..."
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,STOP Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
endif
|
|
endif
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "PMSTAT,Power Mode Status Register"
|
|
bitfld.byte 0x00 6. " PMSTAT_VLLS ,Current power mode is VLLS" "No,Yes"
|
|
bitfld.byte 0x00 5. " PMSTAT_LLS ,Current power mode is LLS" "No,Yes"
|
|
bitfld.byte 0x00 4. " PMSTAT_VLPS ,Current power mode is VLPS" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PMSTAT_VLPW ,Current power mode is VLPW" "No,Yes"
|
|
bitfld.byte 0x00 2. " PMSTAT_VLPR ,Current power mode is VLPR" "No,Yes"
|
|
bitfld.byte 0x00 1. " PMSTAT_STOP ,Current power mode is STOP" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " PMSTAT_RUN ,Current power mode is RUN" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x4007D000
|
|
width 8.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "LVDSC1,Low Voltage Detect Status and Control 1 Register"
|
|
rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "No effect,Clear"
|
|
bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low trip,High trip,?..."
|
|
line.byte 0x01 "LVDSC2,Low Voltage Detect Status and Control 2 Register"
|
|
rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "No effect,Clear"
|
|
bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low trip,Mid 1 trip,Mid 2 trip,High trip"
|
|
line.byte 0x02 "REGSC,Regulator Status and Control Register"
|
|
sif cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")
|
|
bitfld.byte 0x02 6. " VLPO ,VLPx option" "Restricted,Unrestricted"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*")
|
|
bitfld.byte 0x02 4. " BGEN ,Bandgap enable" "Enabled,Disabled"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Disabled,Enabled"
|
|
rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stopped,Running"
|
|
bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
tree "DCDC (DCDC Converter)"
|
|
base ad:0x4005A000
|
|
width 6.
|
|
if (((per.l(ad:0x4005A000))&0x02)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "REG0,Register 0"
|
|
rbitfld.long 0x00 31. " DCDC_STS_DC_OK ,Status register to indicate DCDC lock" "No lock,Lock"
|
|
sif (cpuis("MKW41Z512VHT4*"))
|
|
bitfld.long 0x00 30. " VLPR_VLPW_CONFIG_DCDC_HP ,Selects behavior of DCDC in device VLPR and VLPW low power modes" "Pulsed mode,Continuous mode"
|
|
else
|
|
bitfld.long 0x00 30. " VLPR_VLPW_CONFIG_DCDC_HP ,Selects behavior of DCDC in device VLPR and VLPW low power modes" "Continuous mode,Pulsed mode"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW41Z512VHT4*"))
|
|
bitfld.long 0x00 29. " VLPS_CONFIG_DCDC_HP ,Selects behavior of DCDC in device VLPS low power mode" "Pulsed mode,Continuous mode"
|
|
else
|
|
bitfld.long 0x00 29. " VLPS_CONFIG_DCDC_HP ,Selects behavior of DCDC in device VLPS low power mode" "Continuous mode,Pulsed mode"
|
|
endif
|
|
rbitfld.long 0x00 28. " PSWITCH_STATUS ,Indicate PSWITCH status" "No switch,Switch"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DCDC_XTALOK_DISABLE ,Disable xtalok detection circuit" "No,Yes"
|
|
bitfld.long 0x00 26. " PWD_CMP_OFFSET ,Power down output range comparator" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DCDC_LESS_I ,Reduce DCDC current" "Not reduced,Reduced"
|
|
bitfld.long 0x00 24. " OFFSET_RSNS_LP_DISABLE ,Disable hysteresis in low power voltage sense" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OFFSET_RSNS_LP_ADJ ,Adjust hysteretic value in low power voltage sense" "No,Yes"
|
|
bitfld.long 0x00 22. " HYST_LP_CMP_DISABLE ,Disable hysteretic in low power comparator" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HYST_LP_COMP_ADJ ,Adjust hysteretic value in low power comparator" "No,Yes"
|
|
bitfld.long 0x00 19.--20. " DCDC_LP_STATE_HYS_H ,Configure the hysteretic upper threshold value in low power mode" "+0 mV,+25 mV,+50 mV,+75 mV"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " DCDC_LP_STATE_HYS_L ,Configure the hysteretic lower threshold value in low power mode" "-0 mV,-25 mV,-50 mV,-75 mV"
|
|
bitfld.long 0x00 10.--11. " DCDC_VBAT_DIV_CTRL ,Controls VBAT voltage divider" "OFF,VBAT,VBAT/2,VBAT/4"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DCDC_LP_DF_CMP_ENABLE ,Enable low power differential comparators to sense lower supply in pulse mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DCDC_PWD_OSC_INT ,Power down internal oscillator" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DCDC_SEL_CLK ,Select external clock for DCDC" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DCDC_DISABLE_AUTO_CLK_SWITCH ,Disable automatic clock switch from internal oscillator to external clock" "No,Yes"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "REG0,Register 0"
|
|
rbitfld.long 0x00 31. " DCDC_STS_DC_OK ,Status register to indicate DCDC lock" "No lock,Lock"
|
|
sif (cpuis("MKW41Z512VHT4*"))
|
|
bitfld.long 0x00 30. " VLPR_VLPW_CONFIG_DCDC_HP ,Selects behavior of DCDC in device VLPR and VLPW low power modes" "Pulsed mode,Continuous mode"
|
|
else
|
|
bitfld.long 0x00 30. " VLPR_VLPW_CONFIG_DCDC_HP ,Selects behavior of DCDC in device VLPR and VLPW low power modes" "Continuous mode,Pulsed mode"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW41Z512VHT4*"))
|
|
bitfld.long 0x00 29. " VLPS_CONFIG_DCDC_HP ,Selects behavior of DCDC in device VLPS low power mode" "Pulsed mode,Continuous mode"
|
|
else
|
|
bitfld.long 0x00 29. " VLPS_CONFIG_DCDC_HP ,Selects behavior of DCDC in device VLPS low power mode" "Continuous mode,Pulsed mode"
|
|
endif
|
|
rbitfld.long 0x00 28. " PSWITCH_STATUS ,Indicate PSWITCH status" "No switch,Switch"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DCDC_XTALOK_DISABLE ,Disable xtalok detection circuit" "No,Yes"
|
|
bitfld.long 0x00 26. " PWD_CMP_OFFSET ,Power down output range comparator" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DCDC_LESS_I ,Reduce DCDC current" "Not reduced,Reduced"
|
|
bitfld.long 0x00 24. " OFFSET_RSNS_LP_DISABLE ,Disable hysteresis in low power voltage sense" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OFFSET_RSNS_LP_ADJ ,Adjust hysteretic value in low power voltage sense" "No,Yes"
|
|
bitfld.long 0x00 22. " HYST_LP_CMP_DISABLE ,Disable hysteretic in low power comparator" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HYST_LP_COMP_ADJ ,Adjust hysteretic value in low power comparator" "No,Yes"
|
|
bitfld.long 0x00 19.--20. " DCDC_LP_STATE_HYS_H ,Configure the hysteretic upper threshold value in low power mode" "+0 mV,+25 mV,+50 mV,+75 mV"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " DCDC_LP_STATE_HYS_L ,Configure the hysteretic lower threshold value in low power mode" "-0 mV,-25 mV,-50 mV,-75 mV"
|
|
bitfld.long 0x00 10.--11. " DCDC_VBAT_DIV_CTRL ,Controls VBAT voltage divider" "OFF,VBAT,VBAT/2,VBAT/4"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DCDC_LP_DF_CMP_ENABLE ,Enable low power differential comparators to sense lower supply in pulse mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DCDC_PWD_OSC_INT ,Power down internal oscillator" "No,Yes"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 1. " DCDC_DISABLE_AUTO_CLK_SWITCH ,Disable automatic clock switch from internal oscillator to external clock" "No,Yes"
|
|
endif
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "REG1,Register 1"
|
|
bitfld.long 0x00 24. " DCDC_LOOPCTRL_EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " DCDC_LOOPCTRL_EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparators" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DCDC_LOOPCTRL_DF_HST_THRESH ,Enable hysteresis in switching converter differential mode analog comparators" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DCDC_LOOPCTRL_CM_HST_THRESH ,Enable hysteresis in switching converter common mode analog comparators" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 7.--13. 1. " POSLIMIT_BOOST_IN ,Upper limit duty cycle limit in DC-DC converter"
|
|
hexmask.long.byte 0x00 0.--6. 1. " POSLIMIT_BUCK_IN ,Upper limit duty cycle limit in DC-DC cycle"
|
|
line.long 0x04 "REG2,Register 2"
|
|
hexmask.long.word 0x04 16.--25. 1. " DCDC_BATTMONITOR_BATT_VAL ,Battery voltage"
|
|
bitfld.long 0x04 15. " DCDC_BATTMONITOR_EN_BATADJ ,Enables DC-DC to improve efficiency and minimize ripple using the information from BATT_VAL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " DCDC_LOOPCTRL_HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "Not inverted,Inverted"
|
|
sif (cpuis("MKW?1Z*"))
|
|
textline " "
|
|
bitfld.long 0x04 9.--10. " DCDC_LOOPCTRL_EN_RCSCALE ,Enable analog circuit of DC-DC convert to respond faster under transient load conditions" "0,1,2,3"
|
|
endif
|
|
line.long 0x08 "REG3,Register 3"
|
|
bitfld.long 0x08 30. " DCDC_VDD1P8CTRL_DISABLE_STEP ,Disable stepping for VDD1P8" "No,Yes"
|
|
sif (cpuis("MKW?0Z*"))
|
|
textline " "
|
|
bitfld.long 0x08 29. " DCDC_VDD1P45CTRL_DISABLE_STEP ,Disable stepping for VDD1P45" "No,Yes"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x08 29. " DCDC_VDD1P5CTRL_DISABLE_STEP ,Disable stepping for VDD1P5" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 26. " DCDC_MINPWR_HALF_FETS ,Use half switch FET for the continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DCDC_MINPWR_DOUBLE_FETS ,Use double switch FET for the continuous mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " DCDC_MINPWR_DC_HALFCLK ,Set DCDC clock to half frequency for the continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " DCDC_MINPWR_HALF_FETS_PULSED ,Use half switch FET for the pulsed mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " DCDC_MINPWR_DOUBLE_FETS_PULSED ,Use double switch FET for the pulsed mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " DCDC_MINPWR_DC_HALFCLK_PULSED ,Set DCDC clock to half frequency for the pulsed mode" "Disabled,Enabled"
|
|
sif (cpuis("MKW?0Z*"))
|
|
textline " "
|
|
bitfld.long 0x08 17.--20. " DCDC_VDD1P45CTRL_ADJTN ,Adjust value of duty cycle when switching between VDD1P45 and VDD1P8" "1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32"
|
|
bitfld.long 0x08 11.--15. " DCDC_VDD1P45CTRL_TRG_BOOST ,Target value of VDD1P45 in boost mode" "1.275 V,1.3 V,1.325 V,1.35 V,1.375 V,1.4 V,1.425 V,1.45 V,1.475 V,1.5 V,1.525 V,1.55 V,1.575 V,1.6 V,1.625 V,1.65 V,1.675 V,1.7 V,1.725 V,1.75 V,1.775 V,1.8 V,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " DCDC_VDD1P45CTRL_TRG_BUCK ,Target value of VDD1P45 in buck mode" "1.275 V,1.3 V,1.325 V,1.35 V,1.375 V,1.4 V,1.425 V,1.45 V,1.475 V,1.5 V,1.525 V,1.55 V,1.575 V,1.6 V,1.625 V,1.65 V,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x08 17.--20. " DCDC_VDD1P5CTRL_ADJTN ,Adjust value of duty cycle when switching between VDD1P5 and VDD1P8" "1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32"
|
|
bitfld.long 0x08 11.--15. " DCDC_VDD1P5CTRL_TRG_BOOST ,Target value of VDD1P5 in boost mode" "1.275 V,1.3 V,1.325 V,1.35 V,1.375 V,1.4 V,1.425 V,1.45 V,1.475 V,1.5 V,1.525 V,1.55 V,1.575 V,1.6 V,1.625 V,1.65 V,1.675 V,1.7 V,1.725 V,1.75 V,1.775 V,1.8 V,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " DCDC_VDD1P5CTRL_TRG_BUCK ,Target value of VDD1P5 in buck mode" "1.275 V,1.3 V,1.325 V,1.35 V,1.375 V,1.4 V,1.425 V,1.45 V,1.475 V,1.5 V,1.525 V,1.55 V,1.575 V,1.6 V,1.625 V,1.65 V,?..."
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW41Z512VHT4*"))
|
|
bitfld.long 0x08 0.--5. " DCDC_VDD1P8CTRL_TRG ,Target value of VDD1P8" "1.65 V,1.675 V,1.7 V,1.725 V,1.75 V,1.775 V,1.8 V,1.825 V,1.85 V,1.875 V,1.9 V,1.925 V,1.95 V,1.975 V,2.0 V,2.025 V,2.05 V,2.075 V,2.1 V,2.15 V,2.2 V,2.25 V,2.3 V,2.35 V,2.4 V,2.45 V,2.5 V,2.55 V,2.6 V,2.65 V,2.7 V,2.75 V,2.8 V,2.825 V,2.85 V,2.875 V,2.9 V,2.925 V,2.95 V,2.975 V,3.0 V,3.025 V,3.05 V,3.075 V,3.1 V,3.125 V,3.15 V,3.175 V,3.2 V,3.225 V,3.25 V,3.275 V,3.3 V,3.325 V,3.35 V,3.375 V,3.4 V,3.425 V,3.45 V,3.475 V,3.5 V,3.525 V,3.55 V,3.575 V"
|
|
else
|
|
bitfld.long 0x08 0.--5. " DCDC_VDD1P8CTRL_TRG ,Target value of VDD1P8" "1.65 V,1.675 V,1.7 V,1.725 V,1.75 V,1.775 V,1.8 V,1.825 V,1.85 V,1.875 V,1.9 V,1.925 V,1.95 V,1.975 V,2.0 V,2.025 V,2.05 V,2.075 V,,,,,,,,,,,,,,,2.8 V,2.825 V,2.85 V,2.875 V,2.9 V,2.925 V,2.95 V,2.975 V,3.0 V,3.025 V,3.05 V,3.075 V,3.1 V,3.125 V,3.15 V,3.175 V,3.2 V,3.225 V,3.25 V,3.275 V,3.3 V,3.325 V,3.35 V,3.375 V,3.4 V,3.425 V,3.45 V,3.475 V,3.5 V,3.525 V,3.55 V,3.575 V"
|
|
endif
|
|
line.long 0x0C "REG4,Register 4"
|
|
hexmask.long.word 0x0C 16.--31. 1. " UNLOCK ,Key needed to unlock HW_POWER_RESET"
|
|
bitfld.long 0x0C 0. " SW_SHUTDOWN ,Shut down DCDC in buck mode" "No,Yes"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "REG6,Register 6"
|
|
rbitfld.long 0x00 31. " PSWITCH_INT_STS ,PSWITCH edge detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PSWITCH_INT_MUTE ,Mask interrupt to SoC" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PSWITCH_INT_CLEAR ,Write 1 to clear interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " PSWITCH_INT_FALL_EN ,Enable falling edge detect for interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSWITCH_INT_RISE_EN ,Enable rising edge detect for interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "REG7,Register 7"
|
|
bitfld.long 0x04 20. " PULSE_RUN_SPEEDUP ,Enable pulse run speedup" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " INTEGRATOR_VALUE_SEL ,Select the integrator value from above register or saved value in hardware" "Hardware,This register"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--18. 1. " INTEGRATOR_VALUE ,Integrator value which can be loaded in pulse mode"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "LLWU (Low-Leakage Wakeup Unit)"
|
|
base ad:0x4007C000
|
|
width 7.
|
|
group.byte 0x00++0x06
|
|
line.byte 0x00 "PE1,LLWU Pin Enable 1 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled,Rising edge,Falling edge,Any change"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled,Rising edge,Falling edge,Any change"
|
|
line.byte 0x01 "PE2,LLWU Pin Enable 2 Register"
|
|
bitfld.byte 0x01 6.--7. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x01 4.--5. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x01 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any change"
|
|
textline " "
|
|
bitfld.byte 0x01 0.--1. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled,Rising edge,Falling edge,Any change"
|
|
line.byte 0x02 "PE3,LLWU Pin Enable 3 Register"
|
|
bitfld.byte 0x02 6.--7. " WUPE11 ,Wakeup pin enable for LLWU_P11" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x02 4.--5. " WUPE10 ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x02 2.--3. " WUPE9 ,Wakeup pin enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x02 0.--1. " WUPE8 ,Wakeup pin enable for LLWU_P8" "Disabled,Rising edge,Falling edge,Any change"
|
|
line.byte 0x03 "PE4,LLWU Pin Enable 4 Register"
|
|
bitfld.byte 0x03 6.--7. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x03 4.--5. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x03 2.--3. " WUPE13 ,Wakeup pin enable for LLWU_P13" "Disabled,Rising edge,Falling edge,Any change"
|
|
bitfld.byte 0x03 0.--1. " WUPE12 ,Wakeup pin enable for LLWU_P12" "Disabled,Rising edge,Falling edge,Any change"
|
|
line.byte 0x04 "ME,LLWU Module Enable Register"
|
|
bitfld.byte 0x04 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.byte 0x04 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x04 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
bitfld.byte 0x04 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.byte 0x04 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x04 1. " WUME1 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
bitfld.byte 0x04 0. " WUME0 ,Wakeup module enable for module 0" "Disabled,Enabled"
|
|
line.byte 0x05 "F1,LLWU Flag 1 Register"
|
|
eventfld.byte 0x05 7. " WUF7 ,Wakeup flag for LLWU_P7" "No,Yes"
|
|
eventfld.byte 0x05 6. " WUF6 ,Wakeup flag for LLWU_P6" "No,Yes"
|
|
eventfld.byte 0x05 5. " WUF5 ,Wakeup flag for LLWU_P5" "No,Yes"
|
|
textline " "
|
|
eventfld.byte 0x05 4. " WUF4 ,Wakeup flag for LLWU_P4" "No,Yes"
|
|
eventfld.byte 0x05 3. " WUF3 ,Wakeup flag for LLWU_P3" "No,Yes"
|
|
eventfld.byte 0x05 2. " WUF2 ,Wakeup flag for LLWU_P2" "No,Yes"
|
|
textline " "
|
|
eventfld.byte 0x05 1. " WUF1 ,Wakeup flag for LLWU_P1" "No,Yes"
|
|
eventfld.byte 0x05 0. " WUF0 ,Wakeup flag for LLWU_P0" "No,Yes"
|
|
line.byte 0x06 "F2,LLWU Flag 2 Register"
|
|
eventfld.byte 0x06 7. " WUF15 ,Wakeup flag for LLWU_P15" "No,Yes"
|
|
eventfld.byte 0x06 6. " WUF14 ,Wakeup flag for LLWU_P14" "No,Yes"
|
|
eventfld.byte 0x06 5. " WUF13 ,Wakeup flag for LLWU_P13" "No,Yes"
|
|
textline " "
|
|
eventfld.byte 0x06 4. " WUF12 ,Wakeup flag for LLWU_P12" "No,Yes"
|
|
eventfld.byte 0x06 3. " WUF11 ,Wakeup flag for LLWU_P11" "No,Yes"
|
|
eventfld.byte 0x06 2. " WUF10 ,Wakeup flag for LLWU_P10" "No,Yes"
|
|
textline " "
|
|
eventfld.byte 0x06 1. " WUF9 ,Wakeup flag for LLWU_P9" "No,Yes"
|
|
eventfld.byte 0x06 0. " WUF8 ,Wakeup flag for LLWU_P8" "No,Yes"
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "F3,LLWU Flag 3 Register"
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag for module 6" "No,Yes"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for module 5" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for module 4" "No,Yes"
|
|
bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "No,Yes"
|
|
bitfld.byte 0x00 2. " MWUF2 ,Wakeup flag for module 2" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for module 1" "No,Yes"
|
|
bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for module 0" "No,Yes"
|
|
group.byte 0x08++0x01
|
|
line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register"
|
|
eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No,Yes"
|
|
bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Positive edge,Negative edge,Any edge"
|
|
bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15"
|
|
line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register"
|
|
eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No,Yes"
|
|
bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Positive edge,Negative edge,Any edge"
|
|
bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15"
|
|
sif (cpuis("MKW2?D*"))
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "RST,LLWU Reset Enable Register"
|
|
bitfld.byte 0x00 1. " LLRSTE ,Low-Leakage mode RESET enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RSTFILT ,Digital filter on RESET pin" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RCM (Reset Control Module)"
|
|
base ad:0x4007F000
|
|
width 6.
|
|
rgroup.byte 0x00++0x01
|
|
line.byte 0x00 "SRS0,System Reset Status Register 0"
|
|
bitfld.byte 0x00 7. " POR ,Power-on reset" "Not caused,Caused"
|
|
bitfld.byte 0x00 6. " PIN ,External reset pin" "Not caused,Caused"
|
|
bitfld.byte 0x00 5. " WDOG ,Watchdog" "Not caused,Caused"
|
|
sif (!cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*"))
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LOL ,Loss-of-lock reset" "Not caused,Caused"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "Not caused,Caused"
|
|
bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused"
|
|
line.byte 0x01 "SRS1,System Reset Status Register 1"
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x01 7. " TAMPER ,Tamper detect" "Not caused,Caused"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "Not caused,Caused"
|
|
sif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x01 4. " EZPT ,EzPort reset" "Not caused,Caused"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "Not caused,Caused"
|
|
bitfld.byte 0x01 2. " SW ,Software" "Not caused,Caused"
|
|
bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "Not caused,Caused"
|
|
sif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x01 0. " JTAG ,JTAG generated reset" "Not caused,Caused"
|
|
endif
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "RPFC,Reset Pin Filter Control register"
|
|
bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "Disabled,Bus clock filter enabled,LPO clock filter enabled,?..."
|
|
line.byte 0x01 "RPFW,Reset Pin Filter Width register"
|
|
bitfld.byte 0x01 0.--4. " RSTFLTSEL ,Selects the reset pin bus clock filter width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
sif (cpuis("MKW2?D*"))
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "MR,Mode Register"
|
|
bitfld.byte 0x00 1. " EZP_MS ,EZP_MS_B pin state" "Deasserted,Asserted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCM (Miscellaneous Control Module)"
|
|
sif (cpuis("MKW2?D*"))
|
|
base ad:0xE0080000
|
|
else
|
|
base ad:0xF0003000
|
|
endif
|
|
width 7.
|
|
rgroup.word 0x08++0x03
|
|
line.word 0x00 "PLASC,Crossbar switch (AXBS) slave configuration"
|
|
bitfld.word 0x00 7. " ASC[7] ,Connection to the crossbar switch's slave input port 7" "Not connected,Connected"
|
|
bitfld.word 0x00 6. " [6] ,Connection to the crossbar switch's slave input port 6" "Not connected,Connected"
|
|
bitfld.word 0x00 5. " [5] ,Connection to the crossbar switch's slave input port 5" "Not connected,Connected"
|
|
bitfld.word 0x00 4. " [4] ,Connection to the crossbar switch's slave input port 4" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.word 0x00 3. " [3] ,Connection to the crossbar switch's slave input port 3" "Not connected,Connected"
|
|
bitfld.word 0x00 2. " [2] ,Connection to the crossbar switch's slave input port 2" "Not connected,Connected"
|
|
bitfld.word 0x00 1. " [1] ,Connection to the crossbar switch's slave input port 1" "Not connected,Connected"
|
|
bitfld.word 0x00 0. " [0] ,Connection to the crossbar switch's slave input port 0" "Not connected,Connected"
|
|
line.word 0x02 "PLAMC,Crossbar switch (AXBS) master configuration"
|
|
bitfld.word 0x02 7. " AMC[7] ,Connection to the AXBS master input port 7" "Not connected,Connected"
|
|
bitfld.word 0x02 6. " [6] ,Connection to the AXBS master input port 6" "Not connected,Connected"
|
|
bitfld.word 0x02 5. " [5] ,Connection to the AXBS master input port 5" "Not connected,Connected"
|
|
bitfld.word 0x02 4. " [4] ,Connection to the AXBS master input port 4" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.word 0x02 3. " [3] ,Connection to the AXBS master input port 3" "Not connected,Connected"
|
|
bitfld.word 0x02 2. " [2] ,Connection to the AXBS master input port 2" "Not connected,Connected"
|
|
bitfld.word 0x02 1. " [1] ,Connection to the AXBS master input port 1" "Not connected,Connected"
|
|
bitfld.word 0x02 0. " [0] ,Connection to the AXBS master input port 0" "Not connected,Connected"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLACR,Platform Control Register"
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 16. " ESFC ,Enable stalling flash controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DFCS ,Disable flash controller speculation" "No,Yes"
|
|
bitfld.long 0x00 14. " EFDS ,Enable flash data speculation" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DFCC ,Disable flash controller cache" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DFCIC ,Disable flash controller instruction caching" "No,Yes"
|
|
bitfld.long 0x00 11. " DFCDA ,Disable flash controller data caching" "No,Yes"
|
|
bitfld.long 0x00 10. " CFCC ,Clear flash controller cache" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " ARB ,Arbitration select" "Fixed-priority,Round-robin"
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. " CPOWOI ,Compute operation wake-up on interrupt" "No effect,CPOREQ cleared"
|
|
rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge [Entry/Exit]" "Not completed/Completed,Completed/Not completed"
|
|
bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Cleared,Requested"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
tree.open "MTB (Micro Trace Buffer)"
|
|
tree "MTB_RAM"
|
|
base ad:0xF0000000
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "POSITION,MTB Position Register"
|
|
hexmask.long 0x00 3.--14. 0x08 " POINTER ,Trace packet address pointer"
|
|
bitfld.long 0x00 2. " WRAP ,POINTER value wraps" "Not occured,Occured"
|
|
line.long 0x04 "MASTER,MTB Master Register"
|
|
bitfld.long 0x04 31. " EN ,Main trace enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " HALTREQ ,Halt request" "Not occured,Occured"
|
|
bitfld.long 0x04 8. " RAMPRIV ,RAM privilege" "User or privileged AHB permitted,Only privileged AHB permitted"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SFRWPRIV ,Special function register write privilege" "User or privileged AHB permitted,Only privileged AHB permitted"
|
|
bitfld.long 0x04 6. " TSTOPEN ,Trace stop input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " TSTARTEN ,Trace start input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "FLOW,MTB Flow Register"
|
|
hexmask.long 0x08 3.--31. 1. " WATERMARK ,Watermark"
|
|
bitfld.long 0x08 1. " AUTOHALT ,Autohalt" "Not forced,Forced"
|
|
bitfld.long 0x08 0. " AUTOSTOP ,Autostop" "Not forced,Forced"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BASE,MTB Base Register"
|
|
rgroup.long 0x0F00++0x03
|
|
line.long 0x00 "MODECTRL,Integration Mode Control Register"
|
|
rgroup.long 0x0FA0++0x07
|
|
line.long 0x00 "TAGSET,Claim TAG Set Register"
|
|
line.long 0x04 "TAGCLEAR,Claim TAG Clear Register"
|
|
rgroup.long 0x0FB0++0x0F
|
|
line.long 0x00 "LOCKACCESS,Lock Access Register"
|
|
line.long 0x04 "LOCKSTAT,Lock Status Register"
|
|
line.long 0x08 "AUTHSTAT,Authentication Status Register"
|
|
bitfld.long 0x08 2. " BIT2 ,Bit 2" "Not connected to NIDEN/DBGEN,Connected to NIDEN/DBGEN"
|
|
bitfld.long 0x08 0. " BIT0 ,Bit 0" "Not connected to DBGEN,Connected to DBGEN"
|
|
line.long 0x0C "DEVICEARCH,Device Architecture Register"
|
|
rgroup.long 0x0FC8++0x07
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
line.long 0x04 "DEVICETYPID,Device Type Identifier Register"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PERIPHID4,Peripheral ID 4 Register"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "PERIPHID5,Peripheral ID 5 Register"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "PERIPHID6,Peripheral ID 6 Register"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "PERIPHID7,Peripheral ID 7 Register"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PERIPHID0,Peripheral ID 0 Register"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PERIPHID1,Peripheral ID 1 Register"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PERIPHID2,Peripheral ID 2 Register"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PERIPHID3,Peripheral ID 3 Register"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "COMPID0,Component ID 0 Register"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "COMPID1,Component ID 1 Register"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "COMPID2,Component ID 2 Register"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "COMPID3,Component ID 3 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MTB_DWT"
|
|
base ad:0xF0001000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCMP ,Number of comparators" ",,2,?..."
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Trace sample and exception trace support" ",Not supported"
|
|
bitfld.long 0x00 26. " NOEXTTRIG ,External match signals support" ",Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Cycle counter support" ",Not supported"
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Profiling counters support" ",Not supported"
|
|
bitfld.long 0x00 22. " CYCEBTENA ,POSTCNT underflow packets generation enable" "Disabled,"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Folded instruction counter overflow generation enable" "Disabled,"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,LSU counter overflow events enable" "Disabled,"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Sleep counter overflow events enable" "Disabled,"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Exception overhead counter events enable" "Disabled,"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,CPI counter overflow events enable" "Disabled,"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Generation of exception trace enable" "Disabled,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Periodic PC sample packets generation enable" "Disabled,"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Synchronization packets" "Not supported,?..."
|
|
bitfld.long 0x00 9. " CYCTAP ,Cycle counter support" "Not supported,"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Cycle counter support" "Not supported,?..."
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,POSTPREST" "Not supported,?..."
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Cycle counter enable" "Disabled,"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "COMP0,Comparator 0 Register"
|
|
line.long 0x04 "MASK0,Comparator 0 Mask Register"
|
|
bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "FCT0,Comparator Function Register 0"
|
|
rbitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 12.--15. " DATAVADDR0 ,Data value address 0" "0,1,?..."
|
|
bitfld.long 0x08 10.--11. " DATAVSIZE ,Data value size" "Byte,Halfword,Word,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8. " DATAVMATCH ,Data value match" "Address comparison,Data value comparison"
|
|
bitfld.long 0x08 0.--3. " FUNCTION ,Function" "Disabled,,,,Instruction fetch,Data operand read,Data operand write,Data operand read & write,?..."
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "COMP1,Comparator 1 Register"
|
|
line.long 0x04 "MASK1,Comparator 1 Mask Register"
|
|
bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "FCT1,Comparator Function Register 1"
|
|
rbitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION ,Function" "Disabled,,,,Instruction fetch,Data operand read,Data operand write,Data operand read & write,?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TBCTRL,Trace Buffer Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators" ",2,?..."
|
|
bitfld.long 0x00 1. " ACOMP1 ,Action based on comparator 1 match" "TSTOP,TSTART"
|
|
bitfld.long 0x00 0. " ACOMP0 , Action based on comparator 0 match" "TSTOP,TSTART"
|
|
rgroup.long 0xFC8++0x07
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
line.long 0x04 "DEVICETYPID,Device Type Identifier Register"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PERIPHID4,Peripheral ID 4 Register"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "PERIPHID5,Peripheral ID 5 Register"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "PERIPHID6,Peripheral ID 6 Register"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "PERIPHID7,Peripheral ID 7 Register"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PERIPHID0,Peripheral ID 0 Register"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PERIPHID1,Peripheral ID 1 Register"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PERIPHID2,Peripheral ID 2 Register"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PERIPHID3,Peripheral ID 3 Register"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "COMPID0,Component ID 0 Register"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "COMPID1,Component ID 1 Register"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "COMPID2,Component ID 2 Register"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "COMPID3,Component ID 3 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "System ROM"
|
|
base ad:0xF0002000
|
|
width 13.
|
|
sif cpuis("K32W0?2S1M*")
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "ENTRY_0,Entry Register 0"
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "ENTRY_1,Entry Register 1"
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "ENTRY_2,Entry Register 2"
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "ENTRY_3,Entry Register 3"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "ENTRY_0,Entry Register 0"
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "ENTRY_1,Entry Register 1"
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "ENTRY_2,Entry Register 2"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TABLEMARK,End Of Table Marker Register"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "SYSACCESS,System Access Register"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PERIPHID_4,Peripheral ID Register 4"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "PERIPHID_5,Peripheral ID Register 5"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "PERIPHID_6,Peripheral ID Register 6"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "PERIPHID_7,Peripheral ID Register 7"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PERIPHID_0,Peripheral ID Register 0"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PERIPHID_1,Peripheral ID Register 1"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PERIPHID_2,Peripheral ID Register 2"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PERIPHID_3,Peripheral ID Register 3"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "COMPID_0,Component ID Register 0"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "COMPID_1,Component ID Register 1"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "COMPID_2,Component ID Register 2"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "COMPID_3,Component ID Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "DMAMUX (Direct Memory Access Multiplexer)"
|
|
base ad:0x40021000
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
width 9.
|
|
if (((per.b(ad:0x40021000+0x0))&0x80)==0x80)
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG0,Channel 0 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 0 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 0 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG0,Channel 0 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 0 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 0 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x1))&0x80)==0x80)
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG1,Channel 1 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG1,Channel 1 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 1 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x2))&0x80)==0x80)
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG2,Channel 2 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 2 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG2,Channel 2 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 2 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x3))&0x80)==0x80)
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG3,Channel 3 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 3 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 3 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG3,Channel 3 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 3 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 3 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
elif (cpuis("MKW2?D*"))
|
|
width 9.
|
|
if (((per.b(ad:0x40021000+0x0))&0x80)==0x80)
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG0,Channel 0 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 0 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 0 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG0,Channel 0 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 0 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 0 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x1))&0x80)==0x80)
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG1,Channel 1 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG1,Channel 1 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 1 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x2))&0x80)==0x80)
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG2,Channel 2 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 2 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG2,Channel 2 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 2 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x3))&0x80)==0x80)
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG3,Channel 3 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 3 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 3 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG3,Channel 3 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 3 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 3 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x4))&0x80)==0x80)
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "CHCFG4,Channel 4 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 4 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 4 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "CHCFG4,Channel 4 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 4 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 4 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x5))&0x80)==0x80)
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "CHCFG5,Channel 5 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 5 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 5 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "CHCFG5,Channel 5 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 5 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 5 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x6))&0x80)==0x80)
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "CHCFG6,Channel 6 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 6 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 6 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "CHCFG6,Channel 6 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 6 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 6 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x7))&0x80)==0x80)
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "CHCFG7,Channel 7 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 7 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 7 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "CHCFG7,Channel 7 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 7 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 7 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x8))&0x80)==0x80)
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "CHCFG8,Channel 8 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 8 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 8 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "CHCFG8,Channel 8 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 8 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 8 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0x9))&0x80)==0x80)
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "CHCFG9,Channel 9 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 9 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 9 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "CHCFG9,Channel 9 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 9 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 9 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0xA))&0x80)==0x80)
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "CHCFG10,Channel 10 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 10 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 10 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "CHCFG10,Channel 10 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 10 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 10 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0xB))&0x80)==0x80)
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "CHCFG11,Channel 11 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 11 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 11 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "CHCFG11,Channel 11 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 11 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 11 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0xC))&0x80)==0x80)
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "CHCFG12,Channel 12 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 12 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 12 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "CHCFG12,Channel 12 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 12 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 12 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0xD))&0x80)==0x80)
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "CHCFG13,Channel 13 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 13 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 13 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "CHCFG13,Channel 13 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 13 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 13 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0xE))&0x80)==0x80)
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "CHCFG14,Channel 14 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 14 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 14 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "CHCFG14,Channel 14 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 14 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 14 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40021000+0xF))&0x80)==0x80)
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "CHCFG15,Channel 15 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 15 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 15 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "CHCFG15,Channel 15 Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 15 enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " TRIG ,DMA channel 15 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW01Z128*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,TPM0 ch. 4,TPM0 ch. 5,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,,,Port A,,Port C,Port D,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW2?D*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "Disabled,,UART0 Rx,UART0 Tx,UART1 Rx,UART1 Tx,UART2 Rx,UART2 Tx,,,,,,,I2S0 Rx,I2S0 Tx,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,,,I2C0,I2C1,FTM0 ch. 0,FTM0 ch. 1,FTM0 ch. 2,FTM0 ch. 3,FTM0 ch. 4,FTM0 ch. 5,FTM0 ch. 6,FTM0 ch. 7,FTM1 ch. 0,FTM1 ch. 1,FTM2 ch. 0,FTM2 ch. 1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW20Z*")||cpuis("MKW30Z*")||cpuis("MKW40Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "Disabled,,UART0 Rx,UART0 Tx,,,,,,,,,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif (cpuis("MKW21Z*")||cpuis("MKW31Z*")||cpuis("MKW41Z*"))
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "Disabled,,LPUART0 Rx,LPUART0 Tx,,,,,,,,2.4G Radio,,,,,SPI0 Rx,SPI0 Tx,SPI1 Rx,SPI1 Tx,AESA Input FIFO,AESA Output FIFO,I2C0,I2C1,TPM0 ch. 0,TPM0 ch. 1,TPM0 ch. 2,TPM0 ch. 3,,,,,TPM1 ch. 0,TPM1 ch. 1,TPM2 ch. 0,TPM2 ch. 1,,,,,ADC0,,CMP0,,,DAC0,,CMT,,Port A,Port B,Port C,,,TPM0 Overflow,TPM1 Overflow,TPM2 Overflow,TSI0,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*"))
|
|
tree "eDMA (Enhanced Direct Memory Access)"
|
|
base ad:0x40008000
|
|
sif (cpuis("MKW?1Z*"))
|
|
width 10.
|
|
tree "eDMA Control and Status Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
sif (cpuis("MWK?1Z*"))
|
|
rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing channel"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " CX ,Cancel transfer" "Not cancelled,Cancelled"
|
|
bitfld.long 0x00 16. " ECX ,Error cancel transfer" "Not cancelled,Cancelled"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted"
|
|
bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error"
|
|
bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error"
|
|
bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error"
|
|
bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error"
|
|
bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error"
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 3. " ERQ3 ,Enable DMA request 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERQ2 ,Enable DMA request 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERQ1 ,Enable DMA request 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERQ0 ,Enable DMA request 0" "Disabled,Enabled"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
bitfld.long 0x00 31. " ERQ31 ,Enable DMA request 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ERQ30 ,Enable DMA request 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ERQ29 ,Enable DMA request 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ERQ28 ,Enable DMA request 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ERQ27 ,Enable DMA request 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ERQ26 ,Enable DMA request 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ERQ25 ,Enable DMA request 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERQ24 ,Enable DMA request 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ERQ23 ,Enable DMA request 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ERQ22 ,Enable DMA request 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ERQ21 ,Enable DMA request 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ERQ20 ,Enable DMA request 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERQ19 ,Enable DMA request 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ERQ18 ,Enable DMA request 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ERQ17 ,Enable DMA request 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ERQ16 ,Enable DMA request 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ERQ15 ,Enable DMA request 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERQ14 ,Enable DMA request 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERQ13 ,Enable DMA request 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ERQ12 ,Enable DMA request 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ERQ11 ,Enable DMA request 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ERQ10 ,Enable DMA request 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ERQ9 ,Enable DMA request 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERQ8 ,Enable DMA request 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERQ7 ,Enable DMA request 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ERQ6 ,Enable DMA request 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERQ5 ,Enable DMA request 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERQ4 ,Enable DMA request 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ERQ3 ,Enable DMA request 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERQ2 ,Enable DMA request 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERQ1 ,Enable DMA request 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ERQ0 ,Enable DMA request 0" "Disabled,Enabled"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " ERQ15 ,Enable DMA request 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERQ14 ,Enable DMA request 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERQ13 ,Enable DMA request 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ERQ12 ,Enable DMA request 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ERQ11 ,Enable DMA request 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ERQ10 ,Enable DMA request 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ERQ9 ,Enable DMA request 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERQ8 ,Enable DMA request 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ERQ7 ,Enable DMA request 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ERQ6 ,Enable DMA request 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERQ5 ,Enable DMA request 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ERQ4 ,Enable DMA request 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERQ3 ,Enable DMA request 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERQ2 ,Enable DMA request 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERQ1 ,Enable DMA request 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERQ0 ,Enable DMA request 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 3. " EEI3 ,Enable error interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EEI2 ,Enable error interrupt 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EEI1 ,Enable error interrupt 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EEI0 ,Enable error interrupt 0" "Disabled,Enabled"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
bitfld.long 0x00 31. " EEI31 ,Enable error interrupt 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EEI30 ,Enable error interrupt 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " EEI29 ,Enable error interrupt 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EEI28 ,Enable error interrupt 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EEI27 ,Enable error interrupt 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EEI26 ,Enable error interrupt 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EEI25 ,Enable error interrupt 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EEI24 ,Enable error interrupt 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " EEI23 ,Enable error interrupt 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EEI22 ,Enable error interrupt 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " EEI21 ,Enable error interrupt 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EEI20 ,Enable error interrupt 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EEI19 ,Enable error interrupt 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EEI18 ,Enable error interrupt 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " EEI17 ,Enable error interrupt 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EEI16 ,Enable error interrupt 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EEI15 ,Enable error interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EEI14 ,Enable error interrupt 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EEI13 ,Enable error interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EEI12 ,Enable error interrupt 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EEI11 ,Enable error interrupt 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EEI10 ,Enable error interrupt 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EEI9 ,Enable error interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EEI8 ,Enable error interrupt 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EEI7 ,Enable error interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EEI6 ,Enable error interrupt 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EEI5 ,Enable error interrupt 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EEI4 ,Enable error interrupt 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EEI3 ,Enable error interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EEI2 ,Enable error interrupt 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EEI1 ,Enable error interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EEI0 ,Enable error interrupt 0" "Disabled,Enabled"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " EEI15 ,Enable error interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EEI14 ,Enable error interrupt 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EEI13 ,Enable error interrupt 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EEI12 ,Enable error interrupt 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EEI11 ,Enable error interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EEI10 ,Enable error interrupt 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EEI9 ,Enable error interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EEI8 ,Enable error interrupt 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EEI7 ,Enable error interrupt 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EEI6 ,Enable error interrupt 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EEI5 ,Enable error interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EEI4 ,Enable error interrupt 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EEI3 ,Enable error interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EEI2 ,Enable error interrupt 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EEI1 ,Enable error interrupt 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EEI0 ,Enable error interrupt 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.byte 0x18++0x07
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x01 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x02 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ only,ALL bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x03 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SERQ only only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x03 0.--1. " SERQ ,Set enable request [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x03 0.--4. " SERQ ,Set enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x03 0.--3. " SERQ ,Set enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x04 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x04 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CDNE only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x04 0.--1. " CDNE ,Clear DONE bits [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x05 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x05 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x05 6. " SAST ,Set All START bits" "SSRT only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x05 0.--1. " SSRT ,Set START bits [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x05 0.--4. " SSRT ,Set START bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x05 0.--3. " SSRT ,Set START bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x06 "CERR,Clear Error Register"
|
|
bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x07 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CINT only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt request 3" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt request 2" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt request 1" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt request 0" "Not requested,Requested"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
eventfld.long 0x00 31. " INT31 ,Interrupt request 31" "Not requested,Requested"
|
|
eventfld.long 0x00 30. " INT30 ,Interrupt request 30" "Not requested,Requested"
|
|
eventfld.long 0x00 29. " INT29 ,Interrupt request 29" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 28. " INT28 ,Interrupt request 28" "Not requested,Requested"
|
|
eventfld.long 0x00 27. " INT27 ,Interrupt request 27" "Not requested,Requested"
|
|
eventfld.long 0x00 26. " INT26 ,Interrupt request 26" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 25. " INT25 ,Interrupt request 25" "Not requested,Requested"
|
|
eventfld.long 0x00 24. " INT24 ,Interrupt request 24" "Not requested,Requested"
|
|
eventfld.long 0x00 23. " INT23 ,Interrupt request 23" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 22. " INT22 ,Interrupt request 22" "Not requested,Requested"
|
|
eventfld.long 0x00 21. " INT21 ,Interrupt request 21" "Not requested,Requested"
|
|
eventfld.long 0x00 20. " INT20 ,Interrupt request 20" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 19. " INT19 ,Interrupt request 19" "Not requested,Requested"
|
|
eventfld.long 0x00 18. " INT18 ,Interrupt request 18" "Not requested,Requested"
|
|
eventfld.long 0x00 17. " INT17 ,Interrupt request 17" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 16. " INT16 ,Interrupt request 16" "Not requested,Requested"
|
|
eventfld.long 0x00 15. " INT15 ,Interrupt request 15" "Not requested,Requested"
|
|
eventfld.long 0x00 14. " INT14 ,Interrupt request 14" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INT13 ,Interrupt request 13" "Not requested,Requested"
|
|
eventfld.long 0x00 12. " INT12 ,Interrupt request 12" "Not requested,Requested"
|
|
eventfld.long 0x00 11. " INT11 ,Interrupt request 11" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 10. " INT10 ,Interrupt request 10" "Not requested,Requested"
|
|
eventfld.long 0x00 9. " INT9 ,Interrupt request 9" "Not requested,Requested"
|
|
eventfld.long 0x00 8. " INT8 ,Interrupt request 8" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 7. " INT7 ,Interrupt request 7" "Not requested,Requested"
|
|
eventfld.long 0x00 6. " INT6 ,Interrupt request 6" "Not requested,Requested"
|
|
eventfld.long 0x00 5. " INT5 ,Interrupt request 5" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 4. " INT4 ,Interrupt request 4" "Not requested,Requested"
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt request 3" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt request 2" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt request 1" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt request 0" "Not requested,Requested"
|
|
elif (cpuis("MKW2?D*"))
|
|
eventfld.long 0x00 15. " INT15 ,Interrupt request 15" "Not requested,Requested"
|
|
eventfld.long 0x00 14. " INT14 ,Interrupt request 14" "Not requested,Requested"
|
|
eventfld.long 0x00 13. " INT13 ,Interrupt request 13" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 12. " INT12 ,Interrupt request 12" "Not requested,Requested"
|
|
eventfld.long 0x00 11. " INT11 ,Interrupt request 11" "Not requested,Requested"
|
|
eventfld.long 0x00 10. " INT10 ,Interrupt request 10" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 9. " INT9 ,Interrupt request 9" "Not requested,Requested"
|
|
eventfld.long 0x00 8. " INT8 ,Interrupt request 8" "Not requested,Requested"
|
|
eventfld.long 0x00 7. " INT7 ,Interrupt request 7" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 6. " INT6 ,Interrupt request 6" "Not requested,Requested"
|
|
eventfld.long 0x00 5. " INT5 ,Interrupt request 5" "Not requested,Requested"
|
|
eventfld.long 0x00 4. " INT4 ,Interrupt request 4" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt request 3" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt request 2" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt request 1" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt request 0" "Not requested,Requested"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ERR,Error Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
eventfld.long 0x00 3. " ERR3 ,Error in channel 3" "No error,Error"
|
|
eventfld.long 0x00 2. " ERR2 ,Error in channel 2" "No error,Error"
|
|
eventfld.long 0x00 1. " ERR1 ,Error in channel 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ERR0 ,Error in channel 0" "No error,Error"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
eventfld.long 0x00 31. " ERR31 ,Error in channel 31" "No error,Error"
|
|
eventfld.long 0x00 30. " ERR30 ,Error in channel 30" "No error,Error"
|
|
eventfld.long 0x00 29. " ERR29 ,Error in channel 29" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 28. " ERR28 ,Error in channel 28" "No error,Error"
|
|
eventfld.long 0x00 27. " ERR27 ,Error in channel 27" "No error,Error"
|
|
eventfld.long 0x00 26. " ERR26 ,Error in channel 26" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ERR25 ,Error in channel 25" "No error,Error"
|
|
eventfld.long 0x00 24. " ERR24 ,Error in channel 24" "No error,Error"
|
|
eventfld.long 0x00 23. " ERR23 ,Error in channel 23" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ERR22 ,Error in channel 22" "No error,Error"
|
|
eventfld.long 0x00 21. " ERR21 ,Error in channel 21" "No error,Error"
|
|
eventfld.long 0x00 20. " ERR20 ,Error in channel 20" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ERR19 ,Error in channel 19" "No error,Error"
|
|
eventfld.long 0x00 18. " ERR18 ,Error in channel 18" "No error,Error"
|
|
eventfld.long 0x00 17. " ERR17 ,Error in channel 17" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ERR16 ,Error in channel 16" "No error,Error"
|
|
eventfld.long 0x00 15. " ERR15 ,Error in channel 15" "No error,Error"
|
|
eventfld.long 0x00 14. " ERR14 ,Error in channel 14" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ERR13 ,Error in channel 13" "No error,Error"
|
|
eventfld.long 0x00 12. " ERR12 ,Error in channel 12" "No error,Error"
|
|
eventfld.long 0x00 11. " ERR11 ,Error in channel 11" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ERR10 ,Error in channel 10" "No error,Error"
|
|
eventfld.long 0x00 9. " ERR9 ,Error in channel 9" "No error,Error"
|
|
eventfld.long 0x00 8. " ERR8 ,Error in channel 8" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ERR7 ,Error in channel 7" "No error,Error"
|
|
eventfld.long 0x00 6. " ERR6 ,Error in channel 6" "No error,Error"
|
|
eventfld.long 0x00 5. " ERR5 ,Error in channel 5" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ERR4 ,Error in channel 4" "No error,Error"
|
|
eventfld.long 0x00 3. " ERR3 ,Error in channel 3" "No error,Error"
|
|
eventfld.long 0x00 2. " ERR2 ,Error in channel 2" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERR1 ,Error in channel 1" "No error,Error"
|
|
eventfld.long 0x00 0. " ERR0 ,Error in channel 0" "No error,Error"
|
|
elif (cpuis("MKW2?D*"))
|
|
eventfld.long 0x00 15. " ERR15 ,Error in channel 15" "No error,Error"
|
|
eventfld.long 0x00 14. " ERR14 ,Error in channel 14" "No error,Error"
|
|
eventfld.long 0x00 13. " ERR13 ,Error in channel 13" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 12. " ERR12 ,Error in channel 12" "No error,Error"
|
|
eventfld.long 0x00 11. " ERR11 ,Error in channel 11" "No error,Error"
|
|
eventfld.long 0x00 10. " ERR10 ,Error in channel 10" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ERR9 ,Error in channel 9" "No error,Error"
|
|
eventfld.long 0x00 8. " ERR8 ,Error in channel 8" "No error,Error"
|
|
eventfld.long 0x00 7. " ERR7 ,Error in channel 7" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ERR6 ,Error in channel 6" "No error,Error"
|
|
eventfld.long 0x00 5. " ERR5 ,Error in channel 5" "No error,Error"
|
|
eventfld.long 0x00 4. " ERR4 ,Error in channel 4" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERR3 ,Error in channel 3" "No error,Error"
|
|
eventfld.long 0x00 2. " ERR2 ,Error in channel 2" "No error,Error"
|
|
eventfld.long 0x00 1. " ERR1 ,Error in channel 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ERR0 ,Error in channel 0" "No error,Error"
|
|
endif
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 31. " HRS31 ,Hardware request status channel 31" "Not present,Present"
|
|
bitfld.long 0x00 30. " HRS30 ,Hardware request status channel 30" "Not present,Present"
|
|
bitfld.long 0x00 29. " HRS29 ,Hardware request status channel 29" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 28. " HRS28 ,Hardware request status channel 28" "Not present,Present"
|
|
bitfld.long 0x00 27. " HRS27 ,Hardware request status channel 27" "Not present,Present"
|
|
bitfld.long 0x00 26. " HRS26 ,Hardware request status channel 26" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HRS25 ,Hardware request status channel 25" "Not present,Present"
|
|
bitfld.long 0x00 24. " HRS24 ,Hardware request status channel 24" "Not present,Present"
|
|
bitfld.long 0x00 23. " HRS23 ,Hardware request status channel 23" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 22. " HRS22 ,Hardware request status channel 22" "Not present,Present"
|
|
bitfld.long 0x00 21. " HRS21 ,Hardware request status channel 21" "Not present,Present"
|
|
bitfld.long 0x00 20. " HRS20 ,Hardware request status channel 20" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HRS19 ,Hardware request status channel 19" "Not present,Present"
|
|
bitfld.long 0x00 18. " HRS18 ,Hardware request status channel 18" "Not present,Present"
|
|
bitfld.long 0x00 17. " HRS17 ,Hardware request status channel 17" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HRS16 ,Hardware request status channel 16" "Not present,Present"
|
|
bitfld.long 0x00 15. " HRS15 ,Hardware request status channel 15" "Not present,Present"
|
|
bitfld.long 0x00 14. " HRS14 ,Hardware request status channel 14" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HRS13 ,Hardware request status channel 13" "Not present,Present"
|
|
bitfld.long 0x00 12. " HRS12 ,Hardware request status channel 12" "Not present,Present"
|
|
bitfld.long 0x00 11. " HRS11 ,Hardware request status channel 11" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HRS10 ,Hardware request status channel 10" "Not present,Present"
|
|
bitfld.long 0x00 9. " HRS9 ,Hardware request status channel 9" "Not present,Present"
|
|
bitfld.long 0x00 8. " HRS8 ,Hardware request status channel 8" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HRS7 ,Hardware request status channel 7" "Not present,Present"
|
|
bitfld.long 0x00 6. " HRS6 ,Hardware request status channel 6" "Not present,Present"
|
|
bitfld.long 0x00 5. " HRS5 ,Hardware request status channel 5" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HRS4 ,Hardware request status channel 4" "Not present,Present"
|
|
bitfld.long 0x00 3. " HRS3 ,Hardware request status channel 3" "Not present,Present"
|
|
bitfld.long 0x00 2. " HRS2 ,Hardware request status channel 2" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HRS1 ,Hardware request status channel 1" "Not present,Present"
|
|
bitfld.long 0x00 0. " HRS0 ,Hardware request status channel 0" "Not present,Present"
|
|
elif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 3. " HRS3 ,Hardware request status channel 3" "Not present,Present"
|
|
bitfld.long 0x00 2. " HRS2 ,Hardware request status channel 2" "Not present,Present"
|
|
bitfld.long 0x00 1. " HRS1 ,Hardware request status channel 1" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HRS0 ,Hardware request status channel 0" "Not present,Present"
|
|
elif (cpuis("MKW2?D*"))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 15. " HRS15 ,Hardware request status channel 15" "Not present,Present"
|
|
bitfld.long 0x00 14. " HRS14 ,Hardware request status channel 14" "Not present,Present"
|
|
bitfld.long 0x00 13. " HRS13 ,Hardware request status channel 13" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HRS12 ,Hardware request status channel 12" "Not present,Present"
|
|
bitfld.long 0x00 11. " HRS11 ,Hardware request status channel 11" "Not present,Present"
|
|
bitfld.long 0x00 10. " HRS10 ,Hardware request status channel 10" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HRS9 ,Hardware request status channel 9" "Not present,Present"
|
|
bitfld.long 0x00 8. " HRS8 ,Hardware request status channel 8" "Not present,Present"
|
|
bitfld.long 0x00 7. " HRS7 ,Hardware request status channel 7" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HRS6 ,Hardware request status channel 6" "Not present,Present"
|
|
bitfld.long 0x00 5. " HRS5 ,Hardware request status channel 5" "Not present,Present"
|
|
bitfld.long 0x00 4. " HRS4 ,Hardware request status channel 4" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HRS3 ,Hardware request status channel 3" "Not present,Present"
|
|
bitfld.long 0x00 2. " HRS2 ,Hardware request status channel 2" "Not present,Present"
|
|
bitfld.long 0x00 1. " HRS1 ,Hardware request status channel 1" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HRS0 ,Hardware request status channel 0" "Not present,Present"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 3. " EDREQ_3 ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EDREQ_2 ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EDREQ_1 ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDREQ_0 ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
bitfld.long 0x00 31. " EDREQ_31 ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EDREQ_30 ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " EDREQ_29 ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EDREQ_28 ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EDREQ_27 ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EDREQ_26 ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDREQ_25 ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EDREQ_24 ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " EDREQ_23 ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EDREQ_22 ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " EDREQ_21 ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EDREQ_20 ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDREQ_19 ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EDREQ_18 ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " EDREQ_17 ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EDREQ_16 ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EDREQ_15 ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EDREQ_14 ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDREQ_13 ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EDREQ_12 ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EDREQ_11 ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EDREQ_10 ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EDREQ_9 ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EDREQ_8 ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDREQ_7 ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EDREQ_6 ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EDREQ_5 ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EDREQ_4 ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EDREQ_3 ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EDREQ_2 ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDREQ_1 ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDREQ_0 ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " EDREQ_15 ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EDREQ_14 ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EDREQ_13 ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EDREQ_12 ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EDREQ_11 ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EDREQ_10 ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EDREQ_9 ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EDREQ_8 ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EDREQ_7 ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EDREQ_6 ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EDREQ_5 ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EDREQ_4 ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EDREQ_3 ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EDREQ_2 ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EDREQ_1 ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDREQ_0 ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 10.
|
|
tree "DMA Channel Priority Registers"
|
|
sif ((cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FX512VDC12")||(cpu()=="MK64FX512VLL12")||(cpu()=="MK64FX512VLQ12")||(cpu()=="MK64FX512VMD12")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV31F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||(cpuis("MKW2?D*")))
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "DCHPRI3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "DCHPRI2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "DCHPRI1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "DCHPRI0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "DCHPRI7,Channel 7 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "DCHPRI6,Channel 6 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "DCHPRI5,Channel 5 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "DCHPRI4,Channel 4 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "DCHPRI11,Channel 11 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "DCHPRI10,Channel 10 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "DCHPRI9,Channel 9 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "DCHPRI8,Channel 8 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "DCHPRI15,Channel 15 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "DCHPRI14,Channel 14 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "DCHPRI13,Channel 13 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "DCHPRI12,Channel 12 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "DCHPRI3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "DCHPRI2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "DCHPRI1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "DCHPRI0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "DCHPRI7,Channel 7 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "DCHPRI6,Channel 6 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "DCHPRI5,Channel 5 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "DCHPRI4,Channel 4 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "DCHPRI11,Channel 11 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "DCHPRI10,Channel 10 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "DCHPRI9,Channel 9 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "DCHPRI8,Channel 8 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "DCHPRI15,Channel 15 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "DCHPRI14,Channel 14 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "DCHPRI13,Channel 13 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "DCHPRI12,Channel 12 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x110++0x00
|
|
line.byte 0x00 "DCHPRI19,Channel 19 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x111++0x00
|
|
line.byte 0x00 "DCHPRI18,Channel 18 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x112++0x00
|
|
line.byte 0x00 "DCHPRI17,Channel 17 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x113++0x00
|
|
line.byte 0x00 "DCHPRI16,Channel 16 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "DCHPRI23,Channel 23 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DCHPRI22,Channel 22 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x116++0x00
|
|
line.byte 0x00 "DCHPRI21,Channel 21 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DCHPRI20,Channel 20 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x118++0x00
|
|
line.byte 0x00 "DCHPRI27,Channel 27 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x119++0x00
|
|
line.byte 0x00 "DCHPRI26,Channel 26 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11A++0x00
|
|
line.byte 0x00 "DCHPRI25,Channel 25 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11B++0x00
|
|
line.byte 0x00 "DCHPRI24,Channel 24 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "DCHPRI31,Channel 31 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "DCHPRI30,Channel 30 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "DCHPRI29,Channel 29 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "DCHPRI28,Channel 28 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "DCHPRI3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "DCHPRI2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "DCHPRI1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "DCHPRI0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest"
|
|
endif
|
|
tree.end
|
|
base ad:0x40009000
|
|
width 23.
|
|
tree "Transfer Control Descriptor Registers"
|
|
sif ((cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FX512VDC12")||(cpu()=="MK64FX512VLL12")||(cpu()=="MK64FX512VLQ12")||(cpu()=="MK64FX512VMD12")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV10Z*")||cpuis("MKV30F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW2?D*"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*")||(cpuis("MKW21Z*"))))
|
|
tree "Channel 0"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
group.word (0x0+0x04)++0x03
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x0+0x0c)++0x07
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD0_DADDR,TCD Destination Address"
|
|
group.word (0x0+0x14)++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x0+0x16)))&0x8000)==0x0)
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x0+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
group.word (0x20+0x04)++0x03
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x20+0x0c)++0x07
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD1_DADDR,TCD Destination Address"
|
|
group.word (0x20+0x14)++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x20+0x16)))&0x8000)==0x0)
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x20+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x20+0x1E)))&0x8000)==0x0)
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
group.word (0x40+0x04)++0x03
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x40+0x0c)++0x07
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD2_DADDR,TCD Destination Address"
|
|
group.word (0x40+0x14)++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x40+0x16)))&0x8000)==0x0)
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x40+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x40+0x1E)))&0x8000)==0x0)
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
group.word (0x60+0x04)++0x03
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x60+0x0c)++0x07
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD3_DADDR,TCD Destination Address"
|
|
group.word (0x60+0x14)++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x60+0x16)))&0x8000)==0x0)
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x60+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x60+0x1E)))&0x8000)==0x0)
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
tree "Channel 0"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
group.word (0x0+0x04)++0x03
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x0+0x0c)++0x07
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD0_DADDR,TCD Destination Address"
|
|
group.word (0x0+0x14)++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x0+0x16)))&0x8000)==0x0)
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x0+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
group.word (0x20+0x04)++0x03
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x20+0x0c)++0x07
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD1_DADDR,TCD Destination Address"
|
|
group.word (0x20+0x14)++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x20+0x16)))&0x8000)==0x0)
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x20+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x20+0x1E)))&0x8000)==0x0)
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
group.word (0x40+0x04)++0x03
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x40+0x0c)++0x07
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD2_DADDR,TCD Destination Address"
|
|
group.word (0x40+0x14)++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x40+0x16)))&0x8000)==0x0)
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x40+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x40+0x1E)))&0x8000)==0x0)
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
group.word (0x60+0x04)++0x03
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x60+0x0c)++0x07
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD3_DADDR,TCD Destination Address"
|
|
group.word (0x60+0x14)++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x60+0x16)))&0x8000)==0x0)
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x60+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x60+0x1E)))&0x8000)==0x0)
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
group.word (0x80+0x04)++0x03
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x80+0x0c)++0x07
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD4_DADDR,TCD Destination Address"
|
|
group.word (0x80+0x14)++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x80+0x16)))&0x8000)==0x0)
|
|
group.word (0x80+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x80+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x80+0x18)++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x80+0x1C)++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x80+0x1E)))&0x8000)==0x0)
|
|
group.word (0x80+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x80+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
group.word (0xA0+0x04)++0x03
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xA0+0x0c)++0x07
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD5_DADDR,TCD Destination Address"
|
|
group.word (0xA0+0x14)++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xA0+0x16)))&0x8000)==0x0)
|
|
group.word (0xA0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xA0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xA0+0x1C)++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xA0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xA0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xA0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
group.word (0xC0+0x04)++0x03
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xC0+0x0c)++0x07
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD6_DADDR,TCD Destination Address"
|
|
group.word (0xC0+0x14)++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xC0+0x16)))&0x8000)==0x0)
|
|
group.word (0xC0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xC0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xC0+0x1C)++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xC0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xC0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xC0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
group.word (0xE0+0x04)++0x03
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xE0+0x0c)++0x07
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD7_DADDR,TCD Destination Address"
|
|
group.word (0xE0+0x14)++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xE0+0x16)))&0x8000)==0x0)
|
|
group.word (0xE0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xE0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xE0+0x1C)++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xE0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xE0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xE0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 8"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
group.word (0x100+0x04)++0x03
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD8_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x100+0x0c)++0x07
|
|
line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD8_DADDR,TCD Destination Address"
|
|
group.word (0x100+0x14)++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x100+0x16)))&0x8000)==0x0)
|
|
group.word (0x100+0x16)++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x100+0x16)++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x100+0x18)++0x03
|
|
line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x100+0x1C)++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x100+0x1E)))&0x8000)==0x0)
|
|
group.word (0x100+0x1E)++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x100+0x1E)++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 9"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
group.word (0x120+0x04)++0x03
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD9_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x120+0x0c)++0x07
|
|
line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD9_DADDR,TCD Destination Address"
|
|
group.word (0x120+0x14)++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x120+0x16)))&0x8000)==0x0)
|
|
group.word (0x120+0x16)++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x120+0x16)++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x120+0x18)++0x03
|
|
line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x120+0x1C)++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x120+0x1E)))&0x8000)==0x0)
|
|
group.word (0x120+0x1E)++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x120+0x1E)++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 10"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
group.word (0x140+0x04)++0x03
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x140+0x0c)++0x07
|
|
line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD10_DADDR,TCD Destination Address"
|
|
group.word (0x140+0x14)++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x140+0x16)))&0x8000)==0x0)
|
|
group.word (0x140+0x16)++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x140+0x16)++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x140+0x18)++0x03
|
|
line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x140+0x1C)++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x140+0x1E)))&0x8000)==0x0)
|
|
group.word (0x140+0x1E)++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x140+0x1E)++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 11"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
group.word (0x160+0x04)++0x03
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x160+0x0c)++0x07
|
|
line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD11_DADDR,TCD Destination Address"
|
|
group.word (0x160+0x14)++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x160+0x16)))&0x8000)==0x0)
|
|
group.word (0x160+0x16)++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x160+0x16)++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x160+0x18)++0x03
|
|
line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x160+0x1C)++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x160+0x1E)))&0x8000)==0x0)
|
|
group.word (0x160+0x1E)++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x160+0x1E)++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 12"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
group.word (0x180+0x04)++0x03
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x180+0x0c)++0x07
|
|
line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD12_DADDR,TCD Destination Address"
|
|
group.word (0x180+0x14)++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x180+0x16)))&0x8000)==0x0)
|
|
group.word (0x180+0x16)++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x180+0x16)++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x180+0x18)++0x03
|
|
line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x180+0x1C)++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x180+0x1E)))&0x8000)==0x0)
|
|
group.word (0x180+0x1E)++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x180+0x1E)++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 13"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
group.word (0x1A0+0x04)++0x03
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x1A0+0x0c)++0x07
|
|
line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD13_DADDR,TCD Destination Address"
|
|
group.word (0x1A0+0x14)++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1A0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1A0+0x16)++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1A0+0x16)++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1A0+0x18)++0x03
|
|
line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1A0+0x1C)++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1A0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1A0+0x1E)++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1A0+0x1E)++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 14"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
group.word (0x1C0+0x04)++0x03
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x1C0+0x0c)++0x07
|
|
line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD14_DADDR,TCD Destination Address"
|
|
group.word (0x1C0+0x14)++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1C0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1C0+0x16)++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1C0+0x16)++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1C0+0x18)++0x03
|
|
line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1C0+0x1C)++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1C0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1C0+0x1E)++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1C0+0x1E)++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 15"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
group.word (0x1E0+0x04)++0x03
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x1E0+0x0c)++0x07
|
|
line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD15_DADDR,TCD Destination Address"
|
|
group.word (0x1E0+0x14)++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1E0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1E0+0x16)++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1E0+0x16)++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1E0+0x18)++0x03
|
|
line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1E0+0x1C)++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1E0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1E0+0x1E)++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1E0+0x1E)++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 16"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TCD16_SADDR,TCD Source Address"
|
|
group.word (0x200+0x04)++0x03
|
|
line.word 0x00 "TCD16_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD16_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x200+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x200+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x200+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x200+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x200+0x0c)++0x07
|
|
line.long 0x00 "TCD16_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD16_DADDR,TCD Destination Address"
|
|
group.word (0x200+0x14)++0x01
|
|
line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x200+0x16)))&0x8000)==0x0)
|
|
group.word (0x200+0x16)++0x01
|
|
line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x200+0x16)++0x01
|
|
line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "TCD16_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x200+0x1C)++0x01
|
|
line.word 0x00 "TCD16_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x200+0x1E)))&0x8000)==0x0)
|
|
group.word (0x200+0x1E)++0x01
|
|
line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x200+0x1E)++0x01
|
|
line.word 0x00 "TCD16_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 17"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "TCD17_SADDR,TCD Source Address"
|
|
group.word (0x220+0x04)++0x03
|
|
line.word 0x00 "TCD17_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD17_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x220+0x08)++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x220+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x220+0x08)++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x220+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x220+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x220+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x220+0x08)++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x220+0x0c)++0x07
|
|
line.long 0x00 "TCD17_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD17_DADDR,TCD Destination Address"
|
|
group.word (0x220+0x14)++0x01
|
|
line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x220+0x16)))&0x8000)==0x0)
|
|
group.word (0x220+0x16)++0x01
|
|
line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x220+0x16)++0x01
|
|
line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x220+0x18)++0x03
|
|
line.long 0x00 "TCD17_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x220+0x1C)++0x01
|
|
line.word 0x00 "TCD17_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x220+0x1E)))&0x8000)==0x0)
|
|
group.word (0x220+0x1E)++0x01
|
|
line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x220+0x1E)++0x01
|
|
line.word 0x00 "TCD17_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 18"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "TCD18_SADDR,TCD Source Address"
|
|
group.word (0x240+0x04)++0x03
|
|
line.word 0x00 "TCD18_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD18_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x240+0x08)++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x240+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x240+0x08)++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x240+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x240+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x240+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x240+0x08)++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x240+0x0c)++0x07
|
|
line.long 0x00 "TCD18_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD18_DADDR,TCD Destination Address"
|
|
group.word (0x240+0x14)++0x01
|
|
line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x240+0x16)))&0x8000)==0x0)
|
|
group.word (0x240+0x16)++0x01
|
|
line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x240+0x16)++0x01
|
|
line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x240+0x18)++0x03
|
|
line.long 0x00 "TCD18_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x240+0x1C)++0x01
|
|
line.word 0x00 "TCD18_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x240+0x1E)))&0x8000)==0x0)
|
|
group.word (0x240+0x1E)++0x01
|
|
line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x240+0x1E)++0x01
|
|
line.word 0x00 "TCD18_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 19"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "TCD19_SADDR,TCD Source Address"
|
|
group.word (0x260+0x04)++0x03
|
|
line.word 0x00 "TCD19_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD19_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x260+0x08)++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x260+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x260+0x08)++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x260+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x260+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x260+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x260+0x08)++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x260+0x0c)++0x07
|
|
line.long 0x00 "TCD19_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD19_DADDR,TCD Destination Address"
|
|
group.word (0x260+0x14)++0x01
|
|
line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x260+0x16)))&0x8000)==0x0)
|
|
group.word (0x260+0x16)++0x01
|
|
line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x260+0x16)++0x01
|
|
line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x260+0x18)++0x03
|
|
line.long 0x00 "TCD19_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x260+0x1C)++0x01
|
|
line.word 0x00 "TCD19_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x260+0x1E)))&0x8000)==0x0)
|
|
group.word (0x260+0x1E)++0x01
|
|
line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x260+0x1E)++0x01
|
|
line.word 0x00 "TCD19_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 20"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "TCD20_SADDR,TCD Source Address"
|
|
group.word (0x280+0x04)++0x03
|
|
line.word 0x00 "TCD20_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD20_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x280+0x08)++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x280+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x280+0x08)++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x280+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x280+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x280+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x280+0x08)++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x280+0x0c)++0x07
|
|
line.long 0x00 "TCD20_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD20_DADDR,TCD Destination Address"
|
|
group.word (0x280+0x14)++0x01
|
|
line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x280+0x16)))&0x8000)==0x0)
|
|
group.word (0x280+0x16)++0x01
|
|
line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x280+0x16)++0x01
|
|
line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x280+0x18)++0x03
|
|
line.long 0x00 "TCD20_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x280+0x1C)++0x01
|
|
line.word 0x00 "TCD20_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x280+0x1E)))&0x8000)==0x0)
|
|
group.word (0x280+0x1E)++0x01
|
|
line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x280+0x1E)++0x01
|
|
line.word 0x00 "TCD20_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 21"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "TCD21_SADDR,TCD Source Address"
|
|
group.word (0x2A0+0x04)++0x03
|
|
line.word 0x00 "TCD21_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD21_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x2A0+0x08)++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x2A0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x2A0+0x08)++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x2A0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x2A0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x2A0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x2A0+0x08)++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x2A0+0x0c)++0x07
|
|
line.long 0x00 "TCD21_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD21_DADDR,TCD Destination Address"
|
|
group.word (0x2A0+0x14)++0x01
|
|
line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x2A0+0x16)))&0x8000)==0x0)
|
|
group.word (0x2A0+0x16)++0x01
|
|
line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x2A0+0x16)++0x01
|
|
line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x2A0+0x18)++0x03
|
|
line.long 0x00 "TCD21_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x2A0+0x1C)++0x01
|
|
line.word 0x00 "TCD21_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x2A0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x2A0+0x1E)++0x01
|
|
line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x2A0+0x1E)++0x01
|
|
line.word 0x00 "TCD21_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 22"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "TCD22_SADDR,TCD Source Address"
|
|
group.word (0x2C0+0x04)++0x03
|
|
line.word 0x00 "TCD22_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD22_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x2C0+0x08)++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x2C0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x2C0+0x08)++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x2C0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x2C0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x2C0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x2C0+0x08)++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x2C0+0x0c)++0x07
|
|
line.long 0x00 "TCD22_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD22_DADDR,TCD Destination Address"
|
|
group.word (0x2C0+0x14)++0x01
|
|
line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x2C0+0x16)))&0x8000)==0x0)
|
|
group.word (0x2C0+0x16)++0x01
|
|
line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x2C0+0x16)++0x01
|
|
line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x2C0+0x18)++0x03
|
|
line.long 0x00 "TCD22_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x2C0+0x1C)++0x01
|
|
line.word 0x00 "TCD22_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x2C0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x2C0+0x1E)++0x01
|
|
line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x2C0+0x1E)++0x01
|
|
line.word 0x00 "TCD22_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 23"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "TCD23_SADDR,TCD Source Address"
|
|
group.word (0x2E0+0x04)++0x03
|
|
line.word 0x00 "TCD23_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD23_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x2E0+0x08)++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x2E0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x2E0+0x08)++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x2E0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x2E0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x2E0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x2E0+0x08)++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x2E0+0x0c)++0x07
|
|
line.long 0x00 "TCD23_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD23_DADDR,TCD Destination Address"
|
|
group.word (0x2E0+0x14)++0x01
|
|
line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x2E0+0x16)))&0x8000)==0x0)
|
|
group.word (0x2E0+0x16)++0x01
|
|
line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x2E0+0x16)++0x01
|
|
line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x2E0+0x18)++0x03
|
|
line.long 0x00 "TCD23_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x2E0+0x1C)++0x01
|
|
line.word 0x00 "TCD23_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x2E0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x2E0+0x1E)++0x01
|
|
line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x2E0+0x1E)++0x01
|
|
line.word 0x00 "TCD23_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 24"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "TCD24_SADDR,TCD Source Address"
|
|
group.word (0x300+0x04)++0x03
|
|
line.word 0x00 "TCD24_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD24_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x300+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x300+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x300+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x300+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x300+0x0c)++0x07
|
|
line.long 0x00 "TCD24_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD24_DADDR,TCD Destination Address"
|
|
group.word (0x300+0x14)++0x01
|
|
line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x300+0x16)))&0x8000)==0x0)
|
|
group.word (0x300+0x16)++0x01
|
|
line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x300+0x16)++0x01
|
|
line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x300+0x18)++0x03
|
|
line.long 0x00 "TCD24_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x300+0x1C)++0x01
|
|
line.word 0x00 "TCD24_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x300+0x1E)))&0x8000)==0x0)
|
|
group.word (0x300+0x1E)++0x01
|
|
line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x300+0x1E)++0x01
|
|
line.word 0x00 "TCD24_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 25"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TCD25_SADDR,TCD Source Address"
|
|
group.word (0x320+0x04)++0x03
|
|
line.word 0x00 "TCD25_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD25_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x320+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x320+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x320+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x320+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x320+0x0c)++0x07
|
|
line.long 0x00 "TCD25_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD25_DADDR,TCD Destination Address"
|
|
group.word (0x320+0x14)++0x01
|
|
line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x320+0x16)))&0x8000)==0x0)
|
|
group.word (0x320+0x16)++0x01
|
|
line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x320+0x16)++0x01
|
|
line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x320+0x18)++0x03
|
|
line.long 0x00 "TCD25_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x320+0x1C)++0x01
|
|
line.word 0x00 "TCD25_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x320+0x1E)))&0x8000)==0x0)
|
|
group.word (0x320+0x1E)++0x01
|
|
line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x320+0x1E)++0x01
|
|
line.word 0x00 "TCD25_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 26"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "TCD26_SADDR,TCD Source Address"
|
|
group.word (0x340+0x04)++0x03
|
|
line.word 0x00 "TCD26_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD26_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x340+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x340+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x340+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x340+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x340+0x0c)++0x07
|
|
line.long 0x00 "TCD26_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD26_DADDR,TCD Destination Address"
|
|
group.word (0x340+0x14)++0x01
|
|
line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x340+0x16)))&0x8000)==0x0)
|
|
group.word (0x340+0x16)++0x01
|
|
line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x340+0x16)++0x01
|
|
line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x340+0x18)++0x03
|
|
line.long 0x00 "TCD26_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x340+0x1C)++0x01
|
|
line.word 0x00 "TCD26_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x340+0x1E)))&0x8000)==0x0)
|
|
group.word (0x340+0x1E)++0x01
|
|
line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x340+0x1E)++0x01
|
|
line.word 0x00 "TCD26_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 27"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "TCD27_SADDR,TCD Source Address"
|
|
group.word (0x360+0x04)++0x03
|
|
line.word 0x00 "TCD27_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD27_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x360+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x360+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x360+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x360+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x360+0x0c)++0x07
|
|
line.long 0x00 "TCD27_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD27_DADDR,TCD Destination Address"
|
|
group.word (0x360+0x14)++0x01
|
|
line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x360+0x16)))&0x8000)==0x0)
|
|
group.word (0x360+0x16)++0x01
|
|
line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x360+0x16)++0x01
|
|
line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x360+0x18)++0x03
|
|
line.long 0x00 "TCD27_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x360+0x1C)++0x01
|
|
line.word 0x00 "TCD27_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x360+0x1E)))&0x8000)==0x0)
|
|
group.word (0x360+0x1E)++0x01
|
|
line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x360+0x1E)++0x01
|
|
line.word 0x00 "TCD27_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 28"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "TCD28_SADDR,TCD Source Address"
|
|
group.word (0x380+0x04)++0x03
|
|
line.word 0x00 "TCD28_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD28_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x380+0x08)++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x380+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x380+0x08)++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x380+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x380+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x380+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x380+0x08)++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x380+0x0c)++0x07
|
|
line.long 0x00 "TCD28_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD28_DADDR,TCD Destination Address"
|
|
group.word (0x380+0x14)++0x01
|
|
line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x380+0x16)))&0x8000)==0x0)
|
|
group.word (0x380+0x16)++0x01
|
|
line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x380+0x16)++0x01
|
|
line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x380+0x18)++0x03
|
|
line.long 0x00 "TCD28_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x380+0x1C)++0x01
|
|
line.word 0x00 "TCD28_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x380+0x1E)))&0x8000)==0x0)
|
|
group.word (0x380+0x1E)++0x01
|
|
line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x380+0x1E)++0x01
|
|
line.word 0x00 "TCD28_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 29"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "TCD29_SADDR,TCD Source Address"
|
|
group.word (0x3A0+0x04)++0x03
|
|
line.word 0x00 "TCD29_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD29_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x3A0+0x08)++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x3A0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x3A0+0x08)++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x3A0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x3A0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x3A0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x3A0+0x08)++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x3A0+0x0c)++0x07
|
|
line.long 0x00 "TCD29_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD29_DADDR,TCD Destination Address"
|
|
group.word (0x3A0+0x14)++0x01
|
|
line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x3A0+0x16)))&0x8000)==0x0)
|
|
group.word (0x3A0+0x16)++0x01
|
|
line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x3A0+0x16)++0x01
|
|
line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x3A0+0x18)++0x03
|
|
line.long 0x00 "TCD29_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x3A0+0x1C)++0x01
|
|
line.word 0x00 "TCD29_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x3A0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x3A0+0x1E)++0x01
|
|
line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x3A0+0x1E)++0x01
|
|
line.word 0x00 "TCD29_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 30"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "TCD30_SADDR,TCD Source Address"
|
|
group.word (0x3C0+0x04)++0x03
|
|
line.word 0x00 "TCD30_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD30_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x3C0+0x08)++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x3C0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x3C0+0x08)++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x3C0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x3C0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x3C0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x3C0+0x08)++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x3C0+0x0c)++0x07
|
|
line.long 0x00 "TCD30_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD30_DADDR,TCD Destination Address"
|
|
group.word (0x3C0+0x14)++0x01
|
|
line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x3C0+0x16)))&0x8000)==0x0)
|
|
group.word (0x3C0+0x16)++0x01
|
|
line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x3C0+0x16)++0x01
|
|
line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x3C0+0x18)++0x03
|
|
line.long 0x00 "TCD30_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x3C0+0x1C)++0x01
|
|
line.word 0x00 "TCD30_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x3C0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x3C0+0x1E)++0x01
|
|
line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x3C0+0x1E)++0x01
|
|
line.word 0x00 "TCD30_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 31"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "TCD31_SADDR,TCD Source Address"
|
|
group.word (0x3E0+0x04)++0x03
|
|
line.word 0x00 "TCD31_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD31_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x3E0+0x08)++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x3E0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x3E0+0x08)++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x3E0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x3E0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x3E0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x3E0+0x08)++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x3E0+0x0c)++0x07
|
|
line.long 0x00 "TCD31_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD31_DADDR,TCD Destination Address"
|
|
group.word (0x3E0+0x14)++0x01
|
|
line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x3E0+0x16)))&0x8000)==0x0)
|
|
group.word (0x3E0+0x16)++0x01
|
|
line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x3E0+0x16)++0x01
|
|
line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x3E0+0x18)++0x03
|
|
line.long 0x00 "TCD31_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x3E0+0x1C)++0x01
|
|
line.word 0x00 "TCD31_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x3E0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x3E0+0x1E)++0x01
|
|
line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x3E0+0x1E)++0x01
|
|
line.word 0x00 "TCD31_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
width 10.
|
|
tree "eDMA Control and Status Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
sif (cpuis("MWK?1Z*"))
|
|
rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing channel"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " CX ,Cancel transfer" "Not cancelled,Cancelled"
|
|
bitfld.long 0x00 16. " ECX ,Error cancel transfer" "Not cancelled,Cancelled"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted"
|
|
bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error"
|
|
bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error"
|
|
bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error"
|
|
bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error"
|
|
bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error"
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 3. " ERQ3 ,Enable DMA request 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERQ2 ,Enable DMA request 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERQ1 ,Enable DMA request 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERQ0 ,Enable DMA request 0" "Disabled,Enabled"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
bitfld.long 0x00 31. " ERQ31 ,Enable DMA request 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ERQ30 ,Enable DMA request 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ERQ29 ,Enable DMA request 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ERQ28 ,Enable DMA request 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ERQ27 ,Enable DMA request 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ERQ26 ,Enable DMA request 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ERQ25 ,Enable DMA request 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERQ24 ,Enable DMA request 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ERQ23 ,Enable DMA request 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ERQ22 ,Enable DMA request 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ERQ21 ,Enable DMA request 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ERQ20 ,Enable DMA request 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ERQ19 ,Enable DMA request 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ERQ18 ,Enable DMA request 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ERQ17 ,Enable DMA request 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ERQ16 ,Enable DMA request 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ERQ15 ,Enable DMA request 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERQ14 ,Enable DMA request 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERQ13 ,Enable DMA request 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ERQ12 ,Enable DMA request 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ERQ11 ,Enable DMA request 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ERQ10 ,Enable DMA request 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ERQ9 ,Enable DMA request 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERQ8 ,Enable DMA request 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERQ7 ,Enable DMA request 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ERQ6 ,Enable DMA request 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERQ5 ,Enable DMA request 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERQ4 ,Enable DMA request 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ERQ3 ,Enable DMA request 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERQ2 ,Enable DMA request 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERQ1 ,Enable DMA request 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ERQ0 ,Enable DMA request 0" "Disabled,Enabled"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " ERQ15 ,Enable DMA request 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERQ14 ,Enable DMA request 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERQ13 ,Enable DMA request 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ERQ12 ,Enable DMA request 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ERQ11 ,Enable DMA request 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ERQ10 ,Enable DMA request 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ERQ9 ,Enable DMA request 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERQ8 ,Enable DMA request 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ERQ7 ,Enable DMA request 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ERQ6 ,Enable DMA request 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERQ5 ,Enable DMA request 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ERQ4 ,Enable DMA request 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERQ3 ,Enable DMA request 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERQ2 ,Enable DMA request 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERQ1 ,Enable DMA request 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERQ0 ,Enable DMA request 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 3. " EEI3 ,Enable error interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EEI2 ,Enable error interrupt 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EEI1 ,Enable error interrupt 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EEI0 ,Enable error interrupt 0" "Disabled,Enabled"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
bitfld.long 0x00 31. " EEI31 ,Enable error interrupt 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EEI30 ,Enable error interrupt 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " EEI29 ,Enable error interrupt 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EEI28 ,Enable error interrupt 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EEI27 ,Enable error interrupt 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EEI26 ,Enable error interrupt 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EEI25 ,Enable error interrupt 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EEI24 ,Enable error interrupt 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " EEI23 ,Enable error interrupt 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EEI22 ,Enable error interrupt 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " EEI21 ,Enable error interrupt 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EEI20 ,Enable error interrupt 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EEI19 ,Enable error interrupt 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EEI18 ,Enable error interrupt 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " EEI17 ,Enable error interrupt 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EEI16 ,Enable error interrupt 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EEI15 ,Enable error interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EEI14 ,Enable error interrupt 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EEI13 ,Enable error interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EEI12 ,Enable error interrupt 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EEI11 ,Enable error interrupt 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EEI10 ,Enable error interrupt 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EEI9 ,Enable error interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EEI8 ,Enable error interrupt 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EEI7 ,Enable error interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EEI6 ,Enable error interrupt 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EEI5 ,Enable error interrupt 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EEI4 ,Enable error interrupt 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EEI3 ,Enable error interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EEI2 ,Enable error interrupt 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EEI1 ,Enable error interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EEI0 ,Enable error interrupt 0" "Disabled,Enabled"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " EEI15 ,Enable error interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EEI14 ,Enable error interrupt 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EEI13 ,Enable error interrupt 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EEI12 ,Enable error interrupt 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EEI11 ,Enable error interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EEI10 ,Enable error interrupt 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EEI9 ,Enable error interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EEI8 ,Enable error interrupt 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EEI7 ,Enable error interrupt 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EEI6 ,Enable error interrupt 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EEI5 ,Enable error interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EEI4 ,Enable error interrupt 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EEI3 ,Enable error interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EEI2 ,Enable error interrupt 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EEI1 ,Enable error interrupt 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EEI0 ,Enable error interrupt 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.byte 0x18++0x07
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x01 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x02 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ only,ALL bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x03 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SERQ only only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x03 0.--1. " SERQ ,Set enable request [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x03 0.--4. " SERQ ,Set enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x03 0.--3. " SERQ ,Set enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x04 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x04 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CDNE only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x04 0.--1. " CDNE ,Clear DONE bits [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x05 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x05 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x05 6. " SAST ,Set All START bits" "SSRT only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x05 0.--1. " SSRT ,Set START bits [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x05 0.--4. " SSRT ,Set START bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x05 0.--3. " SSRT ,Set START bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x06 "CERR,Clear Error Register"
|
|
bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x07 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable"
|
|
bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CINT only,All bits"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request [1:0]" "0,1,2,3"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
textline " "
|
|
bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt request 3" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt request 2" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt request 1" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt request 0" "Not requested,Requested"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
eventfld.long 0x00 31. " INT31 ,Interrupt request 31" "Not requested,Requested"
|
|
eventfld.long 0x00 30. " INT30 ,Interrupt request 30" "Not requested,Requested"
|
|
eventfld.long 0x00 29. " INT29 ,Interrupt request 29" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 28. " INT28 ,Interrupt request 28" "Not requested,Requested"
|
|
eventfld.long 0x00 27. " INT27 ,Interrupt request 27" "Not requested,Requested"
|
|
eventfld.long 0x00 26. " INT26 ,Interrupt request 26" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 25. " INT25 ,Interrupt request 25" "Not requested,Requested"
|
|
eventfld.long 0x00 24. " INT24 ,Interrupt request 24" "Not requested,Requested"
|
|
eventfld.long 0x00 23. " INT23 ,Interrupt request 23" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 22. " INT22 ,Interrupt request 22" "Not requested,Requested"
|
|
eventfld.long 0x00 21. " INT21 ,Interrupt request 21" "Not requested,Requested"
|
|
eventfld.long 0x00 20. " INT20 ,Interrupt request 20" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 19. " INT19 ,Interrupt request 19" "Not requested,Requested"
|
|
eventfld.long 0x00 18. " INT18 ,Interrupt request 18" "Not requested,Requested"
|
|
eventfld.long 0x00 17. " INT17 ,Interrupt request 17" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 16. " INT16 ,Interrupt request 16" "Not requested,Requested"
|
|
eventfld.long 0x00 15. " INT15 ,Interrupt request 15" "Not requested,Requested"
|
|
eventfld.long 0x00 14. " INT14 ,Interrupt request 14" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INT13 ,Interrupt request 13" "Not requested,Requested"
|
|
eventfld.long 0x00 12. " INT12 ,Interrupt request 12" "Not requested,Requested"
|
|
eventfld.long 0x00 11. " INT11 ,Interrupt request 11" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 10. " INT10 ,Interrupt request 10" "Not requested,Requested"
|
|
eventfld.long 0x00 9. " INT9 ,Interrupt request 9" "Not requested,Requested"
|
|
eventfld.long 0x00 8. " INT8 ,Interrupt request 8" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 7. " INT7 ,Interrupt request 7" "Not requested,Requested"
|
|
eventfld.long 0x00 6. " INT6 ,Interrupt request 6" "Not requested,Requested"
|
|
eventfld.long 0x00 5. " INT5 ,Interrupt request 5" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 4. " INT4 ,Interrupt request 4" "Not requested,Requested"
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt request 3" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt request 2" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt request 1" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt request 0" "Not requested,Requested"
|
|
elif (cpuis("MKW2?D*"))
|
|
eventfld.long 0x00 15. " INT15 ,Interrupt request 15" "Not requested,Requested"
|
|
eventfld.long 0x00 14. " INT14 ,Interrupt request 14" "Not requested,Requested"
|
|
eventfld.long 0x00 13. " INT13 ,Interrupt request 13" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 12. " INT12 ,Interrupt request 12" "Not requested,Requested"
|
|
eventfld.long 0x00 11. " INT11 ,Interrupt request 11" "Not requested,Requested"
|
|
eventfld.long 0x00 10. " INT10 ,Interrupt request 10" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 9. " INT9 ,Interrupt request 9" "Not requested,Requested"
|
|
eventfld.long 0x00 8. " INT8 ,Interrupt request 8" "Not requested,Requested"
|
|
eventfld.long 0x00 7. " INT7 ,Interrupt request 7" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 6. " INT6 ,Interrupt request 6" "Not requested,Requested"
|
|
eventfld.long 0x00 5. " INT5 ,Interrupt request 5" "Not requested,Requested"
|
|
eventfld.long 0x00 4. " INT4 ,Interrupt request 4" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt request 3" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt request 2" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt request 1" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt request 0" "Not requested,Requested"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ERR,Error Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
eventfld.long 0x00 3. " ERR3 ,Error in channel 3" "No error,Error"
|
|
eventfld.long 0x00 2. " ERR2 ,Error in channel 2" "No error,Error"
|
|
eventfld.long 0x00 1. " ERR1 ,Error in channel 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ERR0 ,Error in channel 0" "No error,Error"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
eventfld.long 0x00 31. " ERR31 ,Error in channel 31" "No error,Error"
|
|
eventfld.long 0x00 30. " ERR30 ,Error in channel 30" "No error,Error"
|
|
eventfld.long 0x00 29. " ERR29 ,Error in channel 29" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 28. " ERR28 ,Error in channel 28" "No error,Error"
|
|
eventfld.long 0x00 27. " ERR27 ,Error in channel 27" "No error,Error"
|
|
eventfld.long 0x00 26. " ERR26 ,Error in channel 26" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ERR25 ,Error in channel 25" "No error,Error"
|
|
eventfld.long 0x00 24. " ERR24 ,Error in channel 24" "No error,Error"
|
|
eventfld.long 0x00 23. " ERR23 ,Error in channel 23" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ERR22 ,Error in channel 22" "No error,Error"
|
|
eventfld.long 0x00 21. " ERR21 ,Error in channel 21" "No error,Error"
|
|
eventfld.long 0x00 20. " ERR20 ,Error in channel 20" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ERR19 ,Error in channel 19" "No error,Error"
|
|
eventfld.long 0x00 18. " ERR18 ,Error in channel 18" "No error,Error"
|
|
eventfld.long 0x00 17. " ERR17 ,Error in channel 17" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ERR16 ,Error in channel 16" "No error,Error"
|
|
eventfld.long 0x00 15. " ERR15 ,Error in channel 15" "No error,Error"
|
|
eventfld.long 0x00 14. " ERR14 ,Error in channel 14" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ERR13 ,Error in channel 13" "No error,Error"
|
|
eventfld.long 0x00 12. " ERR12 ,Error in channel 12" "No error,Error"
|
|
eventfld.long 0x00 11. " ERR11 ,Error in channel 11" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ERR10 ,Error in channel 10" "No error,Error"
|
|
eventfld.long 0x00 9. " ERR9 ,Error in channel 9" "No error,Error"
|
|
eventfld.long 0x00 8. " ERR8 ,Error in channel 8" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ERR7 ,Error in channel 7" "No error,Error"
|
|
eventfld.long 0x00 6. " ERR6 ,Error in channel 6" "No error,Error"
|
|
eventfld.long 0x00 5. " ERR5 ,Error in channel 5" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ERR4 ,Error in channel 4" "No error,Error"
|
|
eventfld.long 0x00 3. " ERR3 ,Error in channel 3" "No error,Error"
|
|
eventfld.long 0x00 2. " ERR2 ,Error in channel 2" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERR1 ,Error in channel 1" "No error,Error"
|
|
eventfld.long 0x00 0. " ERR0 ,Error in channel 0" "No error,Error"
|
|
elif (cpuis("MKW2?D*"))
|
|
eventfld.long 0x00 15. " ERR15 ,Error in channel 15" "No error,Error"
|
|
eventfld.long 0x00 14. " ERR14 ,Error in channel 14" "No error,Error"
|
|
eventfld.long 0x00 13. " ERR13 ,Error in channel 13" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 12. " ERR12 ,Error in channel 12" "No error,Error"
|
|
eventfld.long 0x00 11. " ERR11 ,Error in channel 11" "No error,Error"
|
|
eventfld.long 0x00 10. " ERR10 ,Error in channel 10" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ERR9 ,Error in channel 9" "No error,Error"
|
|
eventfld.long 0x00 8. " ERR8 ,Error in channel 8" "No error,Error"
|
|
eventfld.long 0x00 7. " ERR7 ,Error in channel 7" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ERR6 ,Error in channel 6" "No error,Error"
|
|
eventfld.long 0x00 5. " ERR5 ,Error in channel 5" "No error,Error"
|
|
eventfld.long 0x00 4. " ERR4 ,Error in channel 4" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERR3 ,Error in channel 3" "No error,Error"
|
|
eventfld.long 0x00 2. " ERR2 ,Error in channel 2" "No error,Error"
|
|
eventfld.long 0x00 1. " ERR1 ,Error in channel 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ERR0 ,Error in channel 0" "No error,Error"
|
|
endif
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 31. " HRS31 ,Hardware request status channel 31" "Not present,Present"
|
|
bitfld.long 0x00 30. " HRS30 ,Hardware request status channel 30" "Not present,Present"
|
|
bitfld.long 0x00 29. " HRS29 ,Hardware request status channel 29" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 28. " HRS28 ,Hardware request status channel 28" "Not present,Present"
|
|
bitfld.long 0x00 27. " HRS27 ,Hardware request status channel 27" "Not present,Present"
|
|
bitfld.long 0x00 26. " HRS26 ,Hardware request status channel 26" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HRS25 ,Hardware request status channel 25" "Not present,Present"
|
|
bitfld.long 0x00 24. " HRS24 ,Hardware request status channel 24" "Not present,Present"
|
|
bitfld.long 0x00 23. " HRS23 ,Hardware request status channel 23" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 22. " HRS22 ,Hardware request status channel 22" "Not present,Present"
|
|
bitfld.long 0x00 21. " HRS21 ,Hardware request status channel 21" "Not present,Present"
|
|
bitfld.long 0x00 20. " HRS20 ,Hardware request status channel 20" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HRS19 ,Hardware request status channel 19" "Not present,Present"
|
|
bitfld.long 0x00 18. " HRS18 ,Hardware request status channel 18" "Not present,Present"
|
|
bitfld.long 0x00 17. " HRS17 ,Hardware request status channel 17" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HRS16 ,Hardware request status channel 16" "Not present,Present"
|
|
bitfld.long 0x00 15. " HRS15 ,Hardware request status channel 15" "Not present,Present"
|
|
bitfld.long 0x00 14. " HRS14 ,Hardware request status channel 14" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HRS13 ,Hardware request status channel 13" "Not present,Present"
|
|
bitfld.long 0x00 12. " HRS12 ,Hardware request status channel 12" "Not present,Present"
|
|
bitfld.long 0x00 11. " HRS11 ,Hardware request status channel 11" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HRS10 ,Hardware request status channel 10" "Not present,Present"
|
|
bitfld.long 0x00 9. " HRS9 ,Hardware request status channel 9" "Not present,Present"
|
|
bitfld.long 0x00 8. " HRS8 ,Hardware request status channel 8" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HRS7 ,Hardware request status channel 7" "Not present,Present"
|
|
bitfld.long 0x00 6. " HRS6 ,Hardware request status channel 6" "Not present,Present"
|
|
bitfld.long 0x00 5. " HRS5 ,Hardware request status channel 5" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HRS4 ,Hardware request status channel 4" "Not present,Present"
|
|
bitfld.long 0x00 3. " HRS3 ,Hardware request status channel 3" "Not present,Present"
|
|
bitfld.long 0x00 2. " HRS2 ,Hardware request status channel 2" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HRS1 ,Hardware request status channel 1" "Not present,Present"
|
|
bitfld.long 0x00 0. " HRS0 ,Hardware request status channel 0" "Not present,Present"
|
|
elif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 3. " HRS3 ,Hardware request status channel 3" "Not present,Present"
|
|
bitfld.long 0x00 2. " HRS2 ,Hardware request status channel 2" "Not present,Present"
|
|
bitfld.long 0x00 1. " HRS1 ,Hardware request status channel 1" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HRS0 ,Hardware request status channel 0" "Not present,Present"
|
|
elif (cpuis("MKW2?D*"))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 15. " HRS15 ,Hardware request status channel 15" "Not present,Present"
|
|
bitfld.long 0x00 14. " HRS14 ,Hardware request status channel 14" "Not present,Present"
|
|
bitfld.long 0x00 13. " HRS13 ,Hardware request status channel 13" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HRS12 ,Hardware request status channel 12" "Not present,Present"
|
|
bitfld.long 0x00 11. " HRS11 ,Hardware request status channel 11" "Not present,Present"
|
|
bitfld.long 0x00 10. " HRS10 ,Hardware request status channel 10" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HRS9 ,Hardware request status channel 9" "Not present,Present"
|
|
bitfld.long 0x00 8. " HRS8 ,Hardware request status channel 8" "Not present,Present"
|
|
bitfld.long 0x00 7. " HRS7 ,Hardware request status channel 7" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HRS6 ,Hardware request status channel 6" "Not present,Present"
|
|
bitfld.long 0x00 5. " HRS5 ,Hardware request status channel 5" "Not present,Present"
|
|
bitfld.long 0x00 4. " HRS4 ,Hardware request status channel 4" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HRS3 ,Hardware request status channel 3" "Not present,Present"
|
|
bitfld.long 0x00 2. " HRS2 ,Hardware request status channel 2" "Not present,Present"
|
|
bitfld.long 0x00 1. " HRS1 ,Hardware request status channel 1" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HRS0 ,Hardware request status channel 0" "Not present,Present"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 3. " EDREQ_3 ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EDREQ_2 ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EDREQ_1 ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDREQ_0 ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
bitfld.long 0x00 31. " EDREQ_31 ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EDREQ_30 ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " EDREQ_29 ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EDREQ_28 ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EDREQ_27 ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EDREQ_26 ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDREQ_25 ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EDREQ_24 ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " EDREQ_23 ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EDREQ_22 ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " EDREQ_21 ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EDREQ_20 ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDREQ_19 ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EDREQ_18 ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " EDREQ_17 ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EDREQ_16 ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EDREQ_15 ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EDREQ_14 ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDREQ_13 ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EDREQ_12 ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EDREQ_11 ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EDREQ_10 ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EDREQ_9 ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EDREQ_8 ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDREQ_7 ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EDREQ_6 ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EDREQ_5 ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EDREQ_4 ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EDREQ_3 ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EDREQ_2 ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDREQ_1 ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDREQ_0 ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled"
|
|
elif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 15. " EDREQ_15 ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EDREQ_14 ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EDREQ_13 ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EDREQ_12 ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EDREQ_11 ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EDREQ_10 ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EDREQ_9 ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EDREQ_8 ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EDREQ_7 ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EDREQ_6 ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EDREQ_5 ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EDREQ_4 ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EDREQ_3 ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EDREQ_2 ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EDREQ_1 ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDREQ_0 ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 10.
|
|
tree "DMA Channel Priority Registers"
|
|
sif ((cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FX512VDC12")||(cpu()=="MK64FX512VLL12")||(cpu()=="MK64FX512VLQ12")||(cpu()=="MK64FX512VMD12")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV31F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||(cpuis("MKW2?D*")))
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "DCHPRI3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "DCHPRI2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "DCHPRI1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "DCHPRI0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "DCHPRI7,Channel 7 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "DCHPRI6,Channel 6 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "DCHPRI5,Channel 5 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "DCHPRI4,Channel 4 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "DCHPRI11,Channel 11 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "DCHPRI10,Channel 10 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "DCHPRI9,Channel 9 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "DCHPRI8,Channel 8 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "DCHPRI15,Channel 15 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "DCHPRI14,Channel 14 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "DCHPRI13,Channel 13 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "DCHPRI12,Channel 12 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes"
|
|
textline " "
|
|
sif ((!cpuis("MKV42*"))&&(!cpuis("MKV44*"))&&(!cpuis("MKV46*"))&&(!cpuis("MKW2?D*")))
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "DCHPRI3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "DCHPRI2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "DCHPRI1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "DCHPRI0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "DCHPRI7,Channel 7 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "DCHPRI6,Channel 6 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "DCHPRI5,Channel 5 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "DCHPRI4,Channel 4 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "DCHPRI11,Channel 11 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "DCHPRI10,Channel 10 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "DCHPRI9,Channel 9 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "DCHPRI8,Channel 8 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "DCHPRI15,Channel 15 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "DCHPRI14,Channel 14 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "DCHPRI13,Channel 13 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "DCHPRI12,Channel 12 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x110++0x00
|
|
line.byte 0x00 "DCHPRI19,Channel 19 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x111++0x00
|
|
line.byte 0x00 "DCHPRI18,Channel 18 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x112++0x00
|
|
line.byte 0x00 "DCHPRI17,Channel 17 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x113++0x00
|
|
line.byte 0x00 "DCHPRI16,Channel 16 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "DCHPRI23,Channel 23 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DCHPRI22,Channel 22 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x116++0x00
|
|
line.byte 0x00 "DCHPRI21,Channel 21 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DCHPRI20,Channel 20 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x118++0x00
|
|
line.byte 0x00 "DCHPRI27,Channel 27 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x119++0x00
|
|
line.byte 0x00 "DCHPRI26,Channel 26 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11A++0x00
|
|
line.byte 0x00 "DCHPRI25,Channel 25 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11B++0x00
|
|
line.byte 0x00 "DCHPRI24,Channel 24 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "DCHPRI31,Channel 31 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "DCHPRI30,Channel 30 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "DCHPRI29,Channel 29 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "DCHPRI28,Channel 28 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes"
|
|
rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 Current Group Priority" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest"
|
|
elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "DCHPRI3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "DCHPRI2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "DCHPRI1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "DCHPRI0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest"
|
|
endif
|
|
tree.end
|
|
base ad:0x40009000
|
|
width 23.
|
|
tree "Transfer Control Descriptor Registers"
|
|
sif ((cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FX512VDC12")||(cpu()=="MK64FX512VLL12")||(cpu()=="MK64FX512VLQ12")||(cpu()=="MK64FX512VMD12")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV10Z*")||cpuis("MKV30F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||(cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW2?D*"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*")||(cpuis("MKW21Z*"))))
|
|
tree "Channel 0"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
group.word (0x0+0x04)++0x03
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x0+0x0c)++0x07
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD0_DADDR,TCD Destination Address"
|
|
group.word (0x0+0x14)++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x0+0x16)))&0x8000)==0x0)
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x0+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
group.word (0x20+0x04)++0x03
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x20+0x0c)++0x07
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD1_DADDR,TCD Destination Address"
|
|
group.word (0x20+0x14)++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x20+0x16)))&0x8000)==0x0)
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x20+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x20+0x1E)))&0x8000)==0x0)
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
group.word (0x40+0x04)++0x03
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x40+0x0c)++0x07
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD2_DADDR,TCD Destination Address"
|
|
group.word (0x40+0x14)++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x40+0x16)))&0x8000)==0x0)
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x40+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x40+0x1E)))&0x8000)==0x0)
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
group.word (0x60+0x04)++0x03
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x60+0x0c)++0x07
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD3_DADDR,TCD Destination Address"
|
|
group.word (0x60+0x14)++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x60+0x16)))&0x8000)==0x0)
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x60+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x60+0x1E)))&0x8000)==0x0)
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
group.word (0x80+0x04)++0x03
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x80+0x0c)++0x07
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD4_DADDR,TCD Destination Address"
|
|
group.word (0x80+0x14)++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x80+0x16)))&0x8000)==0x0)
|
|
group.word (0x80+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x80+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x80+0x18)++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x80+0x1C)++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x80+0x1E)))&0x8000)==0x0)
|
|
group.word (0x80+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x80+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
group.word (0xA0+0x04)++0x03
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0xA0+0x0c)++0x07
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD5_DADDR,TCD Destination Address"
|
|
group.word (0xA0+0x14)++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xA0+0x16)))&0x8000)==0x0)
|
|
group.word (0xA0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xA0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xA0+0x1C)++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xA0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xA0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xA0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
group.word (0xC0+0x04)++0x03
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0xC0+0x0c)++0x07
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD6_DADDR,TCD Destination Address"
|
|
group.word (0xC0+0x14)++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xC0+0x16)))&0x8000)==0x0)
|
|
group.word (0xC0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xC0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xC0+0x1C)++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xC0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xC0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xC0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
group.word (0xE0+0x04)++0x03
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0xE0+0x0c)++0x07
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD7_DADDR,TCD Destination Address"
|
|
group.word (0xE0+0x14)++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xE0+0x16)))&0x8000)==0x0)
|
|
group.word (0xE0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xE0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xE0+0x1C)++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xE0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xE0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xE0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 8"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
group.word (0x100+0x04)++0x03
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD8_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x100+0x0c)++0x07
|
|
line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD8_DADDR,TCD Destination Address"
|
|
group.word (0x100+0x14)++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x100+0x16)))&0x8000)==0x0)
|
|
group.word (0x100+0x16)++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x100+0x16)++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x100+0x18)++0x03
|
|
line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x100+0x1C)++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x100+0x1E)))&0x8000)==0x0)
|
|
group.word (0x100+0x1E)++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x100+0x1E)++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 9"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
group.word (0x120+0x04)++0x03
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD9_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x0c)++0x07
|
|
line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD9_DADDR,TCD Destination Address"
|
|
group.word (0x120+0x14)++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x120+0x16)))&0x8000)==0x0)
|
|
group.word (0x120+0x16)++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x120+0x16)++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x120+0x18)++0x03
|
|
line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x120+0x1C)++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x120+0x1E)))&0x8000)==0x0)
|
|
group.word (0x120+0x1E)++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x120+0x1E)++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 10"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
group.word (0x140+0x04)++0x03
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x140+0x0c)++0x07
|
|
line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD10_DADDR,TCD Destination Address"
|
|
group.word (0x140+0x14)++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x140+0x16)))&0x8000)==0x0)
|
|
group.word (0x140+0x16)++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x140+0x16)++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x140+0x18)++0x03
|
|
line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x140+0x1C)++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x140+0x1E)))&0x8000)==0x0)
|
|
group.word (0x140+0x1E)++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x140+0x1E)++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 11"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
group.word (0x160+0x04)++0x03
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x160+0x0c)++0x07
|
|
line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD11_DADDR,TCD Destination Address"
|
|
group.word (0x160+0x14)++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x160+0x16)))&0x8000)==0x0)
|
|
group.word (0x160+0x16)++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x160+0x16)++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x160+0x18)++0x03
|
|
line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x160+0x1C)++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x160+0x1E)))&0x8000)==0x0)
|
|
group.word (0x160+0x1E)++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x160+0x1E)++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 12"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
group.word (0x180+0x04)++0x03
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x180+0x0c)++0x07
|
|
line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD12_DADDR,TCD Destination Address"
|
|
group.word (0x180+0x14)++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x180+0x16)))&0x8000)==0x0)
|
|
group.word (0x180+0x16)++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x180+0x16)++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x180+0x18)++0x03
|
|
line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x180+0x1C)++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x180+0x1E)))&0x8000)==0x0)
|
|
group.word (0x180+0x1E)++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x180+0x1E)++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 13"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
group.word (0x1A0+0x04)++0x03
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x1A0+0x0c)++0x07
|
|
line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD13_DADDR,TCD Destination Address"
|
|
group.word (0x1A0+0x14)++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1A0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1A0+0x16)++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1A0+0x16)++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1A0+0x18)++0x03
|
|
line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1A0+0x1C)++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1A0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1A0+0x1E)++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1A0+0x1E)++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 14"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
group.word (0x1C0+0x04)++0x03
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x1C0+0x0c)++0x07
|
|
line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD14_DADDR,TCD Destination Address"
|
|
group.word (0x1C0+0x14)++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1C0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1C0+0x16)++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1C0+0x16)++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1C0+0x18)++0x03
|
|
line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1C0+0x1C)++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1C0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1C0+0x1E)++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1C0+0x1E)++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 15"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
group.word (0x1E0+0x04)++0x03
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count"
|
|
else
|
|
if (((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
endif
|
|
group.long (0x1E0+0x0c)++0x07
|
|
line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD15_DADDR,TCD Destination Address"
|
|
group.word (0x1E0+0x14)++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1E0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1E0+0x16)++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1E0+0x16)++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
textline " "
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1E0+0x18)++0x03
|
|
line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1E0+0x1C)++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
textline " "
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
sif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))||(cpuis("MKW41Z*"))||(cpuis("MKW31Z*"))||(cpuis("MKW21Z*")))
|
|
rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
else
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1E0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1E0+0x1E)++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1E0+0x1E)++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")))
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
tree "Channel 0"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
group.word (0x0+0x04)++0x03
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x0+0x0c)++0x07
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD0_DADDR,TCD Destination Address"
|
|
group.word (0x0+0x14)++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x0+0x16)))&0x8000)==0x0)
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x0+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
group.word (0x20+0x04)++0x03
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x20+0x0c)++0x07
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD1_DADDR,TCD Destination Address"
|
|
group.word (0x20+0x14)++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x20+0x16)))&0x8000)==0x0)
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x20+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x20+0x1E)))&0x8000)==0x0)
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
group.word (0x40+0x04)++0x03
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x40+0x0c)++0x07
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD2_DADDR,TCD Destination Address"
|
|
group.word (0x40+0x14)++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x40+0x16)))&0x8000)==0x0)
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x40+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x40+0x1E)))&0x8000)==0x0)
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
group.word (0x60+0x04)++0x03
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x60+0x0c)++0x07
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD3_DADDR,TCD Destination Address"
|
|
group.word (0x60+0x14)++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x60+0x16)))&0x8000)==0x0)
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x60+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x60+0x1E)))&0x8000)==0x0)
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
group.word (0x80+0x04)++0x03
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x80+0x0c)++0x07
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD4_DADDR,TCD Destination Address"
|
|
group.word (0x80+0x14)++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x80+0x16)))&0x8000)==0x0)
|
|
group.word (0x80+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x80+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x80+0x18)++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x80+0x1C)++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x80+0x1E)))&0x8000)==0x0)
|
|
group.word (0x80+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x80+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
group.word (0xA0+0x04)++0x03
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xA0+0x0c)++0x07
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD5_DADDR,TCD Destination Address"
|
|
group.word (0xA0+0x14)++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xA0+0x16)))&0x8000)==0x0)
|
|
group.word (0xA0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xA0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xA0+0x1C)++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xA0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xA0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xA0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
group.word (0xC0+0x04)++0x03
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xC0+0x0c)++0x07
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD6_DADDR,TCD Destination Address"
|
|
group.word (0xC0+0x14)++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xC0+0x16)))&0x8000)==0x0)
|
|
group.word (0xC0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xC0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xC0+0x1C)++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xC0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xC0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xC0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
group.word (0xE0+0x04)++0x03
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xE0+0x0c)++0x07
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD7_DADDR,TCD Destination Address"
|
|
group.word (0xE0+0x14)++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xE0+0x16)))&0x8000)==0x0)
|
|
group.word (0xE0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xE0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0xE0+0x1C)++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0xE0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xE0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xE0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 8"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
group.word (0x100+0x04)++0x03
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD8_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x100+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x100+0x0c)++0x07
|
|
line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD8_DADDR,TCD Destination Address"
|
|
group.word (0x100+0x14)++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x100+0x16)))&0x8000)==0x0)
|
|
group.word (0x100+0x16)++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x100+0x16)++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x100+0x18)++0x03
|
|
line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x100+0x1C)++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x100+0x1E)))&0x8000)==0x0)
|
|
group.word (0x100+0x1E)++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x100+0x1E)++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 9"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
group.word (0x120+0x04)++0x03
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD9_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x120+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x120+0x0c)++0x07
|
|
line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD9_DADDR,TCD Destination Address"
|
|
group.word (0x120+0x14)++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x120+0x16)))&0x8000)==0x0)
|
|
group.word (0x120+0x16)++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x120+0x16)++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x120+0x18)++0x03
|
|
line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x120+0x1C)++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x120+0x1E)))&0x8000)==0x0)
|
|
group.word (0x120+0x1E)++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x120+0x1E)++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 10"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
group.word (0x140+0x04)++0x03
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x140+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x140+0x0c)++0x07
|
|
line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD10_DADDR,TCD Destination Address"
|
|
group.word (0x140+0x14)++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x140+0x16)))&0x8000)==0x0)
|
|
group.word (0x140+0x16)++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x140+0x16)++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x140+0x18)++0x03
|
|
line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x140+0x1C)++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x140+0x1E)))&0x8000)==0x0)
|
|
group.word (0x140+0x1E)++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x140+0x1E)++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 11"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
group.word (0x160+0x04)++0x03
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x160+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x160+0x0c)++0x07
|
|
line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD11_DADDR,TCD Destination Address"
|
|
group.word (0x160+0x14)++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x160+0x16)))&0x8000)==0x0)
|
|
group.word (0x160+0x16)++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x160+0x16)++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x160+0x18)++0x03
|
|
line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x160+0x1C)++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x160+0x1E)))&0x8000)==0x0)
|
|
group.word (0x160+0x1E)++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x160+0x1E)++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 12"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
group.word (0x180+0x04)++0x03
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x180+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x180+0x0c)++0x07
|
|
line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD12_DADDR,TCD Destination Address"
|
|
group.word (0x180+0x14)++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x180+0x16)))&0x8000)==0x0)
|
|
group.word (0x180+0x16)++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x180+0x16)++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x180+0x18)++0x03
|
|
line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x180+0x1C)++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x180+0x1E)))&0x8000)==0x0)
|
|
group.word (0x180+0x1E)++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x180+0x1E)++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 13"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
group.word (0x1A0+0x04)++0x03
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x1A0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x1A0+0x0c)++0x07
|
|
line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD13_DADDR,TCD Destination Address"
|
|
group.word (0x1A0+0x14)++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1A0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1A0+0x16)++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1A0+0x16)++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1A0+0x18)++0x03
|
|
line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1A0+0x1C)++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1A0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1A0+0x1E)++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1A0+0x1E)++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 14"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
group.word (0x1C0+0x04)++0x03
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x1C0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x1C0+0x0c)++0x07
|
|
line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD14_DADDR,TCD Destination Address"
|
|
group.word (0x1C0+0x14)++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1C0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1C0+0x16)++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1C0+0x16)++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1C0+0x18)++0x03
|
|
line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1C0+0x1C)++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1C0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1C0+0x1E)++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1C0+0x1E)++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 15"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
group.word (0x1E0+0x04)++0x03
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x1E0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x1E0+0x0c)++0x07
|
|
line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD15_DADDR,TCD Destination Address"
|
|
group.word (0x1E0+0x14)++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x1E0+0x16)))&0x8000)==0x0)
|
|
group.word (0x1E0+0x16)++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x1E0+0x16)++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x1E0+0x18)++0x03
|
|
line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x1E0+0x1C)++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x1E0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x1E0+0x1E)++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x1E0+0x1E)++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 16"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TCD16_SADDR,TCD Source Address"
|
|
group.word (0x200+0x04)++0x03
|
|
line.word 0x00 "TCD16_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD16_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x200+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x200+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x200+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x200+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x200+0x0c)++0x07
|
|
line.long 0x00 "TCD16_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD16_DADDR,TCD Destination Address"
|
|
group.word (0x200+0x14)++0x01
|
|
line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x200+0x16)))&0x8000)==0x0)
|
|
group.word (0x200+0x16)++0x01
|
|
line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x200+0x16)++0x01
|
|
line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "TCD16_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x200+0x1C)++0x01
|
|
line.word 0x00 "TCD16_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x200+0x1E)))&0x8000)==0x0)
|
|
group.word (0x200+0x1E)++0x01
|
|
line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x200+0x1E)++0x01
|
|
line.word 0x00 "TCD16_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 17"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "TCD17_SADDR,TCD Source Address"
|
|
group.word (0x220+0x04)++0x03
|
|
line.word 0x00 "TCD17_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD17_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x220+0x08)++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x220+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x220+0x08)++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x220+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x220+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x220+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x220+0x08)++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x220+0x0c)++0x07
|
|
line.long 0x00 "TCD17_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD17_DADDR,TCD Destination Address"
|
|
group.word (0x220+0x14)++0x01
|
|
line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x220+0x16)))&0x8000)==0x0)
|
|
group.word (0x220+0x16)++0x01
|
|
line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x220+0x16)++0x01
|
|
line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x220+0x18)++0x03
|
|
line.long 0x00 "TCD17_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x220+0x1C)++0x01
|
|
line.word 0x00 "TCD17_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x220+0x1E)))&0x8000)==0x0)
|
|
group.word (0x220+0x1E)++0x01
|
|
line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x220+0x1E)++0x01
|
|
line.word 0x00 "TCD17_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 18"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "TCD18_SADDR,TCD Source Address"
|
|
group.word (0x240+0x04)++0x03
|
|
line.word 0x00 "TCD18_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD18_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x240+0x08)++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x240+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x240+0x08)++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x240+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x240+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x240+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x240+0x08)++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x240+0x0c)++0x07
|
|
line.long 0x00 "TCD18_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD18_DADDR,TCD Destination Address"
|
|
group.word (0x240+0x14)++0x01
|
|
line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x240+0x16)))&0x8000)==0x0)
|
|
group.word (0x240+0x16)++0x01
|
|
line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x240+0x16)++0x01
|
|
line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x240+0x18)++0x03
|
|
line.long 0x00 "TCD18_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x240+0x1C)++0x01
|
|
line.word 0x00 "TCD18_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x240+0x1E)))&0x8000)==0x0)
|
|
group.word (0x240+0x1E)++0x01
|
|
line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x240+0x1E)++0x01
|
|
line.word 0x00 "TCD18_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 19"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "TCD19_SADDR,TCD Source Address"
|
|
group.word (0x260+0x04)++0x03
|
|
line.word 0x00 "TCD19_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD19_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x260+0x08)++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x260+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x260+0x08)++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x260+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x260+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x260+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x260+0x08)++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x260+0x0c)++0x07
|
|
line.long 0x00 "TCD19_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD19_DADDR,TCD Destination Address"
|
|
group.word (0x260+0x14)++0x01
|
|
line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x260+0x16)))&0x8000)==0x0)
|
|
group.word (0x260+0x16)++0x01
|
|
line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x260+0x16)++0x01
|
|
line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x260+0x18)++0x03
|
|
line.long 0x00 "TCD19_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x260+0x1C)++0x01
|
|
line.word 0x00 "TCD19_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x260+0x1E)))&0x8000)==0x0)
|
|
group.word (0x260+0x1E)++0x01
|
|
line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x260+0x1E)++0x01
|
|
line.word 0x00 "TCD19_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 20"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "TCD20_SADDR,TCD Source Address"
|
|
group.word (0x280+0x04)++0x03
|
|
line.word 0x00 "TCD20_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD20_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x280+0x08)++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x280+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x280+0x08)++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x280+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x280+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x280+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x280+0x08)++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x280+0x0c)++0x07
|
|
line.long 0x00 "TCD20_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD20_DADDR,TCD Destination Address"
|
|
group.word (0x280+0x14)++0x01
|
|
line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x280+0x16)))&0x8000)==0x0)
|
|
group.word (0x280+0x16)++0x01
|
|
line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x280+0x16)++0x01
|
|
line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x280+0x18)++0x03
|
|
line.long 0x00 "TCD20_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x280+0x1C)++0x01
|
|
line.word 0x00 "TCD20_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x280+0x1E)))&0x8000)==0x0)
|
|
group.word (0x280+0x1E)++0x01
|
|
line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x280+0x1E)++0x01
|
|
line.word 0x00 "TCD20_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 21"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "TCD21_SADDR,TCD Source Address"
|
|
group.word (0x2A0+0x04)++0x03
|
|
line.word 0x00 "TCD21_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD21_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x2A0+0x08)++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x2A0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x2A0+0x08)++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x2A0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x2A0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x2A0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x2A0+0x08)++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x2A0+0x0c)++0x07
|
|
line.long 0x00 "TCD21_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD21_DADDR,TCD Destination Address"
|
|
group.word (0x2A0+0x14)++0x01
|
|
line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x2A0+0x16)))&0x8000)==0x0)
|
|
group.word (0x2A0+0x16)++0x01
|
|
line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x2A0+0x16)++0x01
|
|
line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x2A0+0x18)++0x03
|
|
line.long 0x00 "TCD21_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x2A0+0x1C)++0x01
|
|
line.word 0x00 "TCD21_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x2A0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x2A0+0x1E)++0x01
|
|
line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x2A0+0x1E)++0x01
|
|
line.word 0x00 "TCD21_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 22"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "TCD22_SADDR,TCD Source Address"
|
|
group.word (0x2C0+0x04)++0x03
|
|
line.word 0x00 "TCD22_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD22_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x2C0+0x08)++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x2C0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x2C0+0x08)++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x2C0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x2C0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x2C0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x2C0+0x08)++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x2C0+0x0c)++0x07
|
|
line.long 0x00 "TCD22_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD22_DADDR,TCD Destination Address"
|
|
group.word (0x2C0+0x14)++0x01
|
|
line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x2C0+0x16)))&0x8000)==0x0)
|
|
group.word (0x2C0+0x16)++0x01
|
|
line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x2C0+0x16)++0x01
|
|
line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x2C0+0x18)++0x03
|
|
line.long 0x00 "TCD22_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x2C0+0x1C)++0x01
|
|
line.word 0x00 "TCD22_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x2C0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x2C0+0x1E)++0x01
|
|
line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x2C0+0x1E)++0x01
|
|
line.word 0x00 "TCD22_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 23"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "TCD23_SADDR,TCD Source Address"
|
|
group.word (0x2E0+0x04)++0x03
|
|
line.word 0x00 "TCD23_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD23_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x2E0+0x08)++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x2E0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x2E0+0x08)++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x2E0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x2E0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x2E0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x2E0+0x08)++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x2E0+0x0c)++0x07
|
|
line.long 0x00 "TCD23_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD23_DADDR,TCD Destination Address"
|
|
group.word (0x2E0+0x14)++0x01
|
|
line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x2E0+0x16)))&0x8000)==0x0)
|
|
group.word (0x2E0+0x16)++0x01
|
|
line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x2E0+0x16)++0x01
|
|
line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x2E0+0x18)++0x03
|
|
line.long 0x00 "TCD23_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x2E0+0x1C)++0x01
|
|
line.word 0x00 "TCD23_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x2E0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x2E0+0x1E)++0x01
|
|
line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x2E0+0x1E)++0x01
|
|
line.word 0x00 "TCD23_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 24"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "TCD24_SADDR,TCD Source Address"
|
|
group.word (0x300+0x04)++0x03
|
|
line.word 0x00 "TCD24_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD24_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x300+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x300+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x300+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x300+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x300+0x0c)++0x07
|
|
line.long 0x00 "TCD24_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD24_DADDR,TCD Destination Address"
|
|
group.word (0x300+0x14)++0x01
|
|
line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x300+0x16)))&0x8000)==0x0)
|
|
group.word (0x300+0x16)++0x01
|
|
line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x300+0x16)++0x01
|
|
line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x300+0x18)++0x03
|
|
line.long 0x00 "TCD24_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x300+0x1C)++0x01
|
|
line.word 0x00 "TCD24_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x300+0x1E)))&0x8000)==0x0)
|
|
group.word (0x300+0x1E)++0x01
|
|
line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x300+0x1E)++0x01
|
|
line.word 0x00 "TCD24_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 25"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TCD25_SADDR,TCD Source Address"
|
|
group.word (0x320+0x04)++0x03
|
|
line.word 0x00 "TCD25_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD25_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x320+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x320+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x320+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x320+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x320+0x0c)++0x07
|
|
line.long 0x00 "TCD25_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD25_DADDR,TCD Destination Address"
|
|
group.word (0x320+0x14)++0x01
|
|
line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x320+0x16)))&0x8000)==0x0)
|
|
group.word (0x320+0x16)++0x01
|
|
line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x320+0x16)++0x01
|
|
line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x320+0x18)++0x03
|
|
line.long 0x00 "TCD25_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x320+0x1C)++0x01
|
|
line.word 0x00 "TCD25_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x320+0x1E)))&0x8000)==0x0)
|
|
group.word (0x320+0x1E)++0x01
|
|
line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x320+0x1E)++0x01
|
|
line.word 0x00 "TCD25_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 26"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "TCD26_SADDR,TCD Source Address"
|
|
group.word (0x340+0x04)++0x03
|
|
line.word 0x00 "TCD26_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD26_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x340+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x340+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x340+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x340+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x340+0x0c)++0x07
|
|
line.long 0x00 "TCD26_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD26_DADDR,TCD Destination Address"
|
|
group.word (0x340+0x14)++0x01
|
|
line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x340+0x16)))&0x8000)==0x0)
|
|
group.word (0x340+0x16)++0x01
|
|
line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x340+0x16)++0x01
|
|
line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x340+0x18)++0x03
|
|
line.long 0x00 "TCD26_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x340+0x1C)++0x01
|
|
line.word 0x00 "TCD26_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x340+0x1E)))&0x8000)==0x0)
|
|
group.word (0x340+0x1E)++0x01
|
|
line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x340+0x1E)++0x01
|
|
line.word 0x00 "TCD26_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 27"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "TCD27_SADDR,TCD Source Address"
|
|
group.word (0x360+0x04)++0x03
|
|
line.word 0x00 "TCD27_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD27_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x360+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x360+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x360+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x360+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x360+0x0c)++0x07
|
|
line.long 0x00 "TCD27_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD27_DADDR,TCD Destination Address"
|
|
group.word (0x360+0x14)++0x01
|
|
line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x360+0x16)))&0x8000)==0x0)
|
|
group.word (0x360+0x16)++0x01
|
|
line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x360+0x16)++0x01
|
|
line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x360+0x18)++0x03
|
|
line.long 0x00 "TCD27_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x360+0x1C)++0x01
|
|
line.word 0x00 "TCD27_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x360+0x1E)))&0x8000)==0x0)
|
|
group.word (0x360+0x1E)++0x01
|
|
line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x360+0x1E)++0x01
|
|
line.word 0x00 "TCD27_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 28"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "TCD28_SADDR,TCD Source Address"
|
|
group.word (0x380+0x04)++0x03
|
|
line.word 0x00 "TCD28_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD28_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x380+0x08)++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x380+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x380+0x08)++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x380+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x380+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x380+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x380+0x08)++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x380+0x0c)++0x07
|
|
line.long 0x00 "TCD28_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD28_DADDR,TCD Destination Address"
|
|
group.word (0x380+0x14)++0x01
|
|
line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x380+0x16)))&0x8000)==0x0)
|
|
group.word (0x380+0x16)++0x01
|
|
line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x380+0x16)++0x01
|
|
line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x380+0x18)++0x03
|
|
line.long 0x00 "TCD28_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x380+0x1C)++0x01
|
|
line.word 0x00 "TCD28_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x380+0x1E)))&0x8000)==0x0)
|
|
group.word (0x380+0x1E)++0x01
|
|
line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x380+0x1E)++0x01
|
|
line.word 0x00 "TCD28_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 29"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "TCD29_SADDR,TCD Source Address"
|
|
group.word (0x3A0+0x04)++0x03
|
|
line.word 0x00 "TCD29_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD29_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x3A0+0x08)++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x3A0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x3A0+0x08)++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x3A0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x3A0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x3A0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x3A0+0x08)++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x3A0+0x0c)++0x07
|
|
line.long 0x00 "TCD29_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD29_DADDR,TCD Destination Address"
|
|
group.word (0x3A0+0x14)++0x01
|
|
line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x3A0+0x16)))&0x8000)==0x0)
|
|
group.word (0x3A0+0x16)++0x01
|
|
line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x3A0+0x16)++0x01
|
|
line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x3A0+0x18)++0x03
|
|
line.long 0x00 "TCD29_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x3A0+0x1C)++0x01
|
|
line.word 0x00 "TCD29_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x3A0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x3A0+0x1E)++0x01
|
|
line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x3A0+0x1E)++0x01
|
|
line.word 0x00 "TCD29_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 30"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "TCD30_SADDR,TCD Source Address"
|
|
group.word (0x3C0+0x04)++0x03
|
|
line.word 0x00 "TCD30_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD30_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x3C0+0x08)++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x3C0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x3C0+0x08)++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x3C0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x3C0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x3C0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x3C0+0x08)++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x3C0+0x0c)++0x07
|
|
line.long 0x00 "TCD30_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD30_DADDR,TCD Destination Address"
|
|
group.word (0x3C0+0x14)++0x01
|
|
line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x3C0+0x16)))&0x8000)==0x0)
|
|
group.word (0x3C0+0x16)++0x01
|
|
line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x3C0+0x16)++0x01
|
|
line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x3C0+0x18)++0x03
|
|
line.long 0x00 "TCD30_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x3C0+0x1C)++0x01
|
|
line.word 0x00 "TCD30_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x3C0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x3C0+0x1E)++0x01
|
|
line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x3C0+0x1E)++0x01
|
|
line.word 0x00 "TCD30_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 31"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "TCD31_SADDR,TCD Source Address"
|
|
group.word (0x3E0+0x04)++0x03
|
|
line.word 0x00 "TCD31_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD31_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
if (((per.l(ad:0x40008000))&0x80)==0x0)
|
|
group.long (0x3E0+0x08)++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&(((per.l(ad:0x40009000+(0x3E0+0x08)))&0xc0000000)==0x0))
|
|
group.long (0x3E0+0x08)++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
elif ((((per.l(ad:0x40008000))&0x80)==0x80)&&((((per.l(ad:0x40009000+(0x3E0+0x08)))&0xc0000000)==0x80000000)||(((per.l(ad:0x40009000+(0x3E0+0x08)))&0xc0000000)==0x40000000)||(((per.l(ad:0x40009000+(0x3E0+0x08)))&0xc0000000)==0xc0000000)))
|
|
group.long (0x3E0+0x08)++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/Destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x3E0+0x0c)++0x07
|
|
line.long 0x00 "TCD31_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD31_DADDR,TCD Destination Address"
|
|
group.word (0x3E0+0x14)++0x01
|
|
line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x3E0+0x16)))&0x8000)==0x0)
|
|
group.word (0x3E0+0x16)++0x01
|
|
line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x3E0+0x16)++0x01
|
|
line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x3E0+0x18)++0x03
|
|
line.long 0x00 "TCD31_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
group.word (0x3E0+0x1C)++0x01
|
|
line.word 0x00 "TCD31_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x3E0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x3E0+0x1E)++0x01
|
|
line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x3E0+0x1E)++0x01
|
|
line.word 0x00 "TCD31_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
elif (cpuis("MKW01Z128*")||cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x40008100
|
|
width 11.
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "SAR0,Source Address Register 0"
|
|
line.long 0x04 "DAR0,Destination Address Register 0"
|
|
line.long 0x08 "DSR_BCR0,DMA Status Register / Byte Count Register 0"
|
|
rbitfld.long 0x08 30. " CE ,Configuration error" "No error,Error"
|
|
rbitfld.long 0x08 29. " BES ,Bus error on source" "No error,Error"
|
|
rbitfld.long 0x08 28. " BED ,Bus error on destination" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x08 26. " REQ ,Request" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 25. " BSY , Busy" "Idle,Busy"
|
|
eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Bytes yet to be transferred counter"
|
|
line.long 0x0C "DMA_DCR0,Control Register 0"
|
|
bitfld.long 0x0C 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ERQ ,Enable peripheral request" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " CS ,Cycle steal" "Continuous,Single"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AA ,Auto-align" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SINC ,Source increment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..."
|
|
bitfld.long 0x0C 19. " DINC ,Destination increment" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 16. " START ,Start transfer" "Inactive,Active"
|
|
bitfld.long 0x0C 12.--15. " SMOD ,Source address modulo" "Disabled,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB"
|
|
bitfld.long 0x0C 8.--11. " DMOD ,Destination address modulo" "Disabled,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " D_REQ ,Disable request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " LINKCC ,Link channel control" "Disabled,After each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0,After cycle-steal transfer,After the BCR decrements to 0"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " LCH1 ,Link channel 1" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
bitfld.long 0x0C 0.--1. " LCH2 ,Link channel 2" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "SAR1,Source Address Register 1"
|
|
line.long 0x04 "DAR1,Destination Address Register 1"
|
|
line.long 0x08 "DSR_BCR1,DMA Status Register / Byte Count Register 1"
|
|
rbitfld.long 0x08 30. " CE ,Configuration error" "No error,Error"
|
|
rbitfld.long 0x08 29. " BES ,Bus error on source" "No error,Error"
|
|
rbitfld.long 0x08 28. " BED ,Bus error on destination" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x08 26. " REQ ,Request" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 25. " BSY , Busy" "Idle,Busy"
|
|
eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Bytes yet to be transferred counter"
|
|
line.long 0x0C "DMA_DCR1,Control Register 1"
|
|
bitfld.long 0x0C 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ERQ ,Enable peripheral request" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " CS ,Cycle steal" "Continuous,Single"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AA ,Auto-align" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SINC ,Source increment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..."
|
|
bitfld.long 0x0C 19. " DINC ,Destination increment" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 16. " START ,Start transfer" "Inactive,Active"
|
|
bitfld.long 0x0C 12.--15. " SMOD ,Source address modulo" "Disabled,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB"
|
|
bitfld.long 0x0C 8.--11. " DMOD ,Destination address modulo" "Disabled,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " D_REQ ,Disable request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " LINKCC ,Link channel control" "Disabled,After each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0,After cycle-steal transfer,After the BCR decrements to 0"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " LCH1 ,Link channel 1" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
bitfld.long 0x0C 0.--1. " LCH2 ,Link channel 2" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SAR2,Source Address Register 2"
|
|
line.long 0x04 "DAR2,Destination Address Register 2"
|
|
line.long 0x08 "DSR_BCR2,DMA Status Register / Byte Count Register 2"
|
|
rbitfld.long 0x08 30. " CE ,Configuration error" "No error,Error"
|
|
rbitfld.long 0x08 29. " BES ,Bus error on source" "No error,Error"
|
|
rbitfld.long 0x08 28. " BED ,Bus error on destination" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x08 26. " REQ ,Request" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 25. " BSY , Busy" "Idle,Busy"
|
|
eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Bytes yet to be transferred counter"
|
|
line.long 0x0C "DMA_DCR2,Control Register 2"
|
|
bitfld.long 0x0C 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ERQ ,Enable peripheral request" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " CS ,Cycle steal" "Continuous,Single"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AA ,Auto-align" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SINC ,Source increment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..."
|
|
bitfld.long 0x0C 19. " DINC ,Destination increment" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 16. " START ,Start transfer" "Inactive,Active"
|
|
bitfld.long 0x0C 12.--15. " SMOD ,Source address modulo" "Disabled,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB"
|
|
bitfld.long 0x0C 8.--11. " DMOD ,Destination address modulo" "Disabled,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " D_REQ ,Disable request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " LINKCC ,Link channel control" "Disabled,After each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0,After cycle-steal transfer,After the BCR decrements to 0"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " LCH1 ,Link channel 1" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
bitfld.long 0x0C 0.--1. " LCH2 ,Link channel 2" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "SAR3,Source Address Register 3"
|
|
line.long 0x04 "DAR3,Destination Address Register 3"
|
|
line.long 0x08 "DSR_BCR3,DMA Status Register / Byte Count Register 3"
|
|
rbitfld.long 0x08 30. " CE ,Configuration error" "No error,Error"
|
|
rbitfld.long 0x08 29. " BES ,Bus error on source" "No error,Error"
|
|
rbitfld.long 0x08 28. " BED ,Bus error on destination" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x08 26. " REQ ,Request" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 25. " BSY , Busy" "Idle,Busy"
|
|
eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Bytes yet to be transferred counter"
|
|
line.long 0x0C "DMA_DCR3,Control Register 3"
|
|
bitfld.long 0x0C 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ERQ ,Enable peripheral request" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " CS ,Cycle steal" "Continuous,Single"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AA ,Auto-align" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SINC ,Source increment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..."
|
|
bitfld.long 0x0C 19. " DINC ,Destination increment" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 16. " START ,Start transfer" "Inactive,Active"
|
|
bitfld.long 0x0C 12.--15. " SMOD ,Source address modulo" "Disabled,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB"
|
|
bitfld.long 0x0C 8.--11. " DMOD ,Destination address modulo" "Disabled,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " D_REQ ,Disable request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " LINKCC ,Link channel control" "Disabled,After each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0,After cycle-steal transfer,After the BCR decrements to 0"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " LCH1 ,Link channel 1" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
bitfld.long 0x0C 0.--1. " LCH2 ,Link channel 2" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "EWM (External Watchdog Monitor)"
|
|
base ad:0x40061000
|
|
width 7.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CTRL,Control Register"
|
|
bitfld.byte 0x00 3. " INTEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " INEN ,Enables the EWM_in port" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ASSIN ,Inverts the assert state to a logic one" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " EWMEN ,EWM module enable" "Disabled,Enabled"
|
|
wgroup.byte 0x01++0x00
|
|
line.byte 0x00 "SERV,Service Register"
|
|
group.byte 0x02++0x01
|
|
line.byte 0x00 "CMPL,Compare Low Register"
|
|
line.byte 0x01 "CMPH,Compare High register"
|
|
sif cpuis("MKV31F*")||cpuis("MKV30F*")
|
|
width 14.
|
|
textline " "
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register"
|
|
endif
|
|
sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")))
|
|
width 14.
|
|
textline " "
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "CLKCTRL,Clock Control Register"
|
|
bitfld.byte 0x00 0.--1. " CLKSEL ,Low Power Source for Running EWM counter" "Lpo_clk[0],Lpo_clk[1],Lpo_clk[2],Lpo_clk[3]"
|
|
line.byte 0x01 "CLKPRESCALER,Clock Prescaler Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer)"
|
|
base ad:0x40052000
|
|
width 9.
|
|
group.word 0x00++0x17
|
|
line.word 0x00 "STCTRLH,Watchdog Status and Control Register High"
|
|
bitfld.word 0x00 14. " DISTESTWDOG ,Allows the WDOG functional test mode to be disabled permanently" "No,Yes"
|
|
bitfld.word 0x00 12.--13. " BYTESEL[1:0] ,Select the byte to be tested when the watchdog is in the byte test mode" "Byte 0,Byte 1,Byte 2,Byte 3"
|
|
bitfld.word 0x00 11. " TESTSEL ,Selects the test to be run on the watchdog timer" "Quick test,Byte test"
|
|
textline " "
|
|
bitfld.word 0x00 10. " TESTWDOG ,Puts the watchdog in the functional test mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " WAITEN ,Enables or disables WDOG in wait mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STOPEN ,Enables or disables WDOG in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DBGEN ,Enables or disables WDOG in debug mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ALLOWUPDATE ,Enables updates to watchdog write once registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " WINEN ,Enable windowing mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " IRQRSTEN ,Enable the debug breadcrumbs feature" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CLKSRC ,Selects clock source for the WDOG timer and other internal timing operations" "LPO Osc,Alternate"
|
|
bitfld.word 0x00 0. " WDOGEN ,Enables or disables the WDOG operation" "Disabled,Enabled"
|
|
line.word 0x02 "STCTRLL,Watchdog Status and Control Register Low"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKW2?D*"))
|
|
eventfld.word 0x02 15. " INT_FLG ,Interrupt Flag" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.word 0x02 15. " INT_FLG ,Interrupt Flag" "No interrupt,Interrupt"
|
|
endif
|
|
line.word 0x04 "TOVALH,Watchdog Time-out Value Register High"
|
|
line.word 0x06 "TOVALL,Watchdog Time-out Value Register Low"
|
|
line.word 0x08 "WINH,Watchdog Window Register High"
|
|
line.word 0x0a "WINL,Watchdog Window Register Low"
|
|
line.word 0x0c "REFRESH,Watchdog Refresh Register"
|
|
line.word 0x0e "UNLOCK,Watchdog Unlock Register"
|
|
line.word 0x10 "TMROUTH,Watchdog Timer Output Register High"
|
|
line.word 0x12 "TMROUTL,Watchdog Timer Output Register Low"
|
|
line.word 0x14 "RSTCNT,Watchdog Reset Count Register"
|
|
line.word 0x16 "PRESC,Watchdog Prescaler Register"
|
|
bitfld.word 0x16 8.--10. " PRESCVAL ,3-bit prescaler for the watchdog clock source" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "MCG (Multipurpose Clock Generator)"
|
|
base ad:0x40064000
|
|
width 7.
|
|
sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24"))
|
|
if (((per.l(ad:0x40064000+0x01))&0x30)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control 1 Register"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..."
|
|
bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control 1 Register"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..."
|
|
bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40064000+0x01))&0x30)==0x00||((per.l(ad:0x40064000+0x0C))&0x01)==0x01)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control 1 Register"
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" ",Internal ref clk,External ref clk,?..."
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..."
|
|
else
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..."
|
|
endif
|
|
bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control 1 Register"
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" ",Internal ref clk,External ref clk,?..."
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..."
|
|
else
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..."
|
|
endif
|
|
bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.byte 0x01++0x01
|
|
line.byte 0x00 "C2,MCG Control 2 Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||(cpuis("MKW4?Z*"))||(cpuis("MKW3?Z*"))||(cpuis("MKW2?Z*")))
|
|
bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease"
|
|
bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain"
|
|
bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext ref,Osc"
|
|
bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast"
|
|
elif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5"))
|
|
bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x00 4.--5. " RANGE0 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2"
|
|
bitfld.byte 0x00 3. " HGO0 ,High gain oscillator select" "Low-power,High-gain"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EREFS0 ,External reference select" "Ext ref,Osc"
|
|
bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast"
|
|
else
|
|
bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease"
|
|
bitfld.byte 0x00 4.--5. " RANGE0 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HGO0 ,High gain oscillator select" "Low-power,High-gain"
|
|
bitfld.byte 0x00 2. " EREFS0 ,External reference select" "Ext ref,Osc"
|
|
bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast"
|
|
endif
|
|
line.byte 0x01 "C3,MCG Control 3 Register"
|
|
if (((per.l(ad:0x40064000+0x03))&0x60)==0x0)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C4,MCG Control 4 Register"
|
|
bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "20-25 mHz,24 mHz"
|
|
bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease"
|
|
elif (((per.l(ad:0x40064000+0x03))&0x60)==0x20)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C4,MCG Control 4 Register"
|
|
bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "40-50 mHz,48 mHz"
|
|
bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease"
|
|
elif (((per.l(ad:0x40064000+0x03))&0x60)==0x40)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C4,MCG Control 4 Register"
|
|
bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "60-75 mHz,72 mHz"
|
|
bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C4,MCG Control 4 Register"
|
|
bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "80-100 mHz,96 mHz"
|
|
bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease"
|
|
endif
|
|
sif (cpuis("MKV10Z*"))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "C6,MCG Control 6 Register"
|
|
bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled"
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "C6,MCG Control 6 Register"
|
|
bitfld.byte 0x00 5. " CME0 ,Clock monitor enable" "Disabled,Enabled"
|
|
elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKW01*")||cpuis("MKW2?D*"))
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "C5,MCG Control 5 Register"
|
|
bitfld.byte 0x00 6. " PLLCLKEN0 ,PLL clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PLLSTEN0 ,PLL stop enable" "Disabled,Enabled"
|
|
sif (cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKW21D256VHA5R")||cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " PRDIV0 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..."
|
|
textline " "
|
|
elif (cpuis("MKW2?D*"))
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " PRDIV0 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,?..."
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
line.byte 0x01 "C6,MCG Control 6 Register"
|
|
bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL"
|
|
bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0.--4. " VDIV0 ,VCO 0 divider" "24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55"
|
|
else
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "C5,MCG Control 5 Register"
|
|
bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
line.byte 0x01 "C6,MCG Control 6 Register"
|
|
bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL"
|
|
bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0.--4. " VDIV ,VCO divider" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47"
|
|
endif
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "S,MCG Status Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal"
|
|
bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,?..."
|
|
bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock"
|
|
else
|
|
bitfld.byte 0x00 7. " LOLS0 ,Loss of lock status" "Not locked,Locked"
|
|
bitfld.byte 0x00 6. " LOCK0 ,Lock status" "Not locked,Locked"
|
|
bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal"
|
|
bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,Output PLL"
|
|
bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock"
|
|
endif
|
|
group.byte 0x08++0x00
|
|
sif ((cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24"))
|
|
line.byte 0x00 "SC,MCG Status And Control Register"
|
|
bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz"
|
|
eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--3. " FCRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
eventfld.byte 0x00 0. " LOCS0 ,OSC0 loss of clock status" "Not occurred,Occurred"
|
|
elif (cpuis("MKW2?D*"))
|
|
line.byte 0x00 "SC,MCG Status And Control Register"
|
|
bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz"
|
|
rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
eventfld.byte 0x00 0. " LOCS ,Loss of clock status" "Not occurred,Occurred"
|
|
else
|
|
line.byte 0x00 "SC,MCG Status And Control Register"
|
|
bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz"
|
|
rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
rbitfld.byte 0x00 0. " LOCS ,Loss of clock status" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
group.byte 0x0A++0x01
|
|
line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register"
|
|
line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register"
|
|
textline " "
|
|
sif (cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12"))
|
|
group.byte 0x0C++0x01
|
|
line.byte 0x00 "C7,MCG Control 7 Register"
|
|
bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32khz RTC,OSCCLK1,?..."
|
|
line.byte 0x01 "C8,MCG Control 8 Register"
|
|
bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred"
|
|
elif ((cpu()!="MKV40F64VLH15")&&(cpu()!="MKV40F128VLH15")&&(cpu()!="MKV40F128VLL15")&&(cpu()!="MKV40F256VLH15")&&(cpu()!="MKV40F256VLL15")&&(cpu()!="MKV43F64VLH15")&&(cpu()!="MKV43F128VLH15")&&(cpu()!="MKV43F128VLL15")&&(cpu()!="MKV44F64VLH15")&&(cpu()!="MKV44F128VLH15")&&(cpu()!="MKV44F128VLL15")&&(cpu()!="MKV45F128VLH15")&&(cpu()!="MKV45F128VLL15")&&(cpu()!="MKV45F256VLH15")&&(cpu()!="MKV45F256VLL15")&&(cpu()!="MKV46F128VLH15")&&(cpu()!="MKV46F128VLL15")&&(cpu()!="MKV46F256VLH15")&&(cpu()!="MKV46F256VLL15")&&(!cpuis("MKV10Z*"))&&(!cpuis("MKV5*")))
|
|
group.byte 0x0C++0x01
|
|
line.byte 0x00 "C7,MCG Control 7 Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.byte 0x00 0. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32 kHz RTC"
|
|
else
|
|
bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32 kHz RTC,OSCCLK1,?..."
|
|
endif
|
|
line.byte 0x01 "C8,MCG Control 8 Register"
|
|
sif (!cpuis("MKW01Z128*")&&!cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*"))
|
|
bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred"
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled"
|
|
eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset"
|
|
endif
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "C9,MCG Control 9 Register"
|
|
bitfld.byte 0x00 5. " PLL_CME ,MCG external PLL clock monitor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PLL_LOCRE ,MCG external PLL loss of clock reset enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " EXT_PLL_LOCS ,External PLL loss of clock status" "Not occurred,Occurred"
|
|
endif
|
|
else
|
|
sif ((cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24"))
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "C8,MCG Control 8 Register"
|
|
bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset"
|
|
elif !cpuis("MKV10Z*")
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "C8,MCG Control 8 Register"
|
|
bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred"
|
|
endif
|
|
endif
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "C11,MCG Control 11 Register"
|
|
bitfld.byte 0x00 4. " PLLCS ,PLL clock select" "PLL0 output,External PLL"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "S2,MCG Status 2 Register"
|
|
bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL clock,EXT_PLL clock"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*"))
|
|
tree "OSC (Oscillator)"
|
|
base ad:0x40065000
|
|
width 5.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR,OSC Control Register"
|
|
bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled"
|
|
sif ((cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV30F*")||cpuis("MKV31F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16"))
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "DIV,OSC Clock Divider Register"
|
|
bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x4001F000
|
|
width 8.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PFAPR,Flash Access Protection Register"
|
|
sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16"))
|
|
bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M2AP[1:0] ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
bitfld.long 0x00 2.--3. " M1AP[1:0] ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
bitfld.long 0x00 0.--1. " M0AP[1:0] ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
elif (cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5"))||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " M7AP[1:0] ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
bitfld.long 0x00 12.--13. " M6AP[1:0] ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " M5AP[1:0] ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
bitfld.long 0x00 8.--9. " M4AP[1:0] ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " M3AP[1:0] ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
bitfld.long 0x00 4.--5. " M2AP[1:0] ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " M1AP[1:0] ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
bitfld.long 0x00 0.--1. " M0AP[1:0] ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
else
|
|
bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " M7AP[1:0] ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
bitfld.long 0x00 12.--13. " M6AP[1:0] ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " M5AP[1:0] ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
bitfld.long 0x00 8.--9. " M4AP[1:0] ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " M3AP[1:0] ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses"
|
|
endif
|
|
line.long 0x04 "PFB0CR,Flash Bank 0 Control Register"
|
|
rbitfld.long 0x04 28.--31. " B0RWSC[3:0] ,Bank 0 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x04 27. " CLCK_WAY[3] ,Cache lock way 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " CLCK_WAY[2] ,Cache lock way 2" "Not locked,Locked"
|
|
bitfld.long 0x04 25. " CLCK_WAY[1] ,Cache lock way 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x04 24. " CLCK_WAY[0] ,Cache lock way 0" "Not locked,Locked"
|
|
bitfld.long 0x04 23. " CINV_WAY[3] ,Cache invalidate way 3" "No effect,Invalidate"
|
|
textline " "
|
|
bitfld.long 0x04 22. " CINV_WAY[2] ,Cache invalidate way 2" "No effect,Invalidate"
|
|
bitfld.long 0x04 21. " CINV_WAY[1] ,Cache invalidate way 1" "No effect,Invalidate"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CINV_WAY[0] ,Cache invalidate way 0" "No effect,Invalidate"
|
|
bitfld.long 0x04 19. " S_B_INV ,Invalidate prefetch speculation buffer" "No effect,Invalidate"
|
|
textline " "
|
|
sif (cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKV44F64*"))
|
|
rbitfld.long 0x04 17.--18. " B0MW[1:0] ,Bank 0 memory width" "32 bits,64 bits,?..."
|
|
else
|
|
rbitfld.long 0x04 17.--18. " B0MW[1:0] ,Bank 0 memory width" "32 bits,64 bits,128 bits,?..."
|
|
endif
|
|
bitfld.long 0x04 5.--7. " CRC[2:0] ,Cache replacement control" "LRU per 4 ways,,LRU with 0-1 ways,LRU with 0-2 ways,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4. " B0DCE ,Bank 0 data cache enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " B0ICE ,Bank 0 instruction cache enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " B0DPE ,Bank 0 data prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " B0IPE ,Bank 0 instruction prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " B0SEBE ,Bank 0 single entry buffer enable" "Disabled,Enabled"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PFB1CR,Flash Bank 1 Control Register"
|
|
rbitfld.long 0x00 28.--31. " B1RWSC[3:0] ,Bank 1 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rbitfld.long 0x00 17.--18. " B1MW[1:0] ,Bank 1 memory width" "32 bits,64 bits,128 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " B1DCE ,Bank 1 data cache enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " B1ICE ,Bank 1 instruction cache enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " B1DPE ,Bank 1 data prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " B1IPE ,Bank 1 instruction prefetch enable" "Disabled,Enabled"
|
|
elif ((cpu()!="MKV40F64VLH15")&&(cpu()!="MKV40F128VLH15")&&(cpu()!="MKV40F128VLL15")&&(cpu()!="MKV40F256VLH15")&&(cpu()!="MKV40F256VLL15")&&(cpu()!="MKV43F64VLH15")&&(cpu()!="MKV43F128VLH15")&&(cpu()!="MKV43F128VLL15")&&(cpu()!="MKV44F64VLH15")&&(cpu()!="MKV44F128VLH15")&&(cpu()!="MKV44F128VLL15")&&(cpu()!="MKV45F128VLH15")&&(cpu()!="MKV45F128VLL15")&&(cpu()!="MKV45F256VLH15")&&(cpu()!="MKV45F256VLL15")&&(cpu()!="MKV46F128VLH15")&&(cpu()!="MKV46F128VLL15")&&(cpu()!="MKV46F256VLH15")&&(cpu()!="MKV46F256VLL15")&&(cpu()!="MKV42F128VLL16")&&(cpu()!="MKV42F256VLL16")&&(cpu()!="MKV44F128VLL16")&&(cpu()!="MKV44F256VLL16")&&(cpu()!="MKV46F128VLL16")&&(cpu()!="MKV46F256VLL16")&&(cpu()!="MKV42F128VLH16")&&(cpu()!="MKV42F256VLH16")&&(cpu()!="MKV44F128VLH16")&&(cpu()!="MKV44F256VLH16")&&(cpu()!="MKV44F64VLH16")&&(cpu()!="MKV46F128VLH16")&&(cpu()!="MKV46F256VLH16")&&(cpu()!="MKV44F128VLF16")&&(cpu()!="MKV44F64VLF16"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PFB1CR,Flash Bank 1 Control Register"
|
|
rbitfld.long 0x00 28.--31. " B1RWSC[3:0] ,Bank 1 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
sif (cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5"))
|
|
rbitfld.long 0x00 17.--18. " B1MW[1:0] ,Bank 1 memory width" "32 bits,64 bits,?..."
|
|
else
|
|
rbitfld.long 0x00 17.--18. " B1MW[1:0] ,Bank 1 memory width" "32 bits,64 bits,128 bits,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " B1DCE ,Bank 1 data cache enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " B1ICE ,Bank 1 instruction cache enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " B1DPE ,Bank 1 data prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " B1IPE ,Bank 1 instruction prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B1SEBE ,Bank 1 single entry buffer enable" "Disabled,Enabled"
|
|
endif
|
|
width 13.
|
|
tree "Cache Directory Storage Registers"
|
|
sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16"))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TAGVDW0S0,Cache Directory Storage Way 0 Set 0"
|
|
hexmask.long.word 0x00 5.--19. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TAGVDW0S1,Cache Directory Storage Way 0 Set 1"
|
|
hexmask.long.word 0x00 5.--19. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TAGVDW1S0,Cache Directory Storage Way 1 Set 0"
|
|
hexmask.long.word 0x00 5.--19. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TAGVDW1S1,Cache Directory Storage Way 1 Set 1"
|
|
hexmask.long.word 0x00 5.--19. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TAGVDW2S0,Cache Directory Storage Way 2 Set 0"
|
|
hexmask.long.word 0x00 5.--19. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TAGVDW2S1,Cache Directory Storage Way 2 Set 1"
|
|
hexmask.long.word 0x00 5.--19. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TAGVDW3S0,Cache Directory Storage Way 3 Set 0"
|
|
hexmask.long.word 0x00 5.--19. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TAGVDW3S1,Cache Directory Storage Way 3 Set 1"
|
|
hexmask.long.word 0x00 5.--19. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
elif cpuis("MKV31F*")||cpuis("MKV30F*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TAGVDW0S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TAGVDW0S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TAGVDW0S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TAGVDW0S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TAGVDW0S4,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TAGVDW0S5,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TAGVDW0S6,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TAGVDW0S7,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TAGVDW1S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TAGVDW1S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TAGVDW1S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TAGVDW1S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TAGVDW1S4,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TAGVDW1S5,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TAGVDW1S6,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TAGVDW1S7,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TAGVDW2S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TAGVDW2S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TAGVDW2S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TAGVDW2S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TAGVDW2S4,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TAGVDW2S5,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TAGVDW2S6,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TAGVDW2S7,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TAGVDW3S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TAGVDW3S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TAGVDW3S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TAGVDW3S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TAGVDW3S4,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TAGVDW3S5,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TAGVDW3S6,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TAGVDW3S7,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[19:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
elif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5"))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TAGVDW0S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 4.--18. 1. " TAG[18:4] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TAGVDW0S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 4.--18. 1. " TAG[18:4] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TAGVDW1S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 4.--18. 1. " TAG[18:4] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TAGVDW1S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 4.--18. 1. " TAG[18:4] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TAGVDW2S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 4.--18. 1. " TAG[18:4] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TAGVDW2S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 4.--18. 1. " TAG[18:4] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TAGVDW3S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 4.--18. 1. " TAG[18:4] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TAGVDW3S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 4.--18. 1. " TAG[18:4] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TAGVDW0S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TAGVDW0S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TAGVDW0S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TAGVDW0S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TAGVDW1S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TAGVDW1S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TAGVDW1S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TAGVDW1S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TAGVDW2S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TAGVDW2S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TAGVDW2S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TAGVDW2S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TAGVDW3S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TAGVDW3S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TAGVDW3S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TAGVDW3S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 6.--21. 1. " TAG[21:6] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TAGVDW0S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TAGVDW0S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TAGVDW0S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TAGVDW0S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TAGVDW1S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TAGVDW1S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TAGVDW1S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TAGVDW1S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TAGVDW2S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TAGVDW2S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TAGVDW2S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TAGVDW2S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TAGVDW3S0,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TAGVDW3S1,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TAGVDW3S2,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TAGVDW3S3,Cache Directory Storage"
|
|
hexmask.long.word 0x00 5.--18. 1. " TAG[18:5] ,Tag for cache entry"
|
|
bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid"
|
|
endif
|
|
tree.end
|
|
tree "Cache Data Storage Registers"
|
|
sif (cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FX512VDC12")||(cpu()=="MK64FX512VLL12")||(cpu()=="MK64FX512VLQ12")||(cpu()=="MK64FX512VMD12")
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x208++0x07
|
|
line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x210++0x07
|
|
line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)"
|
|
group.long 0x218++0x07
|
|
line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)"
|
|
group.long 0x220++0x07
|
|
line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x228++0x07
|
|
line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x230++0x07
|
|
line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)"
|
|
group.long 0x238++0x07
|
|
line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)"
|
|
group.long 0x240++0x07
|
|
line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x248++0x07
|
|
line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x250++0x07
|
|
line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)"
|
|
group.long 0x258++0x07
|
|
line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)"
|
|
group.long 0x260++0x07
|
|
line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x268++0x07
|
|
line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x270++0x07
|
|
line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)"
|
|
group.long 0x278++0x07
|
|
line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
group.long (0x0+0x200)++0x0F
|
|
line.long 0x00 "DATAW0S0UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW0S0MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW0S0ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW0S0LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x10+0x200)++0x0F
|
|
line.long 0x00 "DATAW0S1UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW0S1MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW0S1ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW0S1LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x20+0x200)++0x0F
|
|
line.long 0x00 "DATAW0S2UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW0S2MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW0S2ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW0S2LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x30+0x200)++0x0F
|
|
line.long 0x00 "DATAW0S3UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW0S3MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW0S3ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW0S3LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x40+0x200)++0x0F
|
|
line.long 0x00 "DATAW1S0UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW1S0MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW1S0ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW1S0LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x50+0x200)++0x0F
|
|
line.long 0x00 "DATAW1S1UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW1S1MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW1S1ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW1S1LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x60+0x200)++0x0F
|
|
line.long 0x00 "DATAW1S2UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW1S2MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW1S2ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW1S2LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x70+0x200)++0x0F
|
|
line.long 0x00 "DATAW1S3UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW1S3MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW1S3ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW1S3LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x80+0x200)++0x0F
|
|
line.long 0x00 "DATAW2S0UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW2S0MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW2S0ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW2S0LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x90+0x200)++0x0F
|
|
line.long 0x00 "DATAW2S1UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW2S1MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW2S1ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW2S1LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0xA0+0x200)++0x0F
|
|
line.long 0x00 "DATAW2S2UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW2S2MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW2S2ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW2S2LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0xB0+0x200)++0x0F
|
|
line.long 0x00 "DATAW2S3UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW2S3MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW2S3ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW2S3LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0xC0+0x200)++0x0F
|
|
line.long 0x00 "DATAW3S0UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW3S0MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW3S0ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW3S0LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0xD0+0x200)++0x0F
|
|
line.long 0x00 "DATAW3S1UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW3S1MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW3S1ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW3S1LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0xE0+0x200)++0x0F
|
|
line.long 0x00 "DATAW3S2UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW3S2MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW3S2ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW3S2LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0xF0+0x200)++0x0F
|
|
line.long 0x00 "DATAW3S3UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW3S3MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW3S3ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW3S3LM,Cache Data Storage (Lowermost Word)"
|
|
elif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16"))
|
|
group.long (0x0+0x200)++0x0F
|
|
line.long 0x00 "DATAW0S0UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW0S0MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW0S0ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW0S0LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x10+0x200)++0x0F
|
|
line.long 0x00 "DATAW0S1UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW0S1MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW0S1ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW0S1LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x20+0x200)++0x0F
|
|
line.long 0x00 "DATAW1S0UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW1S0MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW1S0ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW1S0LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x30+0x200)++0x0F
|
|
line.long 0x00 "DATAW1S1UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW1S1MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW1S1ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW1S1LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x40+0x200)++0x0F
|
|
line.long 0x00 "DATAW2S0UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW2S0MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW2S0ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW2S0LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x50+0x200)++0x0F
|
|
line.long 0x00 "DATAW2S1UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW2S1MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW2S1ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW2S1LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x60+0x200)++0x0F
|
|
line.long 0x00 "DATAW3S0UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW3S0MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW3S0ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW3S0LM,Cache Data Storage (Lowermost Word)"
|
|
group.long (0x70+0x200)++0x0F
|
|
line.long 0x00 "DATAW3S1UM,Cache Data Storage (Uppermost Word)"
|
|
line.long 0x04 "DATAW3S1MU,Cache Data Storage (Mid Upper)"
|
|
line.long 0x08 "DATAW3S1ML,Cache Data Storage (Mid Lower)"
|
|
line.long 0x0C "DATAW3S1LM,Cache Data Storage (Lowermost Word)"
|
|
elif cpuis("MKV31F*")||cpuis("MKV30F*")
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x208++0x07
|
|
line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x210++0x07
|
|
line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)"
|
|
group.long 0x218++0x07
|
|
line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)"
|
|
group.long 0x220++0x07
|
|
line.long 0x00 "DATAW0S4U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S4L,Cache Data Storage (Lower Word)"
|
|
group.long 0x228++0x07
|
|
line.long 0x00 "DATAW0S5U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S5L,Cache Data Storage (Lower Word)"
|
|
group.long 0x230++0x07
|
|
line.long 0x00 "DATAW0S6U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S6L,Cache Data Storage (Lower Word)"
|
|
group.long 0x238++0x07
|
|
line.long 0x00 "DATAW0S7U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S7L,Cache Data Storage (Lower Word)"
|
|
group.long 0x240++0x07
|
|
line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x248++0x07
|
|
line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x250++0x07
|
|
line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)"
|
|
group.long 0x258++0x07
|
|
line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)"
|
|
group.long 0x260++0x07
|
|
line.long 0x00 "DATAW1S4U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S4L,Cache Data Storage (Lower Word)"
|
|
group.long 0x268++0x07
|
|
line.long 0x00 "DATAW1S5U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S5L,Cache Data Storage (Lower Word)"
|
|
group.long 0x270++0x07
|
|
line.long 0x00 "DATAW1S6U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S6L,Cache Data Storage (Lower Word)"
|
|
group.long 0x278++0x07
|
|
line.long 0x00 "DATAW1S7U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S7L,Cache Data Storage (Lower Word)"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x288++0x07
|
|
line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x290++0x07
|
|
line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)"
|
|
group.long 0x298++0x07
|
|
line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2A0++0x07
|
|
line.long 0x00 "DATAW2S4U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S4L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2A8++0x07
|
|
line.long 0x00 "DATAW2S5U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S5L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2B0++0x07
|
|
line.long 0x00 "DATAW2S6U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S6L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2B8++0x07
|
|
line.long 0x00 "DATAW2S7U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S7L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2C0++0x07
|
|
line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2C8++0x07
|
|
line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2D0++0x07
|
|
line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2D8++0x07
|
|
line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2E0++0x07
|
|
line.long 0x00 "DATAW3S4U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S4L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2E8++0x07
|
|
line.long 0x00 "DATAW3S5U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S5L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2F0++0x07
|
|
line.long 0x00 "DATAW3S6U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S6L,Cache Data Storage (Lower Word)"
|
|
group.long 0x2F8++0x07
|
|
line.long 0x00 "DATAW3S7U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S7L,Cache Data Storage (Lower Word)"
|
|
elif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5"))
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x208++0x07
|
|
line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x210++0x07
|
|
line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x218++0x07
|
|
line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x220++0x07
|
|
line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x228++0x07
|
|
line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)"
|
|
group.long 0x230++0x07
|
|
line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)"
|
|
group.long 0x238++0x07
|
|
line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)"
|
|
line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "FTFL (Flash Memory Module)"
|
|
base ad:0x40020000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed"
|
|
eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error"
|
|
eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error"
|
|
line.byte 0x01 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased"
|
|
bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended"
|
|
sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKW??Z*")
|
|
sif (cpuis("MKV5*"))
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready"
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not ready,Ready"
|
|
elif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||cpuis("MKV31F*")||cpuis("MKV30F*")||(cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16"))
|
|
textline " "
|
|
rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block,1 block"
|
|
rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "2 flash and 2 flex blocks,?..."
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available"
|
|
elif cpuis("K32W0?2S1M*")
|
|
rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000"
|
|
rbitfld.byte 0x01 2. " CRCRDY ,CRC ready" "Not available,Available"
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
else
|
|
textline " "
|
|
rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "Supported,?..."
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available"
|
|
endif
|
|
endif
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled"
|
|
bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted"
|
|
bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")||cpuis("MKW*")||cpuis("MKV5*")
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "FCCOB3,Flash Common Command Object Registers"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "FCCOB2,Flash Common Command Object Registers"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "FCCOB1,Flash Common Command Object Registers"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "FCCOB0,Flash Common Command Object Registers"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "FCCOB7,Flash Common Command Object Registers"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "FCCOB6,Flash Common Command Object Registers"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "FCCOB5,Flash Common Command Object Registers"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "FCCOB4,Flash Common Command Object Registers"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "FCCOBB,Flash Common Command Object Registers"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "FCCOBA,Flash Common Command Object Registers"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "FCCOB9,Flash Common Command Object Registers"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "FCCOB8,Flash Common Command Object Registers"
|
|
sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKW*")&&!cpuis("MKV5*")
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte (0x10+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x11+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x12+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x13+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5"))
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
elif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROT1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROT0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
elif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROTH3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTH2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTH1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTH0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
elif (cpuis("MKW*"))
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROT1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROT0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
else
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "FPROTH3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTH2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTH1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTH0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte 0x1C++0x03
|
|
line.byte 0x00 "FPROTL3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTL2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTL1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTL0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
endif
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte 0x24++0x01
|
|
line.byte 0x00 "FPROTSL,Secondary Program Flash Protection Registers"
|
|
line.byte 0x01 "FPROTSH,Secondary Program Flash Protection Registers"
|
|
endif
|
|
sif (cpu()!="MK63FN1M0VLQ12")&&(cpu()!="MK63FN1M0VMD12")&&(cpu()!="MKV40F64VLH15")&&(cpu()!="MKV40F128VLH15")&&(cpu()!="MKV40F128VLL15")&&(cpu()!="MKV40F256VLH15")&&(cpu()!="MKV40F256VLL15")&&(cpu()!="MKV43F64VLH15")&&(cpu()!="MKV43F128VLH15")&&(cpu()!="MKV43F128VLL15")&&(cpu()!="MKV44F64VLH15")&&(cpu()!="MKV44F128VLH15")&&(cpu()!="MKV44F128VLL15")&&(cpu()!="MKV45F128VLH15")&&(cpu()!="MKV45F128VLL15")&&(cpu()!="MKV45F256VLH15")&&(cpu()!="MKV45F256VLL15")&&(cpu()!="MKV46F128VLH15")&&(cpu()!="MKV46F128VLL15")&&(cpu()!="MKV46F256VLH15")&&(cpu()!="MKV46F256VLL15")&&cpuis("MKV31F*")&&cpuis("MKV30F*")&&(cpu()=="MK64FN1M0VLQ12")&&(cpu()!="MK64FN1M0VMD12")&&(cpu()!="MK64FN1M0VLL12")&&(cpu()!="MK64FN1M0VDC12")&&(cpu()!="MK65FN2M0CAF18")&&(cpu()!="MK65FN2M0VMF18")&&(cpu()!="MK66FN2M0VLQ18")&&(cpu()!="MK66FN2M0VMD18")&&(!cpuis("K32W0?2S1M*")&&(!cpuis("MKW*")))
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
elif (cpuis("MKW21D*"))
|
|
if (((per.l(ad:0x40020000))&0x80)==0x80)
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected"
|
|
else
|
|
rgroup.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected"
|
|
endif
|
|
elif ((cpuis("MKW22D*"))||(cpuis("MKW24D*")))
|
|
hgroup.byte 0x16++0x01
|
|
hide.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
hide.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
endif
|
|
textline " "
|
|
sif ((cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV30F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x18++0x0F
|
|
line.byte 0x00 "XACCH3,Execute-only Access Register 3"
|
|
bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x01 "XACCH2,Execute-only Access Register 2"
|
|
bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x02 "XACCH1,Execute-only Access Register 1"
|
|
bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x03 "XACCH0,Execute-only Access Register 0"
|
|
bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x04 "XACCL3,Execute-only Access Register 3"
|
|
bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x05 "XACCL2,Execute-only Access Register 2"
|
|
bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x06 "XACCL1,Execute-only Access Register 1"
|
|
bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x07 "XACCL0,Execute-only Access Register 0"
|
|
bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x08 "SACCH3,Supervisor-only Access Register 3"
|
|
bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x09 "SACCH2,Supervisor-only Access Register 2"
|
|
bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0A "SACCH1,Supervisor-only Access Register 1"
|
|
bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0B "SACCH0,Supervisor-only Access Register 0"
|
|
bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0C "SACCL3,Supervisor-only Access Register 3"
|
|
bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0D "SACCL2,Supervisor-only Access Register 2"
|
|
bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0E "SACCL1,Supervisor-only Access Register 1"
|
|
bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0F "SACCL0,Supervisor-only Access Register 0"
|
|
bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No"
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x28++0x03
|
|
line.byte 0x00 "XACCSH,Secondary Execute-only Access Registers"
|
|
bitfld.byte 0x00 7. " XA_S[15] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 6. " [14] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 5. " [13] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [12] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 3. " [11] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 2. " [10] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [9] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 0. " [8] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x01 "XACCSL,Secondary Execute-only Access Registers"
|
|
bitfld.byte 0x01 7. " XA_S[7] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 6. " [6] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 5. " [5] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 3. " [3] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 2. " [2] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 0. " [0] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x02 "SACCSH,Secondary Supervisor-only Access Registers"
|
|
bitfld.byte 0x02 7. " SA_S[15] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 6. " [14] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 5. " [13] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [12] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 3. " [11] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 2. " [10] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [9] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 0. " [8] ,Secondary supervisor-only access control" "Yes,No"
|
|
line.byte 0x03 "SACCSL,Secondary Supervisor-only Access Registers"
|
|
bitfld.byte 0x03 7. " SA_S[7] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 6. " [6] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 5. " [5] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [4] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 3. " [3] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 2. " [2] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [1] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 0. " [0] ,Secondary supervisor-only access control" "Yes,No"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKW2?Z*")||cpuis("MKW3?Z*")||cpuis("MKW4?Z*"))
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "FACSS,Flash Access Segment Size Register"
|
|
rgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "FACSN,Flash Access Segment Number Register"
|
|
elif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")
|
|
rgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "FACSS,Flash Access Segment Size Register"
|
|
rgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "FACSN,Flash Access Segment Number Register"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "FACSSS,Secondary Flash Access Segment Size Register"
|
|
rgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "FACSNS,Secondary Flash Access Segment Number Register"
|
|
group.byte 0x52++0x01
|
|
line.byte 0x00 "FSTDBYCTL,Flash Standby Control Register"
|
|
bitfld.byte 0x00 0. " STDBYDIS ,Standy mode disable" "Enabled,Disabled"
|
|
group.byte 0x53++0x01
|
|
line.byte 0x00 "FSTDBY,Flash Standby Register"
|
|
bitfld.byte 0x00 2. " STDBY2 ,Standy mode for flash block 2" "Enabled,Disabled"
|
|
bitfld.byte 0x00 1. " STDBY1 ,Standy mode for flash block 1" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0. " STDBY0 ,Standy mode for flash block 0" "Enabled,Disabled"
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rgroup.byte 0x2E++0x01
|
|
line.byte 0x00 "FERSTAT,Flash Error Status Register"
|
|
bitfld.byte 0x00 1. " DFDIF ,Double bit fault detect interrupt flag" "Not detected,Detected"
|
|
line.byte 0x01 "FERCNFG,Flash Error Configuration Register"
|
|
bitfld.byte 0x01 5. " FDFD ,Force double bit fault detect" "Not forced,Forced"
|
|
bitfld.byte 0x01 1. " DFDIE ,Double bit fault detect interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
tree "FTFA (Flash Memory Module)"
|
|
base ad:0x40020000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed"
|
|
eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error"
|
|
eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error"
|
|
line.byte 0x01 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased"
|
|
bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended"
|
|
sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKW??Z*")
|
|
sif (cpuis("MKV5*"))
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready"
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not ready,Ready"
|
|
elif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||cpuis("MKV31F*")||cpuis("MKV30F*")||(cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16"))
|
|
textline " "
|
|
rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block,1 block"
|
|
rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "2 flash and 2 flex blocks,?..."
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
textline " "
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available"
|
|
elif cpuis("K32W0?2S1M*")
|
|
rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000"
|
|
rbitfld.byte 0x01 2. " CRCRDY ,CRC ready" "Not available,Available"
|
|
textline " "
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
else
|
|
textline " "
|
|
rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "Supported,?..."
|
|
rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available"
|
|
rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available"
|
|
endif
|
|
endif
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled"
|
|
bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted"
|
|
bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure"
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")||cpuis("MKW*")||cpuis("MKV5*")
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "FCCOB3,Flash Common Command Object Registers"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "FCCOB2,Flash Common Command Object Registers"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "FCCOB1,Flash Common Command Object Registers"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "FCCOB0,Flash Common Command Object Registers"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "FCCOB7,Flash Common Command Object Registers"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "FCCOB6,Flash Common Command Object Registers"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "FCCOB5,Flash Common Command Object Registers"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "FCCOB4,Flash Common Command Object Registers"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "FCCOBB,Flash Common Command Object Registers"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "FCCOBA,Flash Common Command Object Registers"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "FCCOB9,Flash Common Command Object Registers"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "FCCOB8,Flash Common Command Object Registers"
|
|
sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKW*")&&!cpuis("MKV5*")
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte (0x10+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x11+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x12+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
group.byte (0x13+0x01)++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5"))
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
elif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROT1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROT0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
elif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROTH3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTH2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTH1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTH0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
elif (cpuis("MKW*"))
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "FPROT3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROT2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROT1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROT0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
else
|
|
group.byte 0x18++0x03
|
|
line.byte 0x00 "FPROTH3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTH2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTH1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTH0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte 0x1C++0x03
|
|
line.byte 0x00 "FPROTL3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x01 "FPROTL2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x02 "FPROTL1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected"
|
|
line.byte 0x03 "FPROTL0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected"
|
|
endif
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
group.byte 0x24++0x01
|
|
line.byte 0x00 "FPROTSL,Secondary Program Flash Protection Registers"
|
|
line.byte 0x01 "FPROTSH,Secondary Program Flash Protection Registers"
|
|
endif
|
|
sif (cpu()!="MK63FN1M0VLQ12")&&(cpu()!="MK63FN1M0VMD12")&&(cpu()!="MKV40F64VLH15")&&(cpu()!="MKV40F128VLH15")&&(cpu()!="MKV40F128VLL15")&&(cpu()!="MKV40F256VLH15")&&(cpu()!="MKV40F256VLL15")&&(cpu()!="MKV43F64VLH15")&&(cpu()!="MKV43F128VLH15")&&(cpu()!="MKV43F128VLL15")&&(cpu()!="MKV44F64VLH15")&&(cpu()!="MKV44F128VLH15")&&(cpu()!="MKV44F128VLL15")&&(cpu()!="MKV45F128VLH15")&&(cpu()!="MKV45F128VLL15")&&(cpu()!="MKV45F256VLH15")&&(cpu()!="MKV45F256VLL15")&&(cpu()!="MKV46F128VLH15")&&(cpu()!="MKV46F128VLL15")&&(cpu()!="MKV46F256VLH15")&&(cpu()!="MKV46F256VLL15")&&cpuis("MKV31F*")&&cpuis("MKV30F*")&&(cpu()=="MK64FN1M0VLQ12")&&(cpu()!="MK64FN1M0VMD12")&&(cpu()!="MK64FN1M0VLL12")&&(cpu()!="MK64FN1M0VDC12")&&(cpu()!="MK65FN2M0CAF18")&&(cpu()!="MK65FN2M0VMF18")&&(cpu()!="MK66FN2M0VLQ18")&&(cpu()!="MK66FN2M0VMD18")&&(!cpuis("K32W0?2S1M*")&&(!cpuis("MKW*")))
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
elif (cpuis("MKW21D*"))
|
|
if (((per.l(ad:0x40020000))&0x80)==0x80)
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected"
|
|
else
|
|
rgroup.byte 0x16++0x01
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected"
|
|
line.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected"
|
|
bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected"
|
|
endif
|
|
elif ((cpuis("MKW22D*"))||(cpuis("MKW24D*")))
|
|
hgroup.byte 0x16++0x01
|
|
hide.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
hide.byte 0x01 "FDPROT,Data Flash Protection Register"
|
|
endif
|
|
textline " "
|
|
sif ((cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV30F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x18++0x0F
|
|
line.byte 0x00 "XACCH3,Execute-only Access Register 3"
|
|
bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x01 "XACCH2,Execute-only Access Register 2"
|
|
bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x02 "XACCH1,Execute-only Access Register 1"
|
|
bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x03 "XACCH0,Execute-only Access Register 0"
|
|
bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x04 "XACCL3,Execute-only Access Register 3"
|
|
bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x05 "XACCL2,Execute-only Access Register 2"
|
|
bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x06 "XACCL1,Execute-only Access Register 1"
|
|
bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x07 "XACCL0,Execute-only Access Register 0"
|
|
bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x08 "SACCH3,Supervisor-only Access Register 3"
|
|
bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x09 "SACCH2,Supervisor-only Access Register 2"
|
|
bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0A "SACCH1,Supervisor-only Access Register 1"
|
|
bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0B "SACCH0,Supervisor-only Access Register 0"
|
|
bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0C "SACCL3,Supervisor-only Access Register 3"
|
|
bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0D "SACCL2,Supervisor-only Access Register 2"
|
|
bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0E "SACCL1,Supervisor-only Access Register 1"
|
|
bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No"
|
|
line.byte 0x0F "SACCL0,Supervisor-only Access Register 0"
|
|
bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No"
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x28++0x03
|
|
line.byte 0x00 "XACCSH,Secondary Execute-only Access Registers"
|
|
bitfld.byte 0x00 7. " XA_S[15] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 6. " [14] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 5. " [13] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " [12] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 3. " [11] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 2. " [10] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " [9] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x00 0. " [8] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x01 "XACCSL,Secondary Execute-only Access Registers"
|
|
bitfld.byte 0x01 7. " XA_S[7] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 6. " [6] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 5. " [5] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " [4] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 3. " [3] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 2. " [2] ,Execute-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " [1] ,Execute-only access control" "Yes,No"
|
|
bitfld.byte 0x01 0. " [0] ,Execute-only access control" "Yes,No"
|
|
line.byte 0x02 "SACCSH,Secondary Supervisor-only Access Registers"
|
|
bitfld.byte 0x02 7. " SA_S[15] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 6. " [14] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 5. " [13] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " [12] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 3. " [11] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 2. " [10] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " [9] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x02 0. " [8] ,Secondary supervisor-only access control" "Yes,No"
|
|
line.byte 0x03 "SACCSL,Secondary Supervisor-only Access Registers"
|
|
bitfld.byte 0x03 7. " SA_S[7] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 6. " [6] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 5. " [5] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " [4] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 3. " [3] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 2. " [2] ,Secondary supervisor-only access control" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " [1] ,Secondary supervisor-only access control" "Yes,No"
|
|
bitfld.byte 0x03 0. " [0] ,Secondary supervisor-only access control" "Yes,No"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKW2?Z*")||cpuis("MKW3?Z*")||cpuis("MKW4?Z*"))
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "FACSS,Flash Access Segment Size Register"
|
|
rgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "FACSN,Flash Access Segment Number Register"
|
|
elif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")
|
|
rgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "FACSS,Flash Access Segment Size Register"
|
|
rgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "FACSN,Flash Access Segment Number Register"
|
|
endif
|
|
sif (cpuis("K32W0?2S1M*"))
|
|
rgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "FACSSS,Secondary Flash Access Segment Size Register"
|
|
rgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "FACSNS,Secondary Flash Access Segment Number Register"
|
|
group.byte 0x52++0x01
|
|
line.byte 0x00 "FSTDBYCTL,Flash Standby Control Register"
|
|
bitfld.byte 0x00 0. " STDBYDIS ,Standy mode disable" "Enabled,Disabled"
|
|
group.byte 0x53++0x01
|
|
line.byte 0x00 "FSTDBY,Flash Standby Register"
|
|
bitfld.byte 0x00 2. " STDBY2 ,Standy mode for flash block 2" "Enabled,Disabled"
|
|
bitfld.byte 0x00 1. " STDBY1 ,Standy mode for flash block 1" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0. " STDBY0 ,Standy mode for flash block 0" "Enabled,Disabled"
|
|
endif
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
rgroup.byte 0x2E++0x01
|
|
line.byte 0x00 "FERSTAT,Flash Error Status Register"
|
|
bitfld.byte 0x00 1. " DFDIF ,Double bit fault detect interrupt flag" "Not detected,Detected"
|
|
line.byte 0x01 "FERCNFG,Flash Error Configuration Register"
|
|
bitfld.byte 0x01 5. " FDFD ,Force double bit fault detect" "Not forced,Forced"
|
|
bitfld.byte 0x01 1. " DFDIE ,Double bit fault detect interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40032000
|
|
width 7.
|
|
sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKW2?D*")||cpuis("MKV5*")
|
|
if (((per.l(ad:0x40032000+0x08))&0x1000000)==0x00)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DATA,CRC Data Register"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte"
|
|
line.long 0x04 "GPOLY,CRC Polynomial Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal Half-word"
|
|
line.long 0x08 "CTRL,CRC Control Register"
|
|
bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes"
|
|
bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes"
|
|
textline " "
|
|
bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement"
|
|
bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DATA,CRC Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte"
|
|
line.long 0x04 "GPOLY,CRC Polynomial Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " HIGH ,High polynominal Half-word"
|
|
hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal Half-word"
|
|
line.long 0x08 "CTRL,CRC Control Register"
|
|
bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes"
|
|
bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes"
|
|
textline " "
|
|
bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement"
|
|
bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DATA,CRC Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte"
|
|
line.long 0x04 "GPOLY,CRC Polynomial Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " HIGH ,High polynominal Half-word"
|
|
hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal Half-word"
|
|
line.long 0x08 "CTRL,CRC Control Register"
|
|
bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes"
|
|
bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes"
|
|
textline " "
|
|
bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement"
|
|
bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "MMCAU (Memory-Mapped Cryptographic Acceleration Unit)"
|
|
base ad:0xE0081000
|
|
width 6.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CASR,Status Register"
|
|
rbitfld.long 0x00 28.--31. " VER ,CAU version" "Initial,Second,?..."
|
|
bitfld.long 0x00 1. " DPE ,DES parity error" "No error,Error"
|
|
bitfld.long 0x00 0. " IC ,Illegal command" "Not issued,Issued"
|
|
group.long 0x01++0x03
|
|
line.long 0x00 "CAA,Accumulator"
|
|
group.long 0x2++0x03
|
|
line.long 0x00 "CA0,General Purpose Registers"
|
|
group.long 0x3++0x03
|
|
line.long 0x00 "CA1,General Purpose Registers"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "CA2,General Purpose Registers"
|
|
group.long 0x5++0x03
|
|
line.long 0x00 "CA3,General Purpose Registers"
|
|
group.long 0x6++0x03
|
|
line.long 0x00 "CA4,General Purpose Registers"
|
|
group.long 0x7++0x03
|
|
line.long 0x00 "CA5,General Purpose Registers"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CA6,General Purpose Registers"
|
|
group.long 0x9++0x03
|
|
line.long 0x00 "CA7,General Purpose Registers"
|
|
group.long 0xA++0x03
|
|
line.long 0x00 "CA8,General Purpose Registers"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RNGA (Random Number Generator Accelerator)"
|
|
base ad:0x40029000
|
|
width 4.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,RNGA Control Register"
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 4. " SLP ,Sleep mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CLRI ,Clear interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTM ,Interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " HA ,High assurance (Enable notification of security violations)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GO ,Random-data generation and loading enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " SLP ,Sleep mode enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CLRI ,Clear interrupt" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTM ,Interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " HA ,High assurance (Enabled security violation)" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GO ,Load with random data indication" "Not loaded,Loaded"
|
|
endif
|
|
sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SR,RNGA Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SR,RNGA Status Register"
|
|
sif (cpuis("MKW2?D*"))
|
|
hexmask.long.byte 0x00 16.--23. 1. " OREG_SIZE ,Output register size"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OREG_LVL ,Output register level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SLP ,Sleep mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ORU ,Output register underflow" "No underflow,Underflow"
|
|
bitfld.long 0x00 1. " LRS ,Status of the most recent read of the RNGA output register" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECV ,Security violation" "Not occurred,Occurred"
|
|
else
|
|
hexmask.long.byte 0x00 16.--23. 1. " OREG_SIZE ,Output register size"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OREG_LVL ,Output register level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SLP ,Sleep mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ORU ,Output register underflow" "No underflow,Underflow"
|
|
bitfld.long 0x00 1. " LRS ,Status of the most recent read of the RNGA output register" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECV ,Security violation" "Not occurred,Occurred"
|
|
endif
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "ER,RNGA Entropy Register"
|
|
sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKW*")
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "OR,RNGA Output Register"
|
|
in
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "OR,RNGA Output Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x4003B000
|
|
width 15.
|
|
if (((per.l(ad:0x4003B000+0x0))&0x20)==0x0)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ADC0_SC1A,ADC status and control registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV5?F1M0VLL24"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled"
|
|
elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled"
|
|
endif
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ADC0_SC1A,ADC status and control registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV5?F1M0VLL24"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled"
|
|
elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4003B000+0x4))&0x20)==0x0)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "ADC0_SC1B,ADC status and control registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV5?F1M0VLL24"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled"
|
|
elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled"
|
|
endif
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "ADC0_SC1B,ADC status and control registers 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKV5?F1M0VLL24"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled"
|
|
elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24"))
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled"
|
|
else
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4003B000))&0x20)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG1,ADC configuration register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "SE 8-bit,SE 12-bit,SE 10-bit,SE 16-bit"
|
|
sif (cpuis("MKV5*"))
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG1,ADC configuration register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Diff 9-bit,Diff 13-bit,Diff 11-bit,Diff 16-bit"
|
|
sif (cpuis("MKV5*"))
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC0_CFG2,ADC Configuration register 2"
|
|
bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB"
|
|
bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADLSTS ,Long Sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "ADC0_RA,ADC data result register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
line.long 0x04 "ADC0_RB,ADC data result register"
|
|
hexmask.long.word 0x04 0.--15. 1. " D ,Data result"
|
|
group.long 0x18++0x37
|
|
line.long 0x00 "ADC0_CV1,Compare value registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x04 "ADC0_CV2,Compare value registers"
|
|
hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value"
|
|
line.long 0x08 "ADC0_SC2,Status and control register 2"
|
|
rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress"
|
|
bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware"
|
|
bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..."
|
|
line.long 0x0C "ADC0_SC3,Status and control register 3"
|
|
bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started"
|
|
sif (cpuis("MKW*")||cpuis("MKV5*"))
|
|
textline " "
|
|
eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred"
|
|
else
|
|
textline " "
|
|
rbitfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples"
|
|
line.long 0x10 "ADC0_OFS,ADC offset correction register"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value"
|
|
line.long 0x14 "ADC0_PG,ADC plus-side gain register"
|
|
hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain"
|
|
line.long 0x18 "ADC0_MG,ADC minus-side gain register"
|
|
hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side Gain"
|
|
line.long 0x1C "ADC0_CLPD,ADC plus-side general calibration value register"
|
|
bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x20 "ADC0_CLPS,ADC plus-side general calibration value register"
|
|
bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x24 "ADC0_CLP4,ADC plus-side general calibration value register"
|
|
hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value"
|
|
line.long 0x28 "ADC0_CLP3,ADC plus-side general calibration value register"
|
|
hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value"
|
|
line.long 0x2C "ADC0_CLP2,ADC plus-side general calibration value register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value"
|
|
line.long 0x30 "ADC0_CLP1,ADC plus-side general calibration value register"
|
|
hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value"
|
|
line.long 0x34 "ADC0_CLP0,ADC plus-side general calibration value register"
|
|
bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x54++0x1B
|
|
line.long 0x00 "ADC0_CLMD,ADC minus-side general calibration value register"
|
|
bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "ADC0_CLMS,ADC minus-side general calibration value register"
|
|
bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "ADC0_CLM4,ADC minus-side general calibration value register"
|
|
hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value"
|
|
line.long 0x0C "ADC0_CLM3,CLM4,ADC minus-side general calibration value register"
|
|
hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value"
|
|
line.long 0x10 "ADC0_CLM2,ADC minus-side general calibration value register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value"
|
|
line.long 0x14 "ADC0_CLM1,ADC minus-side general calibration value register"
|
|
hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value"
|
|
line.long 0x18 "ADC0_CLM0,ADC minus-side general calibration value register"
|
|
bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CMP (Comparator)"
|
|
tree "CMP0"
|
|
base ad:0x40073000
|
|
width 15.
|
|
group.byte ad:0x00++0x05
|
|
line.byte 0x00 "CMP0_CR0,CMP Control Register 0"
|
|
bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples"
|
|
bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3"
|
|
line.byte 0x01 "CMP0_CR1,CMP Control Register 1"
|
|
bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected"
|
|
bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected"
|
|
sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKV5*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpu()=="MKW01Z128*")
|
|
textline " "
|
|
bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed"
|
|
bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
endif
|
|
line.byte 0x02 "CMP0_FPR,CMP Filter Period Register"
|
|
line.byte 0x03 "CMP0_SCR,CMP Status And Control Register"
|
|
bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred"
|
|
eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred"
|
|
rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1"
|
|
line.byte 0x04 "CMP0_DACCR,DAC Control Register"
|
|
bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2"
|
|
bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
line.byte 0x05 "CMP0_MUXCR,MUX Control Register"
|
|
sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||(cpuis("MKV5*")))
|
|
sif cpuis("MKV10Z*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0"
|
|
elif cpuis("MKV5?F???VLL24")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive Input MUX Control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus Input MUX Control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..."
|
|
textline " "
|
|
elif (cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC"
|
|
textline " "
|
|
elif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,12-bit DAC1 output/in4,VREF output/in5,Bandgap,6-bit DAC0"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,12-bit DAC1 output/in4,VREF output/in5,Bandgap,6-bit DAC0"
|
|
textline " "
|
|
elif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0"
|
|
textline " "
|
|
elif cpuis("MKV30F*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC"
|
|
textline " "
|
|
endif
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*")||cpuis("MKW2?D*"))
|
|
bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
else
|
|
bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "CMP1"
|
|
base ad:0x40073000
|
|
width 15.
|
|
group.byte 0x08++0x05
|
|
line.byte 0x00 "CMP1_CR0,CMP Control Register 0"
|
|
bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples"
|
|
bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3"
|
|
line.byte 0x01 "CMP1_CR1,CMP Control Register 1"
|
|
bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected"
|
|
bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected"
|
|
sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKV5*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpu()=="MKW01Z128*")
|
|
textline " "
|
|
bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed"
|
|
bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
endif
|
|
line.byte 0x02 "CMP1_FPR,CMP Filter Period Register"
|
|
line.byte 0x03 "CMP1_SCR,CMP Status And Control Register"
|
|
bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred"
|
|
eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred"
|
|
rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1"
|
|
line.byte 0x04 "CMP1_DACCR,DAC Control Register"
|
|
bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2"
|
|
bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
line.byte 0x05 "CMP1_MUXCR,MUX Control Register"
|
|
sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||(cpuis("MKV5*")))
|
|
sif cpuis("MKV10Z*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0"
|
|
elif cpuis("MKV5?F???VLL24")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive Input MUX Control" "IN0,IN1,,IN3,,IN5,?..."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus Input MUX Control" "IN0,IN1,,IN3,,IN5,?..."
|
|
elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..."
|
|
textline " "
|
|
elif (cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,IN5,Bandgap,6-bit DAC"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,IN5,Bandgap,6-bit DAC"
|
|
textline " "
|
|
elif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0"
|
|
textline " "
|
|
elif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0"
|
|
textline " "
|
|
elif cpuis("MKV30F*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC"
|
|
textline " "
|
|
endif
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*")||cpuis("MKW2?D*"))
|
|
bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7"
|
|
else
|
|
bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7"
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
base ad:0x4003F000
|
|
sif (cpuis("MKW2?D*"))
|
|
width 16.
|
|
group.byte 0x0++0x01
|
|
line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT0H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x2++0x01
|
|
line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT1H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x4++0x01
|
|
line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT2H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x6++0x01
|
|
line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT3H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x8++0x01
|
|
line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT4H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0xA++0x01
|
|
line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT5H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0xC++0x01
|
|
line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT6H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0xE++0x01
|
|
line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT7H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT8H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x12++0x01
|
|
line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT9H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x14++0x01
|
|
line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT10H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT11H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT12H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x1A++0x01
|
|
line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT13H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT14H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x1E++0x01
|
|
line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT15H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x20++0x01
|
|
line.byte 0x00 "DAC0_SR,DAC Status Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW01Z128*")||cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
else
|
|
bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
endif
|
|
line.byte 0x01 "DAC0_C0,DAC Control Register"
|
|
bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2"
|
|
textline " "
|
|
bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software"
|
|
bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-power,Low-power"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW01Z128*")||cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
textline " "
|
|
bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV5*"))
|
|
if (((per.b(ad:0x4003F000+0x22))&0x06)==0x06)
|
|
group.byte 0x22++0x02
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO"
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4.--7. " READ_POINTER ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " WRITE_POINTER ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.byte 0x22++0x02
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO"
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif (cpuis("MKV10Z*"))
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1"
|
|
bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1"
|
|
elif (cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO"
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (cpuis("MKW01Z128*")||cpuis("MKW40Z")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1"
|
|
bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1"
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan"
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1"
|
|
bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1"
|
|
else
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..."
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 16.
|
|
group.byte 0x0++0x01
|
|
line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT0H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x2++0x01
|
|
line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT1H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
group.byte 0x20++0x01
|
|
line.byte 0x00 "DAC0_SR,DAC Status Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW01Z128*")||cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
else
|
|
bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
endif
|
|
line.byte 0x01 "DAC0_C0,DAC Control Register"
|
|
bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2"
|
|
textline " "
|
|
bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software"
|
|
bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-power,Low-power"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW01Z128*")||cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
textline " "
|
|
bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV5*"))
|
|
if (((per.b(ad:0x4003F000+0x22))&0x06)==0x06)
|
|
group.byte 0x22++0x02
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO"
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4.--7. " READ_POINTER ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " WRITE_POINTER ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.byte 0x22++0x02
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO"
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif (cpuis("MKV10Z*"))
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1"
|
|
bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1"
|
|
elif (cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO"
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (cpuis("MKW01Z128*")||cpuis("MKW40Z")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1"
|
|
bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1"
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan"
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1"
|
|
bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1"
|
|
else
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..."
|
|
bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C2,DAC Control Register 2"
|
|
bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
tree "VREF (Voltage Reference)"
|
|
base ad:0x40074000
|
|
width 10.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TRM,VREF Trim Register"
|
|
bitfld.byte 0x00 6. " CHOPEN ,Chop oscillator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max"
|
|
if (((per.b(ad:0x40074000))&0x40)==0x40)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SC,VREF Status and Control Register"
|
|
bitfld.byte 0x00 7. " VREFEN ,Internal Voltage Reference enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " REGEN ,Internal 1.75V regulator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " MODE_LV ,Buffer Mode selection" "Bandgap,High-power,Low-power,"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SC,VREF Status and Control Register"
|
|
bitfld.byte 0x00 7. " VREFEN ,Internal Voltage Reference enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " REGEN ,Internal 1.75V regulator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " VREFST ,Internal Voltage Reference stable" "Disabled|Not stable,Stable"
|
|
bitfld.byte 0x00 0.--1. " MODE_LV ,Buffer Mode selection" "Bandgap,High-power,Low-power,"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (!cpuis("MKW2?D*"))
|
|
tree.open "TPM (Timer/PWM Module)"
|
|
tree "TPM0"
|
|
base ad:0x40038000
|
|
sif (cpuis("MKW01Z128*"))
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM0_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "1,2,4,8,16,32,64,128"
|
|
line.long 0x04 "TPM0_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM0_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM0_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM0_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x10)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x30)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "TPM0_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x24)&0x30)==0x10)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x24)&0x30)==0x30)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "TPM0_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x0)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x10)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x20)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x30)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x0)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x20)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "TPM0_C4V,Channel 4 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x34)&0x30)==0x0)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x34)&0x30)==0x10)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x34)&0x30)==0x20)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x34)&0x30)==0x30)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x30)==0x0)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x30)==0x20)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "TPM0_C5V,Channel 5 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM0_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
textline " "
|
|
eventfld.long 0x00 7. " CH7F ,Channel 7 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CH6F ,Channel 6 flag" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM0_COMBINE,Combine Channel Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM0_POL,Channel Polarity"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM0_FILTER,Filter Control"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM0_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase encoding,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF position" "Bottom,Top"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKW*"))
|
|
if ((per.l(ad:0x40038000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40038000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM0_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "1,2,4,8,16,32,64,128"
|
|
line.long 0x04 "TPM0_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM0_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM0_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM0_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x10)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x30)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "TPM0_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x24)&0x30)==0x10)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x0)&&((per.l(ad:0x40038000+0x24)&0x30)==0x30)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "TPM0_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM0_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
textline " "
|
|
eventfld.long 0x00 7. " CH7F ,Channel 7 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CH6F ,Channel 6 flag" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM0_COMBINE,Combine Channel Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM0_POL,Channel Polarity"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM0_FILTER,Filter Control"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM0_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase encoding,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF position" "Bottom,Top"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKW*"))
|
|
if ((per.l(ad:0x40038000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40038000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "TPM1"
|
|
base ad:0x40039000
|
|
sif (cpuis("MKW01Z128*"))
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM1_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "1,2,4,8,16,32,64,128"
|
|
line.long 0x04 "TPM1_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM1_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM1_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM1_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x10)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x30)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "TPM1_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x24)&0x30)==0x10)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x24)&0x30)==0x30)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "TPM1_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x2C)&0x30)==0x0)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x2C)&0x30)==0x10)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x2C)&0x30)==0x20)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x2C)&0x30)==0x30)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x2C)&0x30)==0x0)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x2C)&0x30)==0x20)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "TPM1_C4V,Channel 4 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x34)&0x30)==0x0)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x34)&0x30)==0x10)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x34)&0x30)==0x20)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x34)&0x30)==0x30)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x34)&0x30)==0x0)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x34)&0x30)==0x20)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "TPM1_C5V,Channel 5 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM1_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
textline " "
|
|
eventfld.long 0x00 7. " CH7F ,Channel 7 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CH6F ,Channel 6 flag" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM1_COMBINE,Combine Channel Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM1_POL,Channel Polarity"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM1_FILTER,Filter Control"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM1_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase encoding,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF position" "Bottom,Top"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKW*"))
|
|
if ((per.l(ad:0x40039000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40039000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM1_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "1,2,4,8,16,32,64,128"
|
|
line.long 0x04 "TPM1_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM1_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM1_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM1_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x10)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x30)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "TPM1_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x24)&0x30)==0x10)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x0)&&((per.l(ad:0x40039000+0x24)&0x30)==0x30)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "TPM1_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM1_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
textline " "
|
|
eventfld.long 0x00 7. " CH7F ,Channel 7 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CH6F ,Channel 6 flag" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM1_COMBINE,Combine Channel Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM1_POL,Channel Polarity"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM1_FILTER,Filter Control"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM1_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase encoding,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF position" "Bottom,Top"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKW*"))
|
|
if ((per.l(ad:0x40039000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40039000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "TPM2"
|
|
base ad:0x4003A000
|
|
sif (cpuis("MKW01Z128*"))
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM2_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "1,2,4,8,16,32,64,128"
|
|
line.long 0x04 "TPM2_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM2_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM2_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM2_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x10)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x30)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "TPM2_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x10)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x30)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "TPM2_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x2C)&0x30)==0x0)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x2C)&0x30)==0x10)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x2C)&0x30)==0x20)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x2C)&0x30)==0x30)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x2C)&0x30)==0x0)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x2C)&0x30)==0x20)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS4 ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS4 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "TPM2_C4V,Channel 4 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x34)&0x30)==0x0)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x34)&0x30)==0x10)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x34)&0x30)==0x20)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x34)&0x30)==0x30)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x34)&0x30)==0x0)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x34)&0x30)==0x20)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS5 ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS5 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "TPM2_C5V,Channel 5 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM2_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
textline " "
|
|
eventfld.long 0x00 7. " CH7F ,Channel 7 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CH6F ,Channel 6 flag" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM2_COMBINE,Combine Channel Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM2_POL,Channel Polarity"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM2_FILTER,Filter Control"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM2_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase encoding,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF position" "Bottom,Top"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKW*"))
|
|
if ((per.l(ad:0x4003A000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4003A000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM2_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "1,2,4,8,16,32,64,128"
|
|
line.long 0x04 "TPM2_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM2_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x0)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS0 ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS0 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM2_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x0)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS1 ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS1 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM2_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x10)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x30)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x0)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS2 ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS2 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "TPM2_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/Input capture,Software compare/Output compare,Edge-aligned PWM,Output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x10)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x0)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x30)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/Edge-aligned PWM,Software compare/output compare"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,High,Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x0)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,Low,High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MS3 ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/,Software compare/,Software compare/Center-aligned PWM,Software compare/"
|
|
bitfld.long 0x00 2.--3. " ELS3 ,Edge or level select" "Not used,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "TPM2_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM2_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
textline " "
|
|
eventfld.long 0x00 7. " CH7F ,Channel 7 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CH6F ,Channel 6 flag" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM2_COMBINE,Combine Channel Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even channel,Odd channel"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM2_POL,Channel Polarity"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM2_FILTER,Filter Control"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0 CLK cycles,4 CLK cycles,8 CLK cycles,12 CLK cycles,16 CLK cycles,20 CLK cycles,24 CLK cycles,28 CLK cycles,32 CLK cycles,36 CLK cycles,40 CLK cycles,44 CLK cycles,48 CLK cycles,52 CLK cycles,56 CLK cycles,60 CLK cycles"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM2_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase encoding,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF position" "Bottom,Top"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKW*"))
|
|
if ((per.l(ad:0x4003A000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,,,PIT0 out,PIT1 out,,,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR trigger,"
|
|
else
|
|
rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4003A000)&0x18)==0x0)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "External trigger,CMP0,CMP1,CMP2,PIT0 out,PIT1 out,PIT2 out,PIT3 out,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR trigger,Software trigger"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "PDB (Programmable Delay Block)"
|
|
base ad:0x40036000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SC,Status And Control Register"
|
|
bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,PDB reached MOD,Trigger detected,Trigger detected/PDB mod"
|
|
bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 16. " SWTRIG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler factor" "/1*MULT,/2*MULT,/4*MULT,/8*MULT,/16*MULT,/32*MULT,/64*MULT,/128*MULT"
|
|
sif (cpuis("MKV10Z*"))
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger"
|
|
elif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12")
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger"
|
|
elif cpuis("MKV30F*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger"
|
|
elif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5"))
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger"
|
|
elif (cpuis("MKV5*"))
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,XBARA_OUT38,,LPTMR output,Software trigger"
|
|
else
|
|
bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40"
|
|
bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous"
|
|
bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated"
|
|
line.long 0x04 "MOD,Modulus Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IDLY,Interrupt Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*"))
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "CH0C1,Channel 0 Control Register 1"
|
|
bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH0S,Channel 0 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error"
|
|
line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay"
|
|
line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "CH0C1,Channel 0 Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable"
|
|
line.long 0x04 "CH0S,Channel 0 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags"
|
|
line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay"
|
|
line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*"))
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "CH1C1,Channel 1 Control Register 1"
|
|
bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH1S,Channel 1 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error"
|
|
bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error"
|
|
line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay"
|
|
line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay"
|
|
else
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "CH1C1,Channel 1 Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable"
|
|
line.long 0x04 "CH1S,Channel 1 Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags"
|
|
line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay"
|
|
line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay"
|
|
endif
|
|
sif (cpuis("MKV10Z*")||cpuis("MKV5*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV30F*")||cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5"))
|
|
group.long 0x150++0x07
|
|
line.long 0x00 "DACINTC0,DAC Interval Trigger Control Register"
|
|
bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "DACINT0,DAC Interval Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval"
|
|
else
|
|
group.long 0x150++0x07
|
|
line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register"
|
|
bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "DACINT0,DAC Interval 0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval"
|
|
group.long 0x158++0x07
|
|
line.long 0x00 "DACINTC1,DAC Interval Trigger 1 Control Register"
|
|
bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled"
|
|
line.long 0x04 "DACINT1,DAC Interval 1 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval"
|
|
endif
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "POEN,Pulse-Out 0 Enable Register"
|
|
sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")
|
|
else
|
|
bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "FTM (FlexTimer Module)"
|
|
tree "Module 0"
|
|
base ad:0x40038000
|
|
width 18.
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM0_SC,FTM0 Status And Control Register"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM0_SC,FTM0 Status And Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting"
|
|
textline " "
|
|
rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk"
|
|
rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM0_SC,FTM0 Status And Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM0_CNT,FTM0 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM0_MOD,FTM0 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register"
|
|
in
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "C0V,FTM0 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value"
|
|
else
|
|
group.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x8++0x03
|
|
hide.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register"
|
|
in
|
|
group.long (0x8+0x04)++0x03
|
|
line.long 0x00 "C1V,FTM0 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long (0x8+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value"
|
|
else
|
|
group.long (0x8+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register"
|
|
in
|
|
group.long (0x10+0x04)++0x03
|
|
line.long 0x00 "C2V,FTM0 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long (0x10+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value"
|
|
else
|
|
group.long (0x10+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register"
|
|
in
|
|
group.long (0x18+0x04)++0x03
|
|
line.long 0x00 "C3V,FTM0 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long (0x18+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value"
|
|
else
|
|
group.long (0x18+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register"
|
|
in
|
|
group.long (0x20+0x04)++0x03
|
|
line.long 0x00 "C4V,FTM0 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long (0x20+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value"
|
|
else
|
|
group.long (0x20+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register"
|
|
in
|
|
group.long (0x28+0x04)++0x03
|
|
line.long 0x00 "C5V,FTM0 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long (0x28+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value"
|
|
else
|
|
group.long (0x28+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "C6SC,FTM0 Channel 6 Status And Control Register"
|
|
in
|
|
group.long (0x30+0x04)++0x03
|
|
line.long 0x00 "C6V,FTM0 Channel 6 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long (0x30+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C6V,FTM0 Channel 6 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value"
|
|
else
|
|
group.long (0x30+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C6V,FTM0 Channel 6 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "C7SC,FTM0 Channel 7 Status And Control Register"
|
|
in
|
|
group.long (0x38+0x04)++0x03
|
|
line.long 0x00 "C7V,FTM0 Channel 7 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x00)
|
|
group.long (0x38+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C7V,FTM0 Channel 7 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value"
|
|
else
|
|
group.long (0x38+0x0C)++0x07
|
|
line.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_C7V,FTM0 Channel 7 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value"
|
|
endif
|
|
endif
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM0_CNTIN,FTM0 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter"
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register"
|
|
bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x0)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM0_SYNC,FTM0 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM0_OUTINIT,FTM0 Initial State For Channels Output Register"
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM0_OUTMASK,FTM0 Output Mask Register"
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x0)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register"
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register"
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2"
|
|
textline " "
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register"
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register"
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "FTM0_FMS,FTM0 Fault Mode Status Register"
|
|
rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1"
|
|
rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected"
|
|
rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected"
|
|
line.long 0x04 "FTM0_FILTER,FTM0 Input Capture Filter Control Register"
|
|
bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x0)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x0)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM0_CONF,FTM0 Configuration Register"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (Ftm counter/ftm channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/frozen,Functional/functional"
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.l(ad:0x40038000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "FTM0_SYNCONF,FTM0 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared"
|
|
line.long 0x04 "FTM0_INVCTRL,FTM0 Inverting Control Register"
|
|
bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM0_SWOCTRL,FTM0 Software Output Control Register"
|
|
bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x0C "FTM0_PWMLOAD,FTM0 PWM Load Register"
|
|
bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Module 1"
|
|
base ad:0x40039000
|
|
width 18.
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM1_SC,FTM1 Status And Control Register"
|
|
else
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM1_SC,FTM1 Status And Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting"
|
|
textline " "
|
|
rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk"
|
|
rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM1_SC,FTM1 Status And Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM1_CNT,FTM1 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM1_MOD,FTM1 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register"
|
|
in
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "C0V,FTM1 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
else
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x00)
|
|
group.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value"
|
|
else
|
|
group.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x8++0x03
|
|
hide.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register"
|
|
in
|
|
group.long (0x8+0x04)++0x03
|
|
line.long 0x00 "C1V,FTM1 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
else
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x00)
|
|
group.long (0x8+0x0C)++0x07
|
|
line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value"
|
|
else
|
|
group.long (0x8+0x0C)++0x07
|
|
line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value"
|
|
endif
|
|
endif
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM1_CNTIN,FTM1 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter"
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register"
|
|
bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x0)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM1_SYNC,FTM1 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM1_OUTINIT,FTM1 Initial State For Channels Output Register"
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM1_OUTMASK,FTM1 Output Mask Register"
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x0)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register"
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register"
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2"
|
|
textline " "
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register"
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register"
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "FTM1_FMS,FTM1 Fault Mode Status Register"
|
|
rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1"
|
|
rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected"
|
|
rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected"
|
|
line.long 0x04 "FTM1_FILTER,FTM1 Input Capture Filter Control Register"
|
|
bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x0)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x0)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM1_CONF,FTM1 Configuration Register"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (Ftm counter/ftm channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/frozen,Functional/functional"
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.l(ad:0x40039000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "FTM1_SYNCONF,FTM1 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared"
|
|
line.long 0x04 "FTM1_INVCTRL,FTM1 Inverting Control Register"
|
|
bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM1_SWOCTRL,FTM1 Software Output Control Register"
|
|
bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x0C "FTM1_PWMLOAD,FTM1 PWM Load Register"
|
|
bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Module 2"
|
|
base ad:0x4003A000
|
|
width 18.
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "FTM2_SC,FTM2 Status And Control Register"
|
|
else
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM2_SC,FTM2 Status And Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting"
|
|
textline " "
|
|
rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk"
|
|
rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM2_SC,FTM2 Status And Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM2_CNT,FTM2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM2_MOD,FTM2 Modulo Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "C0SC,FTM2 Channel 0 Status And Control Register"
|
|
in
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "C0V,FTM2 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value"
|
|
else
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x00)
|
|
group.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value"
|
|
else
|
|
group.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x8++0x03
|
|
hide.long 0x00 "C1SC,FTM2 Channel 1 Status And Control Register"
|
|
in
|
|
group.long (0x8+0x04)++0x03
|
|
line.long 0x00 "C1V,FTM2 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value"
|
|
else
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x00)
|
|
group.long (0x8+0x0C)++0x07
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value"
|
|
else
|
|
group.long (0x8+0x0C)++0x07
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value"
|
|
endif
|
|
endif
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter"
|
|
sif (cpuis("MKV5*"))
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register"
|
|
bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x0)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State For Channels Output Register"
|
|
bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1"
|
|
bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1"
|
|
bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1"
|
|
bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1"
|
|
bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1"
|
|
bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1"
|
|
bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1"
|
|
line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register"
|
|
bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x0)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register"
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register"
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined"
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2"
|
|
textline " "
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register"
|
|
rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1"
|
|
rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected"
|
|
rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected"
|
|
line.long 0x04 "FTM2_FILTER,FTM2 Input Capture Filter Control Register"
|
|
bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x0)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x0)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register"
|
|
bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min"
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM2_CONF,FTM2 Configuration Register"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (Ftm counter/ftm channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/frozen,Functional/functional"
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.l(ad:0x4003A000+0x54))&0x40)==0x0)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced"
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync"
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared"
|
|
line.long 0x04 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1"
|
|
bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1"
|
|
bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1"
|
|
bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1"
|
|
bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1"
|
|
bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1"
|
|
bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled"
|
|
line.long 0x0C "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included"
|
|
bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included"
|
|
bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included"
|
|
bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included"
|
|
bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included"
|
|
bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "PIT (Periodic Interrupt Timer)"
|
|
base ad:0x40037000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,PIT Module Control Register"
|
|
bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped"
|
|
sif ((cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*")||cpuis("MKV5*"))
|
|
rgroup.long 0xE0++0x07
|
|
line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register"
|
|
line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*"))
|
|
group.long 0x100++0x03 "PIT0 Registers"
|
|
line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register"
|
|
rgroup.long (0x100+0x04)++0x03
|
|
line.long 0x00 "CVAL0,PIT0 Current Timer Value Register"
|
|
group.long (0x100+0x08)++0x07
|
|
line.long 0x00 "TCTRL0,PIT0 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG0,PIT0 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x110++0x03 "PIT1 Registers"
|
|
line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register"
|
|
rgroup.long (0x110+0x04)++0x03
|
|
line.long 0x00 "CVAL1,PIT1 Current Timer Value Register"
|
|
group.long (0x110+0x08)++0x07
|
|
line.long 0x00 "TCTRL1,PIT1 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG1,PIT1 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x100++0x03 "PIT0 Registers"
|
|
line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register"
|
|
rgroup.long (0x100+0x04)++0x03
|
|
line.long 0x00 "CVAL0,PIT0 Current Timer Value Register"
|
|
group.long (0x100+0x08)++0x07
|
|
line.long 0x00 "TCTRL0,PIT0 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG0,PIT0 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x110++0x03 "PIT1 Registers"
|
|
line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register"
|
|
rgroup.long (0x110+0x04)++0x03
|
|
line.long 0x00 "CVAL1,PIT1 Current Timer Value Register"
|
|
group.long (0x110+0x08)++0x07
|
|
line.long 0x00 "TCTRL1,PIT1 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG1,PIT1 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x120++0x03 "PIT2 Registers"
|
|
line.long 0x00 "LDVAL2,PIT2 Timer Load Value Register"
|
|
rgroup.long (0x120+0x04)++0x03
|
|
line.long 0x00 "CVAL2,PIT2 Current Timer Value Register"
|
|
group.long (0x120+0x08)++0x07
|
|
line.long 0x00 "TCTRL2,PIT2 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG2,PIT2 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
group.long 0x130++0x03 "PIT3 Registers"
|
|
line.long 0x00 "LDVAL3,PIT3 Timer Load Value Register"
|
|
rgroup.long (0x130+0x04)++0x03
|
|
line.long 0x00 "CVAL3,PIT3 Current Timer Value Register"
|
|
group.long (0x130+0x08)++0x07
|
|
line.long 0x00 "TCTRL3,PIT3 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG3,PIT3 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPTMR (Low-Power Timer)"
|
|
base ad:0x40040000
|
|
width 5.
|
|
if (((per.l(ad:0x40040000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 8. " TDRE ,Timer DMA request enable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running"
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 8. " TDRE ,Timer DMA request enable" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running"
|
|
rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40040000))&0x01)==0x00)
|
|
if (((per.l(ad:0x40040000))&0x2)==0x0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40040000))&0x2)==0x0)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40040000))&0x01)==0x00)||(((per.l(ad:0x40040000))&0x81)==0x81)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
sif !cpuis("K32W0?2S1M*")
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
endif
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
sif !cpuis("K32W0?2S1M*")
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
endif
|
|
endif
|
|
sif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z128ACLL5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKW*")||cpuis("MKV5*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
elif cpuis("K32W0?2S1M*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("MKW01Z128*"))
|
|
tree "CMT (Carrier Modulator Transmitter)"
|
|
base ad:0x40062000
|
|
width 6.
|
|
group.byte 0x00++0x04
|
|
line.byte 0x00 "CGH1,CMT Carrier Generator High Data Register 1"
|
|
line.byte 0x01 "CGL1,CMT Carrier Generator Low Data Register 1"
|
|
line.byte 0x02 "CGH2,CMT Carrier Generator High Data Register 2"
|
|
line.byte 0x03 "CGL2,CMT Carrier Generator Low Data Register 2"
|
|
line.byte 0x04 "OC,CMT Output Control Register"
|
|
bitfld.byte 0x04 7. " IROL ,IRO latch control" "Low,High"
|
|
bitfld.byte 0x04 6. " CMTPOL ,CMT output polarity" "Active low,Active high"
|
|
bitfld.byte 0x04 5. " IROPEN ,IRO pin enable" "Disabled,Enabled"
|
|
sif ((cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK64FX512VDC12")||(cpu()=="MK64FX512VLL12")||(cpu()=="MK64FX512VLQ12")||(cpu()=="MK64FX512VMD12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*"))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "MSC,CMT Modulator Status And Control Register"
|
|
rbitfld.byte 0x00 7. " EOCF ,End of cycle status flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5.--6. " CMTDIV ,CMT clock divide prescaler" "IF/1,IF/2,IF/4,IF/8"
|
|
bitfld.byte 0x00 4. " EXSPC ,Extended space enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BASE ,Baseband enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FSK ,FSK mode select" "Time or baseband mode,FSK mode"
|
|
bitfld.byte 0x00 1. " EOCIE ,End of cycle interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " MCGEN ,Modulator and carrier generator enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.byte 0x05++0x00
|
|
hide.byte 0x00 "MSC,CMT Modulator Status And Control Register"
|
|
in
|
|
endif
|
|
group.byte 0x06++0x05
|
|
line.byte 0x00 "CMD1,CMT Modulator Data Register Mark High"
|
|
line.byte 0x01 "CMD2,CMT Modulator Data Register Mark Low"
|
|
line.byte 0x02 "CMD3,CMT Modulator Data Register Space High"
|
|
line.byte 0x03 "CMD4,CMT Modulator Data Register Space Low"
|
|
line.byte 0x04 "PPS,CMT Primary Prescaler Register"
|
|
bitfld.byte 0x04 0.--3. " PPSDIV ,Primary prescaler divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
line.byte 0x05 "DMA,CMT Direct Memory Access Register"
|
|
bitfld.byte 0x05 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
width 11.
|
|
tree.end
|
|
endif
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x4003D000
|
|
width 6.
|
|
if ((per.l(ad:0x4003D000+0x14)&0x10)==0x0)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
line.long 0x04 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
line.long 0x04 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler"
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
line.long 0x04 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CIC ,Compensation interval counter"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TCV ,Time compensation value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CIR ,Compensation interval register"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " TCR ,Time compensation register"
|
|
line.long 0x08 "CR,RTC Control Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x08 24.--25. " CPE ,Clock pin enable" "Disabled,Enabled pin 1,Enabled pin 2,Enabled pin 3"
|
|
bitfld.long 0x08 16.--17. " PORS ,POR select" "128ms,64ms,32ms,Enabled"
|
|
bitfld.long 0x08 15. " OSCM ,Oscillator mode select" "Wide range,Limited range"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 13. " SC2P ,Oscillator 2pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SC4P ,Oscillator 4pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " SC8P ,Oscillator 8pF load configure" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SC16P ,Oscillator 16pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CLKO ,Indicate whether clock is output to other peripherals or not" "Output,Not output"
|
|
bitfld.long 0x08 8. " OSCE ,Oscillator enable [32.768 kHz]" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x08 7. " LPOS ,LPO select" "32.768kHz clock,1kHZ clock"
|
|
bitfld.long 0x08 5. " CPS ,Clock pin select" "Prescaler output clock,RTC 32.768kHZ clock"
|
|
textline " "
|
|
endif
|
|
sif ((cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||cpuis("MKW21D256VHA5")||cpuis("MKW21D256VHA5R")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("K32W0?2S1M*"))
|
|
bitfld.long 0x08 4. " WPS ,Wakeup pin select" "RTC IR,RTC output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 3. " UM ,Update mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SUP ,Supervisor write access" "Supervisor,Non-supervisor"
|
|
textline " "
|
|
bitfld.long 0x08 1. " WPE ,Wakeup pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x0C "SR,RTC Status Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
rbitfld.long 0x0C 7. " TIDF ,The tamper interrupt detect flag" "Not asserted,Asserted"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 4. " TCE ,Time counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!(cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")))
|
|
rbitfld.long 0x0C 3. " MOF ,Monotonic overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x0C 2. " TAF ,Time alarm flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x0C 1. " TOF ,Time overflow flag" "No overflow,Overflow"
|
|
rbitfld.long 0x0C 0. " TIF ,Time invalid flag" "Valid,Invalid"
|
|
line.long 0x10 "LR,RTC Lock Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
bitfld.long 0x10 11. " MCHL ,Monotonic counter high lock" "Locked,Not locked"
|
|
bitfld.long 0x10 10. " MCLL ,Monotonic counter low lock" "Locked,Not locked"
|
|
bitfld.long 0x10 9. " MEL ,Monotonic enable lock" "Locked,Not locked"
|
|
textline " "
|
|
bitfld.long 0x10 8. " TTSL ,Tamper time seconds lock" "Locked,Not locked"
|
|
bitfld.long 0x10 6. " LRL ,Lock register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 5. " SRL ,Status register lock" "Locked,Not locked"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CRL ,Control register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 3. " TCL ,Time compensation lock" "Locked,Not locked"
|
|
elif (cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK64FX512VDC12")||(cpu()=="MK64FX512VLL12")||(cpu()=="MK64FX512VLQ12")||(cpu()=="MK64FX512VMD12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||cpuis("K32W0?2S1M*")
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x10 19. " PCL[3] ,Pin configuration lock 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " [2] ,Pin configuration lock 2" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " [1] ,Pin configuration lock 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " [0] ,Pin configuration lock 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 15. " TIL ,Tamper interrupt lock" "Locked,Not locked"
|
|
bitfld.long 0x10 14. " TTL ,Tamper trim lock" "Locked,Not locked"
|
|
bitfld.long 0x10 13. " TDL ,Tamper detect lock" "Locked,Not locked"
|
|
textline " "
|
|
bitfld.long 0x10 12. " TEL ,Tamper enable lock" "Locked,Not locked"
|
|
bitfld.long 0x10 11. " MCHL ,Monotonic counter high lock" "Locked,Not locked"
|
|
bitfld.long 0x10 10. " MCLL ,Monotonic counter low lock" "Locked,Not locked"
|
|
textline " "
|
|
bitfld.long 0x10 9. " MEL ,Monotonic enable lock" "Locked,Not locked"
|
|
bitfld.long 0x10 8. " TTSL ,Tamper time seconds lock" "Locked,Not locked"
|
|
bitfld.long 0x10 6. " LRL ,Lock register lock" "Locked,Not locked"
|
|
textline " "
|
|
bitfld.long 0x10 5. " SRL ,Status register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 4. " CRL ,Control register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 3. " TCL ,Time compensation lock" "Locked,Not locked"
|
|
else
|
|
bitfld.long 0x10 6. " LRL ,Lock register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 5. " SRL ,Status register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 4. " CRL ,Control register lock" "Locked,Not locked"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCL ,Time compensation lock" "Locked,Not locked"
|
|
endif
|
|
line.long 0x14 "IER,RTC Interrupt Enable Register"
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x14 16.--18. " TSIC ,Timer seconds interrupt configuration" "1Hz,2Hz,4Hz,8Hz,16Hz,32Hz,64Hz,128Hz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 7. " WPON ,Wakeup pin on" "No effect,Wake up"
|
|
bitfld.long 0x14 4. " TSIE ,Time seconds interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!(cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")))
|
|
bitfld.long 0x14 3. " MOIE ,Monotonic overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 2. " TAIE ,Time alarm interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " TOIE ,Time overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TIIE ,Time invalid interrupt enable" "Disabled,Enabled"
|
|
sif (cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "TTSR,RTC Tamper Time Seconds Register"
|
|
line.long 0x04 "MER,RTC Monotonic Enable Register"
|
|
bitfld.long 0x04 4. " MCE ,Monotonic counter enable" "Load,Increment"
|
|
line.long 0x08 "MCLR,RTC Monotonic Counter Low Register"
|
|
line.long 0x0C "MCHR,RTC Monotonic Counter High Register"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "TER,RTC Tamper Enable Register"
|
|
bitfld.long 0x00 5. " TME ,Test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FSE ,Flash security enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TTE ,Temperature tamper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CTE ,Clock tamper enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VTE ,Voltage tamper enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")
|
|
bitfld.long 0x00 0. " DTE ,Dryice tamper enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "TDR,RTC Tamper Detect Register"
|
|
eventfld.long 0x00 5. " TMF ,Test mode flag" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " FSF ,Flash security flag" "Not detected,Detected"
|
|
eventfld.long 0x00 3. " TTF ,Temperature tamper flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CTF ,Clock tamper flag" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " VTF ,Voltage tamper flag" "Not detected,Detected"
|
|
textline " "
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")
|
|
eventfld.long 0x00 0. " DTF ,Dryice tamper flag" "Not detected,Detected"
|
|
endif
|
|
line.long 0x04 "TTR,RTC Tamper Trim Register"
|
|
bitfld.long 0x04 17.--21. " TDTH ,Temperature detect trim high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 12.--16. " TDTL ,Temperature detect trim low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 9.--11. " CDTH ,Clock detect trim high" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " CDTL ,Clock detect trim low" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 3.--5. " VDTL ,Voltage detect trim low" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " VDTH ,Voltage detect trim high" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "TIR,RTC Tamper Interrupt Register"
|
|
bitfld.long 0x08 5. " TMIE ,Test mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " FSIE ,Flash security interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TTIE ,Temperature tamper interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " CTIE ,Clock tamper interrupt enable" "Disabled,Enabled"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")
|
|
bitfld.long 0x08 1. " VTIE ,Voltage tamper interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " DTIE ,Dryice tamper interrupt enable" "Disabled,Enabled"
|
|
elif ((cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||(cpu()=="MKW21D256VHA5R"))
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "TTSR,RTC Tamper Time Seconds Register"
|
|
line.long 0x04 "MER,RTC Monotonic Enable Register"
|
|
bitfld.long 0x04 4. " MCE ,Monotonic counter enable" "Load,Increment"
|
|
line.long 0x08 "MCLR,RTC Monotonic Counter Low Register"
|
|
line.long 0x0C "MCHR,RTC Monotonic Counter High Register"
|
|
elif cpuis("K32W0?2S1M*")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TTSR,RTC Tamper Time Seconds Register"
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "MER,RTC Monotonic Enable Register"
|
|
bitfld.long 0x00 4. " MCE ,Monotonic counter enable" "Load,Increment"
|
|
line.long 0x04 "MCLR,RTC Monotonic Counter Low Register"
|
|
line.long 0x08 "MCHR,RTC Monotonic Counter High Register"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "TDR,RTC Tamper Detect Register"
|
|
eventfld.long 0x00 19. " TPF[3] ,Tamper pin flag 19" "Not detected,Detected"
|
|
eventfld.long 0x00 18. " [2] ,Tamper pin flag 18" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " [1] ,Tamper pin flag 17" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 16. " [0] ,Tamper pin flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " TMF ,Test mode flag" "Not detected,Detected"
|
|
eventfld.long 0x00 6. " FSF ,Flash security flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 5. " STF ,Security tamper flag" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " LCTF ,Loss of clock tamper flag" "Not detected,Detected"
|
|
line.long 0x04 "TIR,RTC Tamper Interrupt Register"
|
|
bitfld.long 0x04 19. " TPIE[3] ,Tamper pin interrupt enable 3" "Disabled,Enabled,?..."
|
|
bitfld.long 0x04 18. " [2] ,Tamper pin interrupt enable 2" "Disabled,Enabled,?..."
|
|
bitfld.long 0x04 17. " [1] ,Tamper pin interrupt enable 1" "Disabled,Enabled,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16. " [0] ,Tamper pin interrupt enable 0" "Disabled,Enabled,?..."
|
|
bitfld.long 0x04 7. " TMIE ,Test mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " FSIE ,Flash security interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SIE ,Security tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LCIE ,Loss of clock tamper interrupt enable" "Disabled,Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR0,RTC Pin Configuration Register 0"
|
|
bitfld.long 0x00 31. " TPID ,Tamper pin input data" "0,1"
|
|
bitfld.long 0x00 27. " TPP ,Tamper pin polarity" "High,Low"
|
|
bitfld.long 0x00 26. " TFE ,Tamper filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TPS ,Tamper pull select" "Assert,Negate"
|
|
bitfld.long 0x00 24. " TPE ,Tamper pull enabled" "Disabled,Enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR1,RTC Pin Configuration Register 1"
|
|
bitfld.long 0x00 31. " TPID ,Tamper pin input data" "0,1"
|
|
bitfld.long 0x00 27. " TPP ,Tamper pin polarity" "High,Low"
|
|
bitfld.long 0x00 26. " TFE ,Tamper filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TPS ,Tamper pull select" "Assert,Negate"
|
|
bitfld.long 0x00 24. " TPE ,Tamper pull enabled" "Disabled,Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR2,RTC Pin Configuration Register 2"
|
|
bitfld.long 0x00 31. " TPID ,Tamper pin input data" "0,1"
|
|
bitfld.long 0x00 27. " TPP ,Tamper pin polarity" "High,Low"
|
|
bitfld.long 0x00 26. " TFE ,Tamper filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TPS ,Tamper pull select" "Assert,Negate"
|
|
bitfld.long 0x00 24. " TPE ,Tamper pull enabled" "Disabled,Enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR3,RTC Pin Configuration Register 3"
|
|
bitfld.long 0x00 31. " TPID ,Tamper pin input data" "0,1"
|
|
bitfld.long 0x00 27. " TPP ,Tamper pin polarity" "High,Low"
|
|
bitfld.long 0x00 26. " TFE ,Tamper filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TPS ,Tamper pull select" "Assert,Negate"
|
|
bitfld.long 0x00 24. " TPE ,Tamper pull enabled" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*")&&!cpuis("MKW01Z128*"))
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "WAR,RTC Write Access Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||cpu()=="MKW21D256VHA5R")
|
|
bitfld.long 0x00 11. " MCHW ,Monotonic counter high write" "Ignored,Normal"
|
|
bitfld.long 0x00 10. " MCLW ,Monotonic counter low write" "Ignored,Normal"
|
|
bitfld.long 0x00 9. " MERW ,Monotonic enable register write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TTSW ,Tamper time seconds write" "Ignored,Normal"
|
|
bitfld.long 0x00 7. " IERW ,Interrupt enable register write" "Ignored,Normal"
|
|
bitfld.long 0x00 6. " LRW ,Lock register write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SRW ,Status register write" "Ignored,Normal"
|
|
bitfld.long 0x00 4. " CRW ,Control register write" "Ignored,Normal"
|
|
bitfld.long 0x00 3. " TCRW ,Time compensation register write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TARW ,Time alarm register write" "Ignored,Normal"
|
|
bitfld.long 0x00 1. " TPRW ,Time prescaler register write" "Ignored,Normal"
|
|
bitfld.long 0x00 0. " TSRW ,Time seconds register write" "Ignored,Normal"
|
|
elif (cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK64FX512VDC12")||(cpu()=="MK64FX512VLL12")||(cpu()=="MK64FX512VLQ12")||(cpu()=="MK64FX512VMD12")
|
|
bitfld.long 0x00 7. " IERW ,Interrupt enable register write" "Ignored,Normal"
|
|
bitfld.long 0x00 6. " LRW ,Lock register write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SRW ,Status register write" "Ignored,Normal"
|
|
bitfld.long 0x00 4. " CRW ,Control register write" "Ignored,Normal"
|
|
bitfld.long 0x00 3. " TCRW ,Time compensation register write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TARW ,Time alarm register write" "Ignored,Normal"
|
|
bitfld.long 0x00 1. " TPRW ,Time prescaler register write" "Ignored,Normal"
|
|
bitfld.long 0x00 0. " TSRW ,Time seconds register write" "Ignored,Normal"
|
|
else
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 19. " PCRW[3] ,Pin configuration register write 3" "Ignored,Normal"
|
|
bitfld.long 0x00 18. " [2] ,Pin configuration register write 2" "Ignored,Normal"
|
|
bitfld.long 0x00 17. " [1] ,Pin configuration register write 1" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [0] ,Pin configuration register write 0" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " TIRW ,Tamper interrupt register write" "Ignored,Normal"
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 14. " TTRW ,Tamper trim register write" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " TDRW ,Tamper detect register write" "Ignored,Normal"
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 12. " TERW ,Tamper enable register write" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " MCHW ,Monotonic counter high write" "Ignored,Normal"
|
|
bitfld.long 0x00 10. " MCLW ,Monotonic counter low write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MERW ,Monotonic enable register write" "Ignored,Normal"
|
|
bitfld.long 0x00 8. " TTSW ,Tamper time seconds write" "Ignored,Normal"
|
|
bitfld.long 0x00 7. " IERW ,Interrupt enable register write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LRW ,Lock register write" "Ignored,Normal"
|
|
bitfld.long 0x00 5. " SRW ,Status register write" "Ignored,Normal"
|
|
bitfld.long 0x00 4. " CRW ,Control register write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TCRW ,Time compensation register write" "Ignored,Normal"
|
|
bitfld.long 0x00 2. " TARW ,Time alarm register write" "Ignored,Normal"
|
|
bitfld.long 0x00 1. " TPRW ,Time prescaler register write" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TSRW ,Time seconds register write" "Ignored,Normal"
|
|
endif
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "RAR,RTC Read Access Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpu()=="MKW21D256VHA5R"))
|
|
bitfld.long 0x00 11. " MCHR ,Monotonic counter high read" "Ignored,Normal"
|
|
bitfld.long 0x00 10. " MCLR ,Monotonic counter low read" "Ignored,Normal"
|
|
bitfld.long 0x00 9. " MERR ,Monotonic enable register read" "Ignored,Normal"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
rbitfld.long 0x00 8. " TTSR ,Tamper time seconds read" "Ignored,Normal"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8. " TTSR ,Tamper time seconds read" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IERR ,Interrupt enable register read" "Ignored,Normal"
|
|
bitfld.long 0x00 6. " LRR ,Lock register read" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SRR ,Status register read" "Ignored,Normal"
|
|
bitfld.long 0x00 4. " CRR ,Control register read" "Ignored,Normal"
|
|
bitfld.long 0x00 3. " TCRR ,Time compensation register read" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TARR ,Time alarm register read" "Ignored,Normal"
|
|
bitfld.long 0x00 1. " TPRR ,Time prescaler register read" "Ignored,Normal"
|
|
bitfld.long 0x00 0. " TSRR ,Time seconds register read" "Ignored,Normal"
|
|
textline " "
|
|
elif (cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||cpuis("K32W0?2S1M*")
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 19. " PCRR[3] ,Pin configuration register read 3" "Ignored,Normal"
|
|
bitfld.long 0x00 18. " [2] ,Pin configuration register read 2" "Ignored,Normal"
|
|
bitfld.long 0x00 17. " [1] ,Pin configuration register read 1" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [0] ,Pin configuration register read 0" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " TIRR ,Tamper interrupt register read" "Ignored,Normal"
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 14. " TTRR ,Tamper trim register read" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " TDRR ,Tamper detect register read" "Ignored,Normal"
|
|
textline " "
|
|
sif !cpuis("K32W0?2S1M*")
|
|
bitfld.long 0x00 12. " TERR ,Tamper enable register read" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " MCHR ,Monotonic counter high read" "Ignored,Normal"
|
|
bitfld.long 0x00 10. " MCLR ,Monotonic counter low read" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MERR ,Monotonic enable register read" "Ignored,Normal"
|
|
textline " "
|
|
sif cpuis("K32W0?2S1M*")
|
|
rbitfld.long 0x00 8. " TTSR ,Tamper time seconds read" "Ignored,Normal"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8. " TTSR ,Tamper time seconds read" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IERR ,Interrupt enable register read" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LRR ,Lock register read" "Ignored,Normal"
|
|
bitfld.long 0x00 5. " SRR ,Status register read" "Ignored,Normal"
|
|
bitfld.long 0x00 4. " CRR ,Control register read" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TCRR ,Time compensation register read" "Ignored,Normal"
|
|
bitfld.long 0x00 2. " TARR ,Time alarm register read" "Ignored,Normal"
|
|
bitfld.long 0x00 1. " TPRR ,Time prescaler register read" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TSRR ,Time seconds register read" "Ignored,Normal"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 7. " IERR ,Interrupt enable register read" "Ignored,Normal"
|
|
bitfld.long 0x00 6. " LRR ,Lock register read" "Ignored,Normal"
|
|
bitfld.long 0x00 5. " SRR ,Status register read" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CRR ,Control register read" "Ignored,Normal"
|
|
bitfld.long 0x00 3. " TCRR ,Time compensation register read" "Ignored,Normal"
|
|
bitfld.long 0x00 2. " TARR ,Time alarm register read" "Ignored,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TPRR ,Time prescaler register read" "Ignored,Normal"
|
|
bitfld.long 0x00 0. " TSRR ,Time seconds register read" "Ignored,Normal"
|
|
textline " "
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
tree "USBOTG (Universal Serial Bus OTG Controller)"
|
|
base ad:0x40072000
|
|
width 10.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "PERID,Peripheral ID Register"
|
|
hexmask.byte 0x00 0.--5. 1. " ID ,Peripheral identification"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "IDCOMP,Peripheral ID Complement Register"
|
|
hexmask.byte 0x00 0.--5. 1. " NID ,Ones complement of peripheral identification"
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "REV,Peripheral Revision Register"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "ADDINFO,Peripheral Additional Info Register"
|
|
hexmask.byte 0x00 3.--7. 1. " IRQ_NUM ,Assigned interrupt request number"
|
|
bitfld.byte 0x00 0. " IEHOST ,Host mode enable" "Disabled,Enabled"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register"
|
|
bitfld.byte 0x00 7. " IDCHG ,ID signal from USB connector change interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " ONEMSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSVLDCHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " AVBUSCHG ,VBUS change on A device interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "OTGICR,OTG Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " IDEN ,ID interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ONEMSECEN ,1 millisecond interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LINESTATEEN ,Line state change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSVLDEN ,Session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BSESSEN ,B session END interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AVBUSEN ,A VBUS valid interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "OTGSTAT,OTG Status Register"
|
|
bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/type B cable"
|
|
bitfld.byte 0x00 6. " ONEMSECEN ,1 millisecond interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LINESTATESTABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid"
|
|
bitfld.byte 0x00 2. " BSESSEND ,B session END" "Not END,END"
|
|
bitfld.byte 0x00 0. " AVBUSVLD ,A VBUS valid" "Invalid,Valid"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "OTGCTL,OTG Control Register"
|
|
bitfld.byte 0x00 7. " DPHIGH ,D+ data line pullup resistor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " DMLOW ,D- data line pull-down resistor enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " OTGEN ,On-the-go pullup/pulldown resistor enable" "Disabled,Enabled"
|
|
if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 6. " ATTACH ,Attach interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " RESUME ,Signal remote Wake-up signaling interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (For 3ms) interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " SOFTOK ,Start of frame token interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 0. " USBRST ,USB reset interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " STALLEN ,STALL interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ATTACHEN ,ATTACH interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RESUMEEN ,RESUME interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " SLEEPEN ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TOKDNEEN ,TOK_DNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " SOFTOKEN ,SOF_TOK interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ERROREN ,ERROR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " USBRSTEN ,USB_RST interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " BTSERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DMAERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " BTOERR ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " CRCEOF ,End of frame error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 0. " PIDERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BTSERREN ,BTS_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DMAERREN ,DMA_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BTOERREN ,BTO_ERR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DFN8EN ,DFN8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CRC16EN ,CRC16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CRC5EOFEN ,CRC5/EOF interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " PIDERREN ,PID_ERR interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " RESUME ,Signal remote Wake-up signaling interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (For 3ms) interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " SOFTOK ,Start of frame token interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 0. " USBRST ,USB reset interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " STALLEN ,STALL interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RESUMEEN ,RESUME interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SLEEPEN ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TOKDNEEN ,TOK_DNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " SOFTOKEN ,SOF_TOK interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ERROREN ,ERROR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " USBRSTEN ,USB_RST interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " BTSERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DMAERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " BTOERR ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " CRC5EOF ,CRC5 error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x00 0. " PIDERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BTSERREN ,BTS_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DMAERREN ,DMA_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BTOERREN ,BTO_ERR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DFN8EN ,DFN8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CRC16EN ,CRC16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CRC5EOFEN ,CRC5/EOF interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " PIDERREN ,PID_ERR interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0x084)&0x08)==0x08)
|
|
rgroup.byte 0x90++0x00
|
|
line.byte 0x00 "STAT,Status Register"
|
|
bitfld.byte 0x00 4.--7. " ENDP ,Endpoint address" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.byte 0x00 3. " TX ,Transmit indicator" "Receive,Transmit"
|
|
bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Not odd,Odd"
|
|
else
|
|
hgroup.byte 0x90++0x00
|
|
hide.byte 0x00 "STAT,Status Register"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control Register"
|
|
bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High"
|
|
bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High"
|
|
bitfld.byte 0x00 5. " TOKENBUSY ,USB module is busy executing a USB token" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RESET ,USB reset" "No reset,Reset"
|
|
bitfld.byte 0x00 3. " HOSTMODEEN ,Host mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ODDRST ,BDT ODD ping/pong bits reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " USBENSOFEN ,USB enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control Register"
|
|
bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High"
|
|
bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High"
|
|
bitfld.byte 0x00 5. " TXSUSPEND ,Packet transmission and reception disable" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HOSTMODEEN ,Host mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ODDRST ,BDT ODD ping/pong bits reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " USBENSOFEN ,USB enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "ADDR,Address Register"
|
|
bitfld.byte 0x00 7. " LS_EN ,Low speed enable" "Disabled,Enabled"
|
|
hexmask.byte 0x00 0.--6. 0x01 " ADDR ,USB address"
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "BDTPAGE1,BDT Page Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " BDT_BA[15:9] ,BDT base address bits [15:9]"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "FRMNUML,Frame Number Register Low"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "FRMNUMH,Frame Number Register High"
|
|
bitfld.byte 0x00 0.--2. " FRM[10:8] ,Upper 3 bits of BDT system memory address" "000,001,010,011,100,101,110,111"
|
|
if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "TOKEN,Token Register"
|
|
bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",OUT,,,,,,,,IN,,,,SETUP,?..."
|
|
bitfld.byte 0x00 0.--3. " TOKEN_ENDPT ,Endpoint address for the token command" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "SOFTHLD,SOF Threshold Register"
|
|
else
|
|
hgroup.byte 0xA8++0x00
|
|
hide.byte 0x00 "TOKEN,Token Register"
|
|
hgroup.byte 0xAC++0x00
|
|
hide.byte 0x00 "SOFTHLD,SOF Threshold Register"
|
|
endif
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "BDTPAGE2,BDT Page Register 2"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "BDTPAGE3,BDT Page Register 3"
|
|
textline " "
|
|
if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)&&((per.b(ad:0x40072000+0x0C0)&0x0C)!=0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicated to directly connected low speed device" "Not allowed,Allowed"
|
|
bitfld.byte 0x00 6. " RETRY_DIS ,Negative acknowledgement transactions retry disable" "No,Yes"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
elif ((per.b(ad:0x40072000+0x94)&0x08)==0x00)&&((per.b(ad:0x40072000+0x0C0)&0x0C)!=0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
elif ((per.b(ad:0x40072000+0x94)&0x08)==0x08)&&((per.b(ad:0x40072000+0x0C0)&0x0C)==0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicated to directly connected low speed device" "Not allowed,Allowed"
|
|
bitfld.byte 0x00 6. " RETRY_DIS ,Negative acknowledgement transactions retry disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xC4)&0x0C)!=0x00)
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT1,Endpoint Control Register 1"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT1,Endpoint Control Register 1"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xC8)&0x0C)!=0x00)
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT2,Endpoint Control Register 2"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT2,Endpoint Control Register 2"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xCC)&0x0C)!=0x00)
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT3,Endpoint Control Register 3"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT3,Endpoint Control Register 3"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xD0)&0x0C)!=0x00)
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control Register 4"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control Register 4"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xD4)&0x0C)!=0x00)
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control Register 5"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control Register 5"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xD8)&0x0C)!=0x00)
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT6,Endpoint Control Register 6"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT6,Endpoint Control Register 6"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xDC)&0x0C)!=0x00)
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "ENDPT7,Endpoint Control Register 7"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "ENDPT7,Endpoint Control Register 7"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xE0)&0x0C)!=0x00)
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT8,Endpoint Control Register 8"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT8,Endpoint Control Register 8"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xE4)&0x0C)!=0x00)
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT9,Endpoint Control Register 9"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT9,Endpoint Control Register 9"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xE8)&0x0C)!=0x00)
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ENDPT10,Endpoint Control Register 10"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ENDPT10,Endpoint Control Register 10"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xEC)&0x0C)!=0x00)
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT11,Endpoint Control Register 11"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT11,Endpoint Control Register 11"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xF0)&0x0C)!=0x00)
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT12,Endpoint Control Register 12"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT12,Endpoint Control Register 12"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xF4)&0x0C)!=0x00)
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT13,Endpoint Control Register 13"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT13,Endpoint Control Register 13"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xF8)&0x0C)!=0x00)
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control Register 14"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control Register 14"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xFC)&0x0C)!=0x00)
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control Register 15"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control Register 15"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "USBCTRL,USB Control Register"
|
|
bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended"
|
|
bitfld.byte 0x00 6. " PDE ,USB transceiver weak pulldowns enable" "Disabled,Enabled"
|
|
rgroup.byte 0x104++0x00
|
|
line.byte 0x00 "OBSERVE,USB OTG Observe Register"
|
|
bitfld.byte 0x00 7. " DP_PU ,D+ pull up signal output observability" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DP_PD ,D+ pull down signal output observability" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " DM_PD ,D- pull down signal output observability" "Disabled,Enabled"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "CONTROL,USB OTG Control Register"
|
|
bitfld.byte 0x00 4. " DPPULLUP_NONOTG ,DP PULLUP in the USB OTG control" "Disabled,Enabled"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0"
|
|
bitfld.byte 0x00 7. " USBRESET ,USB_OTG module reset" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
width 14.
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "USBFRMADJUST,Frame Adjust Register"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
width 24.
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "CLK_RECOVER_CTRL,USB Clock Recovery Control"
|
|
bitfld.byte 0x00 7. " CLOCK_RECOVER_EN ,Crystal-less USB enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RESET_RESUME_ROUGH_EN ,Reset/resume to rough phase enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RESTART_IFRTRIM_EN ,Restart from IFR trim value" "Disabled,Enabled"
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "CLK_RECOVER_IRC_EN,IRC48M Oscillator Enable Register"
|
|
bitfld.byte 0x00 1. " IRC_EN ,IRC48M enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " REG_EN ,IRC48M regulator enable" "Disabled,Enabled"
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status"
|
|
eventfld.byte 0x00 4. " OVF_ERROR ,Frequency trim adjustment overflow" "No interrupt,Interrupt"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USBDCD (USB Device Charger Detection Module)"
|
|
base ad:0x40035000
|
|
width 13.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CONTROL,USBDCD Control Register"
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
bitfld.long 0x00 25. " SR ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " START ,Start change detection sequence" "Not started,Started"
|
|
bitfld.long 0x00 16. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " IF ,Interrupt flag" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " IACK ,Interrupt acknowledge" "-,Clear"
|
|
else
|
|
bitfld.long 0x00 25. " SR ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " START ,Start change detection sequence" "Not started,Started"
|
|
bitfld.long 0x00 17. " BC12 ,BC1.2 compatibility" "BC1.1,BC1.2"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " IF ,Interrupt flag" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " IACK ,Interrupt acknowledge" "-,Cleared"
|
|
endif
|
|
line.long 0x04 "CLOCK,USBDCD Clock Register"
|
|
hexmask.long.word 0x04 2.--11. 1. " CLOCK_SPEED ,Numerical value of clock speed in binary"
|
|
bitfld.long 0x04 0. " CLOCK_UNIT ,Unit of measurement encoding for clock speed" "kHz,MHz"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,USBDCD Status Register"
|
|
bitfld.long 0x00 22. " ACTIVE ,Active status indicator" "Not running,Running"
|
|
bitfld.long 0x00 21. " TO ,Timeout flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SEQ_STAT ,Charger detection sequence status" "Disabled/not detected,Data pin contact detected,Charger detected,Charger type detected"
|
|
bitfld.long 0x00 16.--17. " SEQ_RES ,Charger detection sequence results" "No results,Standard host,Charging port,Dedicated charger"
|
|
sif (cpuis("MKW22D*")||cpuis("MKW24D*"))
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "TIMER0,USBDCD TIMER0 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " TSEQ_INIT ,Sequence initiation time (In ms)"
|
|
hexmask.long.word 0x00 0.--11. 1. " TUNITCON ,Unit connection timer elapse (In ms)"
|
|
line.long 0x04 "TIMER1,USBDCD TIMER1 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " TDCD_DBNC ,Time period to debounce D+ signal (In ms)"
|
|
hexmask.long.word 0x04 0.--9. 1. " TVDPSRC_ON ,Time period comparator enabled (In ms)"
|
|
line.long 0x08 "TIMER2,USBDCD TIMER2 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " TVDPSRC_CON ,Time period before enabling D+ pullup (In ms)"
|
|
bitfld.long 0x08 0.--3. " CHECK_DM ,Time before check of D- line (In ms)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if ((per.l(ad:0x40035000)&0x20000)==0x20000)
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "TIMER0,USBDCD TIMER0 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " TSEQ_INIT ,Sequence initiation time (In ms)"
|
|
hexmask.long.word 0x00 0.--11. 1. " TUNIT_CON_ELAPSED ,Unit connection timer elapse (In ms)"
|
|
line.long 0x04 "TIMER1,USBDCD TIMER1 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " TDCD_DBNC ,Time period to debounce D+ signal (In ms)"
|
|
hexmask.long.word 0x04 0.--9. 1. " TVDPSRC_ON ,Time period comparator enabled (In ms)"
|
|
line.long 0x08 "TIMER2_BC11,USBDCD TIMER2 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " TVDPSRC_CON ,Time period before enabling D+ pullup (In ms)"
|
|
bitfld.long 0x08 0.--3. " CHECK_DM ,Time before check of D- line (In ms)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif ((per.l(ad:0x40035000)&0x20000)==0x0)
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "TIMER0,USBDCD TIMER0 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " TSEQ_INIT ,Sequence initiation time (In ms)"
|
|
hexmask.long.word 0x00 0.--11. 1. " TUNIT_CON_ELAPSED ,Unit connection timer elapse (In ms)"
|
|
line.long 0x04 "TIMER1,USBDCD TIMER1 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " TDCD_DBNC ,Time period to debounce D+ signal (In ms)"
|
|
hexmask.long.word 0x04 0.--9. 1. " TVDPSRC_ON ,Time period comparator enabled (In ms)"
|
|
line.long 0x08 "TIMER2_BC12,USBDCD TIMER2 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " TWAIT_AFTER_PRD ,Timer wait after period"
|
|
hexmask.long.word 0x08 0.--9. 1. " TVDMSRC_ON ,Set time that the modules enabled VDM_SRC"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW01Z128*"))
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "Module 0"
|
|
base ad:0x40076000
|
|
width 14.
|
|
sif (cpuis("MKW01Z128*"))
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI0_S,SPI Status Register"
|
|
rbitfld.byte 0x00 7. " SPRF ,SPI read buffer full flag" "No available,Available"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
rbitfld.byte 0x00 5. " SPTEF ,SPI transmit buffer empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
else
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "SPI0_S,SPI Status Register"
|
|
bitfld.byte 0x00 7. " SPRF ,SPI read buffer full flag" "No available,Available"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " SPTEF ,SPI transmit buffer empty flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
endif
|
|
group.byte 0x01++0x01
|
|
line.byte 0x00 "SPI0_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR[2:0] ,SPI baud rate prescale divisor" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.byte 0x00 0.--3. " SPR[3:0] ,SPI baud rate divisor" "/2,/4,/8,/16,/32,/64,/128,/256,/512,?..."
|
|
line.byte 0x01 "SPI0_C2,SPI Control Register 2"
|
|
bitfld.byte 0x01 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x01 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x01 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI receive buffer full interrupt and mode fault" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB"
|
|
if (((per.b(ad:0x40076000+0x02))&0x40)==0x40)
|
|
group.byte 0x04++0x03
|
|
line.byte 0x00 "SPI0_ML,SPI Match Register Low"
|
|
line.byte 0x01 "SPI0_MH,SPI Match Register High"
|
|
line.byte 0x02 "SPI0_DL,SPI Data Register Low"
|
|
line.byte 0x03 "SPI0_DH,SPI Data Register High"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SPI0_ML,SPI Match Register Low"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SPI0_DL,SPI Data Register Low"
|
|
endif
|
|
sif (cpuis("MKW01Z128*"))
|
|
hgroup.byte 0x0A++0x00
|
|
hide.byte 0x00 "SPI0_CI,SPI Clear Interrupt"
|
|
in
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI0_C3,SPI Control Register 3"
|
|
bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less"
|
|
bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more"
|
|
bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled"
|
|
else
|
|
if ("0"=="1")
|
|
if (((per.b(ad:0x40076000+0x0B))&0x08)==0x00)
|
|
rgroup.byte 0x0A++0x00
|
|
line.byte 0x00 "SPI0_CI,SPI Clear Interrupt"
|
|
bitfld.byte 0x00 7. " TXFERR ,Transmit FIFO error flag" "No error,Error"
|
|
bitfld.byte 0x00 6. " RXFERR ,Receive FIFO error flag" "No error,Error"
|
|
bitfld.byte 0x00 5. " TXFOF ,Transmit FIFO overflow flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXFOF ,Receive FIFO overflow flag" "No error,Error"
|
|
elif (((per.b(ad:0x40076000+0x0B))&0x08)==0x08)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SPI0_CI,SPI Clear Interrupt"
|
|
rbitfld.byte 0x00 7. " TXFERR ,Transmit FIFO error flag" "No error,Error"
|
|
rbitfld.byte 0x00 6. " RXFERR ,Receive FIFO error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " TXFOF ,Transmit FIFO overflow flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " RXFOF ,Receive FIFO overflow flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " TNEAREFCI ,Transmit FIFO nearly empty flag clear interrupt" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " RNFULLFCI ,Receive FIFO nearly full empty flag clear interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SPTEFCI ,Transmit FIFO empty flag clear interrupt" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " SPRFCI ,Receive FIFO full flag clear interrupt" "No effect,Clear"
|
|
endif
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")
|
|
if (((per.b(ad:0x40076000+0x0B))&0x01)==0x01)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI0_C3,SPI Control Register 3"
|
|
bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less"
|
|
bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more"
|
|
bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI0_C3,SPI Control Register 3"
|
|
rbitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less"
|
|
rbitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more"
|
|
rbitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI0_C3,SPI Control Register 3"
|
|
bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less"
|
|
bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more"
|
|
bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Module 1"
|
|
base ad:0x40077000
|
|
width 14.
|
|
if (((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x0B))&0x20)==0x00)&&(((per.b(ad:0x40077000+0x0B))&0x10)==0x00)
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7"))
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
rbitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
rbitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 48 bits,Equal to or greater than 48"
|
|
rbitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 16 bits,Equal to or less than 16 bits"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes"
|
|
rbitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty"
|
|
else
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
bitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 48 bits,Equal to or greater than 48"
|
|
bitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 16 bits,Equal to or less than 16 bits"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes"
|
|
bitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty"
|
|
endif
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x0B))&0x20)==0x20)&&(((per.b(ad:0x40077000+0x0B))&0x10)==0x00)
|
|
sif (cpuis("MKW01Z128*"))
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
rbitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
rbitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 48 bits,Equal to or greater than 48"
|
|
rbitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 32 bits,Equal to or less than 32 bits"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes"
|
|
rbitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty"
|
|
else
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
bitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 48 bits,Equal to or greater than 48"
|
|
bitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 32 bits,Equal to or less than 32 bits"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes"
|
|
bitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty"
|
|
endif
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x0B))&0x20)==0x00)&&(((per.b(ad:0x40077000+0x0B))&0x10)==0x10)
|
|
sif (cpuis("MKW01Z128*"))
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
rbitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
rbitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 32 bits,Equal to or greater than 32"
|
|
rbitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 16 bits,Equal to or less than 16 bits"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes"
|
|
rbitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty"
|
|
else
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
bitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 32 bits,Equal to or greater than 32"
|
|
bitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 16 bits,Equal to or less than 16 bits"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes"
|
|
bitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty"
|
|
endif
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x0B))&0x20)==0x20)&&(((per.b(ad:0x40077000+0x0B))&0x10)==0x10)
|
|
sif (cpuis("MKW01Z128*"))
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
rbitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
rbitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
rbitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 32 bits,Equal to or greater than 32"
|
|
rbitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 32 bits,Equal to or less than 32 bits"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes"
|
|
rbitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty"
|
|
else
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
bitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 32 bits,Equal to or greater than 32"
|
|
bitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 32 bits,Equal to or less than 32 bits"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes"
|
|
bitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty"
|
|
endif
|
|
else
|
|
sif (cpuis("MKW01Z128*"))
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
rbitfld.byte 0x00 7. " SPRF ,SPI read buffer full flag" "No available,Available"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
rbitfld.byte 0x00 5. " SPTEF ,SPI transmit buffer empty flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
else
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
bitfld.byte 0x00 7. " SPRF ,SPI read buffer full flag" "No available,Available"
|
|
eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " SPTEF ,SPI transmit buffer empty flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error"
|
|
endif
|
|
endif
|
|
group.byte 0x01++0x01
|
|
line.byte 0x00 "SPI1_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR[2:0] ,SPI baud rate prescale divisor" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.byte 0x00 0.--3. " SPR[3:0] ,SPI baud rate divisor" "/2,/4,/8,/16,/32,/64,/128,/256,/512,?..."
|
|
line.byte 0x01 "SPI1_C2,SPI Control Register 2"
|
|
bitfld.byte 0x01 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x01 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x01 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
if ((((per.b(ad:0x40077000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x00))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI receive buffer full interrupt and mode fault" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB"
|
|
elif ((((per.b(ad:0x40077000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x10))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI receive buffer full interrupt and mode fault" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB"
|
|
elif ((((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x00))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI receive FIFO full interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit FIFO empty interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB"
|
|
elif ((((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x10))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI receive FIFO full interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB"
|
|
endif
|
|
if (((per.b(ad:0x40077000+0x02))&0x40)==0x40)
|
|
group.byte 0x04++0x03
|
|
line.byte 0x00 "SPI1_ML,SPI Match Register Low"
|
|
line.byte 0x01 "SPI1_MH,SPI Match Register High"
|
|
line.byte 0x02 "SPI1_DL,SPI Data Register Low"
|
|
line.byte 0x03 "SPI1_DH,SPI Data Register High"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SPI1_ML,SPI Match Register Low"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SPI1_DL,SPI Data Register Low"
|
|
endif
|
|
sif (cpuis("MKW01Z128*"))
|
|
hgroup.byte 0x0A++0x00
|
|
hide.byte 0x00 "SPI1_CI,SPI Clear Interrupt"
|
|
in
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI1_C3,SPI Control Register 3"
|
|
bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less"
|
|
bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more"
|
|
bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled"
|
|
else
|
|
if ("1"=="1")
|
|
if (((per.b(ad:0x40077000+0x0B))&0x08)==0x00)
|
|
rgroup.byte 0x0A++0x00
|
|
line.byte 0x00 "SPI1_CI,SPI Clear Interrupt"
|
|
bitfld.byte 0x00 7. " TXFERR ,Transmit FIFO error flag" "No error,Error"
|
|
bitfld.byte 0x00 6. " RXFERR ,Receive FIFO error flag" "No error,Error"
|
|
bitfld.byte 0x00 5. " TXFOF ,Transmit FIFO overflow flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXFOF ,Receive FIFO overflow flag" "No error,Error"
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x08)==0x08)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SPI1_CI,SPI Clear Interrupt"
|
|
rbitfld.byte 0x00 7. " TXFERR ,Transmit FIFO error flag" "No error,Error"
|
|
rbitfld.byte 0x00 6. " RXFERR ,Receive FIFO error flag" "No error,Error"
|
|
rbitfld.byte 0x00 5. " TXFOF ,Transmit FIFO overflow flag" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " RXFOF ,Receive FIFO overflow flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " TNEAREFCI ,Transmit FIFO nearly empty flag clear interrupt" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " RNFULLFCI ,Receive FIFO nearly full empty flag clear interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SPTEFCI ,Transmit FIFO empty flag clear interrupt" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " SPRFCI ,Receive FIFO full flag clear interrupt" "No effect,Clear"
|
|
endif
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")
|
|
if (((per.b(ad:0x40077000+0x0B))&0x01)==0x01)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI1_C3,SPI Control Register 3"
|
|
bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less"
|
|
bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more"
|
|
bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI1_C3,SPI Control Register 3"
|
|
rbitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less"
|
|
rbitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more"
|
|
rbitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI1_C3,SPI Control Register 3"
|
|
bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less"
|
|
bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more"
|
|
bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "Module 0"
|
|
base ad:0x4002C000
|
|
width 13.
|
|
sif (cpuis("MKV5*"))
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW*"))
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
else
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
elif (cpuis("MKV*"))
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
else
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TCR,Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR,Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR,Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
endif
|
|
sif (cpuis("MKV*")||cpuis("MKW*"))
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x00000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading"
|
|
bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x10000000)
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading"
|
|
bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
hgroup.long 0x0C++0x07
|
|
hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0"
|
|
hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*"))
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)"
|
|
bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
endif
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*"))
|
|
rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled"
|
|
else
|
|
eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow"
|
|
eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full"
|
|
eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty"
|
|
rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("MKV5*")
|
|
if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA"
|
|
endif
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PUSHR,PUSH TX FIFO Register"
|
|
bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted"
|
|
bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..."
|
|
bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared"
|
|
textline " "
|
|
sif (cpu()=="MKV31F128VLH10"||cpu()=="MKV31F256VLH12"||cpu()=="MKV31F512VLH12")
|
|
bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
elif (cpu()=="MKV30F128VFM10"||cpu()=="MKV30F64VFM10"||cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
else
|
|
bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
endif
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "POPR,POP RX FIFO Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*"))
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,Transmit FIFO Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,Transmit FIFO Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,Transmit FIFO Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,Transmit FIFO Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,Transmit FIFO Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,Transmit FIFO Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,Transmit FIFO Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,Transmit FIFO Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
endif
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,Transmit FIFO Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,Transmit FIFO Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,Transmit FIFO Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,Transmit FIFO Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*"))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "RXFR0,Receive FIFO Register 0"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RXFR1,Receive FIFO Register 1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RXFR2,Receive FIFO Register 2"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RXFR3,Receive FIFO Register 3"
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "RXFR0,Receive FIFO Register 0"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "RXFR1,Receive FIFO Register 1"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "RXFR2,Receive FIFO Register 2"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "RXFR3,Receive FIFO Register 3"
|
|
textfld " "
|
|
in
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKV10Z*"))
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "SREX,Status Register Extended"
|
|
bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1"
|
|
bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Module 1"
|
|
base ad:0x4002D000
|
|
width 13.
|
|
sif (cpuis("MKV5*"))
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW*"))
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
else
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
elif (cpuis("MKV*"))
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
else
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
sif (cpuis("MKV5*"))
|
|
if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TCR,Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR,Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR,Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
endif
|
|
sif (cpuis("MKV*")||cpuis("MKW*"))
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002D000+0x34))&0x70000000)==0x00000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading"
|
|
bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
elif ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002D000+0x34))&0x70000000)==0x10000000)
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading"
|
|
bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
elif ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
hgroup.long 0x0C++0x07
|
|
hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0"
|
|
hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*"))
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
endif
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7"
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)"
|
|
bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
endif
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*"))
|
|
rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled"
|
|
else
|
|
eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow"
|
|
eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full"
|
|
eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty"
|
|
rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("MKV5*")
|
|
if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA"
|
|
endif
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PUSHR,PUSH TX FIFO Register"
|
|
bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..."
|
|
bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared"
|
|
textline " "
|
|
sif (cpu()=="MKV31F128VLH10"||cpu()=="MKV31F256VLH12"||cpu()=="MKV31F512VLH12")
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
else
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register"
|
|
sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
endif
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "POPR,POP RX FIFO Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*"))
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,Transmit FIFO Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,Transmit FIFO Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,Transmit FIFO Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,Transmit FIFO Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,Transmit FIFO Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,Transmit FIFO Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,Transmit FIFO Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,Transmit FIFO Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
endif
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,Transmit FIFO Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,Transmit FIFO Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,Transmit FIFO Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,Transmit FIFO Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*"))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "RXFR0,Receive FIFO Register 0"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RXFR1,Receive FIFO Register 1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RXFR2,Receive FIFO Register 2"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RXFR3,Receive FIFO Register 3"
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "RXFR0,Receive FIFO Register 0"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "RXFR1,Receive FIFO Register 1"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "RXFR2,Receive FIFO Register 2"
|
|
textfld " "
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "RXFR3,Receive FIFO Register 3"
|
|
textfld " "
|
|
in
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKV10Z*"))
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "SREX,Status Register Extended"
|
|
bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1"
|
|
bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "Module 0"
|
|
base ad:0x40066000
|
|
width 6.
|
|
if (((per.b(ad:0x40066000+0x03))&0x40)==0x00)
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "A1,I2C0 Address Register 1"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "A1,I2C0 Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]"
|
|
endif
|
|
group.byte 0x01++0x02
|
|
line.byte 0x00 "F,I2C0 Frequency Divider Register"
|
|
bitfld.byte 0x00 6.--7. " MULT ,Multiplier factor" "1,2,4,?..."
|
|
bitfld.byte 0x00 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921"
|
|
line.byte 0x01 "C1,I2C0 Control Register 1"
|
|
bitfld.byte 0x01 7. " IICEN ,IIC0 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " IICIE ,IIC0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " MST ,Master mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " TX ,Transmit mode select" "Receive,Transmit"
|
|
bitfld.byte 0x01 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged"
|
|
bitfld.byte 0x01 2. " RSTA ,Repeat START" "No effect,Start"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " WUEN ,Wakeup enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
line.byte 0x02 "S,I2C0 Status Register"
|
|
rbitfld.byte 0x02 7. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
bitfld.byte 0x02 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed"
|
|
rbitfld.byte 0x02 5. " BUSY ,Bus busy" "Idle,Busy"
|
|
textline " "
|
|
eventfld.byte 0x02 4. " ARBL ,Arbitration lost" "Not lost,Lost"
|
|
bitfld.byte 0x02 3. " RAM ,Range address match" "Not matched,Matched"
|
|
rbitfld.byte 0x02 2. " SRW ,Slave read/write" "Write,Read"
|
|
textline " "
|
|
eventfld.byte 0x02 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x02 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged"
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "D,I2C0 Data I/O Register"
|
|
in
|
|
if (((per.b(ad:0x40066000+0x05)&0x40)==0x40)&&(((per.b(ad:0x40066000+0x03))&0x40)==0x40))
|
|
group.byte 0x05++0x0
|
|
line.byte 0x00 "C2,I2C0 Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master,Independent"
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
hexmask.byte 0x00 0.--2. 1. " AD[10:8] ,Slave address bits [10:8]"
|
|
else
|
|
group.byte 0x05++0x0
|
|
line.byte 0x00 "C2,I2C0 Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master,Independent"
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x06++0x5
|
|
line.byte 0x00 "FLT,I2C0 Programmable Input Glitch Filter Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
bitfld.byte 0x00 0.--4. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 7. " SHEN ,Stop Hold Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "No start,Start"
|
|
bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x01 "RA,I2C0 Range Address Register"
|
|
hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address"
|
|
line.byte 0x02 "SMB,I2C0 SMBus Control and Status Register"
|
|
bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " SIICAEN ,Second IIC0 address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock/64 freq,Bus clock freq"
|
|
eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred"
|
|
bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x03 "A2,I2C0 Address Register 2"
|
|
hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address"
|
|
line.byte 0x04 "SLTH,I2C0 SCL Low Timeout High Register"
|
|
line.byte 0x05 "SLTL,I2C0 SCL Low Timeout Low Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "S2,I2C0 Status Register 2"
|
|
bitfld.byte 0x00 2. " DFEN ,Double Buffer Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 1. " ERROR ,Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 0. " EMPTY ,Empty Flag" "Not empty,Empty"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Module 1"
|
|
base ad:0x40067000
|
|
width 6.
|
|
if (((per.b(ad:0x40067000+0x03))&0x40)==0x00)
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "A1,I2C1 Address Register 1"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "A1,I2C1 Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]"
|
|
endif
|
|
group.byte 0x01++0x02
|
|
line.byte 0x00 "F,I2C1 Frequency Divider Register"
|
|
bitfld.byte 0x00 6.--7. " MULT ,Multiplier factor" "1,2,4,?..."
|
|
bitfld.byte 0x00 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921"
|
|
line.byte 0x01 "C1,I2C1 Control Register 1"
|
|
bitfld.byte 0x01 7. " IICEN ,IIC1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " IICIE ,IIC1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " MST ,Master mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " TX ,Transmit mode select" "Receive,Transmit"
|
|
bitfld.byte 0x01 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged"
|
|
bitfld.byte 0x01 2. " RSTA ,Repeat START" "No effect,Start"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " WUEN ,Wakeup enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
line.byte 0x02 "S,I2C1 Status Register"
|
|
rbitfld.byte 0x02 7. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
bitfld.byte 0x02 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed"
|
|
rbitfld.byte 0x02 5. " BUSY ,Bus busy" "Idle,Busy"
|
|
textline " "
|
|
eventfld.byte 0x02 4. " ARBL ,Arbitration lost" "Not lost,Lost"
|
|
bitfld.byte 0x02 3. " RAM ,Range address match" "Not matched,Matched"
|
|
rbitfld.byte 0x02 2. " SRW ,Slave read/write" "Write,Read"
|
|
textline " "
|
|
eventfld.byte 0x02 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x02 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged"
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "D,I2C1 Data I/O Register"
|
|
in
|
|
if (((per.b(ad:0x40067000+0x05)&0x40)==0x40)&&(((per.b(ad:0x40067000+0x03))&0x40)==0x40))
|
|
group.byte 0x05++0x0
|
|
line.byte 0x00 "C2,I2C1 Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master,Independent"
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
hexmask.byte 0x00 0.--2. 1. " AD[10:8] ,Slave address bits [10:8]"
|
|
else
|
|
group.byte 0x05++0x0
|
|
line.byte 0x00 "C2,I2C1 Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master,Independent"
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x06++0x5
|
|
line.byte 0x00 "FLT,I2C1 Programmable Input Glitch Filter Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
bitfld.byte 0x00 0.--4. " FLT ,I2C1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x00 7. " SHEN ,Stop Hold Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C1 bus stop detect flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " FLT ,I2C1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C1 bus stop detect flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "No start,Start"
|
|
bitfld.byte 0x00 0.--3. " FLT ,I2C1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.byte 0x01 "RA,I2C1 Range Address Register"
|
|
hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address"
|
|
line.byte 0x02 "SMB,I2C1 SMBus Control and Status Register"
|
|
bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " SIICAEN ,Second IIC1 address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock/64 freq,Bus clock freq"
|
|
eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred"
|
|
bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x03 "A2,I2C1 Address Register 2"
|
|
hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address"
|
|
line.byte 0x04 "SLTH,I2C1 SCL Low Timeout High Register"
|
|
line.byte 0x05 "SLTL,I2C1 SCL Low Timeout Low Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "S2,I2C1 Status Register 2"
|
|
bitfld.byte 0x00 2. " DFEN ,Double Buffer Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 1. " ERROR ,Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 0. " EMPTY ,Empty Flag" "Not empty,Empty"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW2?D*"))
|
|
tree.open "UART (Universal Asynchronous Receiver Transmitter)"
|
|
tree "Module 0"
|
|
base ad:0x4006A000
|
|
width 17.
|
|
tree "UART 0 Standard Features Registers"
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART0_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("MKW01Z128*"))
|
|
newline
|
|
bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART0_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x02 6. " DOZEEN ,Doze enable" "Enabled in wait mode,Disabled in wait mode"
|
|
else
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. Loop-back,Single-wire UART"
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.byte 0x02 2. " ILT ,Idle line type select" "After started bit,After stopped bit"
|
|
bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd"
|
|
line.byte 0x03 "UART0_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up"
|
|
bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break"
|
|
sif (cpuis("MKW01Z128*"))
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
rbitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
newline
|
|
in
|
|
newline
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
endif
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (Detected at lenght of)" "Disabled,11/12 bit times"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
line.byte 0x01 "UART0_C3,UART Control Register 3"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x01 7. " R8T9 ,Received bit 8/transmit bit 9" "No RX/TX,RX/TX"
|
|
bitfld.byte 0x01 6. " R9T8 ,Transmit bit 8" "No TX/RX,TX/RX"
|
|
else
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in Single-Wire mode" "Input,Output"
|
|
bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "UART0_D,UART Data Register"
|
|
newline
|
|
in
|
|
newline
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "UART0_MA1,UART Match Address Registers 1"
|
|
line.byte 0x01 "UART0_MA2,UART Match Address Registers 2"
|
|
line.byte 0x02 "UART0_C4,UART Control Register 4"
|
|
bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x02 0.--4. " OSR ,Over sampling ratio" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
else
|
|
bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
endif
|
|
line.byte 0x03 "UART0_C5,UART Control Register 5"
|
|
bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
sif (cpuis("MKW01Z128*"))
|
|
newline
|
|
bitfld.byte 0x03 1. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "UART0_ED,UART Extended Data Register"
|
|
bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise"
|
|
bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error"
|
|
group.byte 0x0D++0x01
|
|
line.byte 0x00 "UART0_MODEM,UART Modem Register"
|
|
bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg Fifo>=rwfifo(Rxwater)/num of char in RCV data reg Fifo<=rwfifo(Rxwater))" "No effect,Deasserted/asserted"
|
|
bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (Char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/deasserted"
|
|
newline
|
|
bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.byte 0x01 "UART0_IR,UART Infrared Register"
|
|
bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4"
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("MKW01Z128*"))
|
|
tree "UART 0 FIFO Registers"
|
|
sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
if (((per.b(ad:0x4006A000+0x03))&0x0C)==0x00)&&(((per.b(ad:0x4006A000+0x12))&0xC0)==0xC0)
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
else
|
|
rgroup.byte 0x10++0x02
|
|
line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
else
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
group.byte 0x11++0x01
|
|
line.byte 0x00 "UART0_CFIFO,UART FIFO Control Register"
|
|
bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed"
|
|
bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
newline
|
|
bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated"
|
|
line.byte 0x01 "UART0_SFIFO,UART FIFO Status Register"
|
|
rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty"
|
|
rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty"
|
|
newline
|
|
eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow"
|
|
eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow"
|
|
sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
if (((per.b(ad:0x4006A000+0x03))&0x08)==0x00)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark"
|
|
else
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark"
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark"
|
|
endif
|
|
else
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark"
|
|
endif
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "UART0_TCFIFO,UART FIFO Transmit Count"
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "UART0_RCFIFO,UART FIFO Receive Count"
|
|
tree.end
|
|
endif
|
|
width 19.
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART0_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART0_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART0_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006A000+0x18)&0x02)==0x02)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.b(ad:0x4006A000+0x18)&0x02)==0x02)
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
tree.end
|
|
else
|
|
sif ((cpu()!="MKV30F128VLH10")&&(cpu()!="MKV30F128VLF10")&&(cpu()!="MKV30F128VFM10")&&(cpu()!="MKV30F64VLH10")&&(cpu()!="MKV30F64VLF10")&&(cpu()!="MKV30F64VFM10")&&(!cpuis("MKW01Z128*")))
|
|
tree "UART 0 ISO7816 Registers"
|
|
if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00)
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART0_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x18++0x02
|
|
line.byte 0x00 "UART0_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x19++0x01
|
|
line.byte 0x00 "UART0_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D256VHA5R")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5"))
|
|
bitfld.byte 0x00 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.byte 0x00 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "UART0_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x01 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x01 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D256VHA5R")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5"))
|
|
eventfld.byte 0x01 3. " ADT ,ATR duration time interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.byte 0x01 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
newline
|
|
eventfld.byte 0x01 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D256VHA5R")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5"))
|
|
if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816,UART 7816 Wait Parameter Register"
|
|
else
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816,UART 7816 Wait Parameter Register"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x4006A000+0x18)&0x02)==0x00)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")
|
|
if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00)
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
else
|
|
rgroup.byte 0x1C++0x01
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
endif
|
|
else
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
endif
|
|
sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")
|
|
if ((((per.b(ad:0x4006A000+0x18)&0x02)==0x00))&&(((per.b(ad:0x4006A000+0x18)&0x08)==0x08)))
|
|
if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00)
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x00 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.byte 0x1E++0x00
|
|
line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif ((per.b(ad:0x4006A000+0x18)&0x02)==0x00)
|
|
if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00)
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.byte 0x1E++0x00
|
|
line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
hgroup.byte 0x1E++0x00
|
|
hide.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
endif
|
|
else
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x00 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.b(ad:0x4006A000+0x18)&0x02)==0x02)
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
width 19.
|
|
sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5")&&cpu()!="MKW21D256VHA5R")
|
|
if ((per.b(ad:0x4006A000+0x18)&0x02)==0x02)
|
|
if ((per.b(ad:0x4006A000+0x18)&0x1)==0x00)
|
|
hgroup.byte 0x3A++0x01
|
|
hide.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
hide.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
group.byte 0x3C++0x03
|
|
line.byte 0x00 "UART0_WP7816A_T1,UART 7816 Wait Parameter Register A"
|
|
line.byte 0x01 "UART0_WP7816B_T1,UART 7816 Wait Parameter Register B"
|
|
line.byte 0x02 "UART0_WGP7816_T1,UART 7816 Wait And Guard Parameter Register"
|
|
bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
hgroup.byte 0x3A++0x01
|
|
hide.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
hide.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
rgroup.byte 0x3C++0x03
|
|
line.byte 0x00 "UART0_WP7816A_T1,UART 7816 ATR Duration Timer Register A"
|
|
line.byte 0x01 "UART0_WP7816B_T1,UART 7816 ATR Duration Timer Register B"
|
|
line.byte 0x02 "UART0_WGP7816_T1,UART 7816 Wait And Guard Parameter Register"
|
|
bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x4006A000+0x18)&0x1)==0x00)
|
|
group.byte 0x3A++0x03
|
|
line.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
line.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
line.byte 0x02 "UART0_WP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
line.byte 0x03 "UART0_WP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
hgroup.byte 0x3E++0x01
|
|
hide.byte 0x00 "UART0_WGP7816_T1,UART 7816 Wait And Guard Parameter Register"
|
|
hide.byte 0x01 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
else
|
|
rgroup.byte 0x3A++0x03
|
|
line.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
line.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
line.byte 0x02 "UART0_WP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
line.byte 0x03 "UART0_WP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
hgroup.byte 0x3E++0x01
|
|
hide.byte 0x00 "UART0_WGP7816_T1,UART 7816 Wait And Guard Parameter Register"
|
|
hide.byte 0x01 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
endif
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Module 1"
|
|
base ad:0x4006B000
|
|
width 17.
|
|
tree "UART 1 Standard Features Registers"
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART1_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("MKW01Z128*"))
|
|
newline
|
|
bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART1_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x02 6. " DOZEEN ,Doze enable" "Enabled in wait mode,Disabled in wait mode"
|
|
else
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. Loop-back,Single-wire UART"
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.byte 0x02 2. " ILT ,Idle line type select" "After started bit,After stopped bit"
|
|
bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd"
|
|
line.byte 0x03 "UART1_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up"
|
|
bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break"
|
|
sif (cpuis("MKW01Z128*"))
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
rbitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
newline
|
|
in
|
|
newline
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
endif
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (Detected at lenght of)" "Disabled,11/12 bit times"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
line.byte 0x01 "UART1_C3,UART Control Register 3"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x01 7. " R8T9 ,Received bit 8/transmit bit 9" "No RX/TX,RX/TX"
|
|
bitfld.byte 0x01 6. " R9T8 ,Transmit bit 8" "No TX/RX,TX/RX"
|
|
else
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in Single-Wire mode" "Input,Output"
|
|
bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "UART1_D,UART Data Register"
|
|
newline
|
|
in
|
|
newline
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "UART1_MA1,UART Match Address Registers 1"
|
|
line.byte 0x01 "UART1_MA2,UART Match Address Registers 2"
|
|
line.byte 0x02 "UART1_C4,UART Control Register 4"
|
|
bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpuis("MKW01Z128*"))
|
|
else
|
|
bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
endif
|
|
line.byte 0x03 "UART1_C5,UART Control Register 5"
|
|
bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
sif (cpuis("MKW01Z128*"))
|
|
newline
|
|
bitfld.byte 0x03 1. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "UART1_ED,UART Extended Data Register"
|
|
bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise"
|
|
bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error"
|
|
group.byte 0x0D++0x01
|
|
line.byte 0x00 "UART1_MODEM,UART Modem Register"
|
|
bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg Fifo>=rwfifo(Rxwater)/num of char in RCV data reg Fifo<=rwfifo(Rxwater))" "No effect,Deasserted/asserted"
|
|
bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (Char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/deasserted"
|
|
newline
|
|
bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.byte 0x01 "UART1_IR,UART Infrared Register"
|
|
bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4"
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("MKW01Z128*"))
|
|
tree "UART 1 FIFO Registers"
|
|
sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
if (((per.b(ad:0x4006B000+0x03))&0x0C)==0x00)&&(((per.b(ad:0x4006B000+0x12))&0xC0)==0xC0)
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
else
|
|
rgroup.byte 0x10++0x02
|
|
line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
else
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
group.byte 0x11++0x01
|
|
line.byte 0x00 "UART1_CFIFO,UART FIFO Control Register"
|
|
bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed"
|
|
bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
newline
|
|
bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated"
|
|
line.byte 0x01 "UART1_SFIFO,UART FIFO Status Register"
|
|
rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty"
|
|
rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty"
|
|
newline
|
|
eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow"
|
|
eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow"
|
|
sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
if (((per.b(ad:0x4006B000+0x03))&0x08)==0x00)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark"
|
|
else
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark"
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark"
|
|
endif
|
|
else
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark"
|
|
endif
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "UART1_TCFIFO,UART FIFO Transmit Count"
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "UART1_RCFIFO,UART FIFO Receive Count"
|
|
tree.end
|
|
endif
|
|
width 19.
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART1_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART1_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART1_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006B000+0x18)&0x02)==0x02)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.b(ad:0x4006B000+0x18)&0x02)==0x02)
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
tree.end
|
|
else
|
|
sif ((cpu()!="MKV30F128VLH10")&&(cpu()!="MKV30F128VLF10")&&(cpu()!="MKV30F128VFM10")&&(cpu()!="MKV30F64VLH10")&&(cpu()!="MKV30F64VLF10")&&(cpu()!="MKV30F64VFM10")&&(!cpuis("MKW01Z128*")))
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Module 2"
|
|
base ad:0x4006C000
|
|
width 17.
|
|
tree "UART 2 Standard Features Registers"
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART2_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("MKW01Z128*"))
|
|
newline
|
|
bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x02 6. " DOZEEN ,Doze enable" "Enabled in wait mode,Disabled in wait mode"
|
|
else
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. Loop-back,Single-wire UART"
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.byte 0x02 2. " ILT ,Idle line type select" "After started bit,After stopped bit"
|
|
bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd"
|
|
line.byte 0x03 "UART2_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up"
|
|
bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break"
|
|
sif (cpuis("MKW01Z128*"))
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
rbitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
newline
|
|
in
|
|
newline
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
endif
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (Detected at lenght of)" "Disabled,11/12 bit times"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
line.byte 0x01 "UART2_C3,UART Control Register 3"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.byte 0x01 7. " R8T9 ,Received bit 8/transmit bit 9" "No RX/TX,RX/TX"
|
|
bitfld.byte 0x01 6. " R9T8 ,Transmit bit 8" "No TX/RX,TX/RX"
|
|
else
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in Single-Wire mode" "Input,Output"
|
|
bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "UART2_D,UART Data Register"
|
|
newline
|
|
in
|
|
newline
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "UART2_MA1,UART Match Address Registers 1"
|
|
line.byte 0x01 "UART2_MA2,UART Match Address Registers 2"
|
|
line.byte 0x02 "UART2_C4,UART Control Register 4"
|
|
bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpuis("MKW01Z128*"))
|
|
else
|
|
bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
endif
|
|
line.byte 0x03 "UART2_C5,UART Control Register 5"
|
|
bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
sif (cpuis("MKW01Z128*"))
|
|
newline
|
|
bitfld.byte 0x03 1. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
endif
|
|
sif (!cpuis("MKW01Z128*"))
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "UART2_ED,UART Extended Data Register"
|
|
bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise"
|
|
bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error"
|
|
group.byte 0x0D++0x01
|
|
line.byte 0x00 "UART2_MODEM,UART Modem Register"
|
|
bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg Fifo>=rwfifo(Rxwater)/num of char in RCV data reg Fifo<=rwfifo(Rxwater))" "No effect,Deasserted/asserted"
|
|
bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (Char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/deasserted"
|
|
newline
|
|
bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.byte 0x01 "UART2_IR,UART Infrared Register"
|
|
bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4"
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("MKW01Z128*"))
|
|
tree "UART 2 FIFO Registers"
|
|
sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
if (((per.b(ad:0x4006C000+0x03))&0x0C)==0x00)&&(((per.b(ad:0x4006C000+0x12))&0xC0)==0xC0)
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
else
|
|
rgroup.byte 0x10++0x02
|
|
line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
else
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
newline
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
group.byte 0x11++0x01
|
|
line.byte 0x00 "UART2_CFIFO,UART FIFO Control Register"
|
|
bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed"
|
|
bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
newline
|
|
bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated"
|
|
line.byte 0x01 "UART2_SFIFO,UART FIFO Status Register"
|
|
rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty"
|
|
rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty"
|
|
newline
|
|
eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow"
|
|
eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow"
|
|
sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")
|
|
if (((per.b(ad:0x4006C000+0x03))&0x08)==0x00)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark"
|
|
else
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark"
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark"
|
|
endif
|
|
else
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark"
|
|
endif
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "UART2_TCFIFO,UART FIFO Transmit Count"
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "UART2_RCFIFO,UART FIFO Receive Count"
|
|
tree.end
|
|
endif
|
|
width 19.
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART2_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART2_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART2_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006C000+0x18)&0x02)==0x02)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART2_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART2_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART2_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART2_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART2_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.b(ad:0x4006C000+0x18)&0x02)==0x02)
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
tree.end
|
|
else
|
|
sif ((cpu()!="MKV30F128VLH10")&&(cpu()!="MKV30F128VLF10")&&(cpu()!="MKV30F128VFM10")&&(cpu()!="MKV30F64VLH10")&&(cpu()!="MKV30F64VLF10")&&(cpu()!="MKV30F64VFM10")&&(!cpuis("MKW01Z128*")))
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
tree "UART0 (Universal Asynchronous Receiver Transmitter)"
|
|
base ad:0x40054000
|
|
width 11.
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
if ((((per.l(ad:0x40054000))&0x800000)==0x000000)&&(((per.l(ad:0x40054000))&0x200000)==0x000000))
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "BAUD,LPUART0 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "Supported,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--12. 0x01 " SBR ,Baud rate modulo divisor"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "BAUD,LPUART0 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic"
|
|
rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "Supported,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--12. 0x01 " SBR ,Baud rate modulo divisor"
|
|
endif
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "BAUD,LPUART0 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "Supported,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--12. 0x01 " SBR ,Baud rate modulo divisor"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "STAT,LPUART0 Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
sif (!cpuis("MKW40Z*")&&!cpuis("MKW30Z*")&&!cpuis("MKW20Z*"))
|
|
textline " "
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
sif (cpuis("MKW*"))
|
|
if ((per.b(ad:0x40054000+0x08)&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x40054000+0x08)&0x20)==0x20)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "DATA,LPUART0 Data Register"
|
|
rbitfld.long 0x00 15. " NOISY ,DATA[R9:R0] received with noise" "No,Yes"
|
|
rbitfld.long 0x00 14. " PARITYE ,DATA[R9:R0] was received with a parity error" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
rbitfld.long 0x00 13. " FRETSC ,Frame error / transmit special character" "No error/normal char,Error/idle char"
|
|
else
|
|
bitfld.long 0x00 13. " FRETSC ,Frame error / transmit special character" "No error/normal char,Error/idle char"
|
|
rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Valid data,Not data"
|
|
rbitfld.long 0x00 11. " IDLINE ,Idle line" "Not idle,Idle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High"
|
|
bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High"
|
|
bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High"
|
|
bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High"
|
|
bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High"
|
|
bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High"
|
|
bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High"
|
|
line.long 0x04 "MATCH,LPUART0 Match Address Register"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
hexmask.long.byte 0x04 16.--23. 0x01 " MA2 ,Match address 2"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " MA1 ,Match address 1"
|
|
else
|
|
hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2"
|
|
hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1"
|
|
endif
|
|
line.long 0x08 "MODIR,LPUART0 Modem Irda Register"
|
|
bitfld.long 0x08 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
sif (!cpuis("MKW40Z*")&&!cpuis("MKW30Z*")&&!cpuis("MKW20Z*"))
|
|
textline " "
|
|
bitfld.long 0x08 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted receiver match"
|
|
bitfld.long 0x08 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
tree "LPUART0 (Low Power Universal Asynchronous Receiver Transmitter)"
|
|
base ad:0x40054000
|
|
width 11.
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
if ((((per.l(ad:0x40054000))&0x800000)==0x000000)&&(((per.l(ad:0x40054000))&0x200000)==0x000000))
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "BAUD,LPUART0 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "Supported,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--12. 0x01 " SBR ,Baud rate modulo divisor"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "BAUD,LPUART0 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic"
|
|
rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "Supported,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--12. 0x01 " SBR ,Baud rate modulo divisor"
|
|
endif
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "BAUD,LPUART0 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "Supported,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--12. 0x01 " SBR ,Baud rate modulo divisor"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "STAT,LPUART0 Status Register"
|
|
eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x00 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
sif (!cpuis("MKW40Z*")&&!cpuis("MKW30Z*")&&!cpuis("MKW20Z*"))
|
|
textline " "
|
|
eventfld.long 0x00 15. " MA1F ,Match 1 flag" "No match,Match"
|
|
eventfld.long 0x00 14. " MA2F ,Match 2 flag" "No match,Match"
|
|
endif
|
|
sif (cpuis("MKW*"))
|
|
if ((per.b(ad:0x40054000+0x08)&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x40054000+0x08)&0x20)==0x20)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "DATA,LPUART0 Data Register"
|
|
rbitfld.long 0x00 15. " NOISY ,DATA[R9:R0] received with noise" "No,Yes"
|
|
rbitfld.long 0x00 14. " PARITYE ,DATA[R9:R0] was received with a parity error" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
rbitfld.long 0x00 13. " FRETSC ,Frame error / transmit special character" "No error/normal char,Error/idle char"
|
|
else
|
|
bitfld.long 0x00 13. " FRETSC ,Frame error / transmit special character" "No error/normal char,Error/idle char"
|
|
rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Valid data,Not data"
|
|
rbitfld.long 0x00 11. " IDLINE ,Idle line" "Not idle,Idle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High"
|
|
bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High"
|
|
bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High"
|
|
bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High"
|
|
bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High"
|
|
bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High"
|
|
bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High"
|
|
line.long 0x04 "MATCH,LPUART0 Match Address Register"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
hexmask.long.byte 0x04 16.--23. 0x01 " MA2 ,Match address 2"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " MA1 ,Match address 1"
|
|
else
|
|
hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2"
|
|
hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1"
|
|
endif
|
|
line.long 0x08 "MODIR,LPUART0 Modem Irda Register"
|
|
bitfld.long 0x08 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
sif (!cpuis("MKW40Z*")&&!cpuis("MKW30Z*")&&!cpuis("MKW20Z*"))
|
|
textline " "
|
|
bitfld.long 0x08 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted receiver match"
|
|
bitfld.long 0x08 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
tree "I2S (Integrated Interchip Sound)"
|
|
base ad:0x4002F000
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "I2S0_TCSR,SAI Transmit Control Register"
|
|
bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started"
|
|
eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error"
|
|
rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached"
|
|
bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2S0_TCR1,SAI Transmit Configuration 1 Register"
|
|
bitfld.long 0x04 0.--2. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
if (((per.l(ad:0x4002F000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x0F
|
|
line.long 0x00 "I2S0_TCR2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock"
|
|
bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master clock 1,Master clock 2,Master clock 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
line.long 0x04 "I2S0_TCR3,SAI Transmit Configuration 3 Register"
|
|
bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "I2S0_TCR4,SAI Transmit Configuration 4 Register"
|
|
bitfld.long 0x08 16.--19. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit,Bfr. first bit"
|
|
textline " "
|
|
bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x08 0. " FSD ,Frame sync direction" "External,Internal"
|
|
line.long 0x0C "I2S0_TCR5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x0C 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "I2S0_TCR2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock"
|
|
bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master clock 1,Master clock 2,Master clock 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
line.long 0x04 "I2S0_TCR3,SAI Transmit Configuration 3 Register"
|
|
bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "I2S0_TCR4,SAI Transmit Configuration 4 Register"
|
|
bitfld.long 0x08 16.--19. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit,Bfr. First bit"
|
|
textline " "
|
|
bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x08 0. " FSD ,Frame sync direction" "External,Internal"
|
|
line.long 0x0C "I2S0_TCR5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x0C 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
else
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "I2S0_TCR2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock"
|
|
bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master clock 1,Master clock 2,Master clock 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
line.long 0x04 "I2S0_TCR3,SAI Transmit Configuration 3 Register"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
bitfld.long 0x04 24.--25. " CFR ,Channel FIFO reset" "No effect,Reset,?..."
|
|
bitfld.long 0x04 16.--17. " TCE ,Transmit channel enable" "0,1,2,3"
|
|
bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.long 0x04 16.--17. " TCE ,Transmit channel enable" "0,1,2,3"
|
|
bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
line.long 0x08 "I2S0_TCR4,SAI Transmit Configuration 4 Register"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "No set,Set"
|
|
bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,Enabled reads,Enabled writes,Both"
|
|
bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (cpuis("MKW21D256VHA5R"))
|
|
bitfld.long 0x08 16.--19. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit,Bfr. First bit"
|
|
textline " "
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
bitfld.long 0x08 2. " ONDEM ,On demand mode" "No effect,Clear flag"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x08 0. " FSD ,Frame sync direction" "External,Internal"
|
|
line.long 0x0C "I2S0_TCR5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x0C 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "I2S0_TDR0,SAI Transmit Data 0 Register"
|
|
else
|
|
wgroup.long 0x20++0x07
|
|
line.long 0x00 "I2S0_TDR0,SAI Transmit Data 0 Register"
|
|
line.long 0x04 "I2S0_TDR1,SAI Transmit Data 1 Register"
|
|
endif
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "I2S0_TFR0,SAI Transmit FIFO 0 Register"
|
|
bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "I2S0_TFR0,SAI Transmit FIFO 0 Register"
|
|
bitfld.long 0x00 31. " WCP ,Write channel pointer" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "I2S0_TFR1,SAI Transmit FIFO 1 Register"
|
|
bitfld.long 0x04 31. " WCP ,Write channel pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "I2S0_TFR0,SAI Transmit FIFO 0 Register"
|
|
bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "I2S0_TFR1,SAI Transmit FIFO 1 Register"
|
|
bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2S0_TMR,SAI Transmit Mask Register"
|
|
sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5")&&(cpu()!="MKW21D256VHA5R"))
|
|
bitfld.long 0x00 31. " TWM[31] ,Mask bit[31]" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " TWM[30] ,Mask bit[30]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " TWM[29] ,Mask bit[29]" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " TWM[28] ,Mask bit[28]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " TWM[27] ,Mask bit[27]" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " TWM[26] ,Mask bit[26]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TWM[25] ,Mask bit[25]" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " TWM[24] ,Mask bit[24]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TWM[23] ,Mask bit[23]" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " TWM[22] ,Mask bit[22]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TWM[21] ,Mask bit[21]" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " TWM[20] ,Mask bit[20]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TWM[19] ,Mask bit[19]" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " TWM[18] ,Mask bit[18]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TWM[17] ,Mask bit[17]" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " TWM[16] ,Mask bit[16]" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " TWM[15] ,Mask bit[15]" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " TWM[14] ,Mask bit[14]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TWM[13] ,Mask bit[13]" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " TWM[12] ,Mask bit[12]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TWM[11] ,Mask bit[11]" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " TWM[10] ,Mask bit[10]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TWM[9] ,Mask bit[9]" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " TWM[8] ,Mask bit[8]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TWM[7] ,Mask bit[7]" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " TWM[6] ,Mask bit[6]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TWM[5] ,Mask bit[5]" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TWM[4] ,Mask bit[4]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TWM[3] ,Mask bit[3]" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " TWM[2] ,Mask bit[2]" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TWM[1] ,Mask bit[1]" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TWM[0] ,Mask bit[0]" "Not masked,Masked"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "I2S0_RCSR,SAI Receive Control Register"
|
|
bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started"
|
|
eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error"
|
|
rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached"
|
|
bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2S0_RCR1,SAI Receive Configuration 1 Register"
|
|
bitfld.long 0x04 0.--2. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7"
|
|
sif ((cpu()=="MKW21D256VHA5")||(cpu()=="MKW21D512VHA5")||(cpu()=="MKW22D512VHA5")||(cpu()=="MKW24D512VHA5")||(cpu()=="MKW21D256VHA5R"))
|
|
if (((per.l(ad:0x4002F000+0x80))&0x80000000)==0x80000000)
|
|
rgroup.long 0x88++0x0F
|
|
line.long 0x00 "I2S0_RCR2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock"
|
|
bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master clock 1,Master clock 2,Master clock 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
line.long 0x04 "I2S0_RCR3,SAI Receive Configuration 3 Register"
|
|
bitfld.long 0x04 16. " RCE ,Receive channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "I2S0_RCR4,SAI Receive Configuration 4 Register"
|
|
bitfld.long 0x08 16.--19. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB"
|
|
bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame"
|
|
textline " "
|
|
bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x08 0. " FSD ,Frame sync direction" "External,Internal"
|
|
line.long 0x0C "I2S0_RCR5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x0C 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "I2S0_RCR2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock"
|
|
bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master clock 1,Master clock 2,Master clock 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
line.long 0x04 "I2S0_RCR3,SAI Receive Configuration 3 Register"
|
|
bitfld.long 0x04 16. " RCE ,Receive channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "I2S0_RCR4,SAI Receive Configuration 4 Register"
|
|
bitfld.long 0x08 16.--19. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB"
|
|
bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame"
|
|
textline " "
|
|
bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x08 0. " FSD ,Frame sync direction" "External,Internal"
|
|
line.long 0x0C "I2S0_RCR5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x0C 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
else
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "I2S0_RCR2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock"
|
|
bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master clock 1,Master clock 2,Master clock 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
line.long 0x04 "I2S0_RCR3,SAI Receive Configuration 3 Register"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
bitfld.long 0x04 24.--25. " CFR ,Channel FIFO reset" "No effect,Reset,?..."
|
|
bitfld.long 0x04 16.--17. " RCE ,Receive channel enable" "Disabled,,,Enabled"
|
|
bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.long 0x04 16.--17. " RCE ,Receive channel enable" "Disabled,,,Enabled"
|
|
bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
line.long 0x08 "I2S0_RCR4,SAI Receive Configuration 4 Register"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
bitfld.long 0x08 28. " FCONT ,FIFO continue on error" "No set,Set"
|
|
bitfld.long 0x08 26.--27. " FCOMB ,FIFO combine mode" "Disabled,Enabled reads,Enabled writes,Both"
|
|
bitfld.long 0x08 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB"
|
|
bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame"
|
|
sif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
bitfld.long 0x08 2. " ONDEM ,On demand mode" "No effect,Clear flag"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x08 0. " FSD ,Frame sync direction" "External,Internal"
|
|
line.long 0x0C "I2S0_RCR5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x0C 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif ((cpu()=="MKW21D256VHA5")||(cpu()=="MKW21D512VHA5")||(cpu()=="MKW22D512VHA5")||(cpu()=="MKW24D512VHA5")||(cpu()=="MKW21D256VHA5R"))
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "I2S0_RDR0,SAI Receive Data 0 Register"
|
|
else
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "I2S0_RDR0,SAI Receive Data 0 Register"
|
|
line.long 0x04 "I2S0_RDR1,SAI Receive Data 1 Register"
|
|
endif
|
|
sif ((cpu()=="MKW21D256VHA5")||(cpu()=="MKW21D512VHA5")||(cpu()=="MKW22D512VHA5")||(cpu()=="MKW24D512VHA5")||(cpu()=="MKW21D256VHA5R"))
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "I2S0_RFR0,SAI Receive FIFO 0 Register"
|
|
bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")
|
|
rgroup.long 0xC0++0x07
|
|
line.long 0x00 "I2S0_RFR0,SAI Receive FIFO 0 Register"
|
|
bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " WCP ,Receive channel pointer" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "I2S0_RFR1,SAI Receive FIFO 1 Register"
|
|
bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 15. " WCP ,Receive channel pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0xC0++0x07
|
|
line.long 0x00 "I2S0_RFR0,SAI Receive FIFO 0 Register"
|
|
bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "I2S0_RFR1,SAI Receive FIFO 1 Register"
|
|
bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "I2S0_RMR,SAI Receive Mask Register"
|
|
sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5")&&(cpu()!="MKW21D256VHA5R"))
|
|
bitfld.long 0x00 31. " RWM31 ,Receive word mask bit 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " RWM30 ,Receive word mask bit 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " RWM29 ,Receive word mask bit 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RWM28 ,Receive word mask bit 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " RWM27 ,Receive word mask bit 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " RWM6 ,Receive word mask bit 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RWM25 ,Receive word mask bit 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " RWM24 ,Receive word mask bit 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " RWM23 ,Receive word mask bit 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RWM22 ,Receive word mask bit 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " RWM21 ,Receive word mask bit 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " RWM20 ,Receive word mask bit 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RWM19 ,Receive word mask bit 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " RWM18 ,Receive word mask bit 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " RWM17 ,Receive word mask bit 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RWM16 ,Receive word mask bit 16" "Not masked,Masked"
|
|
endif
|
|
bitfld.long 0x00 15. " RWM15 ,Receive word mask bit 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " RWM14 ,Receive word mask bit 14" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " RWM13 ,Receive word mask bit 13" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RWM12 ,Receive word mask bit 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " RWM11 ,Receive word mask bit 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " RWM10 ,Receive word mask bit 10" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RWM9 ,Receive word mask bit 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " RWM8 ,Receive word mask bit 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " RWM7 ,Receive word mask bit 7" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RWM6 ,Receive word mask bit 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " RWM5 ,Receive word mask bit 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " RWM4 ,Receive word mask bit 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RWM3 ,Receive word mask bit 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " RWM2 ,Receive word mask bit 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " RWM1 ,Receive word mask bit 1" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RWM0 ,Receive word mask bit 0" "Not masked,Masked"
|
|
textline " "
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "I2S0_MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updated,Updated"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "MCLK divider input clock 0,MCLK divider input clock 1,MCLK divider input clock 2,MCLK divider input clock 3"
|
|
line.long 0x04 "I2S0_MDR,SAI MCLK Divide Register"
|
|
hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "GPIO (General Purpose Input/Output)"
|
|
tree "GPIOA"
|
|
base ad:0x400FF000
|
|
width 20.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOA_PDOR_SET/CLR,Port A Data Output Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO20 ,Port data output 20" "Logic 0,Logic 1"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port data output 19" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port data output 18" "Logic 0,Logic 1"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW2?D*")||cpuis("MKW01Z128*"))
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1"
|
|
textline " "
|
|
elif (cpuis("MKW4?D*")||cpuis("MKW4?Z*")||cpuis("MKW31Z*")||cpuis("MKW2?Z*"))
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port data output 17" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port data output 16" "Logic 0,Logic 1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIOA_PTOR,Port A Toggle Output Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 20. " PTTO20 ,Port toggle output 20" "No effect,Invert"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
bitfld.long 0x00 19. " PTTO19 ,Port toggle output 19" "No effect,Invert"
|
|
bitfld.long 0x00 18. " PTTO18 ,Port toggle output 18" "No effect,Invert"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW2?D*"))
|
|
bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No effect,Invert"
|
|
bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No effect,Invert"
|
|
textline " "
|
|
elif (cpuis("MKW4?D*")||cpuis("MKW4?Z*")||cpuis("MKW31Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 17. " PTTO17 ,Port toggle output 17" "No effect,Invert"
|
|
bitfld.long 0x00 16. " PTTO16 ,Port toggle output 16" "No effect,Invert"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No effect,Invert"
|
|
bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No effect,Invert"
|
|
bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No effect,Invert"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_PDIR,Port A Data Input Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 20. " PDI20 ,Port data input 20" "Logic 0,Logic 1"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
bitfld.long 0x00 19. " PDI19 ,Port data input 19" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 18. " PDI18 ,Port data input 18" "Logic 0,Logic 1"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW2?D*")||cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1"
|
|
textline " "
|
|
elif (cpuis("MKW4?D*")||cpuis("MKW4?Z*")||cpuis("MKW31Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 17. " PDI17 ,Port data input 17" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 16. " PDI16 ,Port data input 16" "Logic 0,Logic 1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_PDDR,Port A Data Direction Register"
|
|
sif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 20. " PDD20 ,Port data direction 20" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
bitfld.long 0x00 19. " PDD19 ,Port data direction 19" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD18 ,Port data direction 18" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW2?D*")||cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output"
|
|
textline " "
|
|
elif (cpuis("MKW4?D*")||cpuis("MKW4?Z*")||cpuis("MKW31Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 17. " PDD17 ,Port data direction 17" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD16 ,Port data direction 16" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*"))
|
|
tree "GPIOB"
|
|
base ad:0x400FF040
|
|
width 20.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOB_PDOR_SET/CLR,Port B Data Output Register"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1"
|
|
sif (!cpuis("MKW30Z*"))
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1"
|
|
endif
|
|
else
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIOA_PTOR,Port B Toggle Output Register"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No effect,Invert"
|
|
bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No effect,Invert"
|
|
bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No effect,Invert"
|
|
sif (!cpuis("MKW30Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No effect,Invert"
|
|
bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No effect,Invert"
|
|
bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No effect,Invert"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No effect,Invert"
|
|
bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No effect,Invert"
|
|
bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No effect,Invert"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_PDIR,Port B Data Input Register"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1"
|
|
sif (!cpuis("MKW30Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_PDDR,Port B Data Direction Register"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output"
|
|
sif (!cpuis("MKW30Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIOC"
|
|
base ad:0x400FF080
|
|
width 20.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOC_PDOR_SET/CLR,Port C Data Output Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1"
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO7 ,Port Data Output 7" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port Data Output 6" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port Data Output 5" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port Data Output 4" "Logic 0,Logic 1"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*"))
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1"
|
|
endif
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIOC_PTOR,Port C Toggle Output Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No effect,Invert"
|
|
bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No effect,Invert"
|
|
bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No effect,Invert"
|
|
bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No effect,Invert"
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " PTTO7 ,Port Toggle Output 7" "No effect,Invert"
|
|
bitfld.long 0x00 6. " PTTO6 ,Port Toggle Output 6" "No effect,Invert"
|
|
bitfld.long 0x00 5. " PTTO5 ,Port Toggle Output 5" "No effect,Invert"
|
|
bitfld.long 0x00 4. " PTTO4 ,Port Toggle Output 4" "No effect,Invert"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No effect,Invert"
|
|
bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No effect,Invert"
|
|
bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No effect,Invert"
|
|
endif
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No effect,Invert"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_PDIR,Port C Data Input Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 19. " PDI19 ,Port Set Output 19" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1"
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " PDI7 ,Port Data Input 7" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 6. " PDI6 ,Port Data Input 6" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 5. " PDI5 ,Port Data Input 5" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1"
|
|
endif
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_PDDR,Port C Data Direction Register"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output"
|
|
endif
|
|
sif (!cpuis("MKW30Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " PDD7 ,Port Data Direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD6 ,Port Data Direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD5 ,Port Data Direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD4 ,Port Data Direction 4" "Input,Output"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output"
|
|
endif
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*"))
|
|
tree "GPIOD"
|
|
base ad:0x400FF0C0
|
|
width 20.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOD_PDOR_SET/CLR,Port D Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO7 ,Port Data Output 7" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port Data Output 6" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port Data Output 5" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port Data Output 4" "Logic 0,Logic 1"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIOD_PTOR,Port D Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO7 ,Port Toggle Output 7" "No effect,Invert"
|
|
bitfld.long 0x00 6. " PTTO6 ,Port Toggle Output 6" "No effect,Invert"
|
|
bitfld.long 0x00 5. " PTTO5 ,Port Toggle Output 5" "No effect,Invert"
|
|
bitfld.long 0x00 4. " PTTO4 ,Port Toggle Output 4" "No effect,Invert"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No effect,Invert"
|
|
bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No effect,Invert"
|
|
bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No effect,Invert"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No effect,Invert"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_PDIR,Port D Data Input Register"
|
|
bitfld.long 0x00 7. " PDI7 ,Port Data Input 7" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 6. " PDI6 ,Port Data Input 6" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 5. " PDI5 ,Port Data Input 5" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 0"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_PDDR,Port D Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD7 ,Port Data Direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD6 ,Port Data Direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD5 ,Port Data Direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD4 ,Port Data Direction 4" "Input,Output"
|
|
sif (!cpuis("MKW01Z128*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIOE"
|
|
base ad:0x400FF100
|
|
width 20.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOE_PDOR_SET/CLR,Port E Data Output Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port Data Output 4" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1"
|
|
elif (cpuis("MKW01Z128*"))
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO30 ,Port Data Output 30" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1"
|
|
else
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port Data Output 4" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIOE_PTOR,Port E Toggle Output Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No effect,Invert"
|
|
bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No effect,Invert"
|
|
bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No effect,Invert"
|
|
bitfld.long 0x00 4. " PTTO4 ,Port Toggle Output 4" "No effect,Invert"
|
|
bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No effect,Invert"
|
|
bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No effect,Invert"
|
|
bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No effect,Invert"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 30. " PTTO30 ,Port Toggle Output 30" "No effect,Invert"
|
|
bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No effect,Invert"
|
|
bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No effect,Invert"
|
|
bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No effect,Invert"
|
|
bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No effect,Invert"
|
|
bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No effect,Invert"
|
|
bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No effect,Invert"
|
|
else
|
|
bitfld.long 0x00 4. " PTTO4 ,Port Toggle Output 4" "No effect,Invert"
|
|
bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No effect,Invert"
|
|
bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No effect,Invert"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No effect,Invert"
|
|
bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No effect,Invert"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOE_PDIR,Port E Data Input Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 30. " PDI30 ,Port Data Input 30" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1"
|
|
else
|
|
bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1"
|
|
bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOE_PDDR,Port E Data Direction Register"
|
|
sif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW21D256VHA5R"))
|
|
bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD4 ,Port Data Direction 4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output"
|
|
elif (cpuis("MKW01Z128*"))
|
|
bitfld.long 0x00 30. " PDD30 ,Port Data Direction 30" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 4. " PDD4 ,Port Data Direction 4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
tree "TSI (Touch Sensing Input)"
|
|
base ad:0x40045000
|
|
width 14.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TSI0_GENCS,TSI General Control And Status Register"
|
|
eventfld.long 0x00 31. " OUTRGF ,Out of range flag" "No,Yes"
|
|
bitfld.long 0x00 28. " ESOR ,End-of-scan or out-of-range interrupt selection" "Out-of-range,End-of-scan"
|
|
bitfld.long 0x00 24.--27. " MODE ,TSI analog modes setup and status bits" "Sensed capacitive,,,,Detected single threshold noise & disabled frequency limitation circuit,,,,Detected single threshold noise & enabled frequency limitation circuit,,,,Automatic noise detected,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " REFCHRG ,Reference oscillator charge and discharge current value" "500nA,1uA,2uA,4uA,8uA,16uA,32uA,64uA"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 19.--20. " DVOLT ,Oscillator's voltage rails (Dv/Vp/Vm)" "1.03V/1.33V/0.30V,0.59V/1.11V/0.45V,0.43V/1.03V/0.60V,0.29V/0.95V/0.67V"
|
|
else
|
|
bitfld.long 0x00 19.--20. " DVOLT ,Oscillator's voltage rails (Dv/Vp/Vm)" "1.03V/1.33V/0.30V,0.73V/1.18V/0.45V,0.43V/1.03V/0.60V,0.29V/0.95V/0.67V"
|
|
endif
|
|
bitfld.long 0x00 16.--18. " EXTCHRG ,Electrode oscillator charge and discharge current value" "500nA,1uA,2uA,4uA,8uA,16uA,32uA,64uA"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " PS ,Prescaler of the output of electrode oscillator" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x00 8.--12. " NSCN ,Scan number for each electrode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TSIIEN ,Touch sensing input interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STPE ,TSI STOP enable" "Disabled,Running"
|
|
bitfld.long 0x00 4. " STM ,Scan trigger mode" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCNIP ,Scan in progress status" "No,Yes"
|
|
eventfld.long 0x00 2. " EOSF ,End of scan flag" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " CURSW ,Swaps current sources of electrode oscillator and reference oscillator" "Not swapped,Swapped"
|
|
sif (!cpuis("MKW01Z128*")&&!cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOSDMEO ,End-of-Scan DMA transfer request enable only" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "TSI0_DATA,TSI DATA Register"
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 23. " DMAEN ,DMA transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SWTS ,Software trigger start" "No effect,Start"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TSICN ,TSI conversion counter value"
|
|
line.long 0x08 "TSI0_TSHD,TSI Threshold Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " THRESH ,TSI wakeup channel high-threshold"
|
|
hexmask.long.word 0x08 0.--15. 1. " THRESL ,TSI wakeup channel low-threshold"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
tree "LTC (LP Trusted Cryptography)"
|
|
base ad:0x40058000
|
|
width 14.
|
|
if ((((per.l(ad:0x40058000))&0xFF0000)==0x100000)&&(((per.l(ad:0x40058000))&0x1FF0)==0x200))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LTC0_MD,LTC Mode"
|
|
bitfld.long 0x00 16.--23. " ALG ,Algorithm" ",,,,,,,,,,,,,,,,AES,?..."
|
|
hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional Algorithm information"
|
|
bitfld.long 0x00 2.--3. " AS ,Algorithm State" "Updated,Initialized,Finalized,Initialized/Finalized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICV_TEST ,ICV Checking" "Not Compared,Compared"
|
|
bitfld.long 0x00 0. " ENC ,Encrypt/Decrypt" "Decrypted,Encrypted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LTC0_MD,LTC Mode"
|
|
bitfld.long 0x00 16.--23. " ALG ,Algorithm" ",,,,,,,,,,,,,,,,AES,?..."
|
|
hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional Algorithm information"
|
|
bitfld.long 0x00 2.--3. " AS ,Algorithm State" "Updated,Initialized,Finalized,Initialized/Finalized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICV_TEST ,Test AES fault detection" "Not Injected,Injected"
|
|
bitfld.long 0x00 0. " ENC ,Encrypt/Decrypt" "Decrypted,Encrypted"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "LTC0_KS,LTC Key Size"
|
|
bitfld.long 0x00 0.--4. " KS ,Key Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LTC0_DS,LTC Data Size"
|
|
hexmask.long.word 0x00 0.--11. 1. " DS ,Data Size"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LTC0_ICVS,LTC ICV Size"
|
|
bitfld.long 0x00 0.--4. " ICVS ,ICV Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "LTC0_COM,LTC Command"
|
|
bitfld.long 0x00 1. " AES ,Reset AESA" "No effect,Reset"
|
|
bitfld.long 0x00 0. " ALL ,Reset All Internal Logic" "No effect,Reset"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "LTC0_CTL,LTC Control"
|
|
bitfld.long 0x00 31. " KAL ,Key Register Access Lock" "Not locked,Locked"
|
|
bitfld.long 0x00 23. " COS ,Context Register Output Byte Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 22. " CIS ,Context Register Input Byte Swap" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 21. " KOS ,Key Register Output Byte Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 20. " KIS ,Key Register Input Byte Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 17. " OFS ,Output FIFO Byte Swap" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IFS ,Input FIFO Byte Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 13. " OFR ,Output FIFO DMA Request Size" "1 Entry,4 Entries"
|
|
bitfld.long 0x00 12. " OFE ,Output FIFO DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IFR ,Input FIFO DMA Request Size" "1 Entry,4 Entries"
|
|
bitfld.long 0x00 8. " IFE ,Input FIFO DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IM ,Interrupt Mask" "Not masked,Masked"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "LTC0_CW,LTC Clear Written"
|
|
bitfld.long 0x00 31. " CIF ,Clear Input FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 30. " COF ,Clear Output FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CKR ,Clear the Key Register" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CCR ,Clear the Context Register" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CICV ,Clear the ICV Size Register" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CDS ,Clear the Data Size Register" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM ,Clear the Mode Register" "No effect,Clear"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "LTC0_STA,LTC Status"
|
|
rbitfld.long 0x00 20. " EI ,Error Interrupt" "Not error,Error"
|
|
eventfld.long 0x00 16. " DI ,Done Interrupt (Read/Write)" "No done/No effect,Done/Clear"
|
|
rbitfld.long 0x00 1. " AB ,AESA Busy" "Idle,Busy"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "LTC0_ESTA,LTC Error Status"
|
|
bitfld.long 0x00 8.--11. " CL1 ,algorithms" "LTC General Error,AES,?..."
|
|
bitfld.long 0x00 0.--3. " ERRID1 ,Error ID 1" ",Mode,Data size,Key size,,,Data arrived out of sequence,,,,ICV check failed,Internal hardware failure,CCM AAD size,,,Invalid crypto engine selected"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LTC0_AADSZ,LTC AAD Size"
|
|
bitfld.long 0x00 31. " AL ,AAD Last" "Not last,Last"
|
|
bitfld.long 0x00 0.--3. " AADSZ ,AAD size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "LTC0_CTX_0,LTC Context"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "LTC0_CTX_1,LTC Context"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "LTC0_CTX_2,LTC Context"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "LTC0_CTX_3,LTC Context"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "LTC0_CTX_4,LTC Context"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "LTC0_CTX_5,LTC Context"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "LTC0_CTX_6,LTC Context"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "LTC0_CTX_7,LTC Context"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "LTC0_CTX_8,LTC Context"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "LTC0_CTX_9,LTC Context"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "LTC0_CTX_10,LTC Context"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "LTC0_CTX_11,LTC Context"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "LTC0_CTX_12,LTC Context"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "LTC0_CTX_13,LTC Context"
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "LTC0_KEY_0,LTC Keys"
|
|
line.long 0x04 "LTC0_KEY_1,LTC Keys"
|
|
line.long 0x08 "LTC0_KEY_2,LTC Keys"
|
|
line.long 0x0C "LTC0_KEY_3,LTC Keys"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
rgroup.long 0x4F0++0x03
|
|
line.long 0x00 "LTC0_VID1,LTC Version ID"
|
|
hexmask.long.word 0x00 16.--31. 1. " IP_ID ,ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MAJ_REV ,Major revision number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MIN_REV ,Minor revision number"
|
|
endif
|
|
rgroup.long 0x4F4++0x03
|
|
line.long 0x00 "LTC0_VID2,LTC Version ID 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ARCH_ERA ,Architectural ERA"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ECO_REV ,ECO Revision Number"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
rgroup.long 0x4F8++0x03
|
|
line.long 0x00 "LTC0_CHAVID,LTC CHA Version ID"
|
|
bitfld.long 0x00 4.--7. " AESVID ,AES Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " AESREV ,AES Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x7C0++0x03
|
|
line.long 0x00 "LTC0_FIFOSTA,LTC FIFO Status"
|
|
bitfld.long 0x00 31. " OFF ,Output FIFO Full" "Not Full,Full"
|
|
hexmask.long.byte 0x00 16.--22. 1. " OFL ,Output FIFO Level"
|
|
bitfld.long 0x00 15. " IFF ,Input FIFO Full" "Not full,Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " IFL ,Input FIFO Level"
|
|
wgroup.long 0x7E0++0x03
|
|
line.long 0x00 "LTC0_IFIFO,LTC Input Data FIFO"
|
|
hgroup.long 0x7F0++0x03
|
|
hide.long 0x00 "LTC0_OFIFO,LTC Output Data FIFO"
|
|
in
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "LTC0_VID1,LTC Version ID"
|
|
hexmask.long.word 0x00 16.--31. 1. " IP_ID ,ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MAJ_REV ,Major revision number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MIN_REV ,Minor revision number"
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "LTC0_CHAVID,LTC CHA Version ID"
|
|
bitfld.long 0x00 4.--7. " AESVID ,AES Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " AESREV ,AES Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x40029000
|
|
width 12.
|
|
if (((per.l(ad:0x40029000))&0x10000)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,TRNG Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode"
|
|
rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running"
|
|
eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear"
|
|
newline
|
|
rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1"
|
|
rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed"
|
|
rbitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock"
|
|
rbitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value"
|
|
rbitfld.long 0x00 2.--3. " OSC_DIV ,Oscillator divide" "/1,/2,/4,/8"
|
|
rbitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,RNG TRNG Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode"
|
|
rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running"
|
|
eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear"
|
|
newline
|
|
rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1"
|
|
rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed"
|
|
bitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock"
|
|
bitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value"
|
|
bitfld.long 0x00 2.--3. " OSC_DIV ,Ring oscillator divide" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..."
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10000)==0x00)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "PKRRNG,TRNG Poker Range Register"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PKRSQ,TRNG Poker Square Calculation Result Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PKR_SQ ,Poker square calculation result"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SDCTL,TRNG Seed Control Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TOTSAM,Total Samples Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TOT_SAM ,Total samples"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "FRQMIN,TRNG Frequency Count Minimum Limit Register"
|
|
if (((per.l(ad:0x40029000))&0x20)==0x20)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "FRQCNT,TRNG Frequency Count Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_CNT ,Frequency count"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FRQCNT,TRNG Frequency Count Register"
|
|
endif
|
|
rgroup.long 0x20++0x1B
|
|
line.long 0x00 "SCMC,TRNG Statistical Check Monobit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MONO_CNT ,Monobit count"
|
|
line.long 0x04 "SCR1C,TRNG Statistical Check Run Length 1 Count Register"
|
|
hexmask.long.word 0x04 16.--30. 1. " R1_1_COUNT ,Runs of one (length 1 count)"
|
|
hexmask.long.word 0x04 0.--14. 1. " R1_0_COUNT ,Runs of zero (length 1 count)"
|
|
line.long 0x08 "SCR2C,TRNG Statistical Check Run Length 2 Count Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " R2_1_COUNT ,Runs of one (length 2 count)"
|
|
hexmask.long.word 0x08 0.--13. 1. " R2_0_COUNT ,Runs of zero (length 2 count)"
|
|
line.long 0x0C "SCR3C,TRNG Statistical Check Run Length 3 Count Register"
|
|
hexmask.long.word 0x0C 16.--28. 1. " R3_1_COUNT ,Runs of ones (length 3 count)"
|
|
hexmask.long.word 0x0C 0.--12. 1. " R3_0_COUNT ,Runs of zeroes (length 3 count)"
|
|
line.long 0x10 "SCR4C,TRNG Statistical Check Run Length 4 Count Register"
|
|
hexmask.long.word 0x10 16.--27. 1. " R4_1_COUNT ,Runs of one (length 4 count)"
|
|
hexmask.long.word 0x10 0.--11. 1. " R4_0_COUNT ,Runs of zero (length 4 count)"
|
|
line.long 0x14 "SCR5C,TRNG Statistical Check Run Length 5 Count Register"
|
|
hexmask.long.word 0x14 16.--26. 1. " R5_1_COUNT ,Runs of one (length 5 count)"
|
|
hexmask.long.word 0x14 0.--10. 1. " R5_0_COUNT ,Runs of zero (length 5 count)"
|
|
line.long 0x18 "SCR6PC,TRNG Statistical Check Run Length 6+ Count Register"
|
|
hexmask.long.word 0x18 16.--26. 1. " R6P_1_COUNT ,Runs of one (length 6+ count)"
|
|
hexmask.long.word 0x18 0.--10. 1. " R6P_0_COUNT ,Runs of zero (length 6+ count)"
|
|
else
|
|
group.long 0x04++0x37
|
|
line.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register"
|
|
bitfld.long 0x00 16.--19. " RTY_CNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LRUN_MAX ,Long run max limit"
|
|
line.long 0x04 "PKRRNG,TRNG Poker Range Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PKR_RNG ,Poker range"
|
|
line.long 0x08 "PKRMAX,TRNG Poker Maximum Limit Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PKR_MAX ,Poker maximum limit"
|
|
line.long 0x0C "SDCTL,TRNG Seed Control Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " ENT_DLY ,Entropy delay"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SAMP_SIZE ,Sample size"
|
|
line.long 0x10 "SBLIM,TRNG Sparse Bit Limit Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " SB_LIM ,Sparse bit limit"
|
|
line.long 0x14 "FRQMIN,TRNG Frequency Count Minimum Limit Register"
|
|
hexmask.long.tbyte 0x14 0.--21. 1. " FRQ_MIN ,Frequency Count minimum limit"
|
|
line.long 0x18 "FRQMAX,TRNG Frequency Count Maximum Limit Register"
|
|
hexmask.long.tbyte 0x18 0.--21. 1. " FRQ_MAX ,Frequency Counter maximum limit"
|
|
line.long 0x1C "SCML,TRNG Statistical Check Monobit Limit Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " MONO_RNG ,Monobit range"
|
|
hexmask.long.word 0x1C 0.--15. 1. " MONO_MAX ,Monobit maximum limit"
|
|
line.long 0x20 "SCR1L,TRNG Statistical Check Run Length 1 Limit Register"
|
|
hexmask.long.word 0x20 16.--30. 1. " RUN1_RNG ,Run length 1 range"
|
|
hexmask.long.word 0x20 0.--14. 1. " RUN1_MAX ,Run length 1 maximum limit"
|
|
line.long 0x24 "SCR2L,TRNG Statistical Check Run Length 2 Limit Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " RUN2_RNG ,Run length 2 range"
|
|
hexmask.long.word 0x24 0.--13. 1. " RUN2_MAX ,Run length 2 maximum limit"
|
|
line.long 0x28 "SCR3L,TRNG Statistical Check Run Length 3 Limit Register"
|
|
hexmask.long.word 0x28 16.--28. 1. " RUN3_RNG ,Run length 3 range"
|
|
hexmask.long.word 0x28 0.--12. 1. " RUN3_MAX ,Run length 3 maximum limit"
|
|
line.long 0x2C "SCR4L,TRNG Statistical Check Run Length 4 Limit Register"
|
|
hexmask.long.word 0x2C 16.--27. 1. " RUN4_RNG ,Run length 4 range"
|
|
hexmask.long.word 0x2C 0.--11. 1. " RUN4_MAX ,Run length 4 maximum limit"
|
|
line.long 0x30 "SCR5L,TRNG Statistical Check Run Length 5 Limit Register"
|
|
hexmask.long.word 0x30 16.--26. 1. " RUN5_RNG ,Run length 5 range"
|
|
hexmask.long.word 0x30 0.--10. 1. " RUN5_MAX ,Run length 5 maximum limit"
|
|
line.long 0x34 "SCR6PL,TRNG Statistical Check Run Length 6+ Limit Register"
|
|
hexmask.long.word 0x34 16.--26. 1. " RUN6P_RNG ,Run length 6+ range"
|
|
hexmask.long.word 0x34 0.--10. 1. " RUN6P_MAX ,Run length 6+ maximum limit"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10000)==0x10000)
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "STATUS,TRNG Status Register"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "STATUS,TRNG Status Register"
|
|
bitfld.long 0x00 16.--19. " RETRY_COUNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " TFMB ,Mono bit test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 14. " TFP ,Poker test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 13. " TFLR ,Long run test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 12. " TFSB ,Sparse bit test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 11. " TF6PBR1 ,6 Plus bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 10. " TF6PBR0 ,6 Plus bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 9. " TF5BR1 ,5-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 8. " TF5BR0 ,5-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 7. " TF4BR1 ,4-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 6. " TF4BR0 ,4-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 5. " TF3BR1 ,3-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 4. " TF3BR0 ,3-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 3. " TF2BR1 ,2-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 2. " TF2BR0 ,2-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 1. " TF1BR1 ,1-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " TF1BR0 ,1-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
endif
|
|
sif (cpuis("IMX7ULP-CM4")||cpuis("IMX7ULP-CM4"))
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
else
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
else
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
else
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
else
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
else
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
else
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
in
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
in
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
in
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
in
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
in
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
in
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
in
|
|
else
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
in
|
|
else
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
in
|
|
else
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
in
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
in
|
|
else
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
in
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
in
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
in
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
in
|
|
else
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
in
|
|
else
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10420)==0x420)
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
in
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40029000))&0x10000)==0x0)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_1_CT ,Poker 1h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_0_CT ,Poker 0h count"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_3_CT ,Poker 3h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_2_CT ,Poker 2h count"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_5_CT ,Poker 5h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_4_CT ,Poker 4h count"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_7_CT ,Poker 7h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_6_CT ,Poker 6h count"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_9_CT ,Poker 9h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_8_CT ,Poker 8h count"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_B_CT ,Poker Bh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_A_CT ,Poker Ah count"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_D_CT ,Poker Dh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_C_CT ,Poker Ch count"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_F_CT ,Poker Fh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_E_CT ,Poker Eh count"
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register"
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register"
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register"
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register"
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register"
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register"
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register"
|
|
endif
|
|
sif (cpuis("MK8?FN256V*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*"))
|
|
group.long 0xB0++0x0F
|
|
line.long 0x00 "SEC_CFG,TRNG Security Configuration Register"
|
|
bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes"
|
|
line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register"
|
|
bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active"
|
|
line.long 0x08 "INT_MASK,TRNG Mask Register"
|
|
bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked"
|
|
line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register"
|
|
bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid"
|
|
rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error"
|
|
else
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "SEC_CFG,TRNG Security Configuration Register"
|
|
bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes"
|
|
line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register"
|
|
bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active"
|
|
line.long 0x08 "INT_MASK,TRNG Mask Register"
|
|
bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked"
|
|
line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register"
|
|
sif (cpuis("K32W0?2S1M*")||cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4"))
|
|
rbitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
else
|
|
bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid"
|
|
rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error"
|
|
endif
|
|
rgroup.long 0xF0++0x07
|
|
line.long 0x00 "VID1,Version ID (MS) Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TRNG_IP_ID ,Shows IP ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TRNG_MAJ_REV ,Shows IP's major revision of the TRNG"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TRNG_MIN_REV ,Shows IP's minor revision of the TRNG"
|
|
line.long 0x04 "VID2,Version ID (LS) Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TRNG_ERA ,Shows compile options for the TRNG"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRNG_INTG_OPT ,Shows integration options for the TRNG"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TRNG_ECO_REV ,Shows IP's ECO revision of the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " TRNG_CONFIG_OPT ,Shows IP's Configuration options for the TRNG"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))
|
|
tree "RSIM (Radio System Integration Module)"
|
|
base ad:0x40059000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONTROL,Control"
|
|
bitfld.long 0x00 31. " RADIO_RESET ,Software reset for the radio" "No reset,Reset"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 30. " ALLOW_DFT_RESETS ,Block radio outputs" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 29. " BLOCK_RADIO_OUTPUTS ,Block radio outputs" "No,Yes"
|
|
bitfld.long 0x00 28. " BLOCK_RADIO_RESETS ,Block radio resets" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RF_OSC_READY_OVRD ,RF ref osc ready override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 25. " RF_OSC_READY_OVRD_EN ,RF ref osc ready override enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " RF_OSC_READY ,RF ref osc ready" "Not ready,Ready"
|
|
bitfld.long 0x00 23. " STOP_ACK_OVRD ,Stop acknowledge override" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x00 22. " STOP_ACK_OVRD_EN ,Stop acknowledge override enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*"))
|
|
bitfld.long 0x00 20. " RSIM_DSM_EXIT ,BLE force deep sleep mode exit" "Not forced,Forced"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RADIO_RAM_ACCESS_OVRD ,Radio RAM access override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 18. " RADIO_RAM_ACCESS_OVRD_EN ,Radio RAM access override enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IPP_OBE_3V_BLE_RF_ACTIVE_2 ,Enables the outpud driver (OBE) on the SoC port 2 that provides BLE RD active signal as pad interface option" "Disabled,Enabled"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " IPP_OBE_3V_BLE_RF_ACTIVE_1 ,Enables the outpud driver (OBE) on the SoC port 1 that provides BLE RD active signal as pad interface option" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*"))
|
|
bitfld.long 0x00 20. " BLE_DEEP_SLEEP_EXIT ,BLE deep sleep exit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " BLE_ACTIVE_PORT_2_SEL ,BLE active port 2 select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BLE_ACTIVE_PORT_1_SEL ,BLE active port 1 select" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " RF_OSC_BYPASS_EN ,RF ref osc bypass enable" "Disable,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " GASKET_BYPASS_OVRD ,Gasket bypass override" "Not overridden,Overridden"
|
|
bitfld.long 0x00 12. " GASKET_BYPASS_OVRD_EN ,Gasket bypass override enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " RF_OSC_EN ,RF ref osc enable" "Soc/External pin/Link layer,Run/Wait,,Stop,,,,VLPR/VLPW,,,,,,,,VLPS"
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*"))
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLE_RF_OSC_REQ_INT ,BLE ref osc request interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " BLE_RF_OSC_REQ_INT_EN ,BLE ref osc request interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " BLE_RF_OSC_REQ_STAT ,BLE ref osc request status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BLE_RF_OSC_REQ_EN ,BLE ref osc request enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ACTIVE_DELAY,BLE Active Delay"
|
|
bitfld.long 0x00 16.--19. " BLE_ACTIVE_COARSE_DELAY ,BLE active coarse delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. " BLE_ACTIVE_FINE_DELAY ,BLE active fine delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ACTIVE_DELAY,Radio Active Early Warning"
|
|
bitfld.long 0x00 16.--19. " BLE_ACTIVE_COARSE_DELAY ,BLE active coarse delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. " BLE_ACTIVE_FINE_DELAY ,BLE active fine delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (cpuis("MKW20Z*"))
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "ACTIVE_DELAY,BLE Active Delay"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "ACTIVE_DELAY,Radio Active Early Warning"
|
|
endif
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "MAC_MSB,MAC MSB"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " MAC_ADDR_MSB ,MAC address MSB"
|
|
line.long 0x04 "MAC_LSB,MAC LSB"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ANA_TEST,Analog Test"
|
|
bitfld.long 0x00 4. " ATST_GATE_EN[4] ,ATST transmission gate 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,ATST transmission gate 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,ATST transmission gate 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,ATST transmission gate 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,ATST transmission gate 0 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "DSM_TIMER,Deep Sleep Timer"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " DSM_TIMER ,Deep sleep mode timer"
|
|
group.long 0x104++0x07
|
|
line.long 0x00 "DSM_CONTROL,Deep Sleep Timer Control"
|
|
bitfld.long 0x00 31. " DSM_TIMER_EN ,Deep sleep mode timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DSM_TIMER_CLR ,Deep sleep mode timer clear" "Not cleared,Cleared"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
rbitfld.long 0x00 23. " ZIG_SYSCLK_REQ_INT ,Interrupt flag from an 802.15.4 link layer RF OSC request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " ZIG_SYSCLK_INTERRUPT_EN ,802.15.4 link layer RF OSC request interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ZIG_SYSCLK_REQ ,802.15.4 link layer RF OSC request status" "Not requested,Requested"
|
|
rbitfld.long 0x00 20. " ZIG_SLEEP_REQUEST ,802.15.4 link layer deep sleep requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ZIG_SYSCLK_REQUEST_EN ,Enable 802.15.4 link layer to request RF OSC" "Disabled,Enabled"
|
|
rbitfld.long 0x00 18. " DSM_ZIG_FINISHED ,802.15.4 deep sleep time finished" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " ZIG_DEEP_SLEEP_STATUS ,802.15.4 link layer deep sleep mode status" "Not in deep sleep mode,In deep sleep mode"
|
|
rbitfld.long 0x00 16. " DSM_ZIG_READY ,802.15.4 ready for deep sleep mode" "Not ready,Ready"
|
|
endif
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*"))
|
|
textline " "
|
|
rbitfld.long 0x00 15. " GEN_SYSCLK_REQ_INT ,Interrupt flag from an generic FSK link layer RF OSC request" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " GEN_SYSCLK_INTERRUPT_EN ,Generic FSK link layer RF OSC request interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " GEN_SYSCLK_REQ ,Generic FSK link layer RF OSC request status" "Not requested,Requested"
|
|
rbitfld.long 0x00 12. " GEN_SLEEP_REQUEST ,Generic FSK link layer deep sleep requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GEN_SYSCLK_REQUEST_EN ,Enable generic FSK link layer to request RF OSC" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " DSM_GEN_FINISHED ,Generic FSK deep sleep time finished" "Not finished,Finished"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " GEN_DEEP_SLEEP_STATUS ,Generic FSK link layer deep sleep mode status" "Not in deep sleep mode,In deep sleep mode"
|
|
rbitfld.long 0x00 8. " DSM_GEN_READY ,Generic FSK ready for deep sleep mode" "Not ready,Ready"
|
|
endif
|
|
line.long 0x04 "DSM_OSC_OFFSET,Deep Sleep Wakeup Time Offset"
|
|
hexmask.long.word 0x04 0.--9. 1. " DSM_OSC_STABILIZE_TIME ,Deep sleep wakeup RF OSC stabilize time"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW21Z*"))
|
|
group.long 0x114++0x07
|
|
line.long 0x00 "ZIG_SLEEP,802.15.4 Link Layer Sleep Time"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ZIG_SLEEP_TIME ,802.15.4 link layer sleep time"
|
|
line.long 0x04 "ZIG_WAKE,802.15.4 Link Layer Wake Time"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " ZIG_WAKE_TIME ,802.15.4 link layer wake time"
|
|
else
|
|
hgroup.long 0x114++0x07
|
|
hide.long 0x00 "ZIG_SLEEP,802.15.4 Link Layer Sleep Time"
|
|
hide.long 0x04 "ZIG_WAKE,802.15.4 Link Layer Wake Time"
|
|
endif
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*"))
|
|
group.long 0x11C++0x07
|
|
line.long 0x00 "GEN_SLEEP,Generic FSK Link Layer Sleep Time"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GEN_SLEEP_TIME ,Generic FSK link layer sleep time"
|
|
line.long 0x04 "GEN_WAKE,Generic FSK Link Layer Wake Time"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GEN_WAKE_TIME ,Generic FSK link layer wake time"
|
|
else
|
|
hgroup.long 0x11C++0x07
|
|
hide.long 0x00 "GEN_SLEEP,Generic FSK Link Layer Sleep Time"
|
|
hide.long 0x04 "GEN_WAKE,Generic FSK Link Layer Wake Time"
|
|
endif
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "RF_OSC_CTRL,Radio Oscillator Control"
|
|
bitfld.long 0x00 31. " RF_NOT_ALLOWED_OVRD_EN ,RF not allowed override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RF_NOT_ALLOWED_OVRD ,RF not allowed override" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RADIO_EXT_OSC_OVRD_EN ,Radio external request for RF OSC override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " RADIO_EXT_OSC_OVRD ,Radio external request for RF OSC override" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RADIO_EXT_OSC_RF_EN_SEL ,Radio external request for RF OSC select" "PTB0,PTC6"
|
|
bitfld.long 0x00 20.--21. " BB_XTAL_READY_COUNT_SEL ,Program counter for xtal ready signal" "1024 counts,2048 counts,4096 counts,8192 counts"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BB_XTAL_ON_OVRD_ON ,Enable override XO enable bit" "Rfctrl_bb_xtal_on_hv,Rfctrl_bb_xtal_on_ovrd_hv"
|
|
bitfld.long 0x00 17. " BB_XTAL_ON_OVRD ,Override XO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--16. " BB_XTAL_GM ,Amplifier current bumps" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,?..."
|
|
bitfld.long 0x00 11. " BB_XTAL_DIG_CLK_ON ,Enable digital clk output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BB_XTAL_DIAGSEL ,Enable diagnostics for XO block" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BB_XTAL_DC_COUP_MODE_EN ,This bit enables the external dc coupled mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RF_OSC_BYPASS_EN ,RF ref osc bypass enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BB_XTAL_ALC_ON ,Enable ALC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " BB_XTAL_ALC_COUNT_SEL ,Program counter for alc ready signal" "2048,4096,8192,16384"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ANA_TRIM,Radio Analog Trim Registers"
|
|
bitfld.long 0x00 28.--31. " BG_IBIAS_5U_TRIM ,5uA current trim bits" "3.55uA,3.73uA,4.04uA,4.22uA,4.39uA,4.57uA,4.89uA,5.06uA,5.23uA,5.41uA,5.72uA,5.9uA,6.07uA,6.25uA,6.56uA,6.74uA"
|
|
bitfld.long 0x00 24.--27. " BG_1V_TRIM ,Trim bits for VBG output voltage" "954.14mV,959.26mV,964.38mV,969.5mV,974.6mV,979.7mV,984.8mV,989.9mV,995mV,1V,1.005V,1.01V,1.015V,1.02V,1.025V,1.031V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " BB_XTAL_TRIM ,Bump XO load capacitor"
|
|
bitfld.long 0x00 15. " BB_XTAL_SPARE[4] ,BB XTAL spare bit 4 - Force XTAL ready High" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " BB_XTAL_SPARE[3] ,BB XTAL spare bit 3 - XO output polarity invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " BB_XTAL_SPARE[2] ,BB XTAL spare bit 2 - Enable AuxPLL output instead of XO" "XO,AuxPLL"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BB_LDO_XO_TRIM ,Trim settings for LDO" "1.20V,1.25V,1.28V,1.33V,1.40V,1.44V,1.50V,1.66V"
|
|
bitfld.long 0x00 3.--5. " BB_LDO_LS_TRIM ,Trim settings for LDO" "1.20V,1.25V,1.28V,1.33V,1.40V,1.44V,1.50V,1.66V"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Transceiver Registers"
|
|
base ad:0x4005C000
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "RX_DIG_CTRL,RX Digital Control"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
rbitfld.long 0x00 31. " RX_DEC_FILT_SAT_Q ,Decimator output saturation detected for Q channel" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 30. " RX_DEC_FILT_SAT_I ,Decimator output saturation detected for I channel" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " RX_RSSI_FILT_HAZARD ,Decimator output for RSSI hazard condition detected" "Not detected,Detected"
|
|
rbitfld.long 0x00 28. " RX_DEC_FILT_HAZARD ,Decimator output hazard condition detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RX_DEC_FILT_HZD_CORR_DIS ,Decimator filter hazard correction disable" "No,Yes"
|
|
bitfld.long 0x00 20.--24. " RX_DEC_FILT_GAIN ,Decimation filter fractional gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RX_DMA_DTEST_EN ,RX DMA and DTEST enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RX_SRC_RATE ,RX sample rate converter rate selections" "FOH rate of 8/13,ZOH rate of 12/13"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RX_SRC_EN ,RX sample rate converter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RX_DC_RESID_EN ,DC residual enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " RX_IQ_SWAP ,RX IQ swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RX_DCOC_CAL_EN ,DCOC calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_DCOC_EN ,DCOC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RX_AGC_EN ,AGC global enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_RSSI_EN ,RSSI measurement enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RX_NORM_EN ,Normalizer enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*"))
|
|
bitfld.long 0x00 8. " RX_FSK_ZB_SEL ,FSK / 802.15.4 demodulator select" "FSK,802.15.4"
|
|
bitfld.long 0x00 4.--6. " RX_DEC_FILT_OSR ,Decimation filter oversampling" "OSR 4,OSR 8,OSR 16,OSR 6,OSR 32,OSR 12,OSR 24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX_ADC_POL ,Receive ADC polarity" "Output -1/+1,Output +1/-1"
|
|
elif (cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8. " RX_FSK_ZB_SEL ,FSK / 802.15.4 demodulator select" ",802.15.4"
|
|
bitfld.long 0x00 4.--6. " RX_DEC_FILT_OSR ,Decimation filter oversampling" "OSR 4,OSR 8,OSR 16,OSR 6,OSR 32,OSR 12,OSR 24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX_ADC_POL ,Receive ADC polarity" "Output -1/+1,Output +1/-1"
|
|
else
|
|
bitfld.long 0x00 8. " RX_INTERP_EN ,Interpolator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " RX_DEC_FILT_OSR ,Decimation filter oversampling" "OSR 2,OSR 4,OSR 8,OSR 9,OSR 16,OSR 18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " RX_ADC_RAW_EN ,ADC raw mode selection" "Normal,Two 5-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_CH_FILT_BYPASS ,Receive channel filter bypass" "Enabled,Disabled and bypass"
|
|
bitfld.long 0x00 0. " RX_ADC_NEGEDGE ,Receive ADC negative edge selection" "Positive edge,Negative edge"
|
|
line.long 0x04 "AGC_CTRL_0,AGC Control 0"
|
|
hexmask.long.byte 0x04 24.--31. 1. " AGC_DOWN_RSSI_THRESH ,AGC down RSSI threshold"
|
|
hexmask.long.byte 0x04 16.--23. 1. " AGC_UP_RSSI_THRESH ,AGC down RSSI threshold"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x04 12.--15. " AGC_DOWN_LNA_STEP_SZ ,Number of table steps for downward step (LNA) in AGC fast" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " AGC_DOWN_BBA_STEP_SZ ,Number of table steps for downward step (BBA) in AGC fast" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x04 12.--15. " AGC_DOWN_TZA_STEP_SZ ,Number of table steps for downward step (TZA) in AGC fast" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " AGC_DOWN_BBF_STEP_SZ ,Number of table steps for downward step (BBF) in AGC fast" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " AGC_UP_SRC ,AGC up source" "PDET LO,RSSI"
|
|
bitfld.long 0x04 6. " AGC_UP_EN ,AGC up enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x04 4. " AGC_FREEZE_PRE_OR_AA ,AGC freeze source selection" "Access address,Preamble detect"
|
|
bitfld.long 0x04 3. " AGC_FREEZE_EN ,AGC freeze enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1.--2. " SLOW_AGC_SRC ,Slow AGC source selection" "Access address match,Preamble detect,Fast AGC expire timer,?..."
|
|
else
|
|
bitfld.long 0x04 4.--5. " FREEZE_AGC_SRC ,Freeze AGC source selection" "BTLE preamble detect,Zigbee preamble detect,BTLE access match,Zigbee LQI done"
|
|
bitfld.long 0x04 3. " AGC_FREEZE_EN ,AGC freeze enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1.--2. " SLOW_AGC_SRC ,Slow AGC source selection" "BTLE preamble detect,Zigbee preamble detect,Fast AGC expire timer,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 0. " SLOW_AGC_EN ,Slow AGC enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "AGC_CTRL_1,AGC Control 1"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
hexmask.long.byte 0x00 24.--31. 1. " LNA_GAIN_SETTLE_TIME ,Number of clocks to assert LNA peak detector reset"
|
|
bitfld.long 0x00 22. " PRESLOW_EN ,Pre-slow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " USER_BBA_GAIN_EN ,User BBA gain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " USER_LNA_GAIN_EN ,User LNA gain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BBA_USER_GAIN ,User defined BBA gain index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " LNA_USER_GAIN ,User defined LNA gain index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--11. 1. " LNA_ALT_CODE ,Alternate LNA gain code"
|
|
bitfld.long 0x00 0.--3. " BBA_ALT_CODE ,Alternate BBA gain code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hexmask.long.byte 0x00 24.--31. 1. " TZA_GAIN_SETTLE_TIME ,Number of clocks to assert TZA peak detector reset"
|
|
bitfld.long 0x00 22. " PRESLOW_EN ,Pre-slow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " USER_BBF_GAIN_EN ,User BBF gain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " USER_LNM_GAIN_EN ,User LNM gain enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BBF_USER_GAIN ,User defined BBF gain index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " LNM_USER_GAIN ,User defined LNM gain index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--11. 1. " LNM_ALT_CODE ,Alternate LNM gain code"
|
|
bitfld.long 0x00 0.--3. " BBF_ALT_CODE ,Alternate BBF gain code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x04 "AGC_CTRL_2,AGC Control 2"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x04 31. " LNA_HG_ON_OVR ,LNA high gain ON override" "No override,Override"
|
|
bitfld.long 0x04 30. " LNA_LG_ON_OVR ,LNA low gain ON override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x04 24.--29. " AGC_FAST_EXPIRE ,AGC fast expire" ",1uS,2uS,3uS,4uS,5uS,6uS,7uS,8uS,9uS,10uS,11uS,12uS,13uS,14uS,15uS,16uS,17uS,18uS,19uS,20uS,21uS,22uS,23uS,24uS,25uS,26uS,27uS,28uS,29uS,30uS,31uS,32uS,33uS,34uS,35uS,36uS,37uS,38uS,39uS,40uS,41uS,42uS,43uS,44uS,45uS,46uS,47uS,48uS,49uS,50uS,51uS,52uS,53uS,54uS,55uS,56uS,57uS,58uS,59uS,60uS,61uS,62uS,63uS"
|
|
bitfld.long 0x04 21.--23. " TZA_PDET_SEL_HI ,TZA peak detect HI threshold" "0.6V,0.63V,0.66V,0.69V,0.72V,0.75V,0.78V,0.81V"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " TZA_PDET_SEL_LO ,TZA peak detect LO threshold" "0.6V,0.615V,0.63V,0.645V,0.660V,0.675V,0.690V,0.705V"
|
|
bitfld.long 0x04 15.--17. " BBA_PDET_SEL_HI ,BBA peak detect HI threshold" "0.6V,0.795V,0.900V,0.945V,1.005V,1.050V,1.095V,1.155V"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " BBA_PDET_THRESH_LO ,BBA peak detect LO threshold" "0.6V,0.615V,0.630V,0.645V,0.660V,0.675V,0.690V,0.705V"
|
|
hexmask.long.byte 0x04 4.--11. 1. " BBA_GAIN_SETTLE_TIME ,BBA gain settle time"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MAN_PDET_RST ,MAN peak detect reset" "No reset,Reset"
|
|
bitfld.long 0x04 1. " TZA_PDET_RST ,TZA peak detector reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " BBA_PDET_RST ,BBA peak detector reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x04 24.--29. " AGC_FAST_EXPIRE ,AGC fast expire" ",1uS,2uS,3uS,4uS,5uS,6uS,7uS,8uS,9uS,10uS,11uS,12uS,13uS,14uS,15uS,16uS,17uS,18uS,19uS,20uS,21uS,22uS,23uS,24uS,25uS,26uS,27uS,28uS,29uS,30uS,31uS,32uS,33uS,34uS,35uS,36uS,37uS,38uS,39uS,40uS,41uS,42uS,43uS,44uS,45uS,46uS,47uS,48uS,49uS,50uS,51uS,52uS,53uS,54uS,55uS,56uS,57uS,58uS,59uS,60uS,61uS,62uS,63uS"
|
|
bitfld.long 0x04 21.--23. " TZA_PDET_THRESH_HI ,TZA peak detect HI threshold" "0.6V,0.675V,0.75V,0.825V,0.9V,0.975V,1.05V,1.125V"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " TZA_PDET_THRESH_LO ,TZA peak detect LO threshold" "0.6V,0.675V,0.75V,0.825V,0.9V,0.975V,1.05V,1.125V"
|
|
bitfld.long 0x04 15.--17. " BBF_PDET_THRESH_HI ,BBF peak detect HI threshold" "0.6V,0.675V,0.75V,0.825V,0.9V,0.975V,1.05V,1.125V"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " BBF_PDET_THRESH_LO ,BBF peak detect LO threshold" "0.6V,0.675V,0.75V,0.825V,0.9V,0.975V,1.05V,1.125V"
|
|
hexmask.long.byte 0x04 4.--11. 1. " BBF_GAIN_SETTLE_TIME ,BBF gain settle time"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TZA_PDET_RST ,TZA peak detector reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " BBF_PDET_RST ,BBF peak detector reset" "No reset,Reset"
|
|
endif
|
|
line.long 0x08 "AGC_CTRL_3,AGC Control 3"
|
|
bitfld.long 0x08 28.--31. " AGC_UP_STEP_SZ ,AGC step up size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 23.--27. " AGC_H2S_STEP_SZ ,Step size for hold to slow jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--22. 1. " AGC_RSSI_DELT_H2S ,RSSI delta that causes hold to slow transition"
|
|
bitfld.long 0x08 13.--15. " AGC_PDET_LO_DLY ,AGC peak detect low delay" ",1uS,2uS,3uS,4uS,5uS,6uS,7uS"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--12. 1. " AGC_UNFREEZE_TIME ,AGC unfreeze time"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "AGC_STAT,AGC Status"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RSSI_ADC_RAW ,ADC RAW RSSI reading"
|
|
bitfld.long 0x00 9. " AGC_FROZEN ,AGC Frozen Status" "Not frozen,Frozen"
|
|
textline " "
|
|
bitfld.long 0x00 4.--8. " CURR_AGC_IDX ,Current AGC gain index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 3. " TZA_PDET_HI_STAT ,TZA peak detector high status" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TZA_PDET_LO_STAT ,TZA peak detector low status" "Not set,Set"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 1. " BBA_PDET_HI_STAT ,BBA peak detector high status" "Not set,Set"
|
|
bitfld.long 0x00 0. " BBA_PDET_LO_STAT ,BBA peak detector low status" "Not set,Set"
|
|
else
|
|
bitfld.long 0x00 1. " BBF_PDET_HI_STAT ,BBF peak detector high status" "Not set,Set"
|
|
bitfld.long 0x00 0. " BBF_PDET_LO_STAT ,BBF peak detector low status" "Not set,Set"
|
|
endif
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "RSSI_CTRL_0,RSSI Control 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RSSI_ADJ ,RSSI adjustment"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " RSSI_VLD_SETTLE ,RSSI valid settle" "0us,8us,16us,24us,32us,40us,48us,56us"
|
|
bitfld.long 0x00 16.--19. " RSSI_IIR_WEIGHT ,RSSI IIR weighting" "Bypass,1/2,1/4,1/8,1/16,1/32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--15. " RSSI_HOLD_DELAY ,RSSI hold delay" "0us,8us,16us,24us,32us,40us,48us,56us,64us,72us,80us,88us,96us,104us,112us,120us,128us,136us,144us,152us,160us,168us,176us,184us,192us,200us,208us,216us,224us,232us,240us,248us,256us,264us,272us,280us,288us,296us,304us,312us,320us,328us,336us,344us,352us,360us,368us,376us,384us,392us,400us,408us,416us,424us,432us,440us,448us,456us,464us,472us,480us,488us,496us,504us"
|
|
bitfld.long 0x00 8.--9. " RSSI_N_WINDOW_AVG ,RSSI N window average" "No averaging,2 samples,4 samples,8 samples"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RSSI_IIR_WEIGHT ,RSSI IIR weighting" "Bypass,1/2,1/4,1/8,1/16,1/32,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RSSI_IIR_CW_WEIGHT ,RSSI IIR CW weighting" "Bypass,1/8,1/16,1/32"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
sif (cpuis("MKW31Z*"))
|
|
bitfld.long 0x00 3. " RSSI_HOLD_EN ,RSSI hold enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " RSSI_HOLD_SRC ,Hold RSSI source selection" "Access address match,Preamble detect,,"
|
|
else
|
|
bitfld.long 0x00 3. " RSSI_HOLD_EN ,RSSI hold enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " RSSI_HOLD_SRC ,Hold RSSI source selection" "Access address match,Preamble detect,,802.15.4 LQI done"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " RSSI_USE_VALS ,RSSI values selection" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4. " RSSI_DEC_EN ,RSSI decimation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RSSI_HOLD_EN ,RSSI hold enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW40Z*"))
|
|
bitfld.long 0x00 1.--2. " RSSI_HOLD_SRC ,Hold RSSI source selection" ",Zigbee preamble detect,,Zigbee LQI done"
|
|
bitfld.long 0x00 0. " RSSI_USE_VALS ,RSSI values selection" "Disabled,Enabled"
|
|
elif (cpuis("MKW30Z*"))
|
|
bitfld.long 0x00 1.--2. " RSSI_HOLD_SRC ,Hold RSSI source selection" "BTLE preamble detect,,BTLE access match,"
|
|
bitfld.long 0x00 0. " RSSI_USE_VALS ,RSSI values selection" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1.--2. " RSSI_HOLD_SRC ,Hold RSSI source selection" "BTLE preamble detect,Zigbee preamble detect,BTLE access match,Zigbee LQI done"
|
|
bitfld.long 0x00 0. " RSSI_USE_VALS ,RSSI values selection" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
line.long 0x04 "RSSI_CTRL_1,RSSI Control 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RSSI_OUT ,RSSI reading"
|
|
sif (!cpuis("MKW41Z*")&&!cpuis("MKW31Z*")&&!cpuis("MKW21Z*"))
|
|
textline " "
|
|
bitfld.long 0x04 20.--23. " RSSI_ED_THRESH1_H ,RSSI energy detect 1 hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " RSSI_ED_THRESH0_H ,RSSI energy detect 0 hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " RSSI_ED_THRESH1 ,RSSI energy detect 1 threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RSSI_ED_THRESH0 ,RSSI energy detect 0 threshold"
|
|
endif
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DCOC_CTRL_0,DCOC Control 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " DCOC_CORR_HOLD_TIME ,DCOC correction hold time"
|
|
bitfld.long 0x00 16.--20. " DCOC_CORR_DLY ,DCOC correction delay" ",1uS,2uS,3uS,4uS,5uS,6uS,7uS,8uS,9uS,10uS,11uS,12uS,13uS,14uS,15uS,16uS,17uS,18uS,19uS,20uS,21uS,22uS,23uS,24uS,25uS,26uS,27uS,28uS,29uS,30uS,31uS"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " DCOC_CAL_DURATION ,DCOC calibration duration" ",1uS,2uS,3uS,4uS,5uS,6uS,7uS,8uS,9uS,10uS,11uS,12uS,13uS,14uS,15uS,16uS,17uS,18uS,19uS,20uS,21uS,22uS,23uS,24uS,25uS,26uS,27uS,28uS,29uS,30uS,31uS"
|
|
bitfld.long 0x00 7. " TZA_CORR_POL ,TZA correction polarity" "Normal,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BBA_CORR_POL ,BBA correction polarity" "Normal,Negative"
|
|
bitfld.long 0x00 5. " TRACK_FROM_ZERO ,Track from zero" "Current I/Q sample,Zero"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DCOC_CORRECT_EN ,DCOC correction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DCOC_CORRECT_SRC ,DCOC correct source" "DCOC table,DCOC table/tracking estimator"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DCOC_TRK_EST_OVR ,Override for the DCOC tracking estimator" "No override,Override"
|
|
bitfld.long 0x00 1. " DCOC_MAN ,DCOC manual override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DCOC_MIDPWR_TRK_DIS ,DCOC mid power tracking disable" "No,Yes"
|
|
if (((per.l(ad:0x4005C000+0x24))&0x08)==0x08)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCOC_CTRL_1,DCOC Control 1"
|
|
bitfld.long 0x00 24.--28. " DCOC_TRK_MIN_AGC_IDX ,DCOC tracking minimum AGC table index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " DCOC_ALPHA_RADIUS_GS_IDX ,Alpha-R scaling for gearshift" "1,1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DCOC_ALPHAC_SCALE_GS_IDX ,DCOC Alpha-C scaling for gearshift" "1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
bitfld.long 0x00 16.--17. " DCOC_SIGN_SCALE_GS_IDX ,DCOC sign scaling for gearshift" "1/8,1/16,1/32,1/64"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DCOC_TRK_EST_GS_CNT ,DCOC tracking estimator gearshift count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " DCOC_ALPHA_RADIUS_IDX ,Alpha-R scaling" "1,1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " DCOC_ALPHAC_SCALE_IDX ,DCOC Alpha-C scaling" "1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
bitfld.long 0x00 0.--1. " DCOC_SIGN_SCALE_IDX ,DCOC sign scaling" "1/8,1/16,1/32,1/64"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCOC_CTRL_1,DCOC Control 1"
|
|
bitfld.long 0x00 24.--28. " DCOC_TRK_MIN_AGC_IDX ,DCOC tracking minimum AGC table index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--14. " DCOC_TRK_EST_GS_CNT ,DCOC tracking estimator gearshift count" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCOC_DAC_INIT,DCOC DAC Initialization"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TZA_DCOC_INIT_Q ,DCOC TZA init Q"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TZA_DCOC_INIT_I ,DCOC TZA init I"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " BBF_DCOC_INIT_Q ,DCOC BBF init Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " BBF_DCOC_INIT_I ,DCOC BBF init I" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0x4005C000+0x24))&0x02)==0x02)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DCOC_DIG_MAN,DCOC Digital Correction Manual Override"
|
|
hexmask.long.word 0x00 16.--27. 1. " DIG_DCOC_INIT_Q ,DCOC DIG init Q"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIG_DCOC_INIT_I ,DCOC DIG init I"
|
|
else
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "DCOC_DIG_MAN,DCOC Digital Correction Manual Override"
|
|
in
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DCOC_CAL_GAIN,DCOC Calibration Gain"
|
|
bitfld.long 0x00 28.--31. " DCOC_LNA_CAL_GAIN3 ,DCOC LNA calibration gain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DCOC_BBA_CAL_GAIN3 ,DCOC BBA calibration gain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DCOC_LNA_CAL_GAIN2 ,DCOC LNA calibration gain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DCOC_BBA_CAL_GAIN2 ,DCOC BBA calibration gain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DCOC_LNA_CAL_GAIN1 ,DCOC LNA calibration gain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DCOC_BBA_CAL_GAIN1 ,DCOC BBA calibration gain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((per.l(ad:0x4005C000+0x20))&0x08)==0x08)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DCOC_CTRL_0,DCOC Control 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DCOC_CORR_HOLD_TIME ,DCOC correction hold time"
|
|
bitfld.long 0x00 20.--24. " DCOC_CORR_DLY ,DCOC correction delay" ",1uS,2uS,3uS,4uS,5uS,6uS,7uS,8uS,9uS,10uS,11uS,12uS,13uS,14uS,15uS,16uS,17uS,18uS,19uS,20uS,21uS,22uS,23uS,24uS,25uS,26uS,27uS,28uS,29uS,30uS,31uS"
|
|
textline " "
|
|
bitfld.long 0x00 15.--19. " DCOC_CAL_DURATION ,DCOC calibration duration" ",1uS,2uS,3uS,4uS,5uS,6uS,7uS,8uS,9uS,10uS,11uS,12uS,13uS,14uS,15uS,16uS,17uS,18uS,19uS,20uS,21uS,22uS,23uS,24uS,25uS,26uS,27uS,28uS,29uS,30uS,31uS"
|
|
bitfld.long 0x00 12.--14. " DCOC_ALPHA_RADIUS_IDX ,Alpha-R scaling" "1,1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DCOC_ALPHAC_SCALE_IDX ,DCOC alpha-C scaling" "1/2,1/4,1/8,1/16"
|
|
bitfld.long 0x00 5.--6. " DCOC_SIGN_SCALE_IDX ,DCOC sign scaling" "1/4,1/8,1/16,1/32"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DCOC_CORRECT_EN ,DCOC correction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DCOC_TRACK_EN ,DCOC tracking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DCOC_MAN ,DCOC manual override" "No override,Override"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DCOC_CTRL_0,DCOC Control 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DCOC_CORR_HOLD_TIME ,DCOC correction hold time"
|
|
bitfld.long 0x00 20.--24. " DCOC_CORR_DLY ,DCOC correction delay" ",1uS,2uS,3uS,4uS,5uS,6uS,7uS,8uS,9uS,10uS,11uS,12uS,13uS,14uS,15uS,16uS,17uS,18uS,19uS,20uS,21uS,22uS,23uS,24uS,25uS,26uS,27uS,28uS,29uS,30uS,31uS"
|
|
textline " "
|
|
bitfld.long 0x00 15.--19. " DCOC_CAL_DURATION ,DCOC calibration duration" "0uS,1uS,2uS,3uS,4uS,5uS,6uS,7uS,8uS,9uS,10uS,11uS,12uS,13uS,14uS,15uS,16uS,17uS,18uS,19uS,20uS,21uS,22uS,23uS,24uS,25uS,26uS,27uS,28uS,29uS,30uS,31uS"
|
|
bitfld.long 0x00 4. " DCOC_CORRECT_EN ,DCOC correction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCOC_TRACK_EN ,DCOC tracking enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DCOC_MAN ,DCOC manual override" "No override,Override"
|
|
endif
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "DCOC_CTRL_1,DCOC Control 1"
|
|
bitfld.long 0x00 26. " TZA_CORR_POL ,TZA correction polarity" "Normal,Negative"
|
|
bitfld.long 0x00 25. " BBA_CORR_POL ,BBA correction polarity" "Normal,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TRACK_FROM_ZERO ,Track from zero" "Current I/Q sample,Zero"
|
|
hexmask.long.word 0x00 0.--8. 1. " BBF_DCOC_STEP ,DCOC BBF step size"
|
|
line.long 0x04 "DCOC_CTRL_2,DCOC Control 2"
|
|
hexmask.long.word 0x04 0.--12. 1. " BBF_DCOC_STEP_RECIP ,DCOC BBF reciprocal of step size"
|
|
if (((per.l(ad:0x4005C000+0x20))&0x02)==0x02)
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "DCOC_CTRL_3,DCOC Control 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TZA_DCOC_INIT_Q ,DCOC TZA init Q"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TZA_DCOC_INIT_I ,DCOC TZA init I"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " BBF_DCOC_INIT_Q ,DCOC BBF init Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " BBF_DCOC_INIT_I ,DCOC BBF init I" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "DCOC_CTRL_4,DCOC Control 4"
|
|
hexmask.long.word 0x04 16.--27. 1. " DIG_DCOC_INIT_Q ,DCOC DIG init Q"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIG_DCOC_INIT_I ,DCOC DIG init I"
|
|
else
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "DCOC_CTRL_3,DCOC Control 3"
|
|
in
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "DCOC_CTRL_4,DCOC Control 4"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x4005C000))&0x2000)==0x2000)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DCOC_CAL_GAIN,DCOC Calibration Gain"
|
|
bitfld.long 0x00 28.--31. " DCOC_TZA_CAL_GAIN3 ,DCOC TZA calibration gain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DCOC_BBF_CAL_GAIN3 ,DCOC BBF calibration gain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DCOC_TZA_CAL_GAIN2 ,DCOC TZA calibration gain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DCOC_BBF_CAL_GAIN2 ,DCOC BBF calibration gain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DCOC_TZA_CAL_GAIN1 ,DCOC TZA calibration gain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DCOC_BBF_CAL_GAIN1 ,DCOC BBF calibration gain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "DCOC_CAL_GAIN,DCOC Calibration Gain"
|
|
in
|
|
endif
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "DCOC_STAT,DCOC Status"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TZA_DCOC_Q ,Current TZA DAC setting for Q channel"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TZA_DCOC_I ,Current TZA DAC setting for I channel"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " BBF_DCOC_Q ,Current BBF DAC setting for Q channel" "Most negative,-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Most positive"
|
|
bitfld.long 0x00 0.--5. " BBF_DCOC_I ,Current BBF DAC setting for I channel" "Most negative,-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Most positive"
|
|
if (((per.l(ad:0x4005C000+0x20))&0x08)==0x08)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "DCOC_DC_EST,DCOC DC Estimate"
|
|
hexmask.long.word 0x00 16.--27. 1. " DC_EST_Q ,Reflects the current DCOC DC tracking estimate for Q channel"
|
|
hexmask.long.word 0x00 0.--11. 1. " DC_EST_I ,Reflects the current DCOC DC tracking estimate for I channel"
|
|
else
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "DCOC_DC_EST,DCOC DC Estimate"
|
|
endif
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DCOC_CAL_RCP,DCOC Calibration Reciprocals"
|
|
hexmask.long.word 0x00 16.--26. 1. " ALPHA_CALC_RECIP ,Alpha calculation reciprocal"
|
|
hexmask.long.word 0x00 0.--10. 1. " DCOC_TMP_CALC_RECIP ,DCOC calculation reciprocal"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DCOC_CAL_RCP,DCOC Calibration Reciprocals"
|
|
hexmask.long.word 0x00 10.--20. 1. " ALPHA_CALC_RECIP ,Alpha calculation reciprocal"
|
|
hexmask.long.word 0x00 0.--9. 1. " DCOC_TMP_CALC_RECIP ,DCOC calculation reciprocal"
|
|
endif
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
textline " "
|
|
width 27.
|
|
group.long 0x48++0x53
|
|
line.long 0x00 "IQMC_CTRL,IQMC Control"
|
|
hexmask.long.word 0x00 16.--26. 1. " IQMC_DC_GAIN_ADJ ,IQ mismatch correction DC gain coefficient"
|
|
hexmask.long.byte 0x00 8.--15. 1. " IQMC_NUM_ITER ,Number of iterations for IQ Mismatch Calibration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IQMC_CAL_EN ,IQ mismatch cal enable" "Disabled,Enabled"
|
|
line.long 0x04 "IQMC_CAL,IQMC Calibration"
|
|
hexmask.long.word 0x04 16.--27. 1. " IQMC_PHASE_ADJ ,IQ mismatch correction phase coefficient"
|
|
hexmask.long.word 0x04 0.--10. 1. " IQMC_GAIN_ADJ ,IQ mismatch correction gain coefficient"
|
|
line.long 0x08 "LNA_GAIN_VAL_3_0,LNA Gain Step Values 3-0"
|
|
hexmask.long.byte 0x08 24.--31. 1. " LNA_GAIN_VAL_3 ,Gain for LNA step 3 for RSSI calculation"
|
|
hexmask.long.byte 0x08 16.--23. 1. " LNA_GAIN_VAL_2 ,Gain for LNA step 2 for RSSI calculation"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " LNA_GAIN_VAL_1 ,Gain for LNA step 1 for RSSI calculation"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LNA_GAIN_VAL_1 ,Gain for LNA step 1 for RSSI calculation"
|
|
line.long 0x0C "LNA_GAIN_VAL_7_4,LNA Gain Step Values 7-4"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " LNA_GAIN_VAL_7 ,Gain for LNA step 7 for RSSI calculation"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " LNA_GAIN_VAL_6 ,Gain for LNA step 6 for RSSI calculation"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " LNA_GAIN_VAL_5 ,Gain for LNA step 5 for RSSI calculation"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " LNA_GAIN_VAL_4 ,Gain for LNA step 4 for RSSI calculation"
|
|
line.long 0x10 "LNA_GAIN_VAL_8,LNA Gain Step Values 8"
|
|
hexmask.long.byte 0x10 8.--15. 1. " LNA_GAIN_VAL_9 ,Gain for LNA step 9 for RSSI calculation"
|
|
hexmask.long.byte 0x10 0.--7. 1. " LNA_GAIN_VAL_8 ,Gain for LNA step 8 for RSSI calculation"
|
|
line.long 0x14 "BBA_RES_TUNE_VAL_7_0,BBA Resistor Tune Values 7-0"
|
|
bitfld.long 0x14 28.--31. " BBA_RES_TUNE_VAL_7 ,BBA resistor tune step 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " BBA_RES_TUNE_VAL_6 ,BBA resistor tune step 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 20.--23. " BBA_RES_TUNE_VAL_5 ,BBA resistor tune step 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " BBA_RES_TUNE_VAL_4 ,BBA resistor tune step 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 12.--15. " BBA_RES_TUNE_VAL_3 ,BBA resistor tune step 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " BBA_RES_TUNE_VAL_2 ,BBA resistor tune step 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " BBA_RES_TUNE_VAL_1 ,BBA resistor tune step 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " BBA_RES_TUNE_VAL_0 ,BBA resistor tune step 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "BBA_RES_TUNE_VAL_10_8,BBA Resistor Tune Values 10-8"
|
|
bitfld.long 0x18 8.--11. " BBA_RES_TUNE_VAL_10 ,BBA resistor tune step 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 4.--7. " BBA_RES_TUNE_VAL_9 ,BBA resistor tune step 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 0.--3. " BBA_RES_TUNE_VAL_8 ,BBA resistor tune step 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "LNA_GAIN_LIN_VAL_2_0,LNA Linear Gain Values 2..0"
|
|
hexmask.long.word 0x1C 20.--29. 1. " LNA_GAIN_LIN_VAL_2 ,LNA linear gain step 2"
|
|
hexmask.long.word 0x1C 10.--19. 1. " LNA_GAIN_LIN_VAL_1 ,LNA linear gain step 1"
|
|
textline " "
|
|
hexmask.long.word 0x1C 0.--9. 1. " LNA_GAIN_LIN_VAL_0 ,LNA linear gain step 0"
|
|
line.long 0x20 "LNA_GAIN_LIN_VAL_5_3,LNA Linear Gain Values 5-3"
|
|
hexmask.long.word 0x20 20.--29. 1. " LNA_GAIN_LIN_VAL_5 ,LNA linear gain step 5"
|
|
hexmask.long.word 0x20 10.--19. 1. " LNA_GAIN_LIN_VAL_4 ,LNA linear gain step 4"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--9. 1. " LNA_GAIN_LIN_VAL_3 ,LNA linear gain step 3"
|
|
line.long 0x24 "LNA_GAIN_LIN_VAL_8_6,LNA Linear Gain Values 8-6"
|
|
hexmask.long.word 0x24 20.--29. 1. " LNA_GAIN_LIN_VAL_8 ,LNA linear gain step 8"
|
|
hexmask.long.word 0x24 10.--19. 1. " LNA_GAIN_LIN_VAL_7 ,LNA linear gain step 7"
|
|
textline " "
|
|
hexmask.long.word 0x24 0.--9. 1. " LNA_GAIN_LIN_VAL_6 ,LNA linear gain step 6"
|
|
line.long 0x28 "LNA_GAIN_LIN_VAL_9,LNA Linear Gain Values 9"
|
|
hexmask.long.word 0x28 0.--9. 1. " LNA_GAIN_LIN_VAL_9 ,LNA linear gain step 9"
|
|
line.long 0x2C "BBA_RES_TUNE_LIN_VAL_3_0,BBA Resistor Tune Values 3-0"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " BBA_RES_TUNE_LIN_VAL_3 ,BBA resistor tune linear gain step 3"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " BBA_RES_TUNE_LIN_VAL_2 ,BBA resistor tune linear gain step 2"
|
|
textline " "
|
|
hexmask.long.byte 0x2C 8.--15. 1. " BBA_RES_TUNE_LIN_VAL_1 ,BBA resistor tune linear gain step 1"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " BBA_RES_TUNE_LIN_VAL_0 ,BBA resistor tune linear gain step 0"
|
|
line.long 0x30 "BBA_RES_TUNE_LIN_VAL_7_4,BBA Resistor Tune Values 7-4"
|
|
hexmask.long.byte 0x30 24.--31. 1. " BBA_RES_TUNE_LIN_VAL_7 ,BBA resistor tune linear gain step 7"
|
|
hexmask.long.byte 0x30 16.--23. 1. " BBA_RES_TUNE_LIN_VAL_6 ,BBA resistor tune linear gain step 6"
|
|
textline " "
|
|
hexmask.long.byte 0x30 8.--15. 1. " BBA_RES_TUNE_LIN_VAL_5 ,BBA resistor tune linear gain step 5"
|
|
hexmask.long.byte 0x30 0.--7. 1. " BBA_RES_TUNE_LIN_VAL_4 ,BBA resistor tune linear gain step 4"
|
|
line.long 0x34 "BBA_RES_TUNE_LIN_VAL_10_8,BBA Resistor Tune Values 10-8"
|
|
hexmask.long.word 0x34 20.--29. 1. " BBA_RES_TUNE_LIN_VAL_10 ,BBA resistor tune linear gain step 10"
|
|
hexmask.long.word 0x34 10.--19. 1. " BBA_RES_TUNE_LIN_VAL_9 ,BBA resistor tune linear gain step 9"
|
|
textline " "
|
|
hexmask.long.word 0x34 0.--9. 1. " BBA_RES_TUNE_LIN_VAL_8 ,BBA resistor tune linear gain step 8"
|
|
line.long 0x38 "AGC_GAIN_TBL_03_00,AGC Gain Tables Step 03-00"
|
|
bitfld.long 0x38 28.--31. " LNA_GAIN_03 ,LNA gain 03" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x38 24.--27. " BBA_GAIN_03 ,BBA gain 03" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x38 20.--23. " LNA_GAIN_02 ,LNA gain 02" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x38 16.--19. " BBA_GAIN_02 ,BBA gain 02" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x38 12.--15. " LNA_GAIN_01 ,LNA gain 01" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x38 8.--11. " BBA_GAIN_01 ,BBA gain 01" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x38 4.--7. " LNA_GAIN_00 ,LNA gain 00" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x38 0.--3. " BBA_GAIN_00 ,BBA gain 00" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x3C "AGC_GAIN_TBL_07_04,AGC Gain Tables Step 07-04"
|
|
bitfld.long 0x3C 28.--31. " LNA_GAIN_07 ,LNA gain 07" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x3C 24.--27. " BBA_GAIN_07 ,BBA gain 07" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 20.--23. " LNA_GAIN_06 ,LNA gain 06" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x3C 16.--19. " BBA_GAIN_06 ,BBA gain 06" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 12.--15. " LNA_GAIN_05 ,LNA gain 05" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x3C 8.--11. " BBA_GAIN_05 ,BBA gain 05" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 4.--7. " LNA_GAIN_04 ,LNA gain 04" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x3C 0.--3. " BBA_GAIN_04 ,BBA gain 04" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x40 "AGC_GAIN_TBL_11_08,AGC Gain Tables Step 11-08"
|
|
bitfld.long 0x40 28.--31. " LNA_GAIN_11 ,LNA gain 11" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x40 24.--27. " BBA_GAIN_11 ,BBA gain 11" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x40 20.--23. " LNA_GAIN_10 ,LNA gain 10" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x40 16.--19. " BBA_GAIN_10 ,BBA gain 10" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x40 12.--15. " LNA_GAIN_09 ,LNA gain 09" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x40 8.--11. " BBA_GAIN_09 ,BBA gain 09" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x40 4.--7. " LNA_GAIN_08 ,LNA gain 08" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x40 0.--3. " BBA_GAIN_08 ,BBA gain 08" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x44 "AGC_GAIN_TBL_15_12,AGC Gain Tables Step 15-12"
|
|
bitfld.long 0x44 28.--31. " LNA_GAIN_15 ,LNA gain 15" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x44 24.--27. " BBA_GAIN_15 ,BBA gain 15" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x44 20.--23. " LNA_GAIN_14 ,LNA gain 14" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x44 16.--19. " BBA_GAIN_14 ,BBA gain 14" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x44 12.--15. " LNA_GAIN_13 ,LNA gain 13" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x44 8.--11. " BBA_GAIN_13 ,BBA gain 13" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x44 4.--7. " LNA_GAIN_12 ,LNA gain 12" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x44 0.--3. " BBA_GAIN_12 ,BBA gain 12" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x48 "AGC_GAIN_TBL_19_16,AGC Gain Tables Step 19-16"
|
|
bitfld.long 0x48 28.--31. " LNA_GAIN_19 ,LNA gain 19" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x48 24.--27. " BBA_GAIN_19 ,BBA gain 19" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x48 20.--23. " LNA_GAIN_18 ,LNA gain 18" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x48 16.--19. " BBA_GAIN_18 ,BBA gain 18" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x48 12.--15. " LNA_GAIN_17 ,LNA gain 17" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x48 8.--11. " BBA_GAIN_17 ,BBA gain 17" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x48 4.--7. " LNA_GAIN_16 ,LNA gain 16" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x48 0.--3. " BBA_GAIN_16 ,BBA gain 16" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x4C "AGC_GAIN_TBL_23_20,AGC Gain Tables Step 23-20"
|
|
bitfld.long 0x4C 28.--31. " LNA_GAIN_23 ,LNA gain 23" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
|
|
bitfld.long 0x4C 24.--27. " BBA_GAIN_23 ,BBA gain 23" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x4C 20.--23. " LNA_GAIN_22 ,LNA gain 22" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
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|
bitfld.long 0x4C 16.--19. " BBA_GAIN_22 ,BBA gain 22" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
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|
textline " "
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|
bitfld.long 0x4C 12.--15. " LNA_GAIN_21 ,LNA gain 21" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
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|
bitfld.long 0x4C 8.--11. " BBA_GAIN_21 ,BBA gain 21" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
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|
textline " "
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|
bitfld.long 0x4C 4.--7. " LNA_GAIN_20 ,LNA gain 20" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
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bitfld.long 0x4C 0.--3. " BBA_GAIN_20 ,BBA gain 20" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
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line.long 0x50 "AGC_GAIN_TBL_26_24,AGC Gain Tables Step 26-24"
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bitfld.long 0x50 28.--31. " LNA_GAIN_26 ,LNA gain 26" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
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bitfld.long 0x50 24.--27. " BBA_GAIN_26 ,BBA gain 26" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
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|
textline " "
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bitfld.long 0x50 20.--23. " LNA_GAIN_25 ,LNA gain 25" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
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bitfld.long 0x50 16.--19. " BBA_GAIN_25 ,BBA gain 25" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
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|
textline " "
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bitfld.long 0x50 12.--15. " LNA_GAIN_24 ,LNA gain 24" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
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bitfld.long 0x50 8.--11. " BBA_GAIN_24 ,BBA gain 24" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
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textline " "
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bitfld.long 0x50 4.--7. " LNA_GAIN_23 ,LNA gain 23" "-8.6dB,-3.5dB,2.2dB,13.9dB,19.8dB,22.7dB,28.6dB,34.4dB,39.9dB,45.4dB,?..."
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bitfld.long 0x50 0.--3. " BBA_GAIN_23 ,BBA gain 23" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
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else
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textline " "
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|
width 27.
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|
group.long 0x4C++0x4F
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line.long 0x00 "IQMC_CTRL,IQMC Control"
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hexmask.long.byte 0x00 8.--15. 1. " IQMC_NUM_ITER ,Number of iterations for IQ mismatch calibration"
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bitfld.long 0x00 0. " IQMC_CAL_EN ,IQ mismatch calibration enable" "Disabled,Enabled"
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line.long 0x04 "IQMC_CAL,IQMC Calibration"
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hexmask.long.word 0x04 16.--27. 1. " IQMC_PHASE_ADJ ,IQ mismatch correction phase coefficient"
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hexmask.long.word 0x04 0.--10. 1. " IQMC_GAIN_ADJ ,IQ mismatch correction gain coefficient"
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line.long 0x08 "TCA_AGC_VAL_3_0,TCA AGC Step Values 3-0"
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hexmask.long.byte 0x08 24.--31. 1. " TCA_AGC_VAL_3 ,Value of TCA_AGC step 3 for RSSI calculation"
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hexmask.long.byte 0x08 16.--23. 1. " TCA_AGC_VAL_2 ,Value of TCA_AGC step 2 for RSSI calculation"
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|
textline " "
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hexmask.long.byte 0x08 8.--15. 1. " TCA_AGC_VAL_1 ,Value of TCA_AGC step 1 for RSSI calculation"
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hexmask.long.byte 0x08 0.--7. 1. " TCA_AGC_VAL_1 ,Value of TCA_AGC step 1 for RSSI calculation"
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line.long 0x0C "TCA_AGC_VAL_7_4,TCA AGC Step Values 7-4"
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hexmask.long.byte 0x0C 24.--31. 1. " TCA_AGC_VAL_7 ,Value of TCA_AGC step 7 for RSSI calculation"
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|
hexmask.long.byte 0x0C 16.--23. 1. " TCA_AGC_VAL_6 ,Value of TCA_AGC step 6 for RSSI calculation"
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|
textline " "
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hexmask.long.byte 0x0C 8.--15. 1. " TCA_AGC_VAL_5 ,Value of TCA_AGC step 5 for RSSI calculation"
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|
hexmask.long.byte 0x0C 0.--7. 1. " TCA_AGC_VAL_4 ,Value of TCA_AGC step 4 for RSSI calculation"
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line.long 0x10 "TCA_AGC_VAL_8,TCA AGC Step Values 8"
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hexmask.long.byte 0x10 0.--7. 1. " TCA_AGC_VAL_8 ,Value of TCA_AGC step 8 for RSSI calculation"
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line.long 0x14 "BBF_RES_TUNE_VAL_7_0,BBF Resistor Tune Values 7-0"
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bitfld.long 0x14 28.--31. " BBF_RES_TUNE_VAL_7 ,BBF resistor tune step 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 24.--27. " BBF_RES_TUNE_VAL_6 ,BBF resistor tune step 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
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|
bitfld.long 0x14 20.--23. " BBF_RES_TUNE_VAL_5 ,BBF resistor tune step 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. " BBF_RES_TUNE_VAL_4 ,BBF resistor tune step 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x14 12.--15. " BBF_RES_TUNE_VAL_3 ,BBF resistor tune step 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. " BBF_RES_TUNE_VAL_2 ,BBF resistor tune step 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x14 4.--7. " BBF_RES_TUNE_VAL_1 ,BBF resistor tune step 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 0.--3. " BBF_RES_TUNE_VAL_0 ,BBF resistor tune step 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x18 "BBF_RES_TUNE_VAL_10_8,BBF Resistor Tune Values 10-8"
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bitfld.long 0x18 8.--11. " BBF_RES_TUNE_VAL_10 ,BBF resistor tune step 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 4.--7. " BBF_RES_TUNE_VAL_9 ,BBF resistor tune step 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 0.--3. " BBF_RES_TUNE_VAL_8 ,BBF resistor tune step 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x1C "TCA_AGC_LIN_VAL_2_0,TCA AGC Linear Gain Values 2-0"
|
|
hexmask.long.word 0x1C 20.--29. 1. " TCA_AGC_LIN_VAL_2 ,TCA AGC linear gain step 2"
|
|
hexmask.long.word 0x1C 10.--19. 1. " TCA_AGC_LIN_VAL_1 ,TCA AGC linear gain step 1"
|
|
textline " "
|
|
hexmask.long.word 0x1C 0.--9. 1. " TCA_AGC_LIN_VAL_0 ,TCA AGC linear gain step 0"
|
|
line.long 0x20 "TCA_AGC_LIN_VAL_5_3,TCA AGC Linear Gain Values 5-3"
|
|
hexmask.long.word 0x20 20.--29. 1. " TCA_AGC_LIN_VAL_5 ,TCA AGC linear gain step 5"
|
|
hexmask.long.word 0x20 10.--19. 1. " TCA_AGC_LIN_VAL_4 ,TCA AGC linear gain step 4"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--9. 1. " TCA_AGC_LIN_VAL_3 ,TCA AGC linear gain step 3"
|
|
line.long 0x24 "TCA_AGC_LIN_VAL_8_6,TCA AGC Linear Gain Values 8-6"
|
|
hexmask.long.word 0x24 20.--29. 1. " TCA_AGC_LIN_VAL_8 ,TCA AGC linear gain step 8"
|
|
hexmask.long.word 0x24 10.--19. 1. " TCA_AGC_LIN_VAL_7 ,TCA AGC linear gain step 7"
|
|
textline " "
|
|
hexmask.long.word 0x24 0.--9. 1. " TCA_AGC_LIN_VAL_6 ,TCA AGC linear gain step 6"
|
|
line.long 0x28 "BBF_RES_TUNE_LIN_VAL_3_0,BBF Resistor Tune Values 3-0"
|
|
hexmask.long.byte 0x28 24.--31. 1. " BBF_RES_TUNE_LIN_VAL_3 ,BBF Resistor Tune Linear Gain Step 3"
|
|
hexmask.long.byte 0x28 16.--23. 1. " BBF_RES_TUNE_LIN_VAL_2 ,BBF Resistor Tune Linear Gain Step 2"
|
|
textline " "
|
|
hexmask.long.byte 0x28 8.--15. 1. " BBF_RES_TUNE_LIN_VAL_1 ,BBF Resistor Tune Linear Gain Step 1"
|
|
hexmask.long.byte 0x28 0.--7. 1. " BBF_RES_TUNE_LIN_VAL_0 ,BBF Resistor Tune Linear Gain Step 0"
|
|
line.long 0x2C "BBF_RES_TUNE_LIN_VAL_7_4,BBF Resistor Tune Values 7-4"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " BBF_RES_TUNE_LIN_VAL_7 ,BBF Resistor Tune Linear Gain Step 7"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " BBF_RES_TUNE_LIN_VAL_6 ,BBF Resistor Tune Linear Gain Step 6"
|
|
textline " "
|
|
hexmask.long.byte 0x2C 8.--15. 1. " BBF_RES_TUNE_LIN_VAL_5 ,BBF Resistor Tune Linear Gain Step 5"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " BBF_RES_TUNE_LIN_VAL_4 ,BBF Resistor Tune Linear Gain Step 4"
|
|
line.long 0x30 "BBF_RES_TUNE_LIN_VAL_10_8,BBF Resistor Tune Values 10-8"
|
|
hexmask.long.byte 0x30 16.--23. 1. " BBF_RES_TUNE_LIN_VAL_10 ,BBF Resistor Tune Linear Gain Step 10"
|
|
hexmask.long.byte 0x30 8.--15. 1. " BBF_RES_TUNE_LIN_VAL_9 ,BBF Resistor Tune Linear Gain Step 9"
|
|
textline " "
|
|
hexmask.long.byte 0x30 0.--7. 1. " BBF_RES_TUNE_LIN_VAL_8 ,BBF Resistor Tune Linear Gain Step 8"
|
|
line.long 0x34 "AGC_GAIN_TBL_03_00,AGC Gain Tables Step 03-00"
|
|
bitfld.long 0x34 28.--31. " LNM_GAIN_03 ,LNM gain 03" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
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bitfld.long 0x34 24.--27. " BBF_GAIN_03 ,BBF gain 03" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x34 20.--23. " LNM_GAIN_02 ,LNM gain 02" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
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|
bitfld.long 0x34 16.--19. " BBF_GAIN_02 ,BBF gain 02" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x34 12.--15. " LNM_GAIN_01 ,LNM gain 01" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
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|
bitfld.long 0x34 8.--11. " BBF_GAIN_01 ,BBF gain 01" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x34 4.--7. " LNM_GAIN_00 ,LNM gain 00" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x34 0.--3. " BBF_GAIN_00 ,BBF gain 00" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
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|
line.long 0x38 "AGC_GAIN_TBL_07_04,AGC Gain Tables Step 07-04"
|
|
bitfld.long 0x38 28.--31. " LNM_GAIN_07 ,LNM gain 07" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x38 24.--27. " BBF_GAIN_07 ,BBF gain 07" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x38 20.--23. " LNM_GAIN_06 ,LNM gain 06" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x38 16.--19. " BBF_GAIN_06 ,BBF gain 06" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x38 12.--15. " LNM_GAIN_05 ,LNM gain 05" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x38 8.--11. " BBF_GAIN_05 ,BBF gain 05" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x38 4.--7. " LNM_GAIN_04 ,LNM gain 04" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x38 0.--3. " BBF_GAIN_04 ,BBF gain 04" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x3C "AGC_GAIN_TBL_11_08,AGC Gain Tables Step 11-08"
|
|
bitfld.long 0x3C 28.--31. " LNM_GAIN_11 ,LNM gain 11" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x3C 24.--27. " BBF_GAIN_11 ,BBF gain 11" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 20.--23. " LNM_GAIN_10 ,LNM gain 10" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x3C 16.--19. " BBF_GAIN_10 ,BBF gain 10" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 12.--15. " LNM_GAIN_09 ,LNM gain 09" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x3C 8.--11. " BBF_GAIN_09 ,BBF gain 09" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 4.--7. " LNM_GAIN_08 ,LNM gain 08" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x3C 0.--3. " BBF_GAIN_08 ,BBF gain 08" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x40 "AGC_GAIN_TBL_15_12,AGC Gain Tables Step 15-12"
|
|
bitfld.long 0x40 28.--31. " LNM_GAIN_15 ,LNM gain 15" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x40 24.--27. " BBF_GAIN_15 ,BBF gain 15" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x40 20.--23. " LNM_GAIN_14 ,LNM gain 14" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x40 16.--19. " BBF_GAIN_14 ,BBF gain 14" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x40 12.--15. " LNM_GAIN_13 ,LNM gain 13" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x40 8.--11. " BBF_GAIN_13 ,BBF gain 13" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x40 4.--7. " LNM_GAIN_12 ,LNM gain 12" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x40 0.--3. " BBF_GAIN_12 ,BBF gain 12" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x44 "AGC_GAIN_TBL_19_16,AGC Gain Tables Step 19-16"
|
|
bitfld.long 0x44 28.--31. " LNM_GAIN_19 ,LNM gain 19" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x44 24.--27. " BBF_GAIN_19 ,BBF gain 19" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x44 20.--23. " LNM_GAIN_18 ,LNM gain 18" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x44 16.--19. " BBF_GAIN_18 ,BBF gain 18" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x44 12.--15. " LNM_GAIN_17 ,LNM gain 17" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x44 8.--11. " BBF_GAIN_17 ,BBF gain 17" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x44 4.--7. " LNM_GAIN_16 ,LNM gain 16" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x44 0.--3. " BBF_GAIN_16 ,BBF gain 16" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x48 "AGC_GAIN_TBL_23_20,AGC Gain Tables Step 23-20"
|
|
bitfld.long 0x48 28.--31. " LNM_GAIN_23 ,LNM gain 23" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x48 24.--27. " BBF_GAIN_23 ,BBF gain 23" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x48 20.--23. " LNM_GAIN_22 ,LNM gain 22" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x48 16.--19. " BBF_GAIN_22 ,BBF gain 22" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x48 12.--15. " LNM_GAIN_21 ,LNM gain 21" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x48 8.--11. " BBF_GAIN_21 ,BBF gain 21" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x48 4.--7. " LNM_GAIN_20 ,LNM gain 20" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x48 0.--3. " BBF_GAIN_20 ,BBF gain 20" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
line.long 0x4C "AGC_GAIN_TBL_26_24,AGC Gain Tables Step 26-24"
|
|
bitfld.long 0x4C 28.--31. " LNM_GAIN_26 ,LNM gain 26" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x4C 24.--27. " BBF_GAIN_26 ,BBF gain 26" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x4C 20.--23. " LNM_GAIN_25 ,LNM gain 25" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x4C 16.--19. " BBF_GAIN_25 ,BBF gain 25" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x4C 12.--15. " LNM_GAIN_24 ,LNM gain 24" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x4C 8.--11. " BBF_GAIN_24 ,BBF gain 24" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
textline " "
|
|
bitfld.long 0x4C 4.--7. " LNM_GAIN_23 ,LNM gain 23" "-3dB,3dB,9dB,15dB,21dB,27dB,33dB,39dB,45dB,?..."
|
|
bitfld.long 0x4C 0.--3. " BBF_GAIN_23 ,BBF gain 23" "0dB,3dB,6dB,9dB,12dB,15dB,18dB,21dB,24dB,27dB,30dB,?..."
|
|
endif
|
|
textline " "
|
|
width 19.
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DCOC_OFFSET_00,DCOC Offset 00"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "DCOC_OFFSET_01,DCOC Offset 01"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "DCOC_OFFSET_02,DCOC Offset 02"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "DCOC_OFFSET_03,DCOC Offset 03"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DCOC_OFFSET_04,DCOC Offset 04"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DCOC_OFFSET_05,DCOC Offset 05"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "DCOC_OFFSET_06,DCOC Offset 06"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "DCOC_OFFSET_07,DCOC Offset 07"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DCOC_OFFSET_08,DCOC Offset 08"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DCOC_OFFSET_09,DCOC Offset 09"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DCOC_OFFSET_10,DCOC Offset 10"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "DCOC_OFFSET_11,DCOC Offset 11"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DCOC_OFFSET_12,DCOC Offset 12"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "DCOC_OFFSET_13,DCOC Offset 13"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DCOC_OFFSET_14,DCOC Offset 14"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "DCOC_OFFSET_15,DCOC Offset 15"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DCOC_OFFSET_16,DCOC Offset 16"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DCOC_OFFSET_17,DCOC Offset 17"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "DCOC_OFFSET_18,DCOC Offset 18"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "DCOC_OFFSET_19,DCOC Offset 19"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DCOC_OFFSET_20,DCOC Offset 20"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DCOC_OFFSET_21,DCOC Offset 21"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "DCOC_OFFSET_22,DCOC Offset 22"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DCOC_OFFSET_23,DCOC Offset 23"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DCOC_OFFSET_24,DCOC Offset 24"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DCOC_OFFSET_25,DCOC Offset 25"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DCOC_OFFSET_26,DCOC Offset 26"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " DCOC_TZA_OFFSET_Q ,DCOC TZA Q-channel offset"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " DCOC_TZA_OFFSET_I ,DCOC TZA I-channel offset"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 8.--13. " DCOC_BBA_OFFSET_Q ,DCOC BBA Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBA_OFFSET_I ,DCOC BBA I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 8.--13. " DCOC_BBF_OFFSET_Q ,DCOC BBF Q-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DCOC_BBF_OFFSET_I ,DCOC BBF I-channel offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DCOC_BBA_STEP,DCOC BBA DAC Step"
|
|
hexmask.long.word 0x00 16.--24. 1. " BBA_DCOC_STEP ,DCOC BBA step size"
|
|
hexmask.long.word 0x00 0.--12. 1. " BBA_DCOC_STEP_RECIP ,DCOC BBA reciprocal step size"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_0,DCOC TZA DC Step 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN_0 ,DCOC TZA step 0 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_0 ,DCOC TZA step 0 gain"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_1,DCOC TZA DC Step 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN_1 ,DCOC TZA step 1 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_1 ,DCOC TZA step 1 gain"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_2,DCOC TZA DC Step 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN_2 ,DCOC TZA step 2 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_2 ,DCOC TZA step 2 gain"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_3,DCOC TZA DC Step 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN_3 ,DCOC TZA step 3 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_3 ,DCOC TZA step 3 gain"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_4,DCOC TZA DC Step 4"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN_4 ,DCOC TZA step 4 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_4 ,DCOC TZA step 4 gain"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_5,DCOC TZA DC Step 5"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN_5 ,DCOC TZA step 5 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_5 ,DCOC TZA step 5 gain"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_6,DCOC TZA DC Step 6"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN_6 ,DCOC TZA step 6 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_6 ,DCOC TZA step 6 gain"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_7,DCOC TZA DC Step 7"
|
|
hexmask.long.word 0x00 16.--28. 1. " DCOC_TZA_STEP_GAIN_7 ,DCOC TZA step 7 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_7 ,DCOC TZA step 7 gain"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_8,DCOC TZA DC Step 8"
|
|
hexmask.long.word 0x00 16.--28. 1. " DCOC_TZA_STEP_GAIN_8 ,DCOC TZA step 8 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_8 ,DCOC TZA step 8 gain"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_9,DCOC TZA DC Step 9"
|
|
hexmask.long.word 0x00 16.--29. 1. " DCOC_TZA_STEP_GAIN_9 ,DCOC TZA step 9 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_9 ,DCOC TZA step 9 gain"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_10,DCOC TZA DC Step 10"
|
|
hexmask.long.word 0x00 16.--29. 1. " DCOC_TZA_STEP_GAIN_10 ,DCOC TZA step 10 gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP_10 ,DCOC TZA step 10 gain"
|
|
rgroup.long 0x168++0x0F
|
|
line.long 0x00 "DCOC_CAL_ALPHA,DCOC Calibration Alpha"
|
|
hexmask.long.word 0x00 16.--26. 1. " DCOC_CAL_ALPHA_Q ,DCOC calibration Q-channel alpha"
|
|
hexmask.long.word 0x00 0.--10. 1. " DCOC_CAL_ALPHA_I ,DCOC calibration I-channel alpha"
|
|
line.long 0x04 "DCOC_CAL_BETA_Q,DCOC Calibration Beta Q"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " DCOC_CAL_BETA_Q ,DCOC calibration Q-channel beta"
|
|
line.long 0x08 "DCOC_CAL_BETA_I,DCOC Calibration Beta I"
|
|
hexmask.long.tbyte 0x08 0.--16. 1. " DCOC_CAL_BETA_I ,DCOC calibration I-channel beta"
|
|
line.long 0x0C "DCOC_CAL_GAMMA,DCOC Calibration Gamma"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DCOC_CAL_GAMMA_Q ,DCOC calibration Q-channel gamma"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DCOC_CAL_GAMMA_I ,DCOC calibration I-channel gamma"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_00,DCOC TZA DC Step 00"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_01,DCOC TZA DC Step 01"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_02,DCOC TZA DC Step 02"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_03,DCOC TZA DC Step 03"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_04,DCOC TZA DC Step 04"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_05,DCOC TZA DC Step 05"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_06,DCOC TZA DC Step 06"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_07,DCOC TZA DC Step 07"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_08,DCOC TZA DC Step 08"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_09,DCOC TZA DC Step 09"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DCOC_TZA_STEP_10,DCOC TZA DC Step 10"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_TZA_STEP_GAIN ,DCOC TZA step gain"
|
|
hexmask.long.word 0x00 0.--12. 1. " DCOC_TZA_STEP_RCP ,DCOC TZA step gain"
|
|
rgroup.long 0x16C++0x0B
|
|
line.long 0x00 "DCOC_CAL_ALPHA,DCOC Calibration Alpha"
|
|
hexmask.long.word 0x00 16.--31. 1. " DCOC_CAL_ALPHA_Q ,DCOC calibration Q-channel alpha"
|
|
hexmask.long.word 0x00 0.--15. 1. " DCOC_CAL_ALPHA_I ,DCOC calibration I-channel alpha"
|
|
line.long 0x04 "DCOC_CAL_BETA,DCOC Calibration Beta"
|
|
hexmask.long.word 0x04 16.--31. 1. " DCOC_CAL_BETA_Q ,DCOC calibration Q-channel beta"
|
|
hexmask.long.word 0x04 0.--15. 1. " DCOC_CAL_BETA_I ,DCOC calibration I-channel beta"
|
|
line.long 0x08 "DCOC_CAL_GAMMA,DCOC Calibration Gamma"
|
|
hexmask.long.word 0x08 16.--31. 1. " DCOC_CAL_GAMMA_Q ,DCOC calibration Q-channel gamma"
|
|
hexmask.long.word 0x08 0.--15. 1. " DCOC_CAL_GAMMA_I ,DCOC calibration I-channel gamma"
|
|
endif
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "DCOC_CAL_IIR,DCOC Calibration IIR"
|
|
bitfld.long 0x00 4.--5. " DCOC_CAL_IIR3A_IDX ,DCOC calibration IIR 3A index" "1/4,1/8,1/16,1/32"
|
|
bitfld.long 0x00 2.--3. " DCOC_CAL_IIR2A_IDX ,DCOC calibration IIR 2A index" "1/1,1/4,1/8,1/16"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DCOC_CAL_IIR1A_IDX ,DCOC calibration IIR 1A index" "1/1,1/4,1/8,1/16"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "DCOC_CAL1,DCOC Calibration Result 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_CAL_RES_Q ,DCOC calibration result Q channel"
|
|
hexmask.long.word 0x00 0.--11. 1. " DCOC_CAL_RES_I ,DCOC calibration result I channel"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "DCOC_CAL2,DCOC Calibration Result 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_CAL_RES_Q ,DCOC calibration result Q channel"
|
|
hexmask.long.word 0x00 0.--11. 1. " DCOC_CAL_RES_I ,DCOC calibration result I channel"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "DCOC_CAL3,DCOC Calibration Result 3"
|
|
hexmask.long.word 0x00 16.--27. 1. " DCOC_CAL_RES_Q ,DCOC calibration result Q channel"
|
|
hexmask.long.word 0x00 0.--11. 1. " DCOC_CAL_RES_I ,DCOC calibration result I channel"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
group.long 0x190++0x07
|
|
line.long 0x00 "CCA_ED_LQI_CTRL_0,RX DIG CCA ED LQI Control Register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LQI_CNTR ,LQI counter"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CORR_CNTR_THRESH ,Correlation count threshold"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LQI_CORR_THRESH ,LQI correlation threshold"
|
|
line.long 0x04 "CCA_ED_LQI_CTRL_1,RX DIG CCA ED LQI Control Register 1"
|
|
bitfld.long 0x04 28.--31. " LQI_BIAS ,LQI Bias" "-36,-34,-32,-30,-28,-26,-24,-22,-20,-18,-16,-14,-12,-10,-8,-6"
|
|
bitfld.long 0x04 24.--27. " SNR_LQI_WEIGHT ,SNR LQI Weight" "0.0,1.0,1.125,1.25,1.375,1.5,1.625,1.75,1.875,2.0,2.125,2.25,2.375,2.5,2.625,2.75"
|
|
textline " "
|
|
bitfld.long 0x04 21. " MAN_AA_MATCH ,Manual AA match" "Normal,Manual"
|
|
bitfld.long 0x04 20. " MAN_MEAS_COMPLETE ,Manual measurement complete" "Normal,Manual"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CCA1_ED_EN_DIS ,CCA1 ED EN disable" "No,Yes"
|
|
bitfld.long 0x04 18. " MEAS_TRANS_TO_IDLE ,Measurement transition to IDLE" "RSSI state,IDLE state"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SNR_LQI_DIS ,SNR LQI disable" "No,Yes"
|
|
bitfld.long 0x04 12.--15. " LQI_RSSI_SENS ,LQI RSSI sensitivity" "-103,-102,-101,-100,-99,-98,-97,-96,-95,-94,-93,-92,-91,-90,-89,-88"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " LQI_RSSI_WEIGHT ,LQI RSSI weight" "2.0,2.125,2.25,2.375,2.5,2.625,2.75,2.875"
|
|
bitfld.long 0x04 6.--8. " LQI_RSSI_WEIGHT ,RSSI noise averaging factor" "1,64,70,128,139,256,277,512"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " RSSI_NOISE_AVG_DELAY ,RSSI noise averaging delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "CCA_ED_LQI_STAT_0,RX DIG CCA ED LQI Status Register 0"
|
|
bitfld.long 0x00 25. " MEAS_COMPLETE ,Measurement complete" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " CCA1_STATE ,CCA1 state" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " SNR_OUT ,SNR output"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ED_OUT ,ED output"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LQI_OUT ,LQI output"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "RX_CHF_COEF0,Receive Channel Filter Coefficient 0"
|
|
bitfld.long 0x00 0.--5. " RX_CH_FILT_H0 ,RX channel filter coefficient 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "RX_CHF_COEF1,Receive Channel Filter Coefficient 1"
|
|
bitfld.long 0x00 0.--5. " RX_CH_FILT_H1 ,RX channel filter coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "RX_CHF_COEF2,Receive Channel Filter Coefficient 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RX_CH_FILT_H2 ,RX channel filter coefficient 2"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "RX_CHF_COEF3,Receive Channel Filter Coefficient 3"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RX_CH_FILT_H3 ,RX channel filter coefficient 3"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "RX_CHF_COEF4,Receive Channel Filter Coefficient 4"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RX_CH_FILT_H4 ,RX channel filter coefficient 4"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "RX_CHF_COEF5,Receive Channel Filter Coefficient 5"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RX_CH_FILT_H5 ,RX channel filter coefficient 5"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "RX_CHF_COEF6,Receive Channel Filter Coefficient 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_H6 ,RX channel filter coefficient 6"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "RX_CHF_COEF7,Receive Channel Filter Coefficient 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_H7 ,RX channel filter coefficient 7"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "RX_CHF_COEF8,Receive Channel Filter Coefficient 8"
|
|
hexmask.long.word 0x00 0.--8. 1. " RX_CH_FILT_H8 ,RX channel filter coefficient 8"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "RX_CHF_COEF9,Receive Channel Filter Coefficient 9"
|
|
hexmask.long.word 0x00 0.--8. 1. " RX_CH_FILT_H9 ,RX channel filter coefficient 9"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "RX_CHF_COEF10,Receive Channel Filter Coefficient 10"
|
|
hexmask.long.word 0x00 0.--9. 1. " RX_CH_FILT_H10 ,RX channel filter coefficient 10"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "RX_CHF_COEF11,Receive Channel Filter Coefficient 11"
|
|
hexmask.long.word 0x00 0.--9. 1. " RX_CH_FILT_H11 ,RX channel filter coefficient 11"
|
|
group.long 0x1D0++0x07
|
|
line.long 0x00 "AGC_MAN_AGC_IDX,AGC Manual AGC Index"
|
|
bitfld.long 0x00 25. " AGC_DCOC_START_PT ,AGC DCOC start point" "Index 26,AGC_MAN_IDX"
|
|
bitfld.long 0x00 24. " AGC_MAN_IDX_EN ,AGC manual index enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " AGC_MAN_IDX ,AGC manual index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
line.long 0x04 "DC_RESID_CTRL,DC Residual Control"
|
|
bitfld.long 0x04 24.--28. " DC_RESID_MIN_AGC_IDX ,DC residual minimum AGC table index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x04 20. " DC_RESID_EXT_DC_EN ,DC residual external DC enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " DC_RESID_DLY ,DC residual delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--14. " DC_RESID_ALPHA ,DC residual alpha" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DC_RESID_ITER_FREEZE ,DC residual iteration freeze" ",1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.byte 0x04 0.--6. 1. " DC_RESID_NWIN ,DC residual NWIN"
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "DC_RESID_EST,DC Residual Estimate"
|
|
hexmask.long.word 0x00 16.--28. 0x01 " DC_RESID_OFFSET_Q ,DC residual offset Q"
|
|
hexmask.long.word 0x00 0.--12. 0x01 " DC_RESID_OFFSET_I ,DC residual offset I"
|
|
group.long 0x1DC++0x0F
|
|
line.long 0x00 "RX_RCCAL_CTRL0,RX RC Calibration Control0"
|
|
bitfld.long 0x00 25. " TZA_RCCAL_DIS ,TZA RC calibration disable" "No,Yes"
|
|
bitfld.long 0x00 20.--24. " TZA_RCCAL_MANUAL ,TZA RC calibration manual value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TZA_RCCAL_OFFSET ,TZA RC calibration value offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RCCAL_COMP_INV ,RC calibration comp_out Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RCCAL_SMP_DLY ,RC calibration sample delay" "0 clk cycle,1 clk cycle,2 clk cycle,3 clk cycle"
|
|
bitfld.long 0x00 9. " BBA_RCCAL_DIS ,BBA RC calibration disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--8. " BBA_RCCAL_MANUAL ,BBA RC calibration manual value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " BBA_RCCAL_OFFSET ,BBA RC calibration value offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "RX_RCCAL_CTRL1,RX RC Calibration Control1"
|
|
bitfld.long 0x04 25. " BBA2_RCCAL_DIS ,BBA2 RC calibration disable" "No,Yes"
|
|
bitfld.long 0x04 20.--24. " BBA2_RCCAL_MANUAL ,BBA2 RC calibration manual value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " BBA2_RCCAL_OFFSET ,BBA2 RC calibration value offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 9. " ADC_RCCAL_DIS ,ADC RC calibration disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4.--8. " ADC_RCCAL_MANUAL ,ADC RC calibration manual value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--3. " ADC_RCCAL_OFFSET ,ADC RC calibration value offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "RX_RCCAL_STAT,RX RC Calibration Status"
|
|
bitfld.long 0x08 21.--25. " TZA_RCCAL ,TZA RC calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " BBA_RCCAL ,BBA RC calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 10.--14. " BBA2_RCCAL ,BBA2 RC calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 5.--9. " ADC_RCCAL ,ADC RC calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 0.--4. " RCCAL_CODE ,RC calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "AUXPLL_FCAL_CTRL,Aux PLL Frequency Calibration Control"
|
|
hexmask.long.byte 0x0C 16.--22. 1. " DAC_CAL_ADJUST ,Aux PLL DAC calibration adjust value"
|
|
bitfld.long 0x0C 10.--11. " FCAL_SMP_DLY ,Aux PLL frequency calibration sample delay" "1 clk cycle,2 clk cycle,3 clk cycle,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 9. " FCAL_COMP_INV ,Aux PLL frequency calibration comparison invert" "Not inverted,Inverted"
|
|
bitfld.long 0x0C 8. " FCAL_RUN_CNT ,Aux PLL frequency calibration run count" "256 clock cycles,512 clock cycles"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " AUXPLL_DAC_CAL_ADJUST_DIS ,Aux PLL frequency calibration disable" "No,Yes"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " DAC_CAL_ADJUST_MANUAL ,Aux PLL Frequency DAC calibration adjust manual value"
|
|
textline " "
|
|
width 20.
|
|
rgroup.long 0x1EC++0x0F
|
|
line.long 0x00 "AUXPLL_FCAL_CNT6,Aux PLL Frequency Calibration Count 6"
|
|
hexmask.long.word 0x00 16.--25. 1. " FCAL_BESTDIFF ,Aux PLL frequency calibration best difference"
|
|
hexmask.long.word 0x00 0.--9. 1. " FCAL_COUNT_6 ,Aux PLL frequency calibration count 6"
|
|
line.long 0x04 "AUXPLL_FCAL_CNT5_4,Aux PLL Frequency Calibration Count 5 And 4"
|
|
hexmask.long.word 0x04 16.--25. 1. " FCAL_COUNT_5 ,Aux PLL frequency calibration count 5"
|
|
hexmask.long.word 0x04 0.--9. 1. " FCAL_COUNT_4 ,Aux PLL frequency calibration count 4"
|
|
line.long 0x08 "AUXPLL_FCAL_CNT3_2,Aux PLL Frequency Calibration Count 3 And 2"
|
|
hexmask.long.word 0x08 16.--25. 1. " FCAL_COUNT_3 ,Aux PLL frequency calibration count 3"
|
|
hexmask.long.word 0x08 0.--9. 1. " FCAL_COUNT_2 ,Aux PLL frequency calibration count 2"
|
|
line.long 0x0C "AUXPLL_FCAL_CNT1_0,Aux PLL Frequency Calibration Count 1 And 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " FCAL_COUNT_1 ,Aux PLL frequency calibration count 1"
|
|
hexmask.long.word 0x0C 0.--9. 1. " FCAL_COUNT_0 ,Aux PLL frequency calibration count 0"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "RX_CHF_COEF0,Receive Channel Filter Coefficient 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_HX ,RX channel filter coefficient"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "RX_CHF_COEF1,Receive Channel Filter Coefficient 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_HX ,RX channel filter coefficient"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "RX_CHF_COEF2,Receive Channel Filter Coefficient 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_HX ,RX channel filter coefficient"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "RX_CHF_COEF3,Receive Channel Filter Coefficient 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_HX ,RX channel filter coefficient"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "RX_CHF_COEF4,Receive Channel Filter Coefficient 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_HX ,RX channel filter coefficient"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "RX_CHF_COEF5,Receive Channel Filter Coefficient 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_HX ,RX channel filter coefficient"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "RX_CHF_COEF6,Receive Channel Filter Coefficient 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_HX ,RX channel filter coefficient"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "RX_CHF_COEF7,Receive Channel Filter Coefficient 7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_CH_FILT_HX ,RX channel filter coefficient"
|
|
endif
|
|
textline " "
|
|
width 18.
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
if (((per.l(ad:0x4005C000+0x200))&0x0F)==(0x03||0x05||0x07||0x08))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TX_DIG_CTRL,TX Digital Control"
|
|
hexmask.long.word 0x00 22.--31. 1. " FREQ_WORD_ADJ ,GFSK frequency word adjustment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TX_CAPTURE_POL ,Polarity of the Input Data for the Transmitter" "Normal,Inverted"
|
|
bitfld.long 0x00 12.--13. " SOC_TEST_SEL ,Radio Clock Selector for SoC RF Clock Tests" "No clock,PLL Sigma Delta/2,Auxiliary PLL/2,RF Ref Osc/2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " DFT_CLK_SEL ,DFT clock selection" "62.5kHz,125kHz,250kHz,500kHz,1MHz,2MHz,4MHz,Clock off"
|
|
bitfld.long 0x00 7. " LFSR_EN ,DFT LFSR enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " LFSR_LENGTH ,LFSR length" "LFSR 9,LFSR 10,LFSR 11,LFSR 13,LFSR 15,LFSR 17,?..."
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Radio DFT modes" "Normal radio operation,Pattern register mode,LFSR data mode,LFSR symbol mode,,Constant frequency mode,LFSR tone mode,Manual tone mode"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TX_DIG_CTRL,TX Digital Control"
|
|
hexmask.long.word 0x00 22.--31. 1. " FREQ_WORD_ADJ ,GFSK frequency word adjustment"
|
|
bitfld.long 0x00 16. " TX_CAPTURE_POL ,Polarity of the Input Data for the Transmitter" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SOC_TEST_SEL ,Radio Clock Selector for SoC RF Clock Tests" "No clock,PLL Sigma Delta/2,Auxiliary PLL/2,RF Ref Osc/2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_DFT_EN ,DFT Modulation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " DFT_CLK_SEL ,DFT clock selection" "62.5kHz,125kHz,250kHz,500kHz,1MHz,2MHz,4MHz,Clock off"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " LFSR_LENGTH ,LFSR length" "LFSR 9,LFSR 10,LFSR 11,LFSR 13,LFSR 15,LFSR 17,?..."
|
|
bitfld.long 0x00 0.--3. " DFT_MODE ,Radio DFT modes" "Normal radio operation,Carrier frequency only,Pattern register GFSK,Pattern register FSK,LFSR FSK,Pattern register O-QPSK,LFSR O-QPSK,LFSR 802.15.4,PLL modulation from RAM,PLL coarse tune BIST,PLL frequency synthesizer BIST,High port DAC BIST,VCO frequency meter,?..."
|
|
endif
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TX_DATA_PAD_PAT,TX Data Padding Pattern"
|
|
bitfld.long 0x00 31. " LRM ,LFSR reset mask" "Reset,No reset"
|
|
hexmask.long.word 0x00 16.--30. 1. " DFT_LFSR_OUT ,Transmit DFT LFSR output"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_PADDING_PATTERN_1 ,Data padding pattern 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA_PADDING_PATTERN_0 ,Data padding pattern 0"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TX_GFSK_MOD_CTRL,TX GFSK Modulation Control"
|
|
bitfld.long 0x00 31. " TX_IMAGE_FILTER_2_OVRD ,TX image filter 2 override control" "Off,On"
|
|
bitfld.long 0x00 30. " TX_IMAGE_FILTER_1_OVRD ,TX image filter 2 override control" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 29. " TX_IMAGE_FILTER_0_OVRD ,TX image filter 2 override control" "Off,On"
|
|
bitfld.long 0x00 28. " TX_IMAGE_FILTER_OVRD_EN ,TX image filter Override Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GFSK_MOD_INDEX_SCALING ,GFSK modulation index scaling factor" "1,1 + 1/32,1 + 1/16,1 + 1/8,1 - 1/32,1 - 1/16,1 - 1/8,"
|
|
bitfld.long 0x00 21. " GFSK_FLD ,Disable GFSK filter lookup table" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GFSK_MLD ,Disable GFSK multiply lookup table" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " GFSK_MI ,GFSK modulation index" "0.32,0.50,0.80,1.00"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GFSK_MULTIPLY_TABLE_MANUAL ,GFSK multiply lookup table override value"
|
|
if (((per.l(ad:0x4005C000+0x208))&0x200000)==0x200000)
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "TX_GFSK_COEFF2,TX GFSK Filter Coefficients 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " GFSK_FILTER_COEFF_MANUAL2[63:56] ,Filter coeff 5 and 10"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " GFSK_FILTER_COEFF_MANUAL2[55:48] ,Filter coeff 4 and 11"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " GFSK_FILTER_COEFF_MANUAL2[45:40] ,Filter coeff 1 and 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " GFSK_FILTER_COEFF_MANUAL2[36:32] ,Filter coeff 0 and 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TX_GFSK_COEFF1,TX GFSK Filter Coefficients 1"
|
|
hexmask.long.word 0x04 23.--31. 1. " GFSK_FILTER_COEFF_MANUAL1[31:23] ,Filter coeff 7 and 8"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--22. 1. " GFSK_FILTER_COEFF_MANUAL1[22:16] ,Filter coeff 3 and 12"
|
|
textline " "
|
|
hexmask.long.word 0x04 7.--15. 1. " GFSK_FILTER_COEFF_MANUAL1[15:7] ,Filter coeff 6 and 9"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " GFSK_FILTER_COEFF_MANUAL1[6:0] ,Filter coeff 2 and 13"
|
|
else
|
|
hgroup.long 0x20C++0x07
|
|
hide.long 0x00 "TX_GFSK_COEFF2,TX GFSK Filter Coefficients 2"
|
|
hide.long 0x04 "TX_GFSK_COEFF1,TX GFSK Filter Coefficients 1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4005C000+0x200))&0x07)==0x07)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TX_DIG_CTRL,TX Digital Control"
|
|
hexmask.long.word 0x00 22.--31. 1. " FREQ_WORD_ADJ ,GFSK frequency word adjustment"
|
|
bitfld.long 0x00 20. " DP_SEL ,Data padding pattern select" "DATA_PADDING_PATTERN_0,DATA_PADDING_PATTERN_1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL ,Oversample clock capture polarity" "Even,Odd"
|
|
bitfld.long 0x00 12.--13. " TONE_SEL ,DFT tone selection" "Tone 0,Tone 1,Tone 2,Tone 3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Radio DFT modes" "Normal radio operation,Pattern register mode,LFSR data mode,LFSR symbol mode,,Constant frequency mode,LFSR tone mode,Manual tone mode"
|
|
elif (((per.l(ad:0x4005C000+0x200))&0x07)==0x01)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TX_DIG_CTRL,TX Digital Control"
|
|
hexmask.long.word 0x00 22.--31. 1. " FREQ_WORD_ADJ ,GFSK frequency word adjustment"
|
|
bitfld.long 0x00 20. " DP_SEL ,Data padding pattern select" "DATA_PADDING_PATTERN_0,DATA_PADDING_PATTERN_1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL ,Oversample clock capture polarity" "Even,Odd"
|
|
bitfld.long 0x00 8.--10. " DFT_CLK_SEL ,DFT clock selection" "62.5kHz,125kHz,250kHz,500kHz,1MHz,2MHz,4MHz,Clock off"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DFT_LFSR_LEN ,DFT LFSR length" "LFSR 9,LFSR 10,LFSR 11,LFSR 13,LFSR 15,LFSR 17,?..."
|
|
bitfld.long 0x00 3. " DFT_EN ,Radio DFT mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Radio DFT modes" "Normal radio operation,Pattern register mode,LFSR data mode,LFSR symbol mode,,Constant frequency mode,LFSR tone mode,Manual tone mode"
|
|
elif (((per.l(ad:0x4005C000+0x200))&0x07)==(0x02||0x03||0x06))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TX_DIG_CTRL,TX Digital Control"
|
|
hexmask.long.word 0x00 22.--31. 1. " FREQ_WORD_ADJ ,GFSK frequency word adjustment"
|
|
bitfld.long 0x00 20. " DP_SEL ,Data padding pattern select" "DATA_PADDING_PATTERN_0,DATA_PADDING_PATTERN_1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL ,Oversample clock capture polarity" "Even,Odd"
|
|
bitfld.long 0x00 7. " LFSR_EN ,DFT LFSR enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DFT_LFSR_LEN ,DFT LFSR length" "LFSR 9,LFSR 10,LFSR 11,LFSR 13,LFSR 15,LFSR 17,?..."
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Radio DFT modes" "Normal radio operation,Pattern register mode,LFSR data mode,LFSR symbol mode,,Constant frequency mode,LFSR tone mode,Manual tone mode"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TX_DIG_CTRL,TX Digital Control"
|
|
hexmask.long.word 0x00 22.--31. 1. " FREQ_WORD_ADJ ,GFSK frequency word adjustment"
|
|
bitfld.long 0x00 20. " DP_SEL ,Data padding pattern select" "DATA_PADDING_PATTERN_0,DATA_PADDING_PATTERN_1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " POL ,Oversample clock capture polarity" "Even,Odd"
|
|
bitfld.long 0x00 4.--6. " DFT_LFSR_LEN ,DFT LFSR length" "LFSR 9,LFSR 10,LFSR 11,LFSR 13,LFSR 15,LFSR 17,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Radio DFT modes" "Normal radio operation,Pattern register mode,LFSR data mode,LFSR symbol mode,,Constant frequency mode,LFSR tone mode,Manual tone mode"
|
|
endif
|
|
if (((per.l(ad:0x4005C000)+0x200)&0x80000000)==0x80000000)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TX_DATA_PAD_PAT,TX Data Padding Pattern"
|
|
bitfld.long 0x00 31. " LRM ,LFSR reset mask" "Reset,No reset"
|
|
hexmask.long.word 0x00 16.--30. 1. " DFT_LFSR_OUT ,Transmit DFT LFSR output"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA_PADDING_PATTERN_0 ,Data padding pattern 0"
|
|
else
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TX_DATA_PAD_PAT,TX Data Padding Pattern"
|
|
bitfld.long 0x00 31. " LRM ,LFSR reset mask" "Reset,No reset"
|
|
hexmask.long.word 0x00 16.--30. 1. " DFT_LFSR_OUT ,Transmit DFT LFSR output"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_PADDING_PATTERN_1 ,Data padding pattern 1"
|
|
endif
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TX_GFSK_MOD_CTRL,TX GFSK Modulation Control"
|
|
bitfld.long 0x00 28. " GFSK_FLD ,GFSK filter lookup table disable" "No,Yes"
|
|
bitfld.long 0x00 24.--26. " GFSK_SYMBOL_RATE ,GFSK symbol rate" "50 kHz,100 kHz,200 kHz,1 MHz,2 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " GFSK_MLD ,GFSK multiply lookup table disable" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " GFSK_MI ,GFSK modulation index" "0.32,0.50,0.80,1.00"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GFSK_MULTIPLY_TABLE_MANUAL ,GFSK multiply lookup table override value"
|
|
if (((per.l(ad:0x4005C000+0x208))&0x10000000)==0x10000000)
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "TX_GFSK_COEFF2,TX GFSK Filter Coefficients 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " GFSK_FILTER_COEFF_MANUAL2[63:56] ,Filter coeff 5 and 10"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " GFSK_FILTER_COEFF_MANUAL2[55:48] ,Filter coeff 4 and 11"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " GFSK_FILTER_COEFF_MANUAL2[45:40] ,Filter coeff 1 and 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " GFSK_FILTER_COEFF_MANUAL2[36:32] ,Filter coeff 0 and 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TX_GFSK_COEFF1,TX GFSK Filter Coefficients 1"
|
|
hexmask.long.word 0x04 23.--31. 1. " GFSK_FILTER_COEFF_MANUAL1[31:23] ,Filter coeff 7 and 8"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--22. 1. " GFSK_FILTER_COEFF_MANUAL1[22:16] ,Filter coeff 3 and 12"
|
|
textline " "
|
|
hexmask.long.word 0x04 7.--15. 1. " GFSK_FILTER_COEFF_MANUAL1[15:7] ,Filter coeff 6 and 9"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " GFSK_FILTER_COEFF_MANUAL1[6:0] ,Filter coeff 2 and 13"
|
|
else
|
|
hgroup.long 0x20C++0x07
|
|
hide.long 0x00 "TX_GFSK_COEFF2,TX GFSK Filter Coefficients 2"
|
|
hide.long 0x04 "TX_GFSK_COEFF1,TX GFSK Filter Coefficients 1"
|
|
endif
|
|
endif
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "TX_FSK_MOD_SCALE,TX FSK Modulation Scale"
|
|
hexmask.long.word 0x00 16.--28. 1. " FSK_MODULATION_SCALE_1 ,FSK modulation scale for a data 1"
|
|
hexmask.long.word 0x00 0.--12. 1. " FSK_MODULATION_SCALE_0 ,FSK modulation scale for a data 0"
|
|
line.long 0x04 "TX_DFT_MOD_PAT,TX DFT Modulation Pattern"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
group.long 0x21C++0x07
|
|
line.long 0x00 "TX_DFT_TONE_0_1,TX DFT Tones 0 and 1"
|
|
hexmask.long.word 0x00 16.--28. 1. " DFT_TONE_0 ,DFT tone 0"
|
|
hexmask.long.word 0x00 0.--12. 1. " DFT_TONE_1 ,DFT tone 1"
|
|
line.long 0x04 "TX_DFT_TONE_2_3,TX DFT Tones 2 and 3"
|
|
hexmask.long.word 0x04 16.--28. 1. " DFT_TONE_2 ,DFT tone 2"
|
|
hexmask.long.word 0x04 0.--12. 1. " DFT_TONE_3 ,DFT tone 3"
|
|
endif
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
group.long 0x224++0x13
|
|
line.long 0x00 "HPM_BUMP,PLL HPM Analog Bump Control"
|
|
bitfld.long 0x00 12.--13. " HPM_FDB_RES_CAL ,HPM FDB RES during calibration" "29 kohms,58 kohms,13 kohms,23.7 kohms"
|
|
bitfld.long 0x00 8.--9. " HPM_FDB_RES_TX ,HPM FDB RES during transmission" "29 kohms,58 kohms,13 kohms,23.7 kohms"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " HPM_VCM_CAL ,HPM VCM during calibration" "432 mV,328 mV,456 mV,473 mV,488 mV,408 mV,392 mV,376 mV"
|
|
bitfld.long 0x00 0.--2. " HPM_VCM_TX ,HPM VCM during radio transmission" "432 mV,328 mV,456 mV,473 mV,488 mV,408 mV,392 mV,376 mV"
|
|
line.long 0x04 "MOD_CTRL,PLL Modulation Control"
|
|
bitfld.long 0x04 31. " HPM_SDM_OUT_DISABLE ,Disable HPM SDM out" "No,Yes"
|
|
bitfld.long 0x04 28.--29. " HPM_SDM_OUT_MANUAL ,Manual HPM SDM out" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HPM_MOD_DISABLE ,Disable HPM modulation" "No,Yes"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HPM_MOD_MANUAL ,Manual HPM modulation"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MOD_DISABLE ,Disable modulation word" "No,Yes"
|
|
hexmask.long.word 0x04 0.--12. 1. " MODULATION_WORD_MANUAL ,Manual modulation word"
|
|
line.long 0x08 "CHAN_MAP,PLL Channel Mapping"
|
|
sif (cpuis("MKW21*")||cpuis("MKW41*"))
|
|
bitfld.long 0x08 10. " ZOC ,802.15.4 channel number override" "Number comes from the 802.15.4 link layer,Number comes from the CHANNEL_NUM register"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW41*")||cpuis("MKW31*"))
|
|
bitfld.long 0x08 9. " BMR ,BLE MBAN channel remap" "Mapped to BLE channel 39/2.480 GHz,Mapped to MBAN channel 39/2.399 GHz"
|
|
textline " "
|
|
bitfld.long 0x08 8. " BOC ,BLE channel number override" "From BLE link layer,From the CHANNEL_NUM register"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x08 0.--6. 1. " CHANNEL_NUM ,Protocol specific channel number for PLL frequency mapping"
|
|
line.long 0x0C "LOCK_DETECT,PLL Lock Detect Control"
|
|
bitfld.long 0x0C 30.--31. " FREQ_COUNT_TIME ,Frequency meter count time" "10 us,25 us,50 us,100 us"
|
|
rbitfld.long 0x0C 29. " FREQ_COUNT_FINISHED ,Frequency meter has finished the count time" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " FREQ_COUNT_GO ,Start the frequency meter" "Not started,Started"
|
|
bitfld.long 0x0C 27. " FTW_TX ,TX frequency target window time select" "4 us,8 us"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--25. " FTF_TX_THRSH ,TX Frequency target fail threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 19. " FTW_RX ,RX Frequency target window time select" "4 us,8 us"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--17. " FTF_RX_THRSH ,RX frequency target fail threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 8.--11. " CTUNE_LDF_LEV ,CTUNE lock detect fail level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " TAFF ,TSM abort failure flag" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 5. " FTFF ,Frequency target failure flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x0C 4. " FT_FAIL ,Real time status of frequency target failure" "No occurred,Occurred"
|
|
eventfld.long 0x0C 3. " CSFF ,Cycle Slip Failure Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x0C 2. " CS_FAIL ,Real time status of cycle slip circuit" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 1. " CTFF ,CTUNE failure flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x0C 0. " CT_FAIL ,Real time status of coarse tune fail signal" "Not occurred,Occurred"
|
|
line.long 0x10 "HPM_CTRL,PLL High Port Modulator Control"
|
|
bitfld.long 0x10 31. " HPM_MOD_IN_INVERT ,Invert high port modulation" "Not inverted,Inverted"
|
|
bitfld.long 0x10 28. " HPM_CAL_INVERT ,Invert high port modulator calibration" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x10 27. " HPM_INTEGER_INVERT ,Invert high port modulation integer" "Not inverted,Inverted"
|
|
bitfld.long 0x10 24.--25. " HPM_INTEGER_SCALE ,High port modulation integer scale" "No scaling,x2,/2,?..."
|
|
textline " "
|
|
bitfld.long 0x10 23. " HPM_DTH_EN ,Dither enable for HPM LFSR" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " HPM_DTH_SCL ,HPM dither scale" "Not scaled,Scaled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " HPM_LFSR_SIZE ,HPM LFSR length" "LFSR 9,LFSR 10,LFSR 11,LFSR 13,LFSR 15,LFSR 17,?..."
|
|
bitfld.long 0x10 15. " HPM_SDM_IN_DISABLE ,Disable HPM SDM input" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 14. " HPM_SDM_OUT_INVERT ,Invert HPM SDM output" "Not inverted,Inverted"
|
|
eventfld.long 0x10 13. " HPFF ,HPM SDM invalid flag" "Valid,Invalid"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--9. 1. " HPM_SDM_IN_MANUAL ,Manual high port SDM fractional value"
|
|
group.long 0x244++0x13
|
|
line.long 0x00 "HPM_SDM_RES,PLL High Port Sigma Delta Results"
|
|
bitfld.long 0x00 28.--31. " HPM_COUNT_ADJUST ,Value that is used to adjust the high port calibration frequency count difference" "-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. " HPM_DENOM ,High port modulator SDM denominator"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " HPM_NUM_SELECTED ,High port modulator SDM numerator"
|
|
line.long 0x04 "LPM_CTRL,PLL Low Port Modulator Control"
|
|
bitfld.long 0x04 31. " LPM_SDM_USE_NEG ,Use the Negedge of the Sigma Delta clock" "Not used,Used"
|
|
bitfld.long 0x04 24.--27. " LPM_SCALE ,LPM scale factor" "No scaling,2,4,8,16,32,64,128,256,512,1024,2048,?..."
|
|
textline " "
|
|
bitfld.long 0x04 23. " LPM_D_OVRD ,LPM dither override mode select" "No override,Override"
|
|
bitfld.long 0x04 22. " LPM_D_CTRL ,LPM dither control in override mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " LPM_DTH_SCL ,LPM dither scale" ",,,,,,,,-128 to 96,-256 to 192,-512 to 384,-1024 to 768,-2048 to 1536,-4096 to 3072,-8192 to 6144,?..."
|
|
bitfld.long 0x04 15. " LPM_DISABLE ,Disable LPM SDM" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 14. " LPM_SDM_INV ,Invert LPM SDM" "Not inverted,Inverted"
|
|
eventfld.long 0x04 13. " LPFF ,LPM SDM invalid flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PLL_LD_DISABLE ,Disable PLL loop divider" "No,Yes"
|
|
bitfld.long 0x04 0.--5. " PLL_LD_MANUAL ,Manual PLL loop divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "LPM_SDM_CTRL1,PLL Low Port Sigma Delta Control 1"
|
|
bitfld.long 0x08 31. " SDM_MAP_DISABLE ,Disable SDM mapping" "No,Yes"
|
|
hexmask.long.byte 0x08 16.--22. 1. " LPM_INTG ,Manual low port modulation integer value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--14. 1. " HPM_ARRAY_BIAS ,Bias value for high port DAC array midpoint"
|
|
hexmask.long.byte 0x08 0.--6. 1. " LPM_INTG_SELECTED ,Low port modulation integer value selected"
|
|
line.long 0x0C "LPM_SDM_CTRL2,PLL Low Port Sigma Delta Control 2"
|
|
hexmask.long 0x0C 0.--27. 1. " LPM_NUM ,Low port modulation numerator"
|
|
line.long 0x10 "LPM_SDM_CTRL3,PLL Low Port Sigma Delta Control 3"
|
|
hexmask.long 0x10 0.--27. 1. " LPM_DENOM ,Low port modulation denominator"
|
|
rgroup.long 0x258++0x0B
|
|
line.long 0x00 "LPM_SDM_RES1,PLL Low Port Sigma Delta Result 1"
|
|
hexmask.long 0x00 0.--27. 1. " LPM_NUM_SELECTED ,Low port modulation numerator applied"
|
|
line.long 0x04 "LPM_SDM_RES2,PLL Low Port Sigma Delta Result 2"
|
|
hexmask.long 0x04 0.--27. 1. " LPM_DENOM_SELECTED ,Low port modulation denominator selected"
|
|
line.long 0x08 "DELAY_MATCH,PLL Delay Matching"
|
|
bitfld.long 0x08 16.--19. " HPM_INTEGER_DELAY ,High port integer delay matching" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " HPM_SDM_DELAY ,High port SDM delay matching" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LPM_SDM_DELAY ,Low port SDM delay matching" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "CTUNE_CTRL,PLL Coarse Tune Control"
|
|
bitfld.long 0x00 31. " CTUNE_DISABLE ,Coarse tune disable" "No,Yes"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CTUNE_MANUAL ,Manual coarse tune setting"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CTUNE_ADJUST ,Coarse tune count adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " CTUNE_TARGET_DISABLE ,Disable coarse tune target" "No,Yes"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " CTUNE_TARGET_MANUAL ,Manual coarse tune target"
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "CTUNE_RES,PLL Coarse Tune Results"
|
|
hexmask.long.word 0x00 16.--27. 1. " CTUNE_FREQ_SELECTED ,Coarse tune frequency selected"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CTUNE_BEST_DIFF ,Coarse tune absolute best difference"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " CTUNE_SELECTED ,Coarse tune setting to VCO"
|
|
else
|
|
textline " "
|
|
width 22.
|
|
group.long 0x228++0x2F
|
|
line.long 0x00 "PLL_MOD_OVRD,PLL Modulation Overrides"
|
|
bitfld.long 0x00 31. " HPM_LSB_DIS ,Disable HPM LSB" "No,Yes"
|
|
bitfld.long 0x00 28.--29. " HPM_LSB_MANUAL ,Manual HPM LSB" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HPM_BANK_DIS ,Disable HPM bank" "No,Yes"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HPM_BANK_MANUAL ,Manual HPM bank"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOD_DIS ,Disable modulation word" "No,Yes"
|
|
hexmask.long.word 0x00 0.--12. 1. " MODULATION_WORD_MANUAL ,Manual modulation word"
|
|
line.long 0x04 "PLL_CHAN_MAP,PLL Channel Mapping"
|
|
sif (cpuis("MKW20*")||cpuis("MKW40*"))
|
|
bitfld.long 0x04 10. " ZOC ,Zigbee channel number override" "From 802.15.4 link layer,From CHANNEL_NUM register"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("MKW30*")||cpuis("MKW40*"))
|
|
bitfld.long 0x04 9. " BMR ,BLE MBAN channel remap" "BLE CH39 mapped to BLE CH39(2.480GHz),BLE CH39 mapped to MBAN CH39(2.399GHz)"
|
|
bitfld.long 0x04 8. " BOC ,BLE channel number override" "BLE link layer,CHANNEL_NUM register"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x04 0.--6. 1. " CHANNEL_NUM ,Protocol specific channel number for PLL frequency mapping"
|
|
line.long 0x08 "PLL_LOCK_DETECT,PLL Lock Detect"
|
|
bitfld.long 0x08 27. " FTW_TX ,TX frequency target window time select" "4 us,8 us"
|
|
bitfld.long 0x08 20.--25. " FTF_TX_THRSH ,TX frequency target fail threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x08 19. " FTW_RX ,RX frequency target window time select" "4 us,8 us"
|
|
bitfld.long 0x08 12.--17. " FTF_RX_THRSH ,RX frequency target fail threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " CTUNE_LDF_LEV ,CTUNE lock detect fail level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x08 7. " TAFF ,TSM abort failure flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x08 5. " FTFF ,Frequency target failure flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 4. " FT_FAIL ,Real time status of frequency target failure" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x08 3. " CSFF ,Cycle slip failure flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 2. " CS_FAIL ,Real time status of cycle slip circuit" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CTFF ,CTUNE failure flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 0. " CT_FAIL ,Real time status of coarse tune fail signal" "Not occurred,Occurred"
|
|
line.long 0x0C "PLL_HP_MOD_CTRL,PLL High Port Modulation Control"
|
|
bitfld.long 0x0C 31. " HP_MOD_INV ,HPM invert" "Not inverted,Inverted"
|
|
bitfld.long 0x0C 24.--25. " HPM_SCALE ,HPM scale factor" "No scaling,x2,/2,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 23. " HPM_DTH_EN ,Dither enable for HPM LFSR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " HP_DTH_SCL ,HPM dither scale" "No scaling,2"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--18. " HPM_LFSR_LEN ,HPM LFSR length" "LFSR 9,LFSR 10,LFSR 11,LFSR 13,LFSR 15,LFSR 17,?..."
|
|
bitfld.long 0x0C 15. " HP_SDM_DIS ,Disable HPM SDM" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " HP_SDM_INV ,Invert HPM SDM" "Not inverted,Inverted"
|
|
eventfld.long 0x0C 13. " HPFF ,HPM SDM invalid flag" "Not occurred,Occurred"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--9. 1. " HPM_SDM_MANUAL ,PLL HPM SDM manual"
|
|
line.long 0x10 "PLL_HPM_CAL_CTRL,PLL HPM Calibration Control"
|
|
bitfld.long 0x10 31. " HP_CAL_TIME ,High port modulation calibration time" "25 us,50 us"
|
|
bitfld.long 0x10 30. " HP_CAL_ARY ,High port modulation calibration array size" "128,256"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " HPM_CAL_FACTOR_MANUAL ,HPM manual calibration factor"
|
|
bitfld.long 0x10 15. " HP_CAL_DIS ,High port calibration disable" "No,Yes"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--12. 1. " HPM_CAL_FACTOR ,High port modulation calibration factor"
|
|
line.long 0x14 "PLL_LD_HPM_CAL1,PLL Cycle Slip Lock Detect Configuration And HPM Calibration 1"
|
|
bitfld.long 0x14 28.--31. " CS_FCNT ,Cycle slip flag count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--26. " CS_FW ,Cycle slip flag window" "8 us,16 us,24 us,32 us,64 us,96 us,128 us,256 us"
|
|
textline " "
|
|
bitfld.long 0x14 20.--22. " CS_WT ,Cycle slip wait time" "128 us,256 us,384 us,512 us,640 us,768 us,896 us,1024 us"
|
|
hexmask.long.tbyte 0x14 0.--16. 1. " CNT_1 ,High port modulation counter value 1"
|
|
line.long 0x18 "PLL_LD_HPM_CAL2,PLL Cycle Slip Lock Detect Configuration And HPM Calibration 2"
|
|
bitfld.long 0x18 24.--28. " CS_FT ,Cycle slip flag timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 20. " CS_RS ,Cycle slip recycle" "No reset,Reset"
|
|
textline " "
|
|
hexmask.long.tbyte 0x18 0.--16. 1. " CNT_2 ,High port modulation counter value 2"
|
|
line.long 0x1C "PLL_HPM_SDM_FRACTION,PLL HPM SDM Fraction"
|
|
hexmask.long.word 0x1C 16.--25. 1. " HPM_DENOM ,High port modulation denominator"
|
|
hexmask.long.word 0x1C 0.--9. 1. " HPM_NUM_SELECTED ,HPM numerator selected"
|
|
line.long 0x20 "PLL_LP_MOD_CTRL,PLL Low Port Modulation Control"
|
|
bitfld.long 0x20 24.--27. " LPM_SCALE ,LPM scale factor" "No scaling,2,4,8,16,32,64,128,256,512,1024,2048,?..."
|
|
bitfld.long 0x20 23. " LPM_D_OVRD ,LPM dither override mode select" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x20 22. " LPM_D_CTRL ,LPM dither control in override mode" "Disabled,Enabled"
|
|
bitfld.long 0x20 16.--19. " LPM_DTH_SCL ,LPM dither scale" ",,,,,-128 to 96,-256 to 192,-512 to 384,-1024 to 768,-2048 to 1536,-4096 to 3072,-8192 to 6144,?..."
|
|
textline " "
|
|
bitfld.long 0x20 15. " LPM_SDM_DIS ,Disable LPM SDM" "No,Yes"
|
|
bitfld.long 0x20 14. " LPM_SDM_INV ,Invert LPM SDM" "Not inverted,Inverted"
|
|
textline " "
|
|
eventfld.long 0x20 13. " LPFF ,LPM SDM invalid flag" "Not occurred,Occurred"
|
|
bitfld.long 0x20 11. " PLL_LD_DIS ,PLL loop divider disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x20 0.--5. " PLL_LOOP_DIVIDER_MANUAL ,PLL loop divider manual" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x24 "PLL_LP_SDM_CTRL1,PLL Low Port SDM Control 1"
|
|
bitfld.long 0x24 31. " SDM_MAP_DIS ,SDM mapping disable" "No,Yes"
|
|
hexmask.long.byte 0x24 16.--22. 1. " LPM_INTG ,Low port modulation integer manual value"
|
|
textline " "
|
|
hexmask.long.byte 0x24 0.--6. 1. " LPM_INTG_SELECTED ,Low port modulation integer value selected"
|
|
line.long 0x28 "PLL_LP_SDM_CTRL2,PLL Low Port SDM Control 2"
|
|
hexmask.long 0x28 0.--27. 1. " LPM_NUM ,Low port modulation numerator"
|
|
line.long 0x2C "PLL_LP_SDM_CTRL3,PLL Low Port SDM Control 3"
|
|
hexmask.long 0x2C 0.--27. 1. " LPM_DENOM ,Low port modulation denominator"
|
|
rgroup.long 0x258++0x07
|
|
line.long 0x00 "PLL_LP_SDM_NUM,PLL Low Port SDM Numerator Applied"
|
|
hexmask.long 0x00 0.--27. 1. " LPM_NUM_SELECTED ,Low port modulation numerator applied"
|
|
line.long 0x04 "PLL_LP_SDM_DENOM,PLL Low Port SDM Denominator Applied"
|
|
hexmask.long 0x04 0.--27. 1. " LPM_DENOM_SELECTED ,Low port modulation denominator selected"
|
|
group.long 0x260++0x07
|
|
line.long 0x00 "PLL_DELAY_MATCH,PLL Delay Matching"
|
|
bitfld.long 0x00 16.--19. " HPM_BANK_DELAY ,HPM bank delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " HPM_SDM_DELAY ,HPM SDM delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " LP_SDM_DELAY ,LP SDM delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PLL_CTUNE_CTRL,PLL Coarse Tune Control"
|
|
bitfld.long 0x04 31. " CTUNE_DIS ,CTUNE disable" "No,Yes"
|
|
hexmask.long.byte 0x04 24.--30. 1. " CTUNE_MANUAL ,CTUNE manual"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " CTUNE_ADJUST ,CTUNE count adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 15. " CTUNE_TD ,CTUNE target disable" "No,Yes"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--11. 1. " CTUNE_TARGET_MANUAL ,CTUNE target manual"
|
|
rgroup.long 0x268++0x13
|
|
line.long 0x00 "PLL_CTUNE_CNT6,PLL Coarse Tune Count 6"
|
|
hexmask.long.word 0x00 0.--11. 1. " CTUNE_COUNT_6 ,CTUNE count 6"
|
|
line.long 0x04 "PLL_CTUNE_CNT5_4,PLL Coarse Tune Counts 5 And 4"
|
|
hexmask.long.word 0x04 16.--27. 1. " CTUNE_COUNT_5 ,CTUNE count 5"
|
|
hexmask.long.word 0x04 0.--11. 1. " CTUNE_COUNT_4 ,CTUNE count 4"
|
|
line.long 0x08 "PLL_CTUNE_CNT3_2,PLL Coarse Tune Counts 3 And 2"
|
|
hexmask.long.word 0x08 16.--27. 1. " CTUNE_COUNT_3 ,CTUNE count 3"
|
|
hexmask.long.word 0x08 0.--11. 1. " CTUNE_COUNT_2 ,CTUNE count 2"
|
|
line.long 0x0C "PLL_CTUNE_CNT1_0,PLL Coarse Tune Counts 3 And 2"
|
|
hexmask.long.word 0x0C 16.--27. 1. " CTUNE_COUNT_3 ,CTUNE count 3"
|
|
hexmask.long.word 0x0C 0.--11. 1. " CTUNE_COUNT_2 ,CTUNE count 2"
|
|
line.long 0x10 "PLL_CTUNE_RESULTS,PLL Coarse Tune Results"
|
|
hexmask.long.word 0x10 16.--27. 1. " CTUNE_FREQ_TARGET ,Coarse tune frequency target"
|
|
hexmask.long.byte 0x10 8.--15. 1. " CTUNE_BEST_DIFF ,Coarse tune absolute best difference"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--6. 1. " CTUNE_SELECTED ,Coarse tune band to VCO"
|
|
endif
|
|
textline " "
|
|
width 15.
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "XCVR_CTRL,Transceiver Control"
|
|
sif (cpuis("MKW21Z*"))
|
|
bitfld.long 0x00 20.--22. " RADIO1_IRQ_SEL ,Assign radio 1 interrupt to protocol engine" ",Interrupt to 802.15.4,?..."
|
|
bitfld.long 0x00 16.--18. " RADIO0_IRQ_SEL ,Assign radio 0 interrupt to protocol engine" ",Interrupt to 802.15.4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEMOD_SEL ,Demodulator selector" "No demodulator,Freescale constant envelope,Legacy 802.15.4,?..."
|
|
bitfld.long 0x00 11. " SOC_RF_OSC_CLK_GATE_EN ,Enable 3V version of RF OSC clock for use by the SoC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " REF_CLK_FREQ ,Radio reference clock frequency" "32MHz,26MHz,?..."
|
|
bitfld.long 0x00 4.--6. " TGT_PWR_SRC ,Target power source" "PA_POWER[5:0],,802.15.4 link layer,,,,,PROTOCOL[3:0] determined"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PROTOCOL ,Radio protocol selection" ",,,,,802.15.4,802.15.4j,,,,MSK,?..."
|
|
elif (cpuis("MKW31Z*"))
|
|
bitfld.long 0x00 20.--22. " RADIO1_IRQ_SEL ,Assign radio 1 interrupt to protocol engine" "Interrupt to BLE,,,Interrupt to GENERIC_FSK,?..."
|
|
bitfld.long 0x00 16.--18. " RADIO0_IRQ_SEL ,Assign radio 0 interrupt to protocol engine" "Interrupt to BLE,,,Interrupt to GENERIC_FSK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEMOD_SEL ,Demodulator selector" "No demodulator,Freescale constant envelope,,?..."
|
|
bitfld.long 0x00 11. " SOC_RF_OSC_CLK_GATE_EN ,Enable 3V version of RF OSC clock for use by the SoC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " REF_CLK_FREQ ,Radio reference clock frequency" "32MHz,26MHz,?..."
|
|
bitfld.long 0x00 4.--6. " TGT_PWR_SRC ,Target power source" "PA_POWER[5:0],BTLE link layer,,,GENERIC_FSK link layer,,,PROTOCOL[3:0] determined"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PROTOCOL ,Radio protocol selection" "BLE,BLE in MBAN,BLE overlap MBAN,,,,,128 channel FSK,128 channel GFSK,Generic FSK,MSK,?..."
|
|
elif (cpuis("MKW41Z*"))
|
|
bitfld.long 0x00 20.--22. " RADIO1_IRQ_SEL ,Assign radio 1 interrupt to protocol engine" "Interrupt to BLE,Interrupt to 802.15.4,,Interrupt to GENERIC_FSK,?..."
|
|
bitfld.long 0x00 16.--18. " RADIO0_IRQ_SEL ,Assign radio 0 interrupt to protocol engine" "Interrupt to BLE,Interrupt to 802.15.4,,Interrupt to GENERIC_FSK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEMOD_SEL ,Demodulator selector" "No demodulator,Freescale constant envelope,Legacy 802.15.4,?..."
|
|
bitfld.long 0x00 11. " SOC_RF_OSC_CLK_GATE_EN ,Enable 3V version of RF OSC clock for use by the SoC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " REF_CLK_FREQ ,Radio reference clock frequency" "32MHz,26MHz,?..."
|
|
bitfld.long 0x00 4.--6. " TGT_PWR_SRC ,Target power source" "PA_POWER[5:0],BTLE link layer,802.15.4 link layer,,GENERIC_FSK link layer,,,PROTOCOL[3:0] determined"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PROTOCOL ,Radio protocol selection" "BLE,BLE in MBAN,BLE overlap MBAN,,,802.15.4,802.15.4j,128 channel FSK,128 channel GFSK,Generic FSK,MSK,?..."
|
|
elif (cpuis("MKW40Z*"))
|
|
bitfld.long 0x00 6.--7. " REF_CLK_FREQ ,Radio reference clock frequency" "32MHz,?..."
|
|
bitfld.long 0x00 4.--5. " TGT_PWR_SRC ,Target power source" "PA_POWER[3:0],BTLE link layer,Zigbee link layer,PROTOCOL[2:0]"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PROTOCOL ,Radio protocol selection" "BLE,BLE in MBAN,BLE overlap MBAN,,Zigbee,802.15.4j,128 channel FSK,128 channel GFSK"
|
|
elif (cpuis("MKW30Z*"))
|
|
bitfld.long 0x00 6.--7. " REF_CLK_FREQ ,Radio reference clock frequency" "32MHz,?..."
|
|
bitfld.long 0x00 4.--5. " TGT_PWR_SRC ,Target power source" "PA_POWER[3:0],BTLE link layer,,PROTOCOL[2:0]"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PROTOCOL ,Radio protocol selection" "BLE,BLE in MBAN,BLE overlap MBAN,,,,128 channel FSK,128 channel GFSK"
|
|
else
|
|
bitfld.long 0x00 6.--7. " REF_CLK_FREQ ,Radio reference clock frequency" "32MHz,?..."
|
|
bitfld.long 0x00 4.--5. " TGT_PWR_SRC ,Target power source" "PA_POWER[3:0],,Zigbee link layer,PROTOCOL[2:0]"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PROTOCOL ,Radio protocol selection" ",,,,Zigbee,802.15.4j,128 channel FSK,128 channel GFSK"
|
|
endif
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
group.long 0x284++0x07
|
|
line.long 0x00 "XCVR_STATUS,Transceiver Status"
|
|
eventfld.long 0x00 25. " TSM_IRQ1 ,TSM interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TSM_IRQ0 ,TSM interrupt 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " SOC_USING_RF_OSC_CLK ,SOC using RF clock indication" "Low,High"
|
|
rbitfld.long 0x00 18. " XTAL_READY ,RF oscillator Xtal ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " RIF_LL_ACTIVE ,Link layer active indication" "Not active,Active"
|
|
rbitfld.long 0x00 16. " BTLE_SYSCLK_REQ ,BTLE system clock request" "Not requested,Requested"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " TX_MODE ,Transmit mode" "Not in progress,In progress"
|
|
rbitfld.long 0x00 12. " RX_MODE ,Receive mode" "Not in progress,In progress"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--11. " PLL_SEQ_STATE ,PLL sequence state" "PLL OFF,,CTUNE,CTUNE_SETTLE,,,HPMCAL1,,HPMCAL1_SETTLE,,HPMCAL2,,HPMCAL2_SETTLE,,,PLLREADY"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSM_COUNT ,TSM count"
|
|
line.long 0x04 "BLE_ARB_CTRL,BLE Arbitration Control"
|
|
rbitfld.long 0x04 1. " XCVR_BUSY ,Transceiver busy status bit" "Idle,Busy"
|
|
bitfld.long 0x04 0. " BLE_RELINQUISH ,BLE relinquish control" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "XCVR_STATUS,Transceiver Status"
|
|
bitfld.long 0x00 19. " SOC_USING_RF_OSC_CLK ,SOC using RF clock indication" "Low,High"
|
|
bitfld.long 0x00 18. " XTAL_READY ,RF oscillator Xtal ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RIF_LL_ACTIVE ,Link layer active indication" "Not active,Active"
|
|
bitfld.long 0x00 16. " BTLE_SYSCLK_REQ ,BTLE system clock request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TX_MODE ,Transmit mode" "Not in progress,In progress"
|
|
bitfld.long 0x00 12. " RX_MODE ,Receive mode" "Not in progress,In progress"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PLL_SEQ_STATE ,PLL sequence state" "PLL OFF,,CTUNE,CTUNE_SETTLE,,,HPMCAL1,,HPMCAL1_SETTLE,,HPMCAL2,,HPMCAL2_SETTLE,,,PLLREADY"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSM_COUNT ,TSM count"
|
|
endif
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "OVERWRITE_VER,Overwrite Version"
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERWRITE_VER ,Overwrite version number"
|
|
textline " "
|
|
width 17.
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
if (((per.l(ad:0x4005C000+0x294))&0x10)==0x10)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA_CTRL,DMA Control"
|
|
bitfld.long 0x00 8.--11. " DMA_TIMEOUT ,DMA timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x00 7. " DMA_TIMED_OUT ,DMA transfer timed out" "No time out,Time out"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " DMA_TRIGGERED ,DMA triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " BYPASS_DMA_SYNC ,Bypass external DMA synchronization" "No bypass,"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SINGLE_REQ_MODE ,DMA single request mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DMA_PAGE ,Transceiver DMA page selector" "DMA idle,RX_DIG I&Q,RX_DIG I,RX_DIG Q,RAW ADC I&Q,RAW ADC I,RAW ADC Q,DC estimator I&Q,DC estimator I,DC estimator Q,RX_DIG phase output,Demodulator hard decision,Demodulator soft decision,Demodulator data output,Demodulator CFO phase output,?..."
|
|
else
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA_CTRL,DMA Control"
|
|
rbitfld.long 0x00 6. " DMA_TRIGGERED ,DMA triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " BYPASS_DMA_SYNC ,Bypass external DMA synchronization" ",Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SINGLE_REQ_MODE ,DMA single request mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DMA_PAGE ,Transceiver DMA page selector" "DMA idle,RX_DIG I&Q,RX_DIG I,RX_DIG Q,RAW ADC I&Q,RAW ADC I,RAW ADC Q,DC estimator I&Q,DC estimator I,DC estimator Q,RX_DIG phase output,Demodulator hard decision,Demodulator soft decision,Demodulator data output,Demodulator CFO phase output,?..."
|
|
endif
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "DMA_DATA,DMA Data Register"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "PACKET_RAM_CTRL,Packet RAM Control"
|
|
bitfld.long 0x00 17. " RAM1_CE_ON_OVRD ,Override value for RAM1 CE (Chip Enable)" "No override,Override"
|
|
bitfld.long 0x00 16. " RAM1_CE_ON_OVRD_EN ,Override control for RAM1 CE (Chip Enable)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RAM0_CE_ON_OVRD ,Override value for RAM0 CE (Chip Enable)" "No override,Override"
|
|
bitfld.long 0x00 14. " RAM0_CE_ON_OVRD_EN ,Override control for RAM0 CE (Chip Enable)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RAM1_CLK_ON_OVRD ,Override value for RAM1 clock gate enable" "No override,Override"
|
|
bitfld.long 0x00 12. " RAM1_CLK_ON_OVRD_EN ,Override control for RAM1 clock gate enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RAM0_CLK_ON_OVRD ,Override value for RAM0 clock gate enable" "No override,Override"
|
|
bitfld.long 0x00 10. " RAM0_CLK_ON_OVRD_EN ,Override control for RAM0 clock gate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " DBG_RAM_FULL ,DBG RAM[1:0] full status" "RAM0/RAM1 not full,RAM0 full,RAM1 full,RAM0/RAM1 full"
|
|
rbitfld.long 0x00 7. " DBG_TRIGGERED ,DBG network address match status bit" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PROTOCOLS_ALLOW ,Allow IPS bus access to packet RAM for any protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XCVR_RAM_ALLOW ,Allow packet RAM transceiver access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PB_PROTECT ,Packet buffer protect" "Not protected,Protected"
|
|
bitfld.long 0x00 0.--3. " DBG_PAGE ,Packet RAM debug page selector" "RAM debug mode idle,RX_DIG I&Q,,,RAW ADC I&Q,,,DC estimator I&Q,,,RX_DIG phase output,Demodulator hard decision,Demodulator soft decision,Demodulator data output,Demodulator CFO phase output,?..."
|
|
textline " "
|
|
width 21.
|
|
group.long 0x2A4++0x0F
|
|
line.long 0x00 "FAD_CTRL,FAD Control"
|
|
bitfld.long 0x00 15. " FAD_NOT_GPIO[3] ,FAD versus GPIO mode selector 3" "Gpio3_trig_en,Algorithm"
|
|
bitfld.long 0x00 14. " FAD_NOT_GPIO[2] ,FAD versus GPIO mode selector 2" "Gpio2_trig_en,Algorithm"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FAD_NOT_GPIO[1] ,FAD versus GPIO mode selector 1" "Gpio1_trig_en,Algorithm"
|
|
bitfld.long 0x00 12. " FAD_NOT_GPIO[0] ,FAD versus GPIO mode selector 0" "Gpio0_trig_en,Algorithm"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ANTX_POL[3] ,FAD antenna controls polarity 3 - RX_SWITCH" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10. " ANTX_POL[2] ,FAD antenna controls polarity 2 - TX_SWITCH" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ANTX_POL[1] ,FAD antenna controls polarity 1 - ANT_B" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " ANTX_POL[0] ,FAD antenna controls polarity 0 - ANT_A" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ANTX_CTRLMODE ,Antenna diversity control mode" "Single mode,Dual mode"
|
|
bitfld.long 0x00 6. " ANTX_HZ ,FAD pad tristate control" "Normal,High impedance"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ANTX_EN ,FAD antenna controls enable" "All disabled,RX/TX_SWITCH enabled,ANT_A/B enabled,All enabled"
|
|
bitfld.long 0x00 1. " ANTX ,Antenna selection state" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FAD_EN ,Fast antenna diversity enable" "Disabled,Enabled"
|
|
line.long 0x04 "LPPS_CTRL,Low Power Preamble Search Control"
|
|
hexmask.long.byte 0x04 24.--31. 1. " LPPS_DEST_RX ,LLPS fast TSM RX warmup 'jump-to' point"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LPPS_START_RX ,LLPS fast TSM RX warmup 'jump-from' point"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LPPS_DCOC_DIG_ALLOW ,LPPS DCOC digital allow" "Not allowed,Allowed"
|
|
bitfld.long 0x04 8. " LPPS_RX_DIG_ALLOW ,LPPS RX digital allow" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LPPS_SY_LO_BUF_ALLOW ,LPPS SY LO BUF allow" "Not allowed,Allowed"
|
|
bitfld.long 0x04 6. " LPPS_SY_LO_ALLOW ,LPPS SY LO allow" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LPPS_PDET_ALLOW ,LPPS PDET allow" "Not allowed,Allowed"
|
|
bitfld.long 0x04 4. " LPPS_DCOC_ALLOW ,LPPS DCOC allow" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LPPS_ADC_ALLOW ,LPPS ADC allow" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " LPPS_BBA_ALLOW ,LPPS BBA allow" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LPPS_TZA_ALLOW ,LPPS TZA allow" "Not allowed,Allowed"
|
|
bitfld.long 0x04 0. " LPPS_ENABLE ,LPPS enable" "Disabled,Enabled"
|
|
line.long 0x08 "RF_NOT_ALLOWED_CTRL,WIFI Coexistence Control"
|
|
rbitfld.long 0x08 5. " RF_NOT_ALLOWED ,RF not allowed pin state" "Low,High"
|
|
eventfld.long 0x08 4. " RF_NOT_ALLOWED_RX_ABORT ,RF not allowed RX abort" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RF_NOT_ALLOWED_TX_ABORT ,RF not allowed TX abort" "Not occurred,Occurred"
|
|
eventfld.long 0x08 2. " RF_NOT_ALLOWED_ASSERTED ,RF not allowed assert" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RF_NOT_ALLOWED_RX ,RF not allowed RX" "No effect on RX,Can abort RX"
|
|
bitfld.long 0x08 0. " RF_NOT_ALLOWED_TX ,RF not allowed TX" "No effect on TX,Can abort TX"
|
|
line.long 0x0C "CRCW_CFG,CRC/Whitener Control"
|
|
rbitfld.long 0x0C 29. " CRC_EC_FAIL ,CRC error correction fail" "Not failed,Failed"
|
|
rbitfld.long 0x0C 28. " CRC_EC_DONE ,CRC error correction done" "Not done,Done"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--26. 0x01 " CRC_EC_OFFSET ,CRC error correction offset"
|
|
rbitfld.long 0x0C 3. " CRC_RES_OUT_VLD ,CRC result output valid" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x0C 2. " CRC_EARLY_FAIL ,CRC error correction fail" "Not failed,Failed"
|
|
rbitfld.long 0x0C 1. " CRC_ZERO ,CRC zero" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CRCW_EN ,CRC calculation enable" "Disabled,Enabled"
|
|
rgroup.long 0x2B4++0x07
|
|
line.long 0x00 "CRC_EC_MASK,CRC Error Correction Mask"
|
|
line.long 0x04 "CRC_RES_OUT,CRC Result"
|
|
group.long 0x400++0x0B
|
|
line.long 0x00 "PHY_PRE_REF0,Preamble Reference Waveform 0"
|
|
line.long 0x04 "PHY_PRE_REF1,Preamble Reference Waveform 1"
|
|
line.long 0x08 "PHY_PRE_REF2,Preamble Reference Waveform 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " FSK_PREAMBLE_REF2 ,FSK preamble reference"
|
|
group.long 0x420++0x0F
|
|
line.long 0x00 "PHY_CFG1,PHY Configuration Register 1"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*"))
|
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bitfld.long 0x00 28.--30. " BLE_NTW_ADR_THR ,BLE network address match bit error threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " FSK_FTS_TIMEOUT ,FSK FTS timeout" "4 symbols,5 symbols,6 symbols,7 symbols,8 symbols,9 symbols,10 symbols,11 symbols"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CTS_THRESH ,CTS correlation threshold"
|
|
bitfld.long 0x00 6.--7. " DEMOD_CLK_MODE ,Demodulator clock mode" "Normal,Demodulate all samples,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " BSM_EN_BLE ,BLE bit streaming mode enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FSK_BIT_INVERT ,FSK Bit invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AA_OUTPUT_SEL ,Access address output select" "Demodulated,Matched"
|
|
bitfld.long 0x00 1. " AA_PLAYBACK ,Access address playback" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CTS_THRESH ,CTS correlation threshold"
|
|
bitfld.long 0x00 6.--7. " DEMOD_CLK_MODE ,Demodulator clock mode" "Normal,Demodulate all samples,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " BSM_EN_BLE ,BLE bit streaming mode enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AA_OUTPUT_SEL ,Access address output select" "Demodulated,Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AA_PLAYBACK ,Access address playback" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "PHY_CFG2,PHY Configuration Register 2"
|
|
bitfld.long 0x04 31. " PHY_CLK_ON ,Force PHY clock on" "Not forced,Forced"
|
|
bitfld.long 0x04 8.--11. " X2_DEMOD_GAIN ,Gain parameter used in the symbol demodulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " PHY_FIFO_PRECHG ,PHY FIFO precharge level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PHY_EL_CFG,PHY Early/Late Configuration Register"
|
|
bitfld.long 0x08 16.--21. " EL_INTERVAL ,Number of FSK/IEEE 802.15.4 symbols between successive EL operation windows" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 8.--11. " EL_WIN_SIZE ,Number of successive FSK/IEEE 802.15.4 symbols over which one EL operation occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 0. " EL_ENABLE ,EL mechanism enable" "Disabled,Enabled"
|
|
line.long 0x0C "NTW_ADR_BSM,PHY Network Aaddress For BSM"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "PHY_STATUS,PHY Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " CFO_ESTIMATE ,Carrier frequency offset estimate"
|
|
bitfld.long 0x00 12.--15. " DATA_FIFO_DEPTH ,Instantaneous depth of the PHY output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("MKW31Z!")||cpuis("MKW41Z!"))
|
|
bitfld.long 0x00 8.--10. " HAMMING_DISTANCE ,Hamming distance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " AA_MATCHED[3] ,Access address 3 matched" "Not matched,Matched"
|
|
bitfld.long 0x00 6. " AA_MATCHED[2] ,Access address 2 matched" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AA_MATCHED[1] ,Access address 1 matched" "Not matched,Matched"
|
|
bitfld.long 0x00 4. " AA_MATCHED[0] ,Access address 0 matched" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AA_SFD_MATCHED ,Access address or SFD found" "Not matched,Matched"
|
|
bitfld.long 0x00 0. " PREAMBLE_FOUND ,Preamble found" "Not occurred,Occurred"
|
|
group.long 0x480++0x1B
|
|
line.long 0x00 "CORR_CTRL,802.15.4 Demod Correllator Control"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RX_MAX_PREAMBLE ,Max correlator during preamble"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_MAX_CORR ,Max correlator after preamble"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ZBDEM_CLK_ON ,Force 802.15.4 demodulator clock on" "Not forced,Forced"
|
|
bitfld.long 0x00 11. " MAX_CORR_EN ,Max correlator after preamble enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CORR_NVAL ,Number of consecutively detected zero-symbols required to declare a preamble detected" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CORR_VT ,Correlator threshold"
|
|
line.long 0x04 "PL_TYPE,802.15.4 Demod PN Type"
|
|
bitfld.long 0x04 1. " TX_INV ,Test mode to invert the transmission" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " PN_TYPE ,Pseudo noise chip code type" "0,802.15.4"
|
|
line.long 0x08 "PN_CODE,802.15.4 Demod PN Code"
|
|
hexmask.long.word 0x08 16.--31. 1. " PN_MSB ,PN code MS half"
|
|
hexmask.long.word 0x08 0.--15. 1. " PN_LSB ,PN code LS half"
|
|
line.long 0x0C "SYNC_CTRL,802.15.4 Demod Symbol Sync Control"
|
|
bitfld.long 0x0C 3. " TRACK_ENABLE ,Track enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--2. " SYNC_PER ,Symbol sync tracking period" "0,1,2,3,4,?..."
|
|
line.long 0x10 "CCA_LQI_SRC,802.15.4 CCA/LQI Source"
|
|
bitfld.long 0x10 2. " LQI_START_AT_SFD ,Select start point for LQI computation" "At preamble,At SFD detection"
|
|
bitfld.long 0x10 1. " LQI_FROM_RX_DIG ,Selects the source of LQI information provided to the 802.15.4 link layer" "Internal,RX digital"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CCA1_FROM_RX_DIG ,Selects the source of CCA1 information provided to the 802.15.4 link layer" "Internal,RX digital"
|
|
line.long 0x14 "FAD_THR,FAD Correlator Threshold"
|
|
hexmask.long.byte 0x14 0.--7. 1. " FAD_THR ,Correlator threshold at which the FAD will select the antenna"
|
|
line.long 0x18 "ZBDEM_AFC,802.15.4 AFC Status"
|
|
rbitfld.long 0x18 8.--12. " AFC_OUT ,AFC Result from the last received packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 1. " DCD_EN ,DCD enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " AFC_EN ,AFC enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "DMA_CTRL,DMA Control"
|
|
bitfld.long 0x00 1. " DMA_Q_EN ,DMA Q enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DMA_I_EN ,DMA I enable" "Disabled,Enabled"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "DMA_DATA,DMA Data"
|
|
hexmask.long.word 0x00 16.--27. 1. " DMA_DATA_27_16 ,DMA data [27:16]"
|
|
hexmask.long.word 0x00 0.--11. 1. " DMA_DATA_11_0 ,DMA data [11:0]"
|
|
textline " "
|
|
width 15.
|
|
group.long 0x29C++0x07
|
|
line.long 0x00 "DTEST_CTRL,Digital Test Control"
|
|
bitfld.long 0x00 29. " RAW_MODE_Q ,DTEST raw mode enable for Q channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " RAW_MODE_I ,DTEST raw mode enable for I channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " DTEST_SHFT ,DTEST shift control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " TSM_GPIO_OVLAY_1 ,TSM GPIO 1 overlay pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TSM_GPIO_OVLAY_0 ,TSM GPIO 0 overlay pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " GPIO1_OVLAY_PIN ,GPIO 1 overlay pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " GPIO0_OVLAY_PIN ,GPIO 0 overlay pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " DTEST_EN ,DTEST enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DTEST_PAGE ,DTEST page selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "PB_CTRL,Packet Buffer Control Register"
|
|
bitfld.long 0x04 0. " PB_PROTECT ,PB protect" "Not protected,Protected"
|
|
group.long 0x2C0++0x27
|
|
line.long 0x00 "TSM_CTRL,Transceiver Sequence Manager Control"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BKPT ,TSM breakpoint"
|
|
bitfld.long 0x00 20. " ABORT_ON_FREQ_TARG ,Abort on frequency target lock detect failure" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ABORT_ON_CYCLE_SLIP ,Abort on cycle slip lock detect failure" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " ABORT_ON_CTUNE ,Abort on coarse tune lock detect failure" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RX_ABORT_DIS ,Receive abort disable" "No,Yes"
|
|
bitfld.long 0x00 16. " TX_ABORT_DIS ,Transmit abort disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DATA_PADDING_EN ,Data padding enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " PA_RAMP_SEL ,PA ramp selection [Total/Step]" "No ramp/No ramp,2us/0.25us,4us/0.5us,8us/1us"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FORCE_RX_EN ,Force receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FORCE_TX_EN ,Force transmit enable" "Disabled,Enabled"
|
|
line.long 0x04 "END_OF_SEQ,End Of Sequence Control"
|
|
hexmask.long.byte 0x04 24.--31. 1. " END_OF_RX_WD ,End of RX warmdown"
|
|
hexmask.long.byte 0x04 16.--23. 1. " END_OF_RX_WU ,End of RX warmup"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " END_OF_TX_WD ,End of TX warmdown"
|
|
hexmask.long.byte 0x04 0.--7. 1. " END_OF_TX_WU ,End of TX warmup"
|
|
line.long 0x08 "TSM_OVRD0,TSM Override 0"
|
|
bitfld.long 0x08 31. " PLL_RX_LDV_RIPPLE_MUX_EN_OVRD ,Override value for PLL_RX_LDV_RIPPLE_MUX_EN" "No override,Override"
|
|
bitfld.long 0x08 30. " PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN ,Override control for PLL_RX_LDV_RIPPLE_MUX_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " PLL_LDV_EN_OVRD ,Override value for PLL_LDV_EN" "No override,Override"
|
|
bitfld.long 0x08 28. " PLL_LDV_EN_OVRD_EN ,Override control for PLL_LDV_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " PLL_PA_BUF_EN_OVRD ,Override value for PLL_BA_BUF_EN" "No override,Override"
|
|
bitfld.long 0x08 26. " PLL_PA_BUF_EN_OVRD_EN ,Override control for PLL_BA_BUF_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " PLL_VCO_BUF_TX_EN_OVRD ,Override value for PLL_VCO_BUF_TX_EN" "No override,Override"
|
|
bitfld.long 0x08 24. " PLL_VCO_BUF_TX_EN_OVRD_EN ,Override control for PLL_VCO_BUF_TX_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " PLL_VCO_BUF_RX_EN_OVRD ,Override value for PLL_VCO_BUF_RX_EN" "No override,Override"
|
|
bitfld.long 0x08 22. " PLL_VCO_BUF_RX_EN_OVRD_EN ,Override control for PLL_VCO_BUF_RX_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " PLL_VCO_EN_OVRD ,Override value for PLL_VCO_EN" "No override,Override"
|
|
bitfld.long 0x08 20. " PLL_VCO_EN_OVRD_EN ,Override control for PLL_VCO_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PLL_CYCLE_SLIP_LD_EN_OVRD ,Override value for PLL_CYCLE_SLIP_LD_EN" "No override,Override"
|
|
bitfld.long 0x08 18. " PLL_CYCLE_SLIP_LD_EN_OVRD_EN ,Override control for PLL_CYCLE_SLIP_LD_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " PLL_VCO_AUTOTUNE_EN_OVRD ,Override value for PLL_VCO_AUTOTUNE_EN" "No override,Override"
|
|
bitfld.long 0x08 16. " PLL_VCO_AUTOTUNE_EN_OVRD_EN ,Override control for PLL_VCO_AUTOTUNE_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " XTAL_ADC_REF_CLK_EN_OVRD ,Override value for XTAL_ADC_REF_CLK_EN" "No override,Override"
|
|
bitfld.long 0x08 14. " XTAL_ADC_REF_CLK_EN_OVRD_EN ,Override control for XTAL_ADC_REF_CLK_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XTAL_PLL_REF_CLK_EN_OVRD ,Override value for XTAL_PLL_REF_CLK_EN" "No override,Override"
|
|
bitfld.long 0x08 12. " XTAL_PLL_REF_CLK_EN_OVRD_EN ,Override control for XTAL_PLL_REF_CLK_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ADC_DIG_REG_EN_OVRD ,Override value for ADC_DIG_REG_EN" "No override,Override"
|
|
bitfld.long 0x08 10. " ADC_DIG_REG_EN_OVRD_EN ,Override control for ADC_DIG_REG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " ADC_ANA_REG_EN_OVRD ,Override value for ADC_ANA_REG_EN" "No override,Override"
|
|
bitfld.long 0x08 8. " DC_ANA_REG_EN_OVRD_EN ,Override control for ADC_ANA_REG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " TCA_TX_REG_EN_OVRD ,Override value for TCA_TX_REG_EN" "No override,Override"
|
|
bitfld.long 0x08 6. " TCA_TX_REG_EN_OVRD_EN ,Override control for TCA_TX_REG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " QGEN_REG_EN_OVRD ,Override value for QGEN_REG_EN" "No override,Override"
|
|
bitfld.long 0x08 4. " QGEN_REG_EN_OVRD_EN ,Override control for QGEN_REG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PLL_VCO_REG_EN_OVRD ,Override value for PLL_VCO_REG_EN" "No override,Override"
|
|
bitfld.long 0x08 2. " PLL_VCO_REG_EN_OVRD_EN ,Override control for PLL_VCO_REG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PLL_REG_EN_OVRD ,Override value for PLL_REG_EN" "No override,Override"
|
|
bitfld.long 0x08 0. " PLL_REG_EN_OVRD_EN ,Override control for PLL_REG_EN" "Disabled,Enabled"
|
|
line.long 0x0C "TSM_OVRD1,TSM Override 1"
|
|
bitfld.long 0x0C 31. " BBF_PDET_EN_OVRD ,Override value for BBF_PDET_EN" "No override,Override"
|
|
bitfld.long 0x0C 30. " BBF_PDET_EN_OVRD_EN ,Override control for BBF_PDET_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " BBF_Q_EN_OVRD ,Override value for BBF_Q_EN" "No override,Override"
|
|
bitfld.long 0x0C 28. " BBF_Q_EN_OVRD_EN ,Override control for BBF_Q_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " BBF_I_EN_OVRD ,Override value for BBF_I_EN" "No override,Override"
|
|
bitfld.long 0x0C 26. " BBF_I_EN_OVRD_EN ,Override control for BBF_I_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " ADC_RST_EN_OVRD ,Override value for ADC_RST_EN" "No override,Override"
|
|
bitfld.long 0x0C 24. " ADC_RST_EN_OVRD_EN ,Override control for ADC_RST_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " ADC_DAC2_EN_OVRD ,Override value for ADC_DAC2_EN" "No override,Override"
|
|
bitfld.long 0x0C 22. " ADC_DAC2_EN_OVRD_EN ,Override control for ADC_DAC2_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " ADC_DAC1_EN_OVRD ,Override value for ADC_DAC1_EN" "No override,Override"
|
|
bitfld.long 0x0C 20. " ADC_DAC1_EN_OVRD_EN ,Override control for ADC_DAC1_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " ADC_Q_ADC_EN_OVRD ,Override value for ADC_Q_ADC_EN" "No override,Override"
|
|
bitfld.long 0x0C 18. " ADC_Q_ADC_EN_OVRD_EN ,Override control for ADC_Q_ADC_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " ADC_I_ADC_EN_OVRD ,Override value for ADC_I_ADC_EN" "No override,Override"
|
|
bitfld.long 0x0C 16. " ADC_I_ADC_EN_OVRD_EN ,Override control for ADC_I_ADC_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " ADC_CLK_EN_OVRD ,Override value for ADC_CLK_EN" "No override,Override"
|
|
bitfld.long 0x0C 14. " ADC_CLK_EN_OVRD_EN ,Override control for ADC_CLK_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " ADC_BIAS_EN_OVRD ,Override value for ADC_BIAS_EN" "No override,Override"
|
|
bitfld.long 0x0C 12. " ADC_BIAS_EN_OVRD_EN ,Override control for ADC_BIAS_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " ADC_EN_OVRD ,Override value for ADC_EN" "No override,Override"
|
|
bitfld.long 0x0C 10. " ADC_EN_OVRD_EN ,Override control for ADC_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " TX_EN_OVRD ,Override value for TX_EN" "No override,Override"
|
|
bitfld.long 0x0C 8. " TX_EN_OVRD_EN ,Override control for TX_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " QGEN25_EN_OVRD ,Override value for QGEN25_EN" "No override,Override"
|
|
bitfld.long 0x0C 6. " QGEN25_EN_OVRD_EN ,Override control for QGEN25_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " PLL_PHDET_EN_OVRD ,Override value for PLL_PHDET_EN" "No override,Override"
|
|
bitfld.long 0x0C 4. " PLL_PHDET_EN_OVRD_EN ,Override control for PLL_PHDET_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PLL_FILTER_CHARGE_EN_OVRD ,Override value for PLL_FILTER_CHARGE_EN" "No override,Override"
|
|
bitfld.long 0x0C 2. " PLL_FILTER_CHARGE_EN_OVRD_EN ,Override control for PLL_FILTER_CHARGE_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PLL_TX_LDV_RIPPLE_MUX_EN_OVRD ,Override value for PLL_TX_LDV_RIPPLE_MUX_EN" "No override,Override"
|
|
bitfld.long 0x0C 0. " PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN ,Override control for PLL_TX_LDV_RIPPLE_MUX_EN" "Disabled,Enabled"
|
|
line.long 0x10 "TSM_OVRD2,TSM Override 2"
|
|
bitfld.long 0x10 31. " SAR_ADC_TRIG_EN_OVRD ,Override value for SAR_ADC_TRIG_EN" "No override,Override"
|
|
bitfld.long 0x10 30. " SAR_ADC_TRIG_EN_OVRD_EN ,Override control for SAR_ADC_TRIG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FREQ_TARG_LD_EN_OVRD ,Override value for FREQ_TARG_LD_EN" "No override,Override"
|
|
bitfld.long 0x10 28. " FREQ_TARG_LD_EN_OVRD_EN ,Override control for FREQ_TARG_LD_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " DCOC_INIT_OVRD ,Override value for DCOC_INIT" "No override,Override"
|
|
bitfld.long 0x10 26. " DCOC_INIT_OVRD_EN ,Override control for DCOC_INIT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " DCOC_EN_OVRD ,Override value for DCOC_EN" "No override,Override"
|
|
bitfld.long 0x10 24. " DCOC_EN_OVRD_EN ,Override control for DCOC_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " ZBDEM_RX_EN_OVRD ,Override value for ZBDEM_RX_EN" "No override,Override"
|
|
bitfld.long 0x10 22. " ZBDEM_RX_EN_OVRD_EN ,Override control for ZBDEM_RX_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " SIGMA_DELTA_EN_OVRD ,Override value for SIGMA_DELTA_EN" "No override,Override"
|
|
bitfld.long 0x10 20. " SIGMA_DELTA_EN_OVRD_EN ,Override control for SIGMA_DELTA_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " RX_INIT_OVRD ,Override value for RX_INIT" "No override,Override"
|
|
bitfld.long 0x10 18. " RX_INIT_OVRD_EN ,Override control for RX_INIT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " RX_DIG_EN_OVRD ,Override value for RX_DIG_EN" "No override,Override"
|
|
bitfld.long 0x10 16. " RX_DIG_EN_OVRD_EN ,Override control for RX_DIG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " TX_DIG_EN_OVRD ,Override value for TX_DIG_EN" "No override,Override"
|
|
bitfld.long 0x10 14. " TX_DIG_EN_OVRD_EN ,Override control for TX_DIG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " PLL_DIG_EN_OVRD ,Override value for PLL_DIG_EN" "No override,Override"
|
|
bitfld.long 0x10 12. " PLL_DIG_EN_OVRD_EN ,Override control for PLL_DIG_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " TZA_DCOC_EN_OVRD ,Override value for TZA_DCOC_EN" "No override,Override"
|
|
bitfld.long 0x10 10. " TZA_DCOC_EN_OVRD_EN ,Override control for TZA_DCOC_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " TZA_PDET_EN_OVRD ,Override value for TZA_PDET_EN" "No override,Override"
|
|
bitfld.long 0x10 8. " TZA_PDET_EN_OVRD_EN ,Override control for TZA_PDET_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TZA_Q_EN_OVRD ,Override value for TZA_Q_EN" "No override,Override"
|
|
bitfld.long 0x10 6. " TZA_Q_EN_OVRD_EN ,Override control for TZA_Q_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " TZA_I_EN_OVRD ,Override value for TZA_I_EN" "No override,Override"
|
|
bitfld.long 0x10 4. " TZA_I_EN_OVRD_EN ,Override control for TZA_I_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCA_EN_OVRD ,Override value for TCA_EN" "No override,Override"
|
|
bitfld.long 0x10 2. " TCA_EN_OVRD_EN ,Override control for TCA_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " BBF_DCOC_EN_OVRD ,Override value for BBF_DCOC_EN" "No override,Override"
|
|
bitfld.long 0x10 0. " BBF_DCOC_EN_OVRD_EN ,Override control for BBF_DCOC_EN" "Disabled,Enabled"
|
|
line.long 0x14 "TSM_OVRD3,TSM Override 3"
|
|
bitfld.long 0x14 11. " RX_MODE_OVRD ,Override value for RX_MODE" "No override,Override"
|
|
bitfld.long 0x14 10. " RX_MODE_OVRD_EN ,Override control for RX_MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " TX_MODE_OVRD ,Override value for TX_MODE" "No override,Override"
|
|
bitfld.long 0x14 8. " TX_MODE_OVRD_EN ,Override control for TX_MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " TSM_SPARE3_EN_OVRD ,Override value for TSM_SPARE3_EN" "No override,Override"
|
|
bitfld.long 0x14 6. " TSM_SPARE3_EN_OVRD_EN ,Override control for TSM_SPARE3_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " TSM_SPARE2_EN_OVRD ,Override value for TSM_SPARE2_EN" "No override,Override"
|
|
bitfld.long 0x14 4. " TSM_SPARE2_EN_OVRD_EN ,Override control for TSM_SPARE2_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " TSM_SPARE1_EN_OVRD ,Override value for TSM_SPARE1_EN" "No override,Override"
|
|
bitfld.long 0x14 2. " TSM_SPARE1_EN_OVRD_EN ,Override control for TSM_SPARE1_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TSM_SPARE0_EN_OVRD ,Override value for TSM_SPARE0_EN" "No override,Override"
|
|
bitfld.long 0x14 0. " TSM_SPARE0_EN_OVRD_EN ,Override control for TSM_SPARE0_EN" "Disabled,Enabled"
|
|
line.long 0x18 "PA_POWER,PA Power"
|
|
bitfld.long 0x18 0.--3. " PA_POWER ,PA target power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "PA_BIAS_TBL0,PA Bias Table 0"
|
|
bitfld.long 0x1C 24.--27. " PA_BIAS3 ,PA bias 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 16.--19. " PA_BIAS2 ,PA bias 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 8.--11. " PA_BIAS1 ,PA bias 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 0.--3. " PA_BIAS0 ,PA bias 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "PA_BIAS_TBL1,PA Bias Table 1"
|
|
bitfld.long 0x20 24.--27. " PA_BIAS7 ,PA bias 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 16.--19. " PA_BIAS6 ,PA bias 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 8.--11. " PA_BIAS5 ,PA bias 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 0.--3. " PA_BIAS4 ,PA bias 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "RECYCLE_COUNT,Count Register"
|
|
hexmask.long.byte 0x24 8.--15. 1. " RECYCLE_COUNT1 ,TSM RX recycle count 1"
|
|
hexmask.long.byte 0x24 0.--7. 1. " RECYCLE_COUNT0 ,TSM RX recycle count 0"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "TSM_TIMING00,TSM Timing 00"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_REG_EN_RX_LO ,Deassertion time setting for PLL_REG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_REG_EN_RX_HI ,Assertion time setting for PLL_REG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_REG_EN_TX_LO ,Deassertion time setting for PLL_REG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_REG_EN_TX_LO ,Assertion time setting for PLL_REG_EN signal or group TX sequence"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "TSM_TIMING01,TSM Timing 01"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_VCO_REG_EN_RX_LO ,Deassertion time setting for PLL_VCO_REG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_VCO_REG_EN_RX_HI ,Assertion time setting for PLL_VCO_REG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_VCO_REG_EN_TX_LO ,Deassertion time setting for PLL_VCO_REG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_VCO_REG_EN_TX_LO ,Assertion time setting for PLL_VCO_REG_EN signal or group TX sequence"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TSM_TIMING02,TSM Timing 02"
|
|
hexmask.long.byte 0x00 24.--31. 1. " QGEN_REG_EN_RX_LO ,Deassertion time setting for QGEN_REG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " QGEN_REG_EN_RX_HI ,Assertion time setting for QGEN_REG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " QGEN_REG_EN_TX_LO ,Deassertion time setting for QGEN_REG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " QGEN_REG_EN_TX_LO ,Assertion time setting for QGEN_REG_EN signal or group TX sequence"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "TSM_TIMING03,TSM Timing 03"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TCA_TX_REG_EN_RX_LO ,Deassertion time setting for TCA_TX_REG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCA_TX_REG_EN_RX_HI ,Assertion time setting for TCA_TX_REG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TCA_TX_REG_EN_TX_LO ,Deassertion time setting for TCA_TX_REG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCA_TX_REG_EN_TX_LO ,Assertion time setting for TCA_TX_REG_EN signal or group TX sequence"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "TSM_TIMING04,TSM Timing 04"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ADC_REG_EN_RX_LO ,Deassertion time setting for ADC_REG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ADC_REG_EN_RX_HI ,Assertion time setting for ADC_REG_EN signal or group RX sequence"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "TSM_TIMING05,TSM Timing 05"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_REF_CLK_EN_RX_LO ,Deassertion time setting for PLL_REF_CLK_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_REF_CLK_EN_RX_HI ,Assertion time setting for PLL_REF_CLK_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_REF_CLK_EN_TX_LO ,Deassertion time setting for PLL_REF_CLK_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_REF_CLK_EN_TX_LO ,Assertion time setting for PLL_REF_CLK_EN signal or group TX sequence"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "TSM_TIMING06,TSM Timing 06"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ADC_CLK_EN_RX_LO ,Deassertion time setting for ADC_CLK_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ADC_CLK_EN_RX_HI ,Assertion time setting for ADC_CLK_EN signal or group RX sequence"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "TSM_TIMING07,TSM Timing 07"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_VCO_AUTOTUNE_EN_RX_LO ,Deassertion time setting for PLL_VCO_AUTOTUNE_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_VCO_AUTOTUNE_EN_RX_HI ,Assertion time setting for PLL_VCO_AUTOTUNE_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_VCO_AUTOTUNE_EN_TX_LO ,Deassertion time setting for PLL_VCO_AUTOTUNE_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_VCO_AUTOTUNE_EN_TX_LO ,Assertion time setting for PLL_VCO_AUTOTUNE_EN signal or group TX sequence"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "TSM_TIMING08,TSM Timing 08"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_CYCLE_SLIP_LD_EN_RX_LO ,Deassertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_CYCLE_SLIP_LD_EN_RX_HI ,Assertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_CYCLE_SLIP_LD_EN_TX_LO ,Deassertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_CYCLE_SLIP_LD_EN_TX_LO ,Assertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group TX sequence"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "TSM_TIMING09,TSM Timing 09"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_VCO_EN_RX_LO ,Deassertion time setting for PLL_VCO_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_VCO_EN_RX_HI ,Assertion time setting for PLL_VCO_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_VCO_EN_TX_LO ,Deassertion time setting for PLL_VCO_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_VCO_EN_TX_LO ,Assertion time setting for PLL_VCO_EN signal or group TX sequence"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "TSM_TIMING10,TSM Timing 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_VCO_BUF_RX_EN_RX_LO ,Deassertion time setting for PLL_VCO_BUF_RX_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_VCO_BUF_RX_EN_RX_HI ,Assertion time setting for PLL_VCO_BUF_RX_EN signal or group RX sequence"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "TSM_TIMING11,TSM Timing 11"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_VCO_BUF_TX_EN_TX_LO ,Deassertion time setting for PLL_VCO_BUF_TX_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_VCO_BUF_TX_EN_TX_HI ,Assertion time setting for PLL_VCO_BUF_TX_EN signal or group TX sequence"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "TSM_TIMING12,TSM Timing 12"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_PA_BUF_EN_TX_LO ,Deassertion time setting for PLL_PA_BUF_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_PA_BUF_EN_TX_HI ,Assertion time setting for PLL_PA_BUF_EN signal or group TX sequence"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "TSM_TIMING13,TSM Timing 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_LDV_EN_RX_LO ,Deassertion time setting for PLL_LDV_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_LDV_EN_RX_HI ,Assertion time setting for PLL_LDV_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_LDV_EN_TX_LO ,Deassertion time setting for PLL_LDV_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_LDV_EN_TX_HI ,Assertion time setting for PLL_LDV_EN signal or group TX sequence"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TSM_TIMING14,TSM Timing 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO ,Deassertion time setting for PLL_RX_LDV_RIPPLE_MUX_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI ,Assertion time setting for PLL_RX_LDV_RIPPLE_MUX_EN signal or group RX sequence"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "TSM_TIMING15,TSM Timing 15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO ,Deassertion time setting for PLL_TX_LDV_RIPPLE_MUX_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI ,Assertion time setting for PLL_TX_LDV_RIPPLE_MUX_EN signal or group TX sequence"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "TSM_TIMING16,TSM Timing 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_FILTER_CHARGE_EN_RX_LO ,Deassertion time setting for PLL_FILTER_CHARGE_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_FILTER_CHARGE_EN_RX_HI ,Assertion time setting for PLL_FILTER_CHARGE_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_FILTER_CHARGE_EN_TX_LO ,Deassertion time setting for PLL_FILTER_CHARGE_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_FILTER_CHARGE_EN_TX_HI ,Assertion time setting for PLL_FILTER_CHARGE_EN signal or group TX sequence"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "TSM_TIMING17,TSM Timing 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_PHDET_EN_RX_LO ,Deassertion time setting for PLL_PHDET_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_PHDET_EN_RX_HI ,Assertion time setting for PLL_PHDET_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_PHDET_EN_TX_LO ,Deassertion time setting for PLL_PHDET_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_PHDET_EN_TX_HI ,Assertion time setting for PLL_PHDET_EN signal or group TX sequence"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "TSM_TIMING18,TSM Timing 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " QGEN25_EN_RX_LO ,Deassertion time setting for QGEN25_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " QGEN25_EN_RX_HI ,Assertion time setting for QGEN25_EN signal or group RX sequence"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "TSM_TIMING19,TSM Timing 19"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TX_EN_TX_LO ,Deassertion time setting for TX_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_EN_TX_HI ,Assertion time setting for TX_EN signal or group TX sequence"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "TSM_TIMING20,TSM Timing 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ADC_EN_RX_LO ,Deassertion time setting for ADC_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ADC_EN_RX_HI ,Assertion time setting for ADC_EN signal or group RX sequence"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "TSM_TIMING21,TSM Timing 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ADC_I_Q_EN_RX_LO ,Deassertion time setting for ADC_I_Q_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ADC_I_Q_EN_RX_HI ,Assertion time setting for ADC_I_Q_EN signal or group RX sequence"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "TSM_TIMING22,TSM Timing 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ADC_DAC_EN_RX_LO ,Deassertion time setting for ADC_DAC_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ADC_DAC_EN_RX_HI ,Assertion time setting for ADC_DAC_EN signal or group RX sequence"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "TSM_TIMING23,TSM Timing 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ADC_RST_EN_RX_LO ,Deassertion time setting for ADC_RST_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ADC_RST_EN_RX_HI ,Assertion time setting for ADC_RST_EN signal or group RX sequence"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "TSM_TIMING24,TSM Timing 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BBF_EN_RX_LO ,Deassertion time setting for BBF_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BBF_EN_RX_HI ,Assertion time setting for BBF_EN signal or group RX sequence"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "TSM_TIMING25,TSM Timing 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TCA_EN_RX_LO ,Deassertion time setting for TCA_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCA_EN_RX_HI ,Assertion time setting for TCA_EN signal or group RX sequence"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "TSM_TIMING26,TSM Timing 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PLL_DIG_EN_RX_LO ,Deassertion time setting for PLL_DIG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL_DIG_EN_RX_HI ,Assertion time setting for PLL_DIG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLL_DIG_EN_TX_LO ,Deassertion time setting for PLL_DIG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLL_DIG_EN_TX_HI ,Assertion time setting for PLL_DIG_EN signal or group TX sequence"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "TSM_TIMING27,TSM Timing 27"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TX_DIG_EN_TX_LO ,Deassertion time setting for TX_DIG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DIG_EN_TX_HI ,Assertion time setting for TX_DIG_EN signal or group TX sequence"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "TSM_TIMING28,TSM Timing 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RX_DIG_EN_RX_LO ,Deassertion time setting for RX_DIG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_DIG_EN_RX_HI ,Assertion time setting for RX_DIG_EN signal or group RX sequence"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "TSM_TIMING29,TSM Timing 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RX_INIT_EN_RX_LO ,Deassertion time setting for RX_INIT_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_INIT_EN_RX_HI ,Assertion time setting for RX_INIT_EN signal or group RX sequence"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "TSM_TIMING30,TSM Timing 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SIGMA_DELTA_EN_RX_LO ,Deassertion time setting for SIGMA_DELTA_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SIGMA_DELTA_EN_RX_HI ,Assertion time setting for SIGMA_DELTA_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SIGMA_DELTA_EN_TX_LO ,Deassertion time setting for SIGMA_DELTA_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SIGMA_DELTA_EN_TX_HI ,Assertion time setting for SIGMA_DELTA_EN signal or group TX sequence"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "TSM_TIMING31,TSM Timing 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ZBDEM_RX_EN_RX_LO ,Deassertion time setting for ZBDEM_RX_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ZBDEM_RX_EN_RX_HI ,Assertion time setting for ZBDEM_RX_EN signal or group RX sequence"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "TSM_TIMING32,TSM Timing 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DCOC_EN_RX_LO ,Deassertion time setting for DCOC_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCOC_EN_RX_HI ,Assertion time setting for DCOC_EN signal or group RX sequence"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "TSM_TIMING33,TSM Timing 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DCOC_INIT_RX_LO ,Deassertion time setting for DCOC_INIT signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCOC_INIT_RX_HI ,Assertion time setting for DCOC_INIT signal or group RX sequence"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "TSM_TIMING34,TSM Timing 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FREQ_TARG_LD_EN_RX_LO ,Deassertion time setting for FREQ_TARG_LD_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FREQ_TARG_LD_EN_RX_HI ,Assertion time setting for FREQ_TARG_LD_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " FREQ_TARG_LD_EN_TX_LO ,Deassertion time setting for FREQ_TARG_LD_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FREQ_TARG_LD_EN_TX_HI ,Assertion time setting for FREQ_TARG_LD_EN signal or group TX sequence"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "TSM_TIMING35,TSM Timing 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SAR_ADC_TRIG_EN_RX_LO ,Deassertion time setting for SAR_ADC_TRIG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SAR_ADC_TRIG_EN_RX_HI ,Assertion time setting for SAR_ADC_TRIG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SAR_ADC_TRIG_EN_TX_LO ,Deassertion time setting for SAR_ADC_TRIG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAR_ADC_TRIG_EN_TX_HI ,Assertion time setting for SAR_ADC_TRIG_EN signal or group TX sequence"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "TSM_TIMING36,TSM Timing 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TSM_SPARE0_EN_RX_LO ,Deassertion time setting for TSM_SPARE0_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TSM_SPARE0_EN_RX_HI ,Assertion time setting for TSM_SPARE0_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TSM_SPARE0_EN_TX_LO ,Deassertion time setting for TSM_SPARE0_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSM_SPARE0_EN_TX_HI ,Assertion time setting for TSM_SPARE0_EN signal or group TX sequence"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "TSM_TIMING37,TSM Timing 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TSM_SPARE1_EN_RX_LO ,Deassertion time setting for TSM_SPARE1_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TSM_SPARE1_EN_RX_HI ,Assertion time setting for TSM_SPARE1_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TSM_SPARE1_EN_TX_LO ,Deassertion time setting for TSM_SPARE1_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSM_SPARE1_EN_TX_HI ,Assertion time setting for TSM_SPARE1_EN signal or group TX sequence"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "TSM_TIMING38,TSM Timing 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TSM_SPARE2_EN_RX_LO ,Deassertion time setting for TSM_SPARE2_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TSM_SPARE2_EN_RX_HI ,Assertion time setting for TSM_SPARE2_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TSM_SPARE2_EN_TX_LO ,Deassertion time setting for TSM_SPARE2_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSM_SPARE2_EN_TX_HI ,Assertion time setting for TSM_SPARE2_EN signal or group TX sequence"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "TSM_TIMING39,TSM Timing 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TSM_SPARE3_EN_RX_LO ,Deassertion time setting for TSM_SPARE3_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TSM_SPARE3_EN_RX_HI ,Assertion time setting for TSM_SPARE3_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TSM_SPARE3_EN_TX_LO ,Deassertion time setting for TSM_SPARE3_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSM_SPARE3_EN_TX_HI ,Assertion time setting for TSM_SPARE3_EN signal or group TX sequence"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "TSM_TIMING40,TSM Timing 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " GPIO0_TRIG_EN_RX_LO ,Deassertion time setting for GPIO0_TRIG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GPIO0_TRIG_EN_RX_HI ,Assertion time setting for GPIO0_TRIG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GPIO0_TRIG_EN_TX_LO ,Deassertion time setting for GPIO0_TRIG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GPIO0_TRIG_EN_TX_HI ,Assertion time setting for GPIO0_TRIG_EN signal or group TX sequence"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "TSM_TIMING41,TSM Timing 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " GPIO1_TRIG_EN_RX_LO ,Deassertion time setting for GPIO1_TRIG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GPIO1_TRIG_EN_RX_HI ,Assertion time setting for GPIO1_TRIG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GPIO1_TRIG_EN_TX_LO ,Deassertion time setting for GPIO1_TRIG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GPIO1_TRIG_EN_TX_HI ,Assertion time setting for GPIO1_TRIG_EN signal or group TX sequence"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "TSM_TIMING42,TSM Timing 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " GPIO2_TRIG_EN_RX_LO ,Deassertion time setting for GPIO2_TRIG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GPIO2_TRIG_EN_RX_HI ,Assertion time setting for GPIO2_TRIG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GPIO2_TRIG_EN_TX_LO ,Deassertion time setting for GPIO2_TRIG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GPIO2_TRIG_EN_TX_HI ,Assertion time setting for GPIO2_TRIG_EN signal or group TX sequence"
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "TSM_TIMING43,TSM Timing 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " GPIO3_TRIG_EN_RX_LO ,Deassertion time setting for GPIO3_TRIG_EN signal or group RX sequence"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GPIO3_TRIG_EN_RX_HI ,Assertion time setting for GPIO3_TRIG_EN signal or group RX sequence"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GPIO3_TRIG_EN_TX_LO ,Deassertion time setting for GPIO3_TRIG_EN signal or group TX sequence"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GPIO3_TRIG_EN_TX_HI ,Assertion time setting for GPIO3_TRIG_EN signal or group TX sequence"
|
|
group.long 0x3C0++0x1F
|
|
line.long 0x00 "CORR_CTRL,Correlator Control"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RX_MAX_PREAMBLE ,Max correlator during preamble"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_MAX_CORR ,Max correlator after preamble"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MAX_CORR_EN ,Max correlator after preamble enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " CORR_NVAL ,Number of consecutively detected zero-symbols required to declare a preamble detected" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CORR_VT ,Correlator threshold"
|
|
line.long 0x04 "PN_TYPE,Pseudo Noise Type"
|
|
bitfld.long 0x04 1. " TX_INV ,Test mode to invert the transmission" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " PN_TYPE ,Pseudo noise chip code type" "0,ZigBee"
|
|
line.long 0x08 "PN_CODE,Pseudo Noise Chip Code Seed Value"
|
|
hexmask.long.word 0x08 16.--31. 1. " PN_MSB ,PN_CODE MS half"
|
|
hexmask.long.word 0x08 0.--15. 1. " PN_LSB ,PN_CODE LS half"
|
|
line.long 0x0C "SYNC_CTRL,Sync Control"
|
|
bitfld.long 0x0C 3. " TRACK_ENABLE ,Track enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--2. " SYNC_PER ,Symbol Sync Tracking Period" "0,1,2,3,4,?..."
|
|
line.long 0x10 "SNF_THR,SNIFF Threshold"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SNF_THR ,SNIFF mode threshold"
|
|
line.long 0x14 "FAD_THR,FAD Threshold"
|
|
hexmask.long.byte 0x14 0.--7. 1. " FAD_THR ,Correlator threshold at which the FAD will select the antenna"
|
|
line.long 0x18 "ZBDEM_AFC,Zigbee LPPS Mode Timing Control AFC"
|
|
rbitfld.long 0x18 8.--12. " AFC_OUT ,AFC result" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 1. " DCD_EN ,DCD mode enable" "Disable,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " AFC_EN ,Enable the AFC function" "Disabled,Enabled"
|
|
line.long 0x1C "LPPS_CTRL,LPPS Control Register"
|
|
bitfld.long 0x1C 7. " LPPS_TCA_ALLOW ,LPPS TCA allow" "Disallowed,Allowed"
|
|
bitfld.long 0x1C 6. " LPPS_BBF_ALLOW ,LPPS BBF allow" "Disallowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " LPPS_ADC_DAC_ALLOW ,LPPS ADC DAC allow" "Disallowed,Allowed"
|
|
bitfld.long 0x1C 4. " LPPS_ADC_I_Q_ALLOW ,LPPS ADC I Q allow" "Disallowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " LPPS_ADC_CLK_ALLOW ,LPPS ADC CLK allow" "Disallowed,Allowed"
|
|
bitfld.long 0x1C 2. " LPPS_ADC_ALLOW ,LPPS ADC allow" "Disallowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " LPPS_QGEN25_ALLOW ,LPPS QGEN25 allow" "Disallowed,Allowed"
|
|
bitfld.long 0x1C 0. " LPPS_ENABLE ,LPPS mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
width 15.
|
|
group.long 0x400++0x17
|
|
line.long 0x00 "ADC_CTRL,ADC Control"
|
|
bitfld.long 0x00 31. " ADC_COMP_ON[15] ,ADC comparator 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ADC_COMP_ON[14] ,ADC comparator 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ADC_COMP_ON[13] ,ADC comparator 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ADC_COMP_ON[12] ,ADC comparator 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ADC_COMP_ON[11] ,ADC comparator 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ADC_COMP_ON[10] ,ADC comparator 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ADC_COMP_ON[9] ,ADC comparator 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ADC_COMP_ON[8] ,ADC comparator 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ADC_COMP_ON[7] ,ADC comparator 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ADC_COMP_ON[6] ,ADC comparator 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ADC_COMP_ON[5] ,ADC comparator 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ADC_COMP_ON[4] ,ADC comparator 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADC_COMP_ON[3] ,ADC comparator 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ADC_COMP_ON[2] ,ADC comparator 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ADC_COMP_ON[1] ,ADC comparator 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ADC_COMP_ON[0] ,ADC comparator 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ADC_TEST_ON ,ADC test on" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ADC_DITHER_ON ,ADC dither on" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADC_2X_CLK_SEL ,Select 2x Clock option in the ADC" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADC_32MHZ_SEL ,ADC 32MHZ clock select" "36MHz,32MHz"
|
|
line.long 0x04 "ADC_TUNE,ADC Tuning"
|
|
bitfld.long 0x04 20.--23. " ADC_C2_TUNE ,ADC capacitor 2 tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 16.--19. " ADC_C1_TUNE ,ADC capacitor 1 tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " ADC_R2_TUNE ,ADC resistor 2 tuning" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " ADC_R1_TUNE ,ADC resistor 1 tuning" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "ADC_ADJ,ADC Adjustment"
|
|
bitfld.long 0x08 28.--30. " ADC_FLSH_RES_ADJ ,ADC flash resistor adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 24.--26. " ADC_IB_FLSH_ADJ ,ADC quantizer preamplifier adjustment" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " ADC_IB_DAC2_ADJ ,ADC DAC 2 current adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 12.--14. " ADC_IB_DAC1_ADJ ,ADC DAC 1 current adjustment" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " ADC_IB_OPAMP2_ADJ ,ADC 2nd integrator operational amplifier reference current adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--2. " ADC_IB_OPAMP1_ADJ ,ADC 1st integrator operational amplifier reference current adjustment" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "ADC_REGS,ADC Regulators"
|
|
bitfld.long 0x0C 9. " ADC_DIG_REG_BYPASS_ON ,ADC digital regulator bypass mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " ADC_ANA_REG_BYPASS_ON ,ADC analog regulator bypass mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--7. " ADC_REG_DIG_SUPPLY ,ADC digital regulator trim bits to change the output voltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
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bitfld.long 0x0C 0.--3. " ADC_REG_ANA_REG_SUPPLY ,ADC analog regulator trim bits to change the output voltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
|
line.long 0x10 "ADC_TRIMS,ADC Regulator Trims"
|
|
bitfld.long 0x10 8.--10. " ADC_IREF_DAC_RES_TRIM ,Resistor value used to generate the reference current for the DACs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 4.--6. " ADC_IREF_FLSH_RES_TRIM ,Resistor value used to generate the reference current for the quantizer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " ADC_IREF_OPAMPS_RES_TRIM ,Resistor value used to generate the reference current for the integrator's operational amplifiers" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "ADC_TEST_CTRL,ADC Test Control"
|
|
bitfld.long 0x14 24.--26. " DCOC_ALPHA_RADIUS_GS_IDX ,DCOC Alpha-R scaling" "1,1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
bitfld.long 0x14 12.--13. " ADC_ANA_REG_ATST_SEL ,These bits control what internal signals are connected to the ATST bus" "Not connected,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x14 8.--9. " ADC_DIG_REG_ATST_SEL ,These bits control the what internal regulator signals are connected to the ATST bus" "Not connected,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x14 0.--4. " ADC_ATST_SEL ,ADC analog test selection" "Inject 5uA on ATST0/0.6V on ATST1,Monitor Flash on ATST3,Monitor DAC on ATST0/mirrored at ATST1/operational amplifiers at ATST2/buffered 0.6V for opamp1 at ATST3,Monitored buffered 0.6V for opamp2 at ATST0/buffered 0.6V for opam3 at ATST2,?..."
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "BBF_CTRL,Baseband Filter Control"
|
|
bitfld.long 0x00 12.--13. " DCOC_ALPHAC_SCALE_GS_IDX ,DCOC Alpha-C scaling" "1/2,1/4,1/8,1/16"
|
|
bitfld.long 0x00 11. " BBF_TMUX_ON ,Test mode for the baseband filter block enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BBF_CUR_CNTL ,Current in the BBF" "Low current,High current"
|
|
bitfld.long 0x00 4.--7. " BBF_RES_TUNE2 ,Programmable resistor to change the corner frequency of the passive pole" "0,,2,,,5,,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BBF_CAP_TUNE ,Programmable capacitor values to change the corner frequency of the first baseband filter" "0,,2,,,5,,7,?..."
|
|
if (((per.l(ad:0x4005C000+0x420))&0x800)==0x800)
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "RX_ANA_CTRL,RX Analog Controller"
|
|
bitfld.long 0x00 4. " IQMC_DC_GAIN_ADJ_EN ,IQMC gain adjustment enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " RX_ATST_SEL ,Different internal baseband signals to be made available on the ATST bus (ATST0/ATST1/ATST2/ATST3)" "Half supply voltage/Bbf opamp common mode voltage/Bbf_I_out/bbf_I_ouxt,Bba_dcoc_I/Bba_dcoc_Ix/Bba_dcoc_Q/Bba_dcoc_Qx,Tza_out_I/Tza_out_Ix/Tza_out_Q/Tza_out_Qx,Peak det ref hi/Peak det ref lo/Peak det bias check/Tza common mode,Bbf_out_I/Bbf_out_Ix/Bbf_out_Q/Bbf_out_Qx,Tza_dcoc_I/Tza_dcoc_Ix/Tza_dcoc_Q/Tza_dcoc_Qx,Tza_in_I/Tza_in_Ix/Tza_out_I/Tza_out_Ix,?..."
|
|
else
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "RX_ANA_CTRL,RX Analog Controller"
|
|
bitfld.long 0x00 4. " IQMC_DC_GAIN_ADJ_EN ,IQMC gain adjustment enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "XTAL_CTRL,Crystal Oscillator Control Register 1"
|
|
rbitfld.long 0x00 31. " XTAL_READY ,XTAL ready indicator" "Not ready,Ready"
|
|
bitfld.long 0x00 24.--28. " XTAL_COMP_BIAS_HI ,XTAL comparator bias high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " XTAL_ALC_ON ,Enable ALC for the xtal" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " XTAL_ALC_START_512U ,XTAL ALC start at 512 usec" "Start at 256usec,Start at 512usec"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " XTAL_COMP_BIAS_LO ,XTAL comparator bias low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--15. " XTAL_READY_COUNT_SEL ,XTAL ready count select" "1024 cycles,2048 cycles,4096 cycles,8192 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XTAL_BYPASS ,XTAL bypass" "No bypass,Bypass"
|
|
bitfld.long 0x00 8.--12. " XTAL_GM ,This is used adjust the gm of the Crystal core" "Minimum,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Maximum"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " XTAL_TRIM ,XTAL trim"
|
|
if (((per.l(ad:0x4005C000+0x438))&0x500)==0x500)
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "XTAL_CTRL2,Crystal Oscillator Control Register 2"
|
|
bitfld.long 0x00 26. " XTAL_ATST_ON ,Test mode for xtal block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " XTAL_REG_ATST_SEL ,These bits control the what internal regualtor signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x00 12. " XTAL_DIG_CLK_OUT_ON ,XTAL Crystal clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " XTAL_ON_OVRD ,Enable for the xtal in test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XTAL_ON_OVRD_ON ,Mux select for the crystal enable between normal operation and test mode" "Normal operation,Test mode"
|
|
bitfld.long 0x00 9. " XTAL_REG_ON_OVRD ,Enable for the xtal regulator in test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XTAL_REG_ON_OVRD_ON ,Mux select for the crystal enable between normal operation and test mode" "Normal operation,Test mode"
|
|
bitfld.long 0x00 4. " XTAL_REG_BYPASS_ON ,XTAL regualtor bypass mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " XTAL_REG_SUPPLY ,Regulator trim bit to change the outputvoltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
|
elif (((per.l(ad:0x4005C000+0x438))&0x500)==0x100)
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "XTAL_CTRL2,Crystal Oscillator Control Register 2"
|
|
bitfld.long 0x00 26. " XTAL_ATST_ON ,Test mode for xtal block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " XTAL_REG_ATST_SEL ,These bits control the what internal regualtor signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x00 12. " XTAL_DIG_CLK_OUT_ON ,XTAL Crystal clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XTAL_ON_OVRD_ON ,Mux select for the crystal enable between normal operation and test mode" "Normal operation,Test mode"
|
|
bitfld.long 0x00 9. " XTAL_REG_ON_OVRD ,Enable for the xtal regulator in test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XTAL_REG_ON_OVRD_ON ,Mux select for the crystal enable between normal operation and test mode" "Normal operation,Test mode"
|
|
bitfld.long 0x00 4. " XTAL_REG_BYPASS_ON ,XTAL regualtor bypass mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " XTAL_REG_SUPPLY ,Regulator trim bit to change the outputvoltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
|
elif (((per.l(ad:0x4005C000+0x438))&0x500)==0x400)
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "XTAL_CTRL2,Crystal Oscillator Control Register 2"
|
|
bitfld.long 0x00 26. " XTAL_ATST_ON ,Test mode for xtal block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " XTAL_REG_ATST_SEL ,These bits control the what internal regualtor signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x00 12. " XTAL_DIG_CLK_OUT_ON ,XTAL Crystal clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " XTAL_ON_OVRD ,Enable for the xtal in test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XTAL_ON_OVRD_ON ,Mux select for the crystal enable between normal operation and test mode" "Normal operation,Test mode"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XTAL_REG_ON_OVRD_ON ,Mux select for the crystal enable between normal operation and test mode" "Normal operation,Test mode"
|
|
bitfld.long 0x00 4. " XTAL_REG_BYPASS_ON ,XTAL regualtor bypass mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " XTAL_REG_SUPPLY ,Regulator trim bit to change the outputvoltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
|
else
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "XTAL_CTRL2,Crystal Oscillator Control Register 2"
|
|
bitfld.long 0x00 26. " XTAL_ATST_ON ,Test mode for xtal block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " XTAL_REG_ATST_SEL ,These bits control the what internal regualtor signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x00 12. " XTAL_DIG_CLK_OUT_ON ,XTAL Crystal clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XTAL_ON_OVRD_ON ,Mux select for the crystal enable between normal operation and test mode" "Normal operation,Test mode"
|
|
textline " "
|
|
bitfld.long 0x00 8. " XTAL_REG_ON_OVRD_ON ,Mux select for the crystal enable between normal operation and test mode" "Normal operation,Test mode"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XTAL_REG_BYPASS_ON ,XTAL regualtor bypass mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " XTAL_REG_SUPPLY ,Regulator trim bit to change the outputvoltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
|
endif
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "BGAP_CTRL,Bandgap Control"
|
|
bitfld.long 0x00 12. " BGAP_ATST_ON ,This bit enables the test mux for the bangap block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BGAP_ATST_SEL ,Select what internal signals to bring out to ATST bus (ATST2/ATST3)" "1uA/Unfiltered bgap output,2uA/Internal X1 node of bgap,5uA/Internal X2 node of bgap,10uA/No connect,1uA ptat/No connect,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " BGAP_VOLTAGE_TRIM ,Trim the bandgap voltage to 1V in 4mV steps" "0.94V,0.944V,0.948V,0.952V,0.956V,0.96V,0.964V,0.968V,0.972V,0.976V,0.98V,0.984V,0.988V,0.992V,0.996V,1V"
|
|
bitfld.long 0x00 0.--3. " BGAP_CURRENT_TRIM ,Trim the 1uA bandgap current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x444++0x07
|
|
line.long 0x00 "PLL_CTRL,PLL Control Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " HPM_BIAS ,HPM array bias"
|
|
bitfld.long 0x00 17. " PLL_VCO_LDO_BYPASS ,This register bit determines if the regulator is in bypass mode" "No bypass,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PLL_REG_BYPASS_ON ,This register bit determines if the regulator is in bypass mode" "No bypass,Bypass"
|
|
bitfld.long 0x00 8.--11. " PLL_REG_SUPPLY ,Regulator trim bit to change the output voltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLL_LFILT_CNTL ,PLL loop filter control" "25.6K/26K,20.8K/26K,15.4K/26K,10.3K/26K,25.6K/100,20.8K/100,15.4K/100,10.3K/100"
|
|
bitfld.long 0x00 0.--2. " PLL_VCO_BIAS ,PLL VCO bias control" "1.5mA,1.575mA,1.65mA,1.725mA,1.8mA,1.875mA,1.95mA,2.1mA"
|
|
line.long 0x04 "PLL_CTRL2,PLL Control Register 2"
|
|
bitfld.long 0x04 8. " PLL_TMUX_ON ,PLL testmux enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4.--5. " PLL_VCO_REG_SUPPLY ,Regulator trim bits to change the output voltage" "1.15V,1.2V,1.25V,1.3V"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PLL_KMOD_SLOPE ,Slope of the highport capacitor bank" "10KHz,15KHz"
|
|
bitfld.long 0x04 0.--2. " PLL_VCO_KV ,Gain of the VCO" "Minimum,1,2,3,4,5,6,Maximum"
|
|
if (((per.l(ad:0x4005C000+0x448))&0x100)==0x100)
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "PLL_TEST_CTRL,PLL Test Control"
|
|
bitfld.long 0x00 14. " PLL_RIPPLE_COUNTER_TEST_MODE ,PLL ripple counter test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PLL_FORCE_VTUNE_EXTERNALLY ,Force VTUNE externally" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PLL_VCO_TEST_CLK_MODE ,Test mode for the VCO" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PLL_REG_ATST_SEL ,These bits control the what internal regulator signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PLL_VCO_REG_ATST ,These bits determine what internal signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PLL_TMUX_SEL ,Select what internal signals to bring out to ATST pins (ATST0/ATST1/ATST2/ATST3)" "Precharge_filt/Xor_out/Pll_ref_xtal/Pll_ref_xtal_b,Pll_sigma_delta_clk/Pll_loop_div_count[0]/Pll_loop_div_count[1]/Pll_loop_div_count[2],Pll_loop_div_count[3]/Pll_loop_div_count[4]/Pll_loop_div_count[8]/No connect,Pll_ripple_counter_override_clk/No connect/No connect/No connect"
|
|
else
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "PLL_TEST_CTRL,PLL Test Control"
|
|
bitfld.long 0x00 14. " PLL_RIPPLE_COUNTER_TEST_MODE ,PLL ripple counter test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PLL_FORCE_VTUNE_EXTERNALLY ,Force VTUNE externally" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PLL_VCO_TEST_CLK_MODE ,Test mode for the VCO" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PLL_REG_ATST_SEL ,These bits control the what internal regulator signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PLL_VCO_REG_ATST ,These bits determine what internal signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
endif
|
|
textline " "
|
|
width 13.
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "QGEN_CTRL,QGEN Control"
|
|
bitfld.long 0x00 8. " QGEN_BYPASS_ON ,QGEN regulator bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " QGEN_REG_ATST_SEL ,These bits control the what internal regulator signals are connected to the ATST bus" "No connect,Vout,Vin feedback,Vbias,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " QGEN_REG_SUPPLY ,Regulator trim bits to change the output voltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
|
group.long 0x464++0x07
|
|
line.long 0x00 "TCA_CTRL,TCA Control"
|
|
bitfld.long 0x00 8.--9. " TCA_TX_REG_ATST_SEL ,These bits determine what internal signals to connect to ATST bus" "No connect,Vout,Vin feedback,Vbias"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TCA_TX_REG_SUPPLY ,Regulator trim bit to change the output voltage" "1.2V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TCA_TX_REG_BYPASS_ON ,This register bit determines if the regulator is in bypass mode" "No bypass,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TCA_LOW_PWR_ON ,Enable the TCA low power mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TCA_BIAS_CURR ,Programmable bias currrent for the TCA" "0,1,2,3"
|
|
line.long 0x04 "TZA_CTRL,TZA Control"
|
|
bitfld.long 0x04 6.--7. " TZA_CUR_CNTL ,Program the current in TZA" "510 uA,1.0 mA,1.6 mA,2.1 mA"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " TZA_CAP_TUNE ,The bits sets the f3dB filter corner for the TZA block" "0,,2,,,5,,7,?..."
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "TX_ANA_CTRL,TX Analog Control"
|
|
bitfld.long 0x00 0.--3. " HPM_CAL_ADJUST ,HPM Cal Count Adjust" "-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "ANA_SPARE,Analog Spare"
|
|
bitfld.long 0x00 14.--15. " HPM_LSB_INVERT ,High port LSB array inversion control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 11.--13. " DCOC_TRK_EST_GS_CNT ,DCOC tracking estimator gearshift count" "Only parameters,Switch after 1 correction,Switch after 2 corrections,Switch after 3 corrections,Switch after 4 corrections,Switch after 5 corrections,Switch after 6 corrections,Switch after 7 corrections"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " IQMC_DC_GAIN_ADJ ,IQ mismatch correction DC gain coefficient"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*"))
|
|
tree "BLE RF"
|
|
base ad:0x4005BD00
|
|
width 13.
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "BLE_PART_ID,Bluetooth Low Energy Part ID"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "DSM_STATUS,DSM Status"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 2. " XCVR_BUSY ,Transceiver busy status bit" "Idle,Busy"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 1. " RIF_LL_ACTIVE ,Link layer active" "Inactive,Active"
|
|
bitfld.word 0x00 0. " ORF_SYSCLK_REQ ,RF oscillator requested" "Not requested,Requested"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "BLE_AFC,Bluetooth Low Energy AFC"
|
|
bitfld.word 0x00 15. " LATCH_AFC_ON_ACCESS_MATCH ,Latch AFC estimation on access address match" "No,Yes"
|
|
hexmask.word 0x00 0.--13. 1. " BLE_AFC ,BLE AFC result"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "BLE_BSM,Bluetooth Low Energy BSM"
|
|
bitfld.word 0x00 0. " BSM_EN_BLE ,BLE bit streaming mode enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MISC_CTRL,Bluetooth Low Energy Miscellaneous Control"
|
|
bitfld.word 0x00 1. " TSM_INTR_EN ,TSM interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("MKW41Z*")||cpuis("MKW31Z*"))
|
|
tree "BLE RF"
|
|
base ad:0x4005B600
|
|
width 13.
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "BLE_PART_ID,Bluetooth Low Energy Part ID"
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "DSM_STATUS,DSM Status"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*"))
|
|
bitfld.word 0x00 2. " XCVR_BUSY ,Transceiver busy status bit" "Idle,Busy"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 1. " RIF_LL_ACTIVE ,Link layer active" "Inactive,Active"
|
|
bitfld.word 0x00 0. " ORF_SYSCLK_REQ ,RF oscillator requested" "Not requested,Requested"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "BLE_AFC,Bluetooth Low Energy AFC"
|
|
bitfld.word 0x00 15. " LATCH_AFC_ON_ACCESS_MATCH ,Latch AFC estimation on access address match" "No,Yes"
|
|
hexmask.word 0x00 0.--13. 1. " BLE_AFC ,BLE AFC result"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "BLE_BSM,Bluetooth Low Energy BSM"
|
|
bitfld.word 0x00 0. " BSM_EN_BLE ,BLE bit streaming mode enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MISC_CTRL,Bluetooth Low Energy Miscellaneous Control"
|
|
bitfld.word 0x00 1. " TSM_INTR_EN ,TSM interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Generic FSK"
|
|
base ad:0x4005F000
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "IRQ_CTRL,IRQ Control"
|
|
rbitfld.long 0x00 31. " CRC_VALID ,CRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. " CRC_IGNORE ,CRC ignore" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GENERIC_FSK_IRQ_EN ,GENERIC_FSK interrupt master enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TSM_IRQ_EN ,TSM interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_WATERMARK_IRQ_EN ,RX watermark interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " WAKE_IRQ_EN ,Wake interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PLL_UNLOCK_IRQ_EN ,PLL unlock interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " T2_IRQ_EN ,Timer2 (T2) compare interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " T1_IRQ_EN ,Timer1 (T1) compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " NTW_ADR_IRQ_EN ,Network address match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RX_IRQ_EN ,RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TX_IRQ_EN ,TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEQ_END_IRQ_EN ,Sequence end interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " TSM_IRQ ,TSM interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RX_WATERMARK_IRQ ,RX watermark interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " WAKE_IRQ ,Wake interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " PLL_UNLOCK_IRQ ,PLL unlock interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " T2_IRQ ,Timer2 (T2) compare interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " T1_IRQ ,Timer1 (T1) compare interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " NTW_ADR_IRQ ,Network address match interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " RX_IRQ ,RX interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " TX_IRQ ,TX interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " SEQ_END_IRQ ,Sequence end interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "EVENT_TMR,Event Timer"
|
|
bitfld.long 0x04 25. " EVENT_TMR_ADD ,Event timer add" "No effect,Add"
|
|
bitfld.long 0x04 24. " EVENT_TMR_LD ,Event timer load" "No effect,Load"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " EVENT_TMR ,Event timer"
|
|
line.long 0x08 "T1_CMP,T1 Compare"
|
|
bitfld.long 0x08 24. " T1_CMP_EN ,Timer1 (T1) compare enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " T1_CMP ,Timer1 (T1) compare value"
|
|
line.long 0x0C "T2_CMP,T2 Compare"
|
|
bitfld.long 0x0C 24. " T2_CMP_EN ,Timer2 (T2) compare enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " T2_CMP ,Timer2 (T2) compare value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMESTAMP,Timestamp"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TIMESTAMP ,Received packet timestamp"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "XCVR_CTRL,Transceiver Control"
|
|
rbitfld.long 0x00 31. " XCVR_BUSY ,Transceiver busy" "Idle,Busy"
|
|
rbitfld.long 0x00 24.--26. " CMDDEC_CS ,Command decode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SEQCMD ,Sequence commands" "No action,TX start now,TX start @ T1,TX start @ T2,TX cancel,RX start now,RX start @ T1,RX start @ T2,RX stop @ T1,RX stop @ T2,RX cancel,Abort All,?..."
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "XCVR_STS,Transceiver Status"
|
|
hexmask.long.byte 0x00 24.--31. 1. " LQI ,Link quality indicator"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RSSI ,Received signal stength indicator, in dBm"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CRC_VALID ,CRC valid indicator" "Invalid,Valid"
|
|
bitfld.long 0x00 14. " LQI_VALID ,LQI valid indicator" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_IN_WARMDN ,RX warmdown status" "No,Yes"
|
|
bitfld.long 0x00 11. " RX_IN_PROGRESS ,RX in progress status" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_IN_SEARCH ,RX search status" "No,Yes"
|
|
bitfld.long 0x00 9. " RX_IN_WARMUP ,RX warmup status" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RX_STOP_T2_PEND ,RX T2 start pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " RX_STOP_T1_PEND ,RX T1 stop pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RX_START_T2_PEND ,RX T2 start pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " RX_START_T1_PEND ,RX T1 start pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX_IN_WARMDN ,TX warmdown status" "No,Yes"
|
|
bitfld.long 0x00 3. " TX_IN_PROGRESS ,TX in progress status" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_IN_WARMUP ,TX warmup status" "No,Yes"
|
|
bitfld.long 0x00 1. " TX_START_T2_PEND ,TX T2 start pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TX_START_T1_PEND ,TX T1 start pending status" "Not pending,Pending"
|
|
group.long 0x1C++0x23
|
|
line.long 0x00 "XCVR_CFG,Transceiver Configuration"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_WARMUP ,Receive warmup time"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TX_WARMUP ,Transmit warmup time"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PREAMBLE_SZ ,Preamble size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SW_CRC_EN ,Software CRC enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_DEWHITEN_DIS ,RX de-whitening disable" "No,Yes"
|
|
bitfld.long 0x00 0. " TX_WHITEN_DIS ,TX whitening disable" "No,Yes"
|
|
line.long 0x04 "CHANNEL_NUM,Channel Number"
|
|
hexmask.long.byte 0x04 0.--6. 1. " CHANNEL_NUM ,Channel number"
|
|
line.long 0x08 "TX_POWER,Transmit Power"
|
|
bitfld.long 0x08 0.--5. " TX_POWER ,Transmit power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "NTW_ADR_CTRL,Network Address Control"
|
|
bitfld.long 0x0C 28.--30. " NTW_ADR_THR3 ,Network address 3 threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 24.--26. " NTW_ADR_THR2 ,Network address 2 threshold" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--22. " NTW_ADR_THR1 ,Network address 1 threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 16.--18. " NTW_ADR_THR0 ,Network address 0 threshold" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " NTW_ADR3_SZ ,Network address 3 size" "8-bit,16-bit,24-bit,32-bit"
|
|
bitfld.long 0x0C 12.--13. " NTW_ADR2_SZ ,Network address 2 size" "8-bit,16-bit,24-bit,32-bit"
|
|
textline " "
|
|
bitfld.long 0x0C 10.--11. " NTW_ADR1_SZ ,Network address 1 size" "8-bit,16-bit,24-bit,32-bit"
|
|
bitfld.long 0x0C 8.--9. " NTW_ADR0_SZ ,Network address 0 size" "8-bit,16-bit,24-bit,32-bit"
|
|
textline " "
|
|
rbitfld.long 0x0C 7. " NTW_ADR_MCH[3] ,Network address match - address 3" "No match,Match"
|
|
rbitfld.long 0x0C 6. " [2] ,Network address match - address 2" "No match,Match"
|
|
textline ""
|
|
rbitfld.long 0x0C 5. " [1] ,Network address match - address 1" "No match,Match"
|
|
rbitfld.long 0x0C 4. " [0] ,Network address match - address 0 " "No match,Match"
|
|
textline ""
|
|
bitfld.long 0x0C 3. " NTW_ADR_EN[3] ,Network address enable - address 3" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [2] ,Network address enable - address 2" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x0C 1. " [1] ,Network address enable - address 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [0] ,Network address enable - address 0" "Disabled,Enabled"
|
|
line.long 0x10 "NTW_ADR_0,Network Address 0"
|
|
line.long 0x14 "NTW_ADR_1,Network Address 1"
|
|
line.long 0x18 "NTW_ADR_2,Network Address 2"
|
|
line.long 0x1C "NTW_ADR_3,Network Address 3"
|
|
line.long 0x20 "RX_WATERMARK,Receive Watermark"
|
|
hexmask.long.word 0x20 16.--28. 1. " BYTE_COUNTER ,Byte counter"
|
|
hexmask.long.word 0x20 0.--12. 1. " RX_WATERMARK ,Receive watermark"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "DSM_CTRL,DSM Control"
|
|
bitfld.long 0x00 0. " GENERIC_FSK_SLEEP_EN ,GENERIC_FSK DSM sleep enable" "Disable,Enable"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PART_ID,Part Id"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_ID ,Part ID"
|
|
group.long 0x60++0x27
|
|
line.long 0x00 "PACKET_CFG,Packet Configuration"
|
|
bitfld.long 0x00 31. " H1_FAIL ,H1 violated status bit" "Not violated,Violated"
|
|
bitfld.long 0x00 24.--28. " H1_SZ ,H1 size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " H0_FAIL ,H0 violated status bit" "Not violated,Violated"
|
|
bitfld.long 0x00 16.--20. " H0_SZ ,H0 size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " LENGTH_FAIL ,Maximum length violated status bit" "Not violated,Violated"
|
|
bitfld.long 0x00 8.--13. " LENGTH_ADJ ,Length adjustment" "PAYLOAD + CRC,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SYNC_ADDR_SZ ,Sync address size" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LENGTH_BIT_ORD ,LENGTH bit order" "LS first,MS first"
|
|
bitfld.long 0x00 0.--4. " LENGTH_SZ ,LENGTH size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x04 "H0_CFG,H0 Configuration"
|
|
bitfld.long 0x04 31. " H0_MASK ,H0 mask register - bit 15" "0,1"
|
|
bitfld.long 0x04 30. ",H0 mask register - bit 14" "0,1"
|
|
bitfld.long 0x04 29. ",H0 mask register - bit 13" "0,1"
|
|
bitfld.long 0x04 28. ",H0 mask register - bit 12" "0,1"
|
|
bitfld.long 0x04 27. ",H0 mask register - bit 11" "0,1"
|
|
bitfld.long 0x04 26. ",H0 mask register - bit 10" "0,1"
|
|
bitfld.long 0x04 25. ",H0 mask register - bit 9" "0,1"
|
|
bitfld.long 0x04 24. ",H0 mask register - bit 8" "0,1"
|
|
bitfld.long 0x04 23. ",H0 mask register - bit 7" "0,1"
|
|
bitfld.long 0x04 22. ",H0 mask register - bit 6" "0,1"
|
|
bitfld.long 0x04 21. ",H0 mask register - bit 5" "0,1"
|
|
bitfld.long 0x04 20. ",H0 mask register - bit 4" "0,1"
|
|
bitfld.long 0x04 19. ",H0 mask register - bit 3" "0,1"
|
|
bitfld.long 0x04 18. ",H0 mask register - bit 2" "0,1"
|
|
bitfld.long 0x04 17. ",H0 mask register - bit 1" "0,1"
|
|
bitfld.long 0x04 16. ",H0 mask register - bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 15. " H0_MATCH ,H0 match register - bit 15" "0,1"
|
|
bitfld.long 0x04 14. ",H0 match register - bit 14" "0,1"
|
|
bitfld.long 0x04 13. ",H0 match register - bit 13" "0,1"
|
|
bitfld.long 0x04 12. ",H0 match register - bit 12" "0,1"
|
|
bitfld.long 0x04 11. ",H0 match register - bit 11" "0,1"
|
|
bitfld.long 0x04 10. ",H0 match register - bit 10" "0,1"
|
|
bitfld.long 0x04 9. ",H0 match register - bit 9" "0,1"
|
|
bitfld.long 0x04 8. ",H0 match register - bit 8" "0,1"
|
|
bitfld.long 0x04 7. ",H0 match register - bit 7" "0,1"
|
|
bitfld.long 0x04 6. ",H0 match register - bit 6" "0,1"
|
|
bitfld.long 0x04 5. ",H0 match register - bit 5" "0,1"
|
|
bitfld.long 0x04 4. ",H0 match register - bit 4" "0,1"
|
|
bitfld.long 0x04 3. ",H0 match register - bit 3" "0,1"
|
|
bitfld.long 0x04 2. ",H0 match register - bit 2" "0,1"
|
|
bitfld.long 0x04 1. ",H0 match register - bit 1" "0,1"
|
|
bitfld.long 0x04 0. ",H0 match register - bit 0" "0,1"
|
|
line.long 0x08 "H1_CFG,H1 Configuration"
|
|
bitfld.long 0x08 31. " H1_MASK ,H1 mask register - bit 15" "0,1"
|
|
bitfld.long 0x08 30. ",H1 mask register - bit 14" "0,1"
|
|
bitfld.long 0x08 29. ",H1 mask register - bit 13" "0,1"
|
|
bitfld.long 0x08 28. ",H1 mask register - bit 12" "0,1"
|
|
bitfld.long 0x08 27. ",H1 mask register - bit 11" "0,1"
|
|
bitfld.long 0x08 26. ",H1 mask register - bit 10" "0,1"
|
|
bitfld.long 0x08 25. ",H1 mask register - bit 9" "0,1"
|
|
bitfld.long 0x08 24. ",H1 mask register - bit 8" "0,1"
|
|
bitfld.long 0x08 23. ",H1 mask register - bit 7" "0,1"
|
|
bitfld.long 0x08 22. ",H1 mask register - bit 6" "0,1"
|
|
bitfld.long 0x08 21. ",H1 mask register - bit 5" "0,1"
|
|
bitfld.long 0x08 20. ",H1 mask register - bit 4" "0,1"
|
|
bitfld.long 0x08 19. ",H1 mask register - bit 3" "0,1"
|
|
bitfld.long 0x08 18. ",H1 mask register - bit 2" "0,1"
|
|
bitfld.long 0x08 17. ",H1 mask register - bit 1" "0,1"
|
|
bitfld.long 0x08 16. ",H1 mask register - bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 15. " H1_MATCH ,H1 match register - bit 15" "0,1"
|
|
bitfld.long 0x08 14. ",H1 match register - bit 14" "0,1"
|
|
bitfld.long 0x08 13. ",H1 match register - bit 13" "0,1"
|
|
bitfld.long 0x08 12. ",H1 match register - bit 12" "0,1"
|
|
bitfld.long 0x08 11. ",H1 match register - bit 11" "0,1"
|
|
bitfld.long 0x08 10. ",H1 match register - bit 10" "0,1"
|
|
bitfld.long 0x08 9. ",H1 match register - bit 9" "0,1"
|
|
bitfld.long 0x08 8. ",H1 match register - bit 8" "0,1"
|
|
bitfld.long 0x08 7. ",H1 match register - bit 7" "0,1"
|
|
bitfld.long 0x08 6. ",H1 match register - bit 6" "0,1"
|
|
bitfld.long 0x08 5. ",H1 match register - bit 5" "0,1"
|
|
bitfld.long 0x08 4. ",H1 match register - bit 4" "0,1"
|
|
bitfld.long 0x08 3. ",H1 match register - bit 3" "0,1"
|
|
bitfld.long 0x08 2. ",H1 match register - bit 2" "0,1"
|
|
bitfld.long 0x08 1. ",H1 match register - bit 1" "0,1"
|
|
bitfld.long 0x08 0. ",H1 match register - bit 0" "0,1"
|
|
line.long 0x0C "CRC_CFG,CRC Configuration"
|
|
bitfld.long 0x0C 18. " CRC_BYTE_ORD ,CRC byte order" "LSB first,MSB first"
|
|
bitfld.long 0x0C 17. " CRC_REF_OUT ,CRC reflect out" "LSB first,MSB first"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " CRC_REF_IN ,CRC reflect in" "Not reflected,Reflected"
|
|
bitfld.long 0x0C 8.--11. " CRC_START_BYTE ,Configure CRC start point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " CRC_SZ ,CRC size (in octets)" "0,1,2,3,4,?..."
|
|
line.long 0x10 "CRC_INIT,CRC Initialization"
|
|
line.long 0x14 "CRC_POLY,CRC Polynomial"
|
|
line.long 0x18 "CRC_XOR_OUT,CRC Xor Out"
|
|
line.long 0x1C "WHITEN_CFG,Whitener Configuration"
|
|
hexmask.long.word 0x1C 16.--24. 1. " WHITEN_INIT ,Initialization value for whitening/de-whitening"
|
|
bitfld.long 0x1C 14. " MANCHESTER_START ,Configure manchester encoding start point" "Payload,Header"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " MANCHESTER_INV ,Configure for inverted manchester encoding" "Not inverted,Inverted"
|
|
bitfld.long 0x1C 12. " MANCHESTER_EN ,Configure for manchester encoding/decoding" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8.--11. " WHITEN_SIZE ,Length of whitener LFSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 6. " WHITEN_PAYLOAD_REINIT ,Configure for whitener re-initialization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " WHITEN_REF_IN ,Whiten reflect input" "Not reflected,Reflected"
|
|
bitfld.long 0x1C 4. " WHITEN_POLY_TYPE ,Whiten polynomial type" "Galois,Fibonacci"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " WHITEN_B4_CRC ,Configure for whitening-before-CRC" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " WHITEN_END ,Configure end-of-whitening" "Payload,CRC"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--1. " WHITEN_START ,Configure whitener start point" "Disabled,Start-of-H0,Start-of-H1 if LENGTH > WHITEN_SZ_THR,Start-of-payload if LENGTH > WHITEN_SZ_THR"
|
|
line.long 0x20 "WHITEN_POLY,Whitener Polynomial"
|
|
hexmask.long.word 0x20 0.--8. 1. " WHITEN_POLY ,Whitener polynomial"
|
|
line.long 0x24 "WHITEN_SZ_THR,Whitener Size Threshold"
|
|
bitfld.long 0x24 23. " REC_BAD_PKT ,Receive bad packets" "Disabled,Enabled"
|
|
hexmask.long.byte 0x24 16.--22. 1. " LENGTH_MAX ,Maximum length for received packets"
|
|
textline " "
|
|
hexmask.long.word 0x24 0.--11. 1. " WHITEN_SZ_THR ,Whitener size threshold"
|
|
if (((per.l(ad:0x4005F000+0x7C))&0x1000)==0x0000)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "BITRATE,Bit Rate"
|
|
bitfld.long 0x00 0.--1. " BITRATE ,Bit rate" "1Mbit/sec,500Kbit/sec,250Kbit/sec,?..."
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "BITRATE,Bit Rate"
|
|
bitfld.long 0x00 0.--1. " BITRATE ,Bit rate" "1Mbit/sec,500Kbit/sec,?..."
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PB_PARTITION,Packet Buffer Partition Point"
|
|
hexmask.long.word 0x00 0.--10. 1. " PB_PARTITION ,Packet buffer partition point"
|
|
group.word 0x700++0x01
|
|
line.word 0x00 "PACKET_BUFFER,Packet Buffer"
|
|
textfld " "
|
|
button "Data" "d ad:ad:0x4005F000+0x700--ad:ad:0x4005F000+0xF7F /word"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW20Z*")||cpuis("MKW41Z*")||cpuis("MKW21Z*"))
|
|
tree "ZigBee"
|
|
base ad:0x4005D000
|
|
width 19.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "IRQSTS,Interrupt Request Status"
|
|
hexmask.long.byte 0x00 24.--30. 1. " RX_FRAME_LENGTH ,Receive Frame Length"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TMR4MSK ,Timer comperator 4 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " TMR3MSK ,Timer comperator 3 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TMR2MSK ,Timer comperator 2 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " TMR1MSK ,Timer comperator 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
eventfld.long 0x00 19. " TMR4IRQ ,Timer 4 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " TMR3IRQ ,Timer 3 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " TMR2IRQ ,Timer 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " TMR1IRQ ,Timer 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " CRCVALID ,CRC valid status" "Invalid,Valid"
|
|
rbitfld.long 0x00 14. " CCA ,CCA status" "Idle,Busy"
|
|
rbitfld.long 0x00 13. " SRCADDR ,Source address match status" "Not matched,Matched"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " PI ,Poll indication" "Not data request,Data request"
|
|
rbitfld.long 0x00 11. " ENH_PKT_STATUS ,Enhanced packet status" "Not enhanced,Enhanced"
|
|
textline " "
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW20Z*"))
|
|
eventfld.long 0x00 9. " PB_ERR_IRQ ,Packet buffer underrun error interrupt" "No interrupt,Interrupt"
|
|
else
|
|
rbitfld.long 0x00 10. " TSM_IRQTSM ,TSM interrupt request" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 8. " WAKE_IRQ ,WAKE interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " RX_FRM_PEND ,RX frame pending" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " PLL_UNLOCK_IRQ ,PLL unlock interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " FILTERFAIL_IRQ ,Filter fail interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " RXWTRMRKIRQ ,Receive watermark interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " CCAIRQ ,Clear channel assessment interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " RXIRQ ,Receiver interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " TXIRQ ,Transmitter interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SEQIRQ ,Sequencer interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "PHY_CTRL,Phy Control"
|
|
bitfld.long 0x04 31. " TRCV_MSK ,Transceiver global interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " TC3TMOUT ,TMR3 timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " PANCORDNTR0 ,Device is a PAN coordinator on PAN0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 27.--28. " CCATYPE ,Clear channel assessment type" "ENERGY DETECT,CCA MODE 1,CCA MODE 2,CCA MODE 3"
|
|
textline " "
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW20Z*"))
|
|
bitfld.long 0x04 26. " TMRLOAD ,Event timer load enable" "No effect,Load"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 25. " PROMISCUOUS ,Promiscuous mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " TC2PRIME_EN ,Timer 2 prime compare enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " TMR4CMP_EN ,Timer 4 compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " TMR3CMP_EN ,Timer 3 compare enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " TMR2CMP_EN ,Timer 2 compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " TMR1CMP_EN ,Timer 1 compare enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW20Z*"))
|
|
bitfld.long 0x04 17. " PB_ERR_MSK ,Packet buffer error interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " CRC_MSK ,CRC mask" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " PLL_UNLOCK_MSK ,PLL unlock interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " FILTERFAIL_MSK ,FilterFail interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RX_WMRK_MSK ,RX watermark interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 11. " CCAMSK ,CCA interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " RXMSK ,RX interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " TXMSK ,TX interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " SEQMSK ,Sequencer interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " TMRTRIGEN ,Timer2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " SLOTTED ,Slotted mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CCABFRTX ,CCA before TX" "Not required,Required"
|
|
bitfld.long 0x04 4. " RXACKRQD ,Receive acknowledge frame required" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " AUTOACK ,Auto acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--2. " XCVSEQ ,802.15.4 transceiver sequence selector" "Idle,Receive,Transmit,CCA,Transmit/Receive,Continuous CCA,?..."
|
|
line.long 0x08 "EVENT_TMR,Event Timer"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW20Z*"))
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " EVENT_TMR ,Event timer"
|
|
else
|
|
hexmask.long.tbyte 0x08 8.--31. 1. " EVENT_TMR ,Event timer integer component"
|
|
bitfld.long 0x08 4.--7. " EVENT_TMR_FRAC ,Event timer fractional component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 1. " EVENT_TMR_ADD ,Event timer add" "No effect,Add"
|
|
textline " "
|
|
bitfld.long 0x08 0. " EVENT_TMR_LD ,Event timer load" "No effect,Load"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TIMESTAMP,Timestamp"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TIMESTAMP ,Timestamp"
|
|
group.long 0x10++0x1B
|
|
line.long 0x00 "T1CMP,T1 Compare"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " T1CMP ,TMR1 compare value"
|
|
line.long 0x04 "T2CMP,T2 Compare"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " T2CMP ,TMR2 compare value"
|
|
line.long 0x08 "T2PRIMECMP,T2 Prime Compare"
|
|
hexmask.long.word 0x08 0.--15. 1. " T2PRIMECMP ,TMR2 prime compare value"
|
|
line.long 0x0C "T3CMP,T3 Compare"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " T3CMP ,TMR3 compare value"
|
|
line.long 0x10 "T4CMP,T4 Compare"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " T4CMP ,TMR4 compare value"
|
|
line.long 0x14 "PA_PWR,Pa Power"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW20Z*"))
|
|
bitfld.long 0x14 0.--3. " PA_PWR ,PA power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x14 0.--5. " PA_PWR ,PA power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
line.long 0x18 "CHANNEL_NUM0,Channel Number 0"
|
|
hexmask.long.byte 0x18 0.--6. 1. " CHANNEL_NUM0 ,Mapped channel number used to transmit and receive 802.15.4 packets"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "LQI_AND_RSSI,LQI And RSSI"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CCA1_ED_FNL ,Final result for CCA mode 1 and energy detect"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RSSI ,RSSI value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LQI_VALUE ,LQI value"
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "MACSHORTADDRS0,Mac Short Address 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " MACSHORTADDRS0 ,MAC short address for PAN0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MACPANID0 ,MAC PAN ID for PAN0"
|
|
line.long 0x04 "MACLONGADDRS0_LSB,Mac Long Address 0 LSB"
|
|
line.long 0x08 "MACLONGADDRS0_MSB,Mac Long Address 0 MSB"
|
|
line.long 0x0C "RX_FRAME_FILTER,Receive Frame Filter"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW20Z*"))
|
|
bitfld.long 0x0C 6.--7. " FRM_VER ,Frame version selector" "Any,Version 0,Version 1,Version 0 & 1"
|
|
bitfld.long 0x0C 5. " ACTIVE_PROMISCUOUS ,Active promiscuous" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " NS_FT ,'Not specified' frame type enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CMD_FT ,MAC command frame type enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " ACK_FT ,ACK frame type enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DATA_FT ,Data frame type enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " BEACON_FT ,Beacon frame type enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x0C 23. " EXTENDED_RECD ,Extended packet received" "Not received,Received"
|
|
rbitfld.long 0x0C 21. " MULTIPURPOSE_RECD ,Multipurpose packet received" "Not received,Received"
|
|
rbitfld.long 0x0C 20. " LLDN_RECD ,LLDN packet received" "Not received,Received"
|
|
textline " "
|
|
rbitfld.long 0x0C 19. " FV2_CMD_RECD ,Frame version 2 MAC command packet received" "Not received,Received"
|
|
rbitfld.long 0x0C 18. " FV2_ACK_RECD ,Frame version 2 acknowledge packet received" "Not received,Received"
|
|
rbitfld.long 0x0C 17. " FV2_DATA_RECD ,Frame version 2 data packet received" "Not received,Received"
|
|
textline " "
|
|
rbitfld.long 0x0C 16. " FV2_BEACON_RECD ,Frame version 2 beacon packet received" "Not received,Received"
|
|
bitfld.long 0x0C 15. " EXTENDED_FCS_CHK ,Verify FCS on frame type extended" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " ACTIVE_PROMISCUOUS ,Active promiscuous" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " FRM_VER_FILTER[3] ,Frame version selector - version 3" "Not accepted,Accepted"
|
|
bitfld.long 0x0C 10. " [2] ,Frame version selector - version 2" "Not accepted,Accepted"
|
|
bitfld.long 0x0C 9. " [1] ,Frame version selector - version 1" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " [0] ,Frame version selector - version 0" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " EXTENDED_FT ,Extended frame type enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " NS_FT ,'Not specified' frame type enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " LLDN_FT ,LLDN frame type enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CMD_FT ,MAC command frame type enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " ACK_FT ,ACK frame type enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DATA_FT ,Data frame type enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " BEACON_FT ,Beacon frame type enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x10 "CCA_LQI_CTRL,CCA And LQI Control"
|
|
bitfld.long 0x10 27. " CCA3_AND_NOT_OR ,CCA mode 3 AND not OR" "OR,AND"
|
|
hexmask.long.byte 0x10 16.--23. 1. " LQI_OFFSET_COMP ,LQI offset compensation"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CCA1_THRESH ,CCA mode 1 threshold"
|
|
line.long 0x14 "CCA2_CTRL,CCA2 Control"
|
|
hexmask.long.byte 0x14 8.--15. 1. " CCA2_CORR_THRESH ,CCA mode 2 correlation threshold"
|
|
bitfld.long 0x14 4.--6. " CCA2_MIN_NUM_CORR_TH ,CCA mode 2 threshold number of correlation peaks" "1,2,3,4,5,6,7,8"
|
|
rbitfld.long 0x14 0.--3. " CCA2_NUM_CORR_PEAKS ,CCA mode 2 number of correlation peaks detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("MKW40Z*")||cpuis("MKW20Z*"))
|
|
if (((per.l(ad:0x4005D000+0x48))&0x04)==0x04)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FAD_CTRL,Fast Antenna Diversity Control"
|
|
bitfld.long 0x00 15. " ANTX_POL[3] ,Antenna diversity PAD polarity - RX_SWITCH output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " [2] ,Antenna diversity PAD polarity - TX_SWITCH output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " [1] ,Antenna diversity PAD polarity - ANT_B output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [0] ,Antenna diversity PAD polarity - ANT_A output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ANTX_CTRLMODE ,Antenna diversity control mode" "Single mode,Dual mode"
|
|
bitfld.long 0x00 10. " ANTX_HZ ,FAD PAD tristate control" "Not Hi-Z,Hi-Z"
|
|
bitfld.long 0x00 8.--9. " ANTX_EN ,FAD antenna controls enable" "Disabled,RX/TX_SWITCH,ANT_A/B,All enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FAD_NOT_GPIO ,FAD/GPIO selector" "GPIO,FAD"
|
|
bitfld.long 0x00 1. " ANTX ,Antenna selection" "0,1"
|
|
bitfld.long 0x00 0. " FAD_EN ,Enable fast antenna diversity for Zigbee" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FAD_CTRL,Fast Antenna Diversity Control"
|
|
bitfld.long 0x00 15. " ANTX_POL[3] ,Antenna diversity PAD polarity - RX_SWITCH output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " [2] ,Antenna diversity PAD polarity - TX_SWITCH output" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " [1] ,Antenna diversity PAD polarity - ANT_B output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [0] ,Antenna diversity PAD polarity - ANT_A output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ANTX_CTRLMODE ,Antenna diversity control mode" "Single mode,Dual mode"
|
|
bitfld.long 0x00 10. " ANTX_HZ ,FAD PAD tristate control" "Not Hi-Z,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FAD_NOT_GPIO ,FAD/GPIO selector" "GPIO,FAD"
|
|
bitfld.long 0x00 1. " ANTX ,Antenna selection" "0,1"
|
|
bitfld.long 0x00 0. " FAD_EN ,Enable fast antenna diversity for Zigbee" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SNF_CTRL,SNIFF Mode Control"
|
|
bitfld.long 0x00 0. " SNF_EN ,SNF enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DSM_CTRL,Deep Sleep Mode Control"
|
|
bitfld.long 0x00 0. " ZIGBEE_SLEEP_EN ,802.15.4 sleep enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "BSM_CTRL,Bit Streaming Mode Control"
|
|
bitfld.long 0x00 0. " BSM_EN ,Bit streaming mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "MACSHORTADDRS1,Mac Short Address For Pan1"
|
|
hexmask.long.word 0x04 16.--31. 1. " MACSHORTADDRS1 ,MAC short address for PAN1"
|
|
hexmask.long.word 0x04 0.--15. 1. " MACPANID1 ,MAC PAN ID for PAN1"
|
|
line.long 0x08 "MACLONGADDRS1_LSB,Mac Long Address For PAN1 LSB"
|
|
line.long 0x0C "MACLONGADDRS1_MSB,Mac Long Address For PAN1 MSB"
|
|
if (((per.l(ad:0x4005D000+0x60))&0x02)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DUAL_PAN_CTRL,Dual Pan Control"
|
|
rbitfld.long 0x00 23. " RECD_ON_PAN1 ,Last packet was received on PAN1" "No,Yes"
|
|
rbitfld.long 0x00 22. " RECD_ON_PAN0 ,Last packet was received on PAN0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ZB_DP_CHAN_OVRD_SEL ,Dual PAN channel override selector" "PAN0,PAN1"
|
|
bitfld.long 0x00 4. " ZB_DP_CHAN_OVRD_EN ,Dual PAN channel override enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " CURRENT_NETWORK ,Indicates which PAN is currently selected by hardware" "PAN0,PAN1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PANCORDNTR1 ,Device is a PAN coordinator on PAN1" "No,Yes"
|
|
bitfld.long 0x00 1. " DUAL_PAN_AUTO ,Activates automatic dual PAN operating mode" "Manual,Automatic"
|
|
bitfld.long 0x00 0. " ACTIVE_NETWORK ,Active network selector" "PAN0,PAN1"
|
|
elif (((per.l(ad:0x4005D000+0x60))&0x302)==0x002)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DUAL_PAN_CTRL,Dual Pan Control"
|
|
rbitfld.long 0x00 23. " RECD_ON_PAN1 ,Last packet was received on PAN1" "No,Yes"
|
|
rbitfld.long 0x00 22. " RECD_ON_PAN0 ,Last packet was received on PAN0" "No,Yes"
|
|
rbitfld.long 0x00 16.--21. " DUAL_PAN_REMAIN ,Time remaining before next PAN switch in auto dual PAN mode" "0 ms,0.5 ms,1 ms,1.5 ms,2 ms,2.5 ms,3 ms,3.5 ms,4 ms,4.5 ms,5 ms,5.5 ms,6 ms,6.5 ms,7 ms,7.5 ms,8 ms,8.5 ms,9 ms,9.5 ms,10 ms,10.5 ms,11 ms,11.5 ms,12 ms,12.5 ms,13 ms,13.5 ms,14 ms,14.5 ms,15 ms,15.5 ms,16 ms,16.5 ms,17 ms,17.5 ms,18 ms,18.5 ms,19 ms,19.5 ms,20 ms,20.5 ms,21 ms,21.5 ms,22 ms,22.5 ms,23 ms,23.5 ms,24 ms,24.5 ms,25 ms,25.5 ms,26 ms,26.5 ms,27 ms,27.5 ms,28 ms,28.5 ms,29 ms,29.5 ms,30 ms,30.5 ms,31 ms,31.5 ms"
|
|
textline " "
|
|
bitfld.long 0x00 10.--15. " DUAL_PAN_DWELL[7:2] ,Dual PAN channel frequency dwell time - timebase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--9. " DUAL_PAN_DWELL[1:0] ,Dual PAN channel frequency dwell time - prescaler" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ZB_DP_CHAN_OVRD_SEL ,Dual PAN channel override selector" "PAN0,PAN1"
|
|
bitfld.long 0x00 4. " ZB_DP_CHAN_OVRD_EN ,Dual PAN channel override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CURRENT_NETWORK ,Indicates which PAN is currently selected by hardware" "PAN0,PAN1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PANCORDNTR1 ,Device is a PAN coordinator on PAN1" "No,Yes"
|
|
bitfld.long 0x00 1. " DUAL_PAN_AUTO ,Activates automatic Dual PAN operating mode" "Manual,Automatic"
|
|
bitfld.long 0x00 0. " ACTIVE_NETWORK ,Active network selector" "PAN0,PAN1"
|
|
elif (((per.l(ad:0x4005D000+0x60))&0x300)==0x100)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DUAL_PAN_CTRL,Dual Pan Control"
|
|
rbitfld.long 0x00 23. " RECD_ON_PAN1 ,Last packet was received on PAN1" "No,Yes"
|
|
rbitfld.long 0x00 22. " RECD_ON_PAN0 ,Last packet was received on PAN0" "No,Yes"
|
|
rbitfld.long 0x00 16.--21. " DUAL_PAN_REMAIN ,Time remaining before next PAN switch in auto dual PAN mode" "0 ms,2.5 ms,5 ms,7.5 ms,10 ms,12.5 ms,15 ms,17.5 ms,20 ms,22.5 ms,25 ms,27.5 ms,30 ms,32.5 ms,35 ms,37.5 ms,40 ms,42.5 ms,45 ms,47.5 ms,50 ms,52.5 ms,55 ms,57.5 ms,60 ms,62.5 ms,65 ms,67.5 ms,70 ms,72.5 ms,75 ms,77.5 ms,80 ms,82.5 ms,85 ms,87.5 ms,90 ms,92.5 ms,95 ms,97.5 ms,100 ms,102.5 ms,105 ms,107.5 ms,110 ms,112.5 ms,115 ms,117.5 ms,120 ms,122.5 ms,125 ms,127.5 ms,130 ms,132.5 ms,135 ms,137.5 ms,140 ms,142.5 ms,145 ms,147.5 ms,150 ms,152.5 ms,155 ms,157.5 ms"
|
|
textline " "
|
|
bitfld.long 0x00 10.--15. " DUAL_PAN_DWELL[7:2] ,Dual PAN channel frequency dwell time - timebase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--9. " DUAL_PAN_DWELL[1:0] ,Dual PAN channel frequency dwell time - prescaler" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ZB_DP_CHAN_OVRD_SEL ,Dual PAN channel override selector" "PAN0,PAN1"
|
|
bitfld.long 0x00 4. " ZB_DP_CHAN_OVRD_EN ,Dual PAN channel override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CURRENT_NETWORK ,Indicates which PAN is currently selected by hardware" "PAN0,PAN1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PANCORDNTR1 ,Device is a PAN coordinator on PAN1" "No,Yes"
|
|
bitfld.long 0x00 1. " DUAL_PAN_AUTO ,Activates automatic dual PAN operating mode" "Manual,Automatic"
|
|
bitfld.long 0x00 0. " ACTIVE_NETWORK ,Active network selector" "PAN0,PAN1"
|
|
elif (((per.l(ad:0x4005D000+0x60))&0x300)==0x200)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DUAL_PAN_CTRL,Dual Pan Control"
|
|
rbitfld.long 0x00 23. " RECD_ON_PAN1 ,Last packet was received on PAN1" "No,Yes"
|
|
rbitfld.long 0x00 22. " RECD_ON_PAN0 ,Last packet was received on PAN0" "No,Yes"
|
|
rbitfld.long 0x00 16.--21. " DUAL_PAN_REMAIN ,Time remaining before next PAN switch in auto dual PAN mode" "0 ms,10 ms,20 ms,30 ms,40 ms,50 ms,60 ms,70 ms,80 ms,90 ms,100 ms,110 ms,120 ms,130 ms,140 ms,150 ms,160 ms,170 ms,180 ms,190 ms,200 ms,210 ms,220 ms,230 ms,240 ms,250 ms,260 ms,270 ms,280 ms,290 ms,300 ms,310 ms,320 ms,330 ms,340 ms,350 ms,360 ms,370 ms,380 ms,390 ms,400 ms,410 ms,420 ms,430 ms,440 ms,450 ms,460 ms,470 ms,480 ms,490 ms,500 ms,510 ms,520 ms,530 ms,540 ms,550 ms,560 ms,570 ms,580 ms,590 ms,600 ms,610 ms,620 ms,630 ms"
|
|
textline " "
|
|
bitfld.long 0x00 10.--15. " DUAL_PAN_DWELL[7:2] ,Dual PAN channel frequency dwell time - timebase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--9. " DUAL_PAN_DWELL[1:0] ,Dual PAN channel frequency dwell time - prescaler" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ZB_DP_CHAN_OVRD_SEL ,Dual PAN channel override selector" "PAN0,PAN1"
|
|
bitfld.long 0x00 4. " ZB_DP_CHAN_OVRD_EN ,Dual PAN channel override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CURRENT_NETWORK ,Indicates which PAN is currently selected by hardware" "PAN0,PAN1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PANCORDNTR1 ,Device is a PAN coordinator on PAN1" "No,Yes"
|
|
bitfld.long 0x00 1. " DUAL_PAN_AUTO ,Activates automatic dual PAN operating mode" "Manual,Automatic"
|
|
bitfld.long 0x00 0. " ACTIVE_NETWORK ,Active network selector" "PAN0,PAN1"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DUAL_PAN_CTRL,Dual Pan Control"
|
|
rbitfld.long 0x00 23. " RECD_ON_PAN1 ,Last packet was received on PAN1" "No,Yes"
|
|
rbitfld.long 0x00 22. " RECD_ON_PAN0 ,Last packet was received on PAN0" "No,Yes"
|
|
rbitfld.long 0x00 16.--21. " DUAL_PAN_REMAIN ,Time remaining before next PAN switch in auto dual PAN mode" "0 ms,50 ms,100 ms,150 ms,200 ms,250 ms,300 ms,350 ms,400 ms,450 ms,500 ms,550 ms,600 ms,650 ms,700 ms,750 ms,800 ms,850 ms,900 ms,950 ms,1000 ms,1050 ms,1100 ms,1150 ms,1200 ms,1250 ms,1300 ms,1350 ms,1400 ms,1450 ms,1500 ms,1550 ms,1600 ms,1650 ms,1700 ms,1750 ms,1800 ms,1850 ms,1900 ms,1950 ms,2000 ms,2050 ms,2100 ms,2150 ms,2200 ms,2250 ms,2300 ms,2350 ms,2400 ms,2450 ms,2500 ms,2550 ms,2600 ms,2650 ms,2700 ms,2750 ms,2800 ms,2850 ms,2900 ms,2950 ms,3000 ms,3050 ms,3100 ms,3150 ms"
|
|
textline " "
|
|
bitfld.long 0x00 10.--15. " DUAL_PAN_DWELL[7:2] ,Dual PAN channel frequency dwell time - timebase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--9. " DUAL_PAN_DWELL[1:0] ,Dual PAN channel frequency dwell time - prescaler" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ZB_DP_CHAN_OVRD_SEL ,Dual PAN channel override selector" "PAN0,PAN1"
|
|
bitfld.long 0x00 4. " ZB_DP_CHAN_OVRD_EN ,Dual PAN channel override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CURRENT_NETWORK ,Indicates which PAN is currently selected by hardware" "PAN0,PAN1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PANCORDNTR1 ,Device is a PAN coordinator on PAN1" "No,Yes"
|
|
bitfld.long 0x00 1. " DUAL_PAN_AUTO ,Activates automatic dual PAN operating mode" "Manual,Automatic"
|
|
bitfld.long 0x00 0. " ACTIVE_NETWORK ,Active network selector" "PAN0,PAN1"
|
|
endif
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "CHANNEL_NUM1,Channel Number 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANNEL_NUM1 ,Channel number for PAN1"
|
|
line.long 0x04 "SAM_CTRL,Sam Control"
|
|
hexmask.long.byte 0x04 24.--31. 1. " SAA1_START ,First index of SAA1 partition"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SAP1_START ,First index of SAP1 partition"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SAA0_START ,First index of SAA0 partition"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SAA1_EN ,Enables SAA1 partition of the SAM table" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SAP1_EN ,Enables SAP1 partition of the SAM table" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SAA0_EN ,Enables SAA0 partition of the SAM table" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SAP0_EN ,Enables SAP0 partition of the SAM table" "Disabled,Enabled"
|
|
if ((((per.l(ad:0x4005D000+0x6C))&0x8000000)==0x8000000)||(((per.l(ad:0x4005D000+0x68))&0x0F)==0x00))
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SAM_TABLE,Source Address Management Table"
|
|
rbitfld.long 0x00 31. " SAM_BUSY ,SAM table update status bit" "Not updating,Updating"
|
|
bitfld.long 0x00 29. " INVALIDATE_ALL ,Invalidate entire SAM table" "No effect,Invalidate"
|
|
bitfld.long 0x00 28. " FIND_FREE_IDX ,Find first free index" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ACK_FRM_PND_CTRL ,Manual control for AutoTxAck FramePending field" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ACK_FRM_PND ,State of AutoTxAck FramePending field when SAM accelleration is disabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SAM_INDEX_EN ,Enable the SAM table index selected by SAM_INDEX" "No effect,Enable"
|
|
bitfld.long 0x00 24. " SAM_INDEX_INV ,Invalidate the SAM table index selected by SAM_INDEX" "No effect,Invalidate"
|
|
hexmask.long.word 0x00 8.--23. 1. " SAM_CHECKSUM ,Software-computed source address checksum"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SAM_INDEX_WR ,Enables SAM table contents to be updated" "No effect,Enable"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SAM_INDEX ,SAM table index"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SAM_TABLE,Source Address Management Table"
|
|
rbitfld.long 0x00 31. " SAM_BUSY ,SAM table update status bit" "Not updating,Updating"
|
|
bitfld.long 0x00 29. " INVALIDATE_ALL ,Invalidate entire SAM table" "No effect,Invalidate"
|
|
bitfld.long 0x00 28. " FIND_FREE_IDX ,Find first free index" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ACK_FRM_PND_CTRL ,Manual control for AutoTxAck FramePending field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SAM_INDEX_EN ,Enable the SAM table index selected by SAM_INDEX" "No effect,Enable"
|
|
bitfld.long 0x00 24. " SAM_INDEX_INV ,Invalidate the SAM table index selected by SAM_INDEX" "No effect,Invalidate"
|
|
hexmask.long.word 0x00 8.--23. 1. " SAM_CHECKSUM ,Software-computed source address checksum"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SAM_INDEX_WR ,Enables SAM table contents to be updated" "No effect,Enable"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SAM_INDEX ,SAM table index"
|
|
endif
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "SAM_MATCH,Source Address Management Match"
|
|
bitfld.long 0x00 31. " SAA1_ADDR_ABSENT ,A checksum match is absent in the SAP1 partition of the SAM table" "No,Yes"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SAA1_MATCH ,Index in the SAA1 partition of the SAM Table corresponding to the first checksum match"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SAP1_ADDR_PRESENT ,A checksum match is present in the SAP1 partition of the SAM table" "No,Yes"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SAP1_MATCH ,Index in the SAP1 partition of the SAM table corresponding to the first checksum match"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SAA0_ADDR_ABSENT ,A checksum match is absent in the SAA0 partition of the SAM table" "No,Yes"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SAA0_MATCH ,Index in the SAA0 partition of the SAM table corresponding to the first checksum match"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SAP0_ADDR_PRESENT ,A checksum match is present in the SAP0 partition of the SAM table" "No,Yes"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SAP0_MATCH ,Index in the SAP0 partition of the SAM table corresponding to the first checksum match"
|
|
line.long 0x04 "SAM_FREE_IDX,Sam Free Index"
|
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hexmask.long.byte 0x04 24.--31. 1. " SAA1_1ST_FREE_IDX ,First non-enabled (invalid) index in the SAA1 partition"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SAP1_1ST_FREE_IDX ,First non-enabled (invalid) index in the SAP1 partition"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " SAA0_1ST_FREE_IDX ,First non-enabled (invalid) index in the SAA0 partition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SAP0_1ST_FREE_IDX ,First non-enabled (invalid) index in the SAP0 partition"
|
|
group.long 0x78++0x0F
|
|
line.long 0x00 "SEQ_CTRL_STS,Sequence Control And Status"
|
|
rbitfld.long 0x00 26. " PLL_ABORTED ,Autosequence has terminated due to an PLL unlock event" "No,Yes"
|
|
rbitfld.long 0x00 25. " TC3_ABORTED ,Autosequence has terminated due to an TMR3 timeout" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW21Z*"))
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|
rbitfld.long 0x00 24. " SW_ABORTED ,Autosequence has terminated due to a software abort" "No,Yes"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 21. " SEQ_T_STATUS[5] ,Status of the just-completed or ongoing sequence T or sequence TR - TxAck operation complete" "No,Yes"
|
|
rbitfld.long 0x00 20. " [4] ,Status of the just-completed or ongoing sequence T or sequence TR - Rx operation complete" "No,Yes"
|
|
rbitfld.long 0x00 19. " [3] ,Status of the just-completed or ongoing sequence T or sequence TR - Rx recycle occurred" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 18. " [2] ,Status of the just-completed or ongoing sequence T or sequence TR - Tx operation complete" "No,Yes"
|
|
rbitfld.long 0x00 17. " [1] ,Status of the just-completed or ongoing sequence T or sequence TR - 2nd CCA complete" "No,Yes"
|
|
rbitfld.long 0x00 16. " [0] ,Status of the just-completed or ongoing sequence T or sequence TR - 1st CCA complete" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " TMR2_SEQ_TRIG_ARMED ,TMR2 has been programmed and is armed to trigger a new autosequence" "No,Yes"
|
|
rbitfld.long 0x00 14. " RX_MODE ,RX operation in progress" "No,Yes"
|
|
rbitfld.long 0x00 13. " RX_TIMEOUT_PENDING ,TMR3 RX timeout is pending" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " NEW_SEQ_INHIBIT ,New sequence inhibit" "No,Yes"
|
|
rbitfld.long 0x00 11. " SEQ_IDLE ,SM sequence idle indicator" "No,Yes"
|
|
rbitfld.long 0x00 8.--10. " XCVSEQ_ACTUAL ,Indicates the programmed sequence that has been recognized by the ZSM sequence manager" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CONTINUOUS_EN ,Enable continuous TX or RX mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FORCE_CRC_ERROR ,Induce a CRC error in transmitted packets" "No,Yes"
|
|
bitfld.long 0x00 5. " NO_RX_RECYCLE ,Disable automatic RX sequence recycling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATCH_PREAMBLE ,Stickiness control for preamble detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EVENT_TMR_DO_NOT_LATCH ,Overrides the automatic hardware latching of the event timer" "Not overridden,Overridden"
|
|
bitfld.long 0x00 2. " CLR_NEW_SEQ_INHIBIT ,Overrides the automatic hardware locking of the programmed XCVSEQ" "Not overridden,Overridden"
|
|
line.long 0x04 "ACKDELAY,ACK Delay"
|
|
bitfld.long 0x04 8.--13. " TXDELAY ,TX delay" "0us,2us,4us,6us,8us,10us,12us,14us,16us,18us,20us,22us,24us,26us,28us,30us,32us,34us,36us,38us,40us,42us,44us,46us,48us,50us,52us,54us,56us,58us,60us,62us,,,,,,,,,,,,,,-38us,-36us,-34us,-32us,-30us,-28us,-26us,-24us,-22us,-20us,-18us,-16us,-14us,-12us,-10us,-8us,-6us,-4us,-2us"
|
|
bitfld.long 0x04 0.--5. " ACKDELAY ,ACK delay" "0us,2us,4us,6us,8us,10us,12us,14us,16us,18us,20us,22us,24us,26us,28us,30us,32us,34us,36us,38us,40us,42us,44us,46us,48us,50us,52us,54us,56us,58us,60us,62us,,,,,,,,,,,,,,-38us,-36us,-34us,-32us,-30us,-28us,-26us,-24us,-22us,-20us,-18us,-16us,-14us,-12us,-10us,-8us,-6us,-4us,-2us"
|
|
line.long 0x08 "FILTERFAIL_CODE,Filter Fail Code"
|
|
bitfld.long 0x08 15. " FILTERFAIL_PAN_SEL ,PAN selector for filter fail code" "PAN0,PAN1"
|
|
hexmask.long.word 0x08 0.--9. 1. " FILTERFAIL_CODE ,Filter fail code"
|
|
line.long 0x0C "RX_WTR_MARK,Receive Water Mark"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RX_WTR_MARK ,Receive water mark"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SLOT_PRELOAD,Slot Preload"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_PRELOAD ,Slotted mode preload"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "SEQ_STATE,802.15.4 Sequence State"
|
|
bitfld.long 0x00 24.--29. " CCCA_BUSY_CNT ,Number of CCA measurements resulting in busy channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_BYTE_COUNT ,Realtime received byte count"
|
|
bitfld.long 0x00 13. " PLL_ABORTED ,Autosequence has terminated due to an PLL unlock event" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PLL_ABORT ,Raw PLL abort signal" "None unlocked,Unlocked"
|
|
bitfld.long 0x00 11. " CRCVALID ,CRC valid indicator" "Invalid,Valid"
|
|
bitfld.long 0x00 10. " FILTERFAIL_FLAG_SEL ,Consolidated filter fail flag" "Not failed,Failed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SFD_DET ,SFD detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " PREAMBLE_DET ,Preamble detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0.--4. " SEQ_STATE ,ZSM sequence state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x94++0x0B
|
|
line.long 0x00 "TMR_PRESCALE,Timer Prescaler"
|
|
bitfld.long 0x00 0.--2. " TMR_PRESCALE ,Timer prescaler" ",,500kHz,250kHz,125kHz,62.5kHz,31.25kHz,15.625kHz"
|
|
line.long 0x04 "LENIENCY_LSB,Leniency LSB"
|
|
line.long 0x08 "LENIENCY_MSB,Leniency MSB"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LENIENCY_MSB ,Leniency MSB register"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "PART_ID,Part ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_ID ,802.15.4 part ID"
|
|
sif (cpuis("MKW41Z*")||cpuis("MKW21Z*"))
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "PKT_BUFFER_TX,Packet Buffer TX"
|
|
textfld " "
|
|
button "Data" "d ad:ad:0x4005D000+0x100--ad:ad:0x4005D000+0x7F /word"
|
|
group.word 0x180++0x01
|
|
line.word 0x00 "PKT_BUFFER_RX,Packet Buffer RX"
|
|
textfld " "
|
|
button "Data" "d ad:ad:0x4005D000+0x180--ad:ad:0x4005D000+0x1FF /word"
|
|
else
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "PKT_BUFFER_TX,Packet Buffer TX"
|
|
textfld " "
|
|
button "Data" "d ad:ad:0x4005D000+0x100--ad:ad:0x4005D000+0x3F /word"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
endif
|
|
textline ""
|