11654 lines
1.0 MiB
11654 lines
1.0 MiB
; --------------------------------------------------------------------------------
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; @Title: K32W041A On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-02-09 JDU
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; 2023-11-09 NEJ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: Generated (TRACE32, build: 164352.), based on:
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; K32W041A.svd (Ver. 1.0)
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; @Core: Cortex-M4F
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; @Chip: K32W041A
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perk32w041a.per 16973 2023-11-09 17:44:24Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (12-bit Analog to Digital Converter)"
|
|
base ad:0x40089000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,ADC Control register. Contains the clock divide value. resolution selection. sampling time selection. and mode controls."
|
|
bitfld.long 0x0 12.--14. "TSAMP,Sample Time. The default sampling period (TSAMP = 000 ) at the start of each conversion is 2.5 ADC clock periods. Depending on a variety of factors including operating conditions and the output impedance of the analog source longer sampling times.." "0: The sample period will be the default 2,1: The sample period will be extended by one ADC..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 11. "RESOL_MASK_DIS,According RESOL bit LSB bits are automatickly masked if RESOL_MASK_DIS = 0. If RESOL_MASK_DIS = 1 the 12bits comming from ADC are directly connect to register RESULT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "RESOL,The number of bits of ADC resolution. Note whatever the resolution setting the ADC data will always be shifted to use the MSBs of any ADC data words. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one.." "0,1,2,3"
|
|
bitfld.long 0x0 8. "ASYNMODE,Select clock mode. 0: Synchronous mode. Not Supported. 1: Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block." "0: Synchronous mode,1: Asynchronous mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "CLKDIV,Reserved. No changes to this fiedl are necessary."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "SEQ_CTRLA,ADC Conversion Sequence-A control register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A."
|
|
bitfld.long 0x0 31. "SEQ_ENA,Sequence Enable. In order to avoid spuriously triggering the sequence care should be taken to only set the SEQA_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met the.." "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "MODE,Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion or the individual channel result registers at the end of.." "0: End of conversion,1: End of sequence"
|
|
newline
|
|
bitfld.long 0x0 28. "SINGLESTEP,When this bit is set a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels.." "0,1"
|
|
bitfld.long 0x0 27. "BURST,Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "START,Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. Remark: This bit is only set to a 1.." "0,1"
|
|
bitfld.long 0x0 25. "START_BEHAVIOUR,the Start behavior used on gpadc: writing 0 for repeat start after each input selection changed used for seqA with multiple inputs. writing 1 for continuous start this bit is only if seqA is used to have full speed on a single input." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SYNCBYPASS,Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or.." "0: Enable trigger synchronization,1: Bypass trigger synchronization"
|
|
bitfld.long 0x0 18. "TRIGPOL,Select the polarity of the selected input trigger for this conversion sequence. Remark: In order to avoid generating a spurious trigger it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field.." "0: A negative edge launches the conversion sequence..,1: A positive edge launches the conversion sequence.."
|
|
newline
|
|
hexmask.long.byte 0x0 12.--17. 1. "TRIGGER,Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. Setting: 0 : PINT0; 1 : PWM8; 2 : PWM9; 3 : ARM TX EV. Remark: In order to avoid.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHANNELS,Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence where bit 0 corresponds to.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SEQ_GDATA,ADC Sequence-A Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-A."
|
|
bitfld.long 0x0 31. "DATAVALID,This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE.." "0,1"
|
|
bitfld.long 0x0 30. "OVERRUN,This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared along with the DATAVALID bit whenever this register is read. This bit.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 26.--29. 1. "CHN,These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0 0001 channel 1 etc.)."
|
|
bitfld.long 0x0 18.--19. "THCMPCROSS,Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold.." "0: No threshold Crossing detected: The most recent..,1: Reserved,2: Downward Threshold Crossing Detected,3: Upward Threshold Crossing Detected"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "THCMPRANGE,Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the.." "0: In Range: The last completed conversion was..,1: Below Range: The last completed conversion on..,2: Above Range: The last completed conversion was..,3: Reserved"
|
|
hexmask.long.word 0x0 4.--15. 1. "RESULT,This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. DATAVALID = 1 indicates that this result has not yet been read. If less than 12-bit resolultion.."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "DAT[$1],ADC Channel X [0:7] Data register. This register contains the result of the most recent conversion completed on channel X [0:7] ."
|
|
bitfld.long 0x0 31. "DATAVALID,This bit is set to 1 at the end of each conversion for this channel when a new result is loaded into the RESULT field. It is cleared whenever this register is read or when the data related to this channel is read from the global SEQA_GDAT.." "0,1"
|
|
bitfld.long 0x0 30. "OVERRUN,This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared along with the DATAVALID bit whenever this register is read or when the.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 26.--29. 1. "CHANNEL,This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register 0b0001 for the DAT1 register etc)"
|
|
bitfld.long 0x0 18.--19. "THCMPCROSS,Threshold Crossing Comparison result for this channel. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated.." "0: No threshold Crossing detected: The most recent..,1: Reserved,2: Downward Threshold Crossing Detected,3: Upward Threshold Crossing Detected"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "THCMPRANGE,Threshold Range Comparison result for this channel. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value.." "0: In Range: The last completed conversion was..,1: Below Range: The last completed conversion on..,2: Above Range: The last completed conversion was..,3: Reserved"
|
|
hexmask.long.word 0x0 4.--15. 1. "RESULT,This field contains the 12-bit ADC conversion result from the most recent conversion performed for this channel under conversion sequence associated with this register. DATAVALID = 1 indicates that this result has not yet been read. If less than.."
|
|
repeat.end
|
|
group.long 0x50++0x27
|
|
line.long 0x0 "THR0_LOW,ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0."
|
|
hexmask.long.word 0x0 4.--15. 1. "THRLOW,Low threshold value against which ADC results will be compared"
|
|
line.long 0x4 "THR1_LOW,ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1."
|
|
hexmask.long.word 0x4 4.--15. 1. "THRLOW,Low threshold value against which ADC results will be compared"
|
|
line.long 0x8 "THR0_HIGH,ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0."
|
|
hexmask.long.word 0x8 4.--15. 1. "THRHIGH,High threshold value against which ADC results will be compared"
|
|
line.long 0xC "THR1_HIGH,ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1."
|
|
hexmask.long.word 0xC 4.--15. 1. "THRHIGH,High threshold value against which ADC results will be compared"
|
|
line.long 0x10 "CHAN_THRSEL,ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel"
|
|
bitfld.long 0x10 7. "CH7_THRSEL,Threshold select for channel 7. See description for channel 0." "0,1"
|
|
bitfld.long 0x10 6. "CH6_THRSEL,Threshold select for channel 6. See description for channel 0." "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "CH5_THRSEL,Threshold select for channel 5. See description for channel 0." "0,1"
|
|
bitfld.long 0x10 4. "CH4_THRSEL,Threshold select for channel 4. See description for channel 0." "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH3_THRSEL,Threshold select for channel 3. See description for channel 0." "0,1"
|
|
bitfld.long 0x10 2. "CH2_THRSEL,Threshold select for channel 2. See description for channel 0." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CH1_THRSEL,Threshold select for channel 1. See description for channel 0." "0,1"
|
|
bitfld.long 0x10 0. "CH0_THRSEL,Threshold select for channel 0. 0: Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. 1: Threshold 1. Results for this channel will be compared against the.." "0: Threshold 0,1: Threshold 1"
|
|
line.long 0x14 "INTEN,ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A. sequence-B. threshold compare and data overrun interrupts to be generated."
|
|
bitfld.long 0x14 17.--18. "ADCMPINTEN7,Channel 7 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
|
|
bitfld.long 0x14 15.--16. "ADCMPINTEN6,Channel 6 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 13.--14. "ADCMPINTEN5,Channel 5 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
|
|
bitfld.long 0x14 11.--12. "ADCMPINTEN4,Channel 4 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 9.--10. "ADCMPINTEN3,Channel 3 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
|
|
bitfld.long 0x14 7.--8. "ADCMPINTEN2,Channel 2 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 5.--6. "ADCMPINTEN1,Channel 1 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
|
|
bitfld.long 0x14 3.--4. "ADCMPINTEN0,Threshold comparison interrupt enable for channel 0. 0x0: Disabled. 0x1: Outside threshold. 0x2: Crossing threshold. 0x3: Reserved" "0: Disabled,1: Outside threshold,2: Crossing threshold,3: Reserved"
|
|
newline
|
|
bitfld.long 0x14 2. "OVR_INTEN,Overrun interrupt enable. 0: Disabled. The overrun interrupt is disabled. 1: Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In.." "0: Disabled,1: Enabled"
|
|
bitfld.long 0x14 0. "SEQA_INTEN,Sequence A interrupt enable. 0: Disabled. The sequence A interrupt/DMA trigger is disabled. 1: Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part.." "0: Disabled,1: Enabled"
|
|
line.long 0x18 "FLAGS,ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)."
|
|
rbitfld.long 0x18 31. "OVR_INT,Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register.." "0,1"
|
|
rbitfld.long 0x18 30. "THCMP_INT,Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison.." "0,1"
|
|
newline
|
|
bitfld.long 0x18 28. "SEQA_INT,Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0 this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT) which is set at the end of every ADC conversion performed as part of.." "0,1"
|
|
rbitfld.long 0x18 24. "SEQA_OVR,Mirrors the global OVERRUN status flag in the SEQA_GDAT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 19. "OVERRUN7,Mirrors the OVERRRUN status flag from the result register for ADC channel 7" "0,1"
|
|
rbitfld.long 0x18 18. "OVERRUN6,Mirrors the OVERRRUN status flag from the result register for ADC channel 6" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 17. "OVERRUN5,Mirrors the OVERRRUN status flag from the result register for ADC channel 5" "0,1"
|
|
rbitfld.long 0x18 16. "OVERRUN4,Mirrors the OVERRRUN status flag from the result register for ADC channel 4" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 15. "OVERRUN3,Mirrors the OVERRRUN status flag from the result register for ADC channel 3" "0,1"
|
|
rbitfld.long 0x18 14. "OVERRUN2,Mirrors the OVERRRUN status flag from the result register for ADC channel 2" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 13. "OVERRUN1,Mirrors the OVERRRUN status flag from the result register for ADC channel 1" "0,1"
|
|
rbitfld.long 0x18 12. "OVERRUN0,Mirrors the OVERRRUN status flag from the result register for ADC channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "THCMP7,Threshold comparison event on Channel 7. See description for channel 0." "0,1"
|
|
bitfld.long 0x18 6. "THCMP6,Threshold comparison event on Channel 6. See description for channel 0." "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "THCMP5,Threshold comparison event on Channel 5. See description for channel 0." "0,1"
|
|
bitfld.long 0x18 4. "THCMP4,Threshold comparison event on Channel 4. See description for channel 0." "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "THCMP3,Threshold comparison event on Channel 3. See description for channel 0." "0,1"
|
|
bitfld.long 0x18 2. "THCMP2,Threshold comparison event on Channel 2. See description for channel 0." "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "THCMP1,Threshold comparison event on Channel 1. See description for channel 0." "0,1"
|
|
bitfld.long 0x18 0. "THCMP0,Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." "0,1"
|
|
line.long 0x1C "STARTUP,ADC Startup register (typically only used by the ADC API)."
|
|
bitfld.long 0x1C 0. "ADC_ENA,ADC Enable bit. This bit can only be set to a 1 by software. It is cleared automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds after the ADC is powered up (typically by altering a system-level.." "0,1"
|
|
line.long 0x20 "GPADC_CTRL0,Second ADC Control register : ADC internal LDO (within ADC sub-system)"
|
|
bitfld.long 0x20 14.--15. "TEST,Mode selection: '00': Normal functional mode (DIV4 mode). Input range is 0 to 3.6V although max input voltage is affected by supply voltage of the device. '01': Multiplexer test mode '10': ADC in unity gain mode. (DIV1 mode). Input range is 0 to.." "0,1,2,3"
|
|
hexmask.long.byte 0x20 9.--13. 1. "GPADC_TSAMP,Extand ADC sampling time according to source impedance 1: 0.621 kOhm 20 (default): 55 kOhm 31: 87 kOhm"
|
|
newline
|
|
bitfld.long 0x20 8. "PASS_ENABLE,Enable pass mode when set to high. This is for the LDO within the ADC itself. There is also LDOADC controlled from PMC that is outside the ADC block." "0,1"
|
|
hexmask.long.byte 0x20 3.--7. 1. "LDO_SEL_OUT,Select LDO output voltage (10mV step) [between 0.64V and 0.95V]. This is for the LDO within the ADC itself. There is also LDOADC controlled from PMC that is outside the ADC block."
|
|
newline
|
|
bitfld.long 0x20 0. "LDO_POWER_EN,LDO Power enable signal (active high). This is for the LDO within the ADC itself. There is also LDOADC controlled from PMC that is outside the ADC block. The LDOADC should have been enabled for 10usec before enabling this LDO. After enabling.." "0,1"
|
|
line.long 0x24 "GPADC_CTRL1,Third ADC Control register : ADC internal gain and offset"
|
|
hexmask.long.word 0x24 10.--19. 1. "GAIN_CAL,gain_cal the setting is used within the ADC to compensate for any gain variation for this particular device."
|
|
hexmask.long.word 0x24 0.--9. 1. "OFFSET_CAL,offset_cal the setting is used within the ADC to compensate for a DC shift in values for this particular device."
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0x40086000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CFG,Configuration"
|
|
bitfld.long 0x0 24.--25. "OUTTEXT_SEL,Output Text Selection From: 00: Output Block. 01: Output Block XOR Input Text. 10: Output Block XOR Holding. 11: Reserved." "0: Output Block,1: Output Block XOR Input Text,?,?"
|
|
bitfld.long 0x0 20.--21. "HOLD_SEL,Holding Select From: 00: Counter. 01: Input Text. 10: Output Block. 11: Input Text XOR Output Block." "0: Counter,1: Input Text,?,?"
|
|
bitfld.long 0x0 16.--17. "INBLK_SEL,Input Block Selection From: 00: Reserved. 01: Input Text. 10: Holding. 11: Input Text XOR Holding." "0: Reserved,1: Input Text,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "KEY_CFG,Key Configuration. 00: 128 Bit Key. 01: 192 Bit Key. 10: 256 Bit Key. 11: Reserved." "0,1,2,3"
|
|
bitfld.long 0x0 7. "OUTTEXT_WSWAP,Output Text Word Swap" "0,1"
|
|
bitfld.long 0x0 6. "OUTTEXT_BSWAP,Output Text Byte Swap" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INTEXT_WSWAP,Input Text Word Swap" "0,1"
|
|
bitfld.long 0x0 4. "INTEXT_BSWAP,Input Text Byte Swap" "0,1"
|
|
bitfld.long 0x0 2. "GF128_SEL,GF128 Select Mode. 0: GF128 Hash Input Text. 1: GF128 Hash Output Text." "0: GF128 Hash Input Text,1: GF128 Hash Output Text"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PROC_EN,Processing Mode Enable. 00: Reserved. 01: Encrypt/Decrypt Only. 10: GF128 Hash Only. 11: Encrypt/Decrypt and Hash." "0: Reserved,1: Encrypt/Decrypt Only,?,?"
|
|
line.long 0x4 "CMD,Command"
|
|
bitfld.long 0x4 9. "WIPE,Performs Abort clears KEY disables cipher and clears GF128_Y" "0,1"
|
|
bitfld.long 0x4 8. "ABORT,Aborts Encrypt/Decrypt and GF128 Hash clears INTEXT clears OUTTEXT and clears HOLDING" "0,1"
|
|
bitfld.long 0x4 4. "SWITCH_MODE,Switches mode from Forward to Reverse or from Reverse to Forward. Must wait for Idle after command. Typically used for non-counter modes (ECB CBC CFB OFB) to switch from forward to reverse mode for decryption." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "COPY_TO_Y,Copies Output Text to GF128 Y. Typically used for GCM where the Hash requires a Y input which is the result of an ECB encryption of 0s. Should be performed after encryption of 0s." "0,1"
|
|
bitfld.long 0x4 0. "COPY_SKEY,Copies Secret Key and enables cipher. Secret key is typically held in OTP or other secure memory." "0,1"
|
|
line.long 0x8 "STAT,Status"
|
|
bitfld.long 0x8 5. "KEY_VALID,When set Key is valid" "0,1"
|
|
bitfld.long 0x8 4. "REVERSE,When set Cipher in reverse mode" "0,1"
|
|
bitfld.long 0x8 2. "OUT_READY,When set output Text can be read" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "IN_READY,When set input Text can be written" "0,1"
|
|
bitfld.long 0x8 0. "IDLE,When set all state machines are idle" "0,1"
|
|
line.long 0xC "CTR_INCR,Counter Increment. Increment value for HOLDING when in Counter modes"
|
|
hexmask.long 0xC 0.--31. 1. "CTR_INCR,Counter Increment. Increment value for HOLDING when in Counter modes"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEY[$1],Bits of the AES key"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Contains the bits of the AES key."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "INTEXT[$1],Input text bits"
|
|
hexmask.long 0x0 0.--31. 1. "INTEXT,Contains bits of the AES key."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "HOLDING[$1],Holding register bits"
|
|
hexmask.long 0x0 0.--31. 1. "HOLDING,Contains the first word (bits 31:0) of the 128 bit Holding value."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "OUTTEXT[$1],Output text bits"
|
|
hexmask.long 0x0 0.--31. 1. "OUTTEXT,Contains the bits of the 128 bit Output text data."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x70)++0x3
|
|
line.long 0x0 "GF128_Y[$1],Y bits input of GF128 hash"
|
|
hexmask.long 0x0 0.--31. 1. "GF128_Y,Contains the bits of the Y input of GF128 hash."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x80)++0x3
|
|
line.long 0x0 "GF128_Z[$1],Result bits of GF128 hash"
|
|
hexmask.long 0x0 0.--31. 1. "GF128_Z,Contains bits of the result of GF128 hash."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x90)++0x3
|
|
line.long 0x0 "GCM_TAG[$1],GCM Tag bits"
|
|
hexmask.long 0x0 0.--31. 1. "GCM_TAG,Contains bits of the 128 bit GCM tag."
|
|
repeat.end
|
|
tree.end
|
|
tree "ASYNC_SYSCON (Async System Configuration)"
|
|
base ad:0x40020000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ASYNCPRESETCTRL,Asynchronous peripherals reset control. The ASYNCPRESETCTRL register allows software to reset specific peripherals attached to the async APB bridge. Writing a zero to any assigned bit in this register clears the reset and allows the.."
|
|
bitfld.long 0x0 2. "CT32B1,Controls the reset for Counter/Timer CT32B1" "0: Clear reset to Counter/Timer CT32B1.,1: Assert reset to Counter/Timer CT32B1."
|
|
newline
|
|
bitfld.long 0x0 1. "CT32B0,Controls the reset for Counter/Timer CT32B0" "0: Clear reset to Counter/Timer CT32B0.,1: Assert reset to Counter/Timer CT32B0."
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "ASYNCPRESETCTRLSET,Set bits in ASYNCPRESETCTRL. Writing ones to this register sets the corresponding bit or bits in the ASYNCPRESETCTRL register. if they are implemented"
|
|
bitfld.long 0x0 2. "CT32B1,Writing 1 to this register sets the bit ASYNCPRESETCTRL.CT32B1" "0: No effect.,1: Set the bit ASYNCPRESETCTRL.CT32B1."
|
|
newline
|
|
bitfld.long 0x0 1. "CT32B0,Writing 1 to this register sets the bit ASYNCPRESETCTRL.CT32B0" "0: No effect.,1: Set the bit ASYNCPRESETCTRL.CT32B0."
|
|
line.long 0x4 "ASYNCPRESETCTRLCLR,Clear bits in ASYNCPRESETCTRL. Writing ones to this register clears the corresponding bit or bits in the ASYNCPRESETCTRL register. if they are implemented"
|
|
bitfld.long 0x4 2. "CT32B1,Writing 1 to this register clears the bit ASYNCPRESETCTRL.CT32B1" "0: No effect.,1: Clear the bit ASYNCPRESETCTRL.CT32B1."
|
|
newline
|
|
bitfld.long 0x4 1. "CT32B0,Writing 1 to this register clears the bit ASYNCPRESETCTRL.CT32B0" "0: No effect.,1: Clear the bit ASYNCPRESETCTRL.CT32B0."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ASYNCAPBCLKCTRL,Asynchronous peripherals clock control. This register controls how the clock selected for the asynchronous APB peripherals is divided to provide the clock to the asynchronous peripherals"
|
|
bitfld.long 0x0 2. "CT32B1,Controls the clock for Counter/Timer CT32B1" "0: Disable clock to Counter/Timer CT32B1.,1: Enable clock to Counter/Timer CT32B1."
|
|
newline
|
|
bitfld.long 0x0 1. "CT32B0,Controls the clock for Counter/Timer CT32B0" "0: Disable clock to Counter/Timer CT32B0.,1: Enable clock to Counter/Timer CT32B0."
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "ASYNCAPBCLKCTRLSET,Set bits in ASYNCAPBCLKCTRL. Writing ones to this register sets the corresponding bit or bits in the ASYNCAPBCLKCTRLSET register. if they are implemented"
|
|
bitfld.long 0x0 2. "CT32B1,Writing 1 to this register sets the bit ASYNCAPBCLKCTRL.CT32B1" "0: No effect.,1: Set the bit ASYNCAPBCLKCTRL.CT32B1."
|
|
newline
|
|
bitfld.long 0x0 1. "CT32B0,Writing 1 to this register sets the bit ASYNCAPBCLKCTRL.CT32B0" "0: No effect.,1: Set the bit ASYNCAPBCLKCTRL.CT32B0."
|
|
line.long 0x4 "ASYNCAPBCLKCTRLCLR,Clear bits in ASYNCAPBCLKCTRL. Writing ones to this register sets the corresponding bit or bits in the ASYNCAPBCLKCTRLSET register. if they are implemented"
|
|
bitfld.long 0x4 2. "CT32B1,Writing 1 to this register clears the bit ASYNCAPBCLKCTRL.CT32B1" "0: No effect.,1: Clear the bit ASYNCAPBCLKCTRL.CT32B1."
|
|
newline
|
|
bitfld.long 0x4 1. "CT32B0,Writing 1 to this register clears the bit ASYNCAPBCLKCTRL.CT32B0" "0: No effect.,1: Clear the ASYNCAPBCLKCTRL.CT32B0."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ASYNCAPBCLKSELA,Asynchronous APB clock source select"
|
|
bitfld.long 0x0 0.--1. "SEL,Clock source for modules beyond asynchronous Bus bridge: ASYNC_SYSCON itself timers 0/1." "0: System Bus clock.,1: 32 MHz crystal oscillator (XTAL32M).,2: 32 MHz free running oscillator (FRO32M).,3: 48 MHz free running oscillator (FRO48M)."
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "TEMPSENSORCTRL,Temperature Sensor controls"
|
|
bitfld.long 0x0 2.--3. "CM,Temerature sensor common mode output voltage selection: 0x0: high negative offset added; 0x1: intermediate negative offset added; 0x2: no offset added; 0x3: low positive offset added. Only setting 0x2 should be used." "0: high negative offset added; 0x1: intermediate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,Temperature sensor enable" "0,1"
|
|
group.long 0xA8++0x7
|
|
line.long 0x0 "XTAL32MLDOCTRL,XTAL 32 MHz LDO control register. If XTAL has been auto started due to EFUSE XTAL32MSTART_ENA or BLE low power timers then the effect of these need disabling via SYSCON.XTAL32MCTRL before the full control by this register is possible."
|
|
bitfld.long 0x0 8.--9. "STABMODE,Stability configuration only required for test purposes." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "IBIAS,Adjust the biasing current setting managed by software API." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "VOUT,Adjust the output voltage level setting managed by software API." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable the LDO when set. Setting managed by software API." "0,1"
|
|
line.long 0x4 "XTAL32MCTRL,XTAL 32 MHz control register. If XTAL has been auto started due to EFUSE XTAL32MSTART_ENA or BLE low power timers then the effect of these need disabling via SYSCON.XTAL32MCTRL before the full control by this register is possible."
|
|
bitfld.long 0x4 29. "CLK_TO_GPADC_ENABLE,Enable the 16MHz clock to General Purpose ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "XO32M_TO_MCU_ENABLE,Enable the 32MHz clock to MCU and the clock generators." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "XO_STANDALONE_ENABLE,Selection of the LDO and core XO reference biasing sources (1uA bandgap current and 0.6V bandgap voltage): 0: biasing provided by radio reference biasing sources. Don't switch to this value without prior radio biasing LDO XO core.." "0: biasing provided by radio reference biasing..,1: biasing is provided by Power Management Unit"
|
|
newline
|
|
bitfld.long 0x4 26. "XO_SLAVE,XTAL in slave mode. Setting managed by software API." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23.--25. "XO_GM,Gm value for XTAL.. Setting managed by software API." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 22. "XO_ENABLE,Enable signal for 32MHz XTAL." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 11.--17. 1. "XO_OSC_CAP_OUT,Internal Capacitor Selection for XTAL_N. Each XTAL pin has a capacitance value up to approximately 25pF. Device test calibration data is stored on chip so that a software function can configure a capacitiance with high accuracy."
|
|
newline
|
|
hexmask.long.byte 0x4 4.--10. 1. "XO_OSC_CAP_IN,Internal Capacitor Selection for XTAL_P. Each XTAL pin has a capacitance value up to approximately 25pF. Device test calibration data is stored on chip so that a software function can configure a capacitiance with high accuracy."
|
|
newline
|
|
bitfld.long 0x4 1.--3. "XO_AMP,Amplitude selection Min amp: 001 Max amp: 110. Setting managed by software API." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0. "XO_ACBUF_PASS_ENABLE,Bypass enable of XTAL AC buffer enable in pll and top level. Setting managed by software API." "0,1"
|
|
rgroup.long 0xB0++0x7
|
|
line.long 0x0 "ANALOGID,Analog Interfaces (PMU and Radio) identity registers"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PMUID,PMU Identitty register used ti indicate a version of the PMU."
|
|
line.long 0x4 "RADIOSTATUS,All Radio Analog modules status register."
|
|
bitfld.long 0x4 0. "PLLXOREADY,Value of status output by 32M XTAL oscillator. Aserted to indicate that the clock is active. Note that the quality of the 32M clock may improve even after this is asserted. Additionally if settings are changed such as ibias control then this.." "0,1"
|
|
group.long 0xBC++0x7
|
|
line.long 0x0 "DCBUSCTRL,DC Bus can be used during device test and evaluation to give observation of internal signals."
|
|
hexmask.long.word 0x0 0.--8. 1. "ADDR,ADDR[8] should be set to 1 before entering power down to prevent the risk of a small amount of leakage current during power down."
|
|
line.long 0x4 "FREQMECTRL,Frequency measure register"
|
|
bitfld.long 0x4 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
|
|
newline
|
|
hexmask.long 0x4 0.--30. 1. "CAPVAL,Frequency Measure control and status; the function differs for a read and write operation. CAPVAL: FREQMECTRL[30:0] (Read-only) : Stores the target counter result from the last frequency measure activiation this is used in the calculation of the.."
|
|
wgroup.long 0xCC++0x3
|
|
line.long 0x0 "SWRESETCTRL,Full IC reset request (from Software application)."
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEY,Register Key: On write write 0x05FA to VECTKEY otherwise the write is ignored."
|
|
newline
|
|
bitfld.long 0x0 0. "ICRESETREQ,IC reset request. This bit is only valid if VECTKEY is set correctly. 0: No effect; 1: Request a fulll IC reset level reset" "0: No effect;,1: Request a fulll IC reset level reset"
|
|
tree.end
|
|
tree "BLE_DP_TOP (Bluetooth Low Energy Data Path)"
|
|
base ad:0x40014000
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "ANT_DIVERSITY,Antenna diversity"
|
|
bitfld.long 0x0 0. "ble_ant_selected,Selection of antenna when selection mode is direct from register see ble_ant_mode. 0: ADE is asserted. 1: ADE de-asserted. ADO is always the inverse of ADE and so is also controlled by this setting as well." "0: ADE is asserted,1: ADE de-asserted"
|
|
tree.end
|
|
tree "CIC_IRB (Infra-Red Modulator)"
|
|
base ad:0x40007000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CONF,IR Blaster configuration"
|
|
bitfld.long 0x0 5. "CAR_INI,Initial carrier value." "0: Carrier starts with '0' (the carrier is low..,1: Carrier starts with '1' (the carrier is high.."
|
|
bitfld.long 0x0 4. "NO_CAR,No carrier" "0: Normal. IR_OUT = envelope + carrier,1: Carrier is inhibited. IR_OUT = envelope only"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "OUT,Output logic function" "0: envelope AND carrier,1: envelope OR carrier,2: envelope NAND carrier,3: envelope NOR carrier"
|
|
bitfld.long 0x0 1. "MODE,Blaster mode" "0: Normal mode. IR Blaster will stop when it..,1: Automatic restart. IR Blaster will transmit all.."
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|
newline
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bitfld.long 0x0 0. "ENV_INI,Initial envelope value. This is the level of the first envelope after IR Blaster start or restart." "0: First envelope will be a low level,1: First envelope will be a high level"
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|
line.long 0x4 "CARRIER,IR Blaster carrier configuration"
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|
bitfld.long 0x4 19.--20. "CHIGH,Carrier high period Carrier high level duration = (CHIGH + 1) * CTU. It is recommended to modify this field when the blaster unit is disable (i.e when ENA_ST = '0' in STATUS register)" "0,1,2,3"
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|
bitfld.long 0x4 16.--18. "CLOW,Carrier low period. Carrier low level duration = (CLOW + 1) * CTU. It is recommended to modify this field when the blaster unit is disable (i.e when ENA_ST = '0' in STATUS register)" "0,1,2,3,4,5,6,7"
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|
newline
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hexmask.long.word 0x4 0.--15. 1. "CTU,Carrier Time Unit (CTU) CTU = CTU * TIRCP TIRCP = IR module clock period = 1/48MHz. Value 0x0 is equivalent to 0x1. It is recommended to modify this field when the blaster unit is disable (i.e when ENA_ST = '0' in STATUS register)"
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|
line.long 0x8 "FIFO_IN,IR Blaster Envelope FIFO input"
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bitfld.long 0x8 13. "ENV_LAST,Last envelope." "0: IR Blaster loads the next envelope when this..,1: IR Blaster stops and generates an interrupt when.."
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bitfld.long 0x8 12. "ENV_INT,Generate an interrupt when starting emission of the envelope" "0: Don't generate interrupt,1: Generate interrupt"
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|
newline
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hexmask.long.word 0x8 0.--11. 1. "ENV,Envelope duration expressed in carrier period number. Tenvelope = ENV * (CHIGH + CLOW + 2 ) * CTU. Value 0x000 has the same behaviour has value 0x001."
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|
rgroup.long 0xC++0x3
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|
line.long 0x0 "STATUS,IR Blaster Status"
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|
bitfld.long 0x0 8. "RUN_ST,IR Blaster run status" "0: IR Blaster is not running. Either transmission..,1: IR Blaster is running."
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bitfld.long 0x0 7. "ENA_ST,IR Blaster status" "0: IR Blaster is disabled,1: IR Blaster is enabled"
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newline
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bitfld.long 0x0 6. "FIFO_EMPTY,IR Blaster FIFO empty flag" "0: FIFO is not empty,1: FIFO is empty (FIFO level = 000000)"
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bitfld.long 0x0 5. "FIFO_FULL,IR Blaster FIFO full flag" "0: FIFO is not full,1: FIFO is full (FIFO level = 100000)"
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|
newline
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hexmask.long.byte 0x0 0.--4. 1. "FIFO_LVL,Current IR Blaster FIFO level"
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|
wgroup.long 0x10++0x3
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line.long 0x0 "CMD,IR Blaster Commands"
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bitfld.long 0x0 3. "FIFO_RST,Reset IR Blaster FIFO. This bit is self clearing." "0: No effect,1: Reset FIFO. IR Blaster FIFO is completly.."
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bitfld.long 0x0 2. "START,Start IR Blaster. This bit is self clearing." "0: No effect,1: Start transmission Before setting this field the.."
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newline
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bitfld.long 0x0 1. "DIS,Disable IR Blaster. This bit is self clearing." "0: No effect,1: Disable IR Blaster. The transmission of.."
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|
bitfld.long 0x0 0. "ENA,Enable IR Blaster. This bit is self clearing." "0: No effect,1: Enable IR Blaster"
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|
rgroup.long 0xFE0++0x3
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line.long 0x0 "INT_STATUS,Interrupt Status"
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bitfld.long 0x0 2. "FIFO_UFL_INT,IR Blaster FIFO underflow. IR Blaster has tried to transmit a data but the FIFO was empty." "0: Interrupt is not pending,1: Interrupt is pending"
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bitfld.long 0x0 1. "ENV_LAST_INT,IR Blaster has finished to transmit an envelope with ENV_LAST bit = '1'." "0: Interrupt is not pending,1: Interrupt is pending"
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newline
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bitfld.long 0x0 0. "ENV_START_INT,IR Blaster has started to transmit an envelope with ENV_INT bit = '1" "0: Interrupt is not pending,1: Interrupt is pending"
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group.long 0xFE4++0x3
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line.long 0x0 "INT_ENA,Interrupt Enable"
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|
bitfld.long 0x0 2. "FIFO_UFL_ENA,Enable/Disable FIFO_UFL interrupt" "0: Disable FIFO_UFL interrupt,1: Enable FIFO_UFL nterrupt"
|
|
bitfld.long 0x0 1. "ENV_LAST_ENA,Enable/Disable ENV_LAST interrupt" "0: Disable ENV_LAST interrupt,1: Enable ENV_LAST interrupt"
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|
newline
|
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bitfld.long 0x0 0. "ENV_START_ENA,Enable/Disable ENV_START interrupt" "0: Disable ENV_START interrupt,1: Enable ENV_START interrupt"
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|
wgroup.long 0xFE8++0x7
|
|
line.long 0x0 "INT_CLR,Interrupt Clear"
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|
bitfld.long 0x0 2. "FIFO_UFL_CLR,Clear FIFO_UFL interrupt" "0: no effect,1: clear FIFO_UFL interrupt This bit is self clearing"
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|
bitfld.long 0x0 1. "ENV_LAST_CLR,Clear ENV_LAST interrupt" "0: no effect,1: clear ENV_LAST interrupt This bit is self clearing"
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|
newline
|
|
bitfld.long 0x0 0. "ENV_START_CLR,Clear ENV_START interrupt" "0: no effect,1: clear ENV_START interrupt This bit is self.."
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|
line.long 0x4 "INT_SET,Interrupt Set"
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|
bitfld.long 0x4 2. "FIFO_UFL_SET,Set FIFO_UFL interrupt" "0: no effect,1: set FIFO_UFL interrupt This bit is self clearing"
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|
bitfld.long 0x4 1. "ENV_LAST_SET,Set ENV_LAST interrupt" "0: no effect,1: set ENV_LAST interrupt This bit is self clearing"
|
|
newline
|
|
bitfld.long 0x4 0. "ENV_START_SET,Set ENV_START interrupt" "0: no effect,1: set ENV_START interrupt This bit is self clearing"
|
|
rgroup.long 0xFFC++0x3
|
|
line.long 0x0 "MODULE_ID,IR Blaster Module Identifier"
|
|
hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. implies software modifications"
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|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
|
|
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
|
|
tree.end
|
|
tree "CTIMER (Counter/Timer)"
|
|
base ad:0x0
|
|
tree "CTIMER0"
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|
base ad:0x40021000
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|
group.long 0x0++0x17
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line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
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bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
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bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
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|
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
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|
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
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|
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
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|
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
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|
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
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line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
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bitfld.long 0x4 1. "CRST,Counter reset. 0 Disabled. Do nothing. 1 Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero." "0,1"
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bitfld.long 0x4 0. "CEN,Counter enable. 0 Disabled.The counters are disabled. 1 Enabled. The Timer Counter and Prescale Counter are enabled." "0,1"
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|
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
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|
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
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|
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
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hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
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line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
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hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
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line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
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bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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|
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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newline
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bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x18)++0x3
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line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
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hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
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repeat.end
|
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group.long 0x28++0x3
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line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
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bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
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bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
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bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
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repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
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rgroup.long ($2+0x2C)++0x3
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line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn.0 input."
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hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
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repeat.end
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group.long 0x3C++0x3
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line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
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bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 0x2 Set. Set the corresponding External Match bit/output.." "0,1,2,3"
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bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 0x2 Set. Set the corresponding External Match bit/output.." "0,1,2,3"
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bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 0x2 Set. Set the corresponding External Match bit/output.." "0,1,2,3"
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bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 0x2 Set. Set the corresponding External Match bit/output.." "0,1,2,3"
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bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3 whether or not this output is connected to a pin. When a match occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
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bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2 whether or not this output is connected to a pin. When a match occurs between the TC and MR2 this bit can either toggle go LOW go HIGH or do nothing as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
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newline
|
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bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1 whether or not this output is connected to a pin. When a match occurs between the TC and MR1 this bit can either toggle go LOW go HIGH or do nothing as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
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bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0 whether or not this output is connected to a pin. When a match occurs between the TC and MR0 this bit can either toggle go LOW go HIGH or do nothing as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
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group.long 0x70++0x7
|
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line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
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bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1 these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. 0 0x0 Channel 0 Rising Edge." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
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bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00 these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR the 3 bits for that input in the Capture Control.." "0,1,2,3"
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bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer s Prescale Counter (PC) or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0,1,2,3"
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line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
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bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 0 Match. CT32Bn_MAT3 is controlled by EM3. 1 PWM. PWM mode is enabled for CT132Bn_MAT3" "0,1"
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bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2. 0 Match. CT32Bn_MAT2 is controlled by EM2. 1 PWM. PWM mode is enabled for CT32Bn_MAT2." "0,1"
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bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1. 0 Match. CT32Bn_MAT01 is controlled by EM1. 1 PWM. PWM mode is enabled for CT32Bn_MAT1." "0,1"
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bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0. 0 Match. CT32Bn_MAT0 is controlled by EM0. 1 PWM. PWM mode is enabled for CT32Bn_MAT0." "0,1"
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tree.end
|
|
tree "CTIMER1"
|
|
base ad:0x40022000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
|
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bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
|
|
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
|
|
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
|
|
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
|
|
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
|
|
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
|
|
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
|
|
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
|
|
bitfld.long 0x4 1. "CRST,Counter reset. 0 Disabled. Do nothing. 1 Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero." "0,1"
|
|
bitfld.long 0x4 0. "CEN,Counter enable. 0 Disabled.The counters are disabled. 1 Enabled. The Timer Counter and Prescale Counter are enabled." "0,1"
|
|
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
|
|
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
|
|
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
|
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hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
|
|
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
|
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hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
|
|
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
|
|
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
|
|
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
|
|
repeat.end
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
|
|
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
|
|
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
|
|
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn.0 input."
|
|
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
|
|
repeat.end
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
|
|
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 0x2 Set. Set the corresponding External Match bit/output.." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 0x2 Set. Set the corresponding External Match bit/output.." "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 0x2 Set. Set the corresponding External Match bit/output.." "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 0x2 Set. Set the corresponding External Match bit/output.." "0,1,2,3"
|
|
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3 whether or not this output is connected to a pin. When a match occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2 whether or not this output is connected to a pin. When a match occurs between the TC and MR2 this bit can either toggle go LOW go HIGH or do nothing as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
|
|
newline
|
|
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1 whether or not this output is connected to a pin. When a match occurs between the TC and MR1 this bit can either toggle go LOW go HIGH or do nothing as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0 whether or not this output is connected to a pin. When a match occurs between the TC and MR0 this bit can either toggle go LOW go HIGH or do nothing as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
|
|
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1 these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. 0 0x0 Channel 0 Rising Edge." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
|
|
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00 these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR the 3 bits for that input in the Capture Control.." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer s Prescale Counter (PC) or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0,1,2,3"
|
|
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
|
|
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 0 Match. CT32Bn_MAT3 is controlled by EM3. 1 PWM. PWM mode is enabled for CT132Bn_MAT3" "0,1"
|
|
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2. 0 Match. CT32Bn_MAT2 is controlled by EM2. 1 PWM. PWM mode is enabled for CT32Bn_MAT2." "0,1"
|
|
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1. 0 Match. CT32Bn_MAT01 is controlled by EM1. 1 PWM. PWM mode is enabled for CT32Bn_MAT1." "0,1"
|
|
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0. 0 Match. CT32Bn_MAT0 is controlled by EM0. 1 PWM. PWM mode is enabled for CT32Bn_MAT0." "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x40085000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,DMA control."
|
|
bitfld.long 0x0 0. "ENABLE,DMA controller master enable. 0: Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled but does not prevent re-triggering when the DMA controller is re-enabled. 1: Enabled. The DMA.." "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "INTSTAT,Interrupt status."
|
|
bitfld.long 0x0 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending. 0: Not pending. No error interrupts are pending. 1: Pending. At least one error interrupt is pending." "0: Not pending,1: Pending"
|
|
bitfld.long 0x0 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending. 0: Not pending. No enabled interrupts are pending. 1: Pending. At least one enabled interrupt is pending." "0: Not pending,1: Pending"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "SRAMBASE,SRAM address of the channel configuration table."
|
|
hexmask.long.tbyte 0x0 9.--31. 1. "OFFSET,Address bits 31:9 of the beginning of the DMA descriptor table. For 19 channels the table must begin on a 512 byte boundary. The SRAMBASE register must be configured with an address (preferably in on-chip SRAM) where DMA descriptors will be stored."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ENABLESET0,Channel Enable read and Set for all DMA channels"
|
|
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. 0: disabled. 1: enabled."
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "ENABLECLR0,Channel Enable Clear for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "ACTIVE0,Channel Active status for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0: not active. 1: active."
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "BUSY0,Channel Busy status for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 : not busy. 1: busy."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "ERRINT0,Error Interrupt status for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0: error interrupt is not active. 1: error interrupt is active."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "INTENSET0,Interrupt Enable read and Set for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. 0: interrupt for DMA channel is disabled. 1: interrupt for DMA channel is enabled."
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x0 "INTENCLR0,Interrupt Enable Clear for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "INTA0,Interrupt A status for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0: the DMA channel interrupt A is not active. 1: the DMA channel interrupt A is active."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "INTB0,Interrupt B status for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0: the DMA channel interrupt B is not active. 1: the DMA channel interrupt B is active."
|
|
wgroup.long 0x68++0x3
|
|
line.long 0x0 "SETVALID0,Set ValidPending control bits for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0: no effect. 1: sets the VALIDPENDING control bit for DMA channel n"
|
|
wgroup.long 0x70++0x3
|
|
line.long 0x0 "SETTRIG0,Set Trigger control bits for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel n. Bit n corresponds to DMA channel n. 0: no effect. 1: sets the TRIG bit for DMA channel n."
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x0 "ABORT0,Channel Abort control for all DMA channels."
|
|
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0: no effect. 1: aborts DMA operations on channel n."
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40085400 ad:0x40085410 ad:0x40085420 ad:0x40085430 ad:0x40085440 ad:0x40085450 ad:0x40085460 ad:0x40085470 ad:0x40085480 ad:0x40085490 ad:0x400854A0 ad:0x400854B0 ad:0x400854C0 ad:0x400854D0 ad:0x400854E0 ad:0x400854F0)
|
|
tree "CHANNEL[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CFG,Configuration register for DMA channel x"
|
|
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
|
|
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled the destination data address for the DMA is wrapped meaning that the destination address range for each burst will be the same. As an example this could be used to write several sequential registers.." "0,1"
|
|
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled the source data address for the DMA is wrapped meaning that the source address range for each burst will be the same. As an example this could be used to read several sequential registers from a peripheral.." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1 Burst.."
|
|
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 0 Single transfer. Hardware trigger causes a single transfer. 1 Burst transfer. When the trigger for this channel is set to edge triggered a hardware trigger.." "0,1"
|
|
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered. 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed as specified for a single trigger. 1 Level. Hardware trigger is level triggered." "0,1"
|
|
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered based on TRIGTYPE. 1 Active high - rising edge. Hardware trigger is active high.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel. 0 Disabled. Hardware triggering is not used. 1 Enabled. Use hardware triggering." "0,1"
|
|
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0.." "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CTLSTAT,Control and status register for DMA channel x"
|
|
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not.." "0,1"
|
|
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 No effect. No effect on DMA operation. 1 Valid pending." "0,1"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel x"
|
|
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). Remark: The DMA controller uses this bit field during transfer to count down. Hence .."
|
|
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer. 0x0 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. 0x1 1 x width. The.." "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer. 0x0 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 0x1 1 x width. The source address.." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel. 0x0 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 0x1 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 0x2 32-bit. 32-bit transfers are.." "0,1,2,3"
|
|
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention interrupt A may be used when only one interrupt flag is.." "0,1"
|
|
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention interrupt A may be used when only one interrupt flag is.." "0,1"
|
|
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger. 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload the next descriptor will be started. 1 Cleared. The trigger is cleared when this descriptor is exhausted." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWTRIG,Software Trigger. 0 Not set. When written by software the trigger for this channel is not set. A new trigger as defined by the HWTRIGEN TRIGPOL and TRIGTYPE will be needed to start the channel. 1 Set. When written by software the trigger for.." "0,1"
|
|
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel s control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 0 Disabled. Do not reload the channels control structure when the current descriptor is.." "0,1"
|
|
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon if all other activation criteria are fulfilled. 0 Not valid. The channel descriptor is not considered valid until.." "0,1"
|
|
line.long 0x4 "RESERVED0,Reserved"
|
|
hexmask.long 0x4 0.--31. 1. "DUMMYWORD,Reserved. The value read from a reserved bit is not defined."
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 0x10 0x11 0x12)(list ad:0x40085500 ad:0x40085510 ad:0x40085520)
|
|
tree "CHANNEL[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CFG,Configuration register for DMA channel x"
|
|
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
|
|
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled the destination data address for the DMA is wrapped meaning that the destination address range for each burst will be the same. As an example this could be used to write several sequential registers.." "0,1"
|
|
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled the source data address for the DMA is wrapped meaning that the source address range for each burst will be the same. As an example this could be used to read several sequential registers from a peripheral.." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1 Burst.."
|
|
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 0 Single transfer. Hardware trigger causes a single transfer. 1 Burst transfer. When the trigger for this channel is set to edge triggered a hardware trigger.." "0,1"
|
|
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered. 0 Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed as specified for a single trigger. 1 Level. Hardware trigger is level triggered." "0,1"
|
|
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 0 Active low - falling edge. Hardware trigger is active low or falling edge triggered based on TRIGTYPE. 1 Active high - rising edge. Hardware trigger is active high.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel. 0 Disabled. Hardware triggering is not used. 1 Enabled. Use hardware triggering." "0,1"
|
|
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0.." "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CTLSTAT,Control and status register for DMA channel x"
|
|
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 0 Not triggered. The trigger for this DMA channel is not set. DMA operations will not.." "0,1"
|
|
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 No effect. No effect on DMA operation. 1 Valid pending." "0,1"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel x"
|
|
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). Remark: The DMA controller uses this bit field during transfer to count down. Hence .."
|
|
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer. 0x0 No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. 0x1 1 x width. The.." "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer. 0x0 No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 0x1 1 x width. The source address.." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel. 0x0 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 0x1 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 0x2 32-bit. 32-bit transfers are.." "0,1,2,3"
|
|
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention interrupt A may be used when only one interrupt flag is.." "0,1"
|
|
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention interrupt A may be used when only one interrupt flag is.." "0,1"
|
|
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger. 0 Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload the next descriptor will be started. 1 Cleared. The trigger is cleared when this descriptor is exhausted." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWTRIG,Software Trigger. 0 Not set. When written by software the trigger for this channel is not set. A new trigger as defined by the HWTRIGEN TRIGPOL and TRIGTYPE will be needed to start the channel. 1 Set. When written by software the trigger for.." "0,1"
|
|
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel s control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 0 Disabled. Do not reload the channels control structure when the current descriptor is.." "0,1"
|
|
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon if all other activation criteria are fulfilled. 0 Not valid. The channel descriptor is not considered valid until.." "0,1"
|
|
line.long 0x4 "RESERVED0,Reserved"
|
|
hexmask.long 0x4 0.--31. 1. "DUMMYWORD,Reserved. The value read from a reserved bit is not defined."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DMIC (Digital Microphone Interface)"
|
|
base ad:0x4008A000
|
|
repeat 2. (list 0x0 0x1)(list ad:0x4008A000 ad:0x4008A100)
|
|
tree "CHANNEL[$1]"
|
|
base $2
|
|
group.long ($2)++0x13
|
|
line.long 0x0 "OSR,Oversample Rate register 0. This register selects the oversample rate (CIC decimation rate) for the input channel."
|
|
hexmask.long.byte 0x0 0.--7. 1. "OSR,Selects the oversample rate for the related input channel."
|
|
line.long 0x4 "DIVHFCLK,DMIC Clock Register 0. This register controls the clock pre-divider for the input channel."
|
|
hexmask.long.byte 0x4 0.--3. 1. "PDMDIV,PDM clock divider value. 0: divide by 1; 1: divide by 2; 2: divide by 3; 3: divide by 4; 4: divide by 6; 5: divide by 8; 6: divide by 12; 7: divide by 16; 8: divide by 24; 9: divide by 32; 10: divide by 48; 11: divide by 64; 12: divide by 96; 13:.."
|
|
line.long 0x8 "PREAC2FSCOEF,Pre-Emphasis Filter Coefficient for 2 FS register 0. This register seclects the pre-emphasis filter coeffcient for the input channel when 2 FS mode is used."
|
|
bitfld.long 0x8 0.--1. "COMP,Pre-emphasis filer coefficient for 2 FS mode. 0: Compensation = 0 1: Compensation = -0.16 2: Compensation = -0.15 3: Compensation = -0.13" "0: Compensation = 0,1: Compensation = -0,2: Compensation = -0,3: Compensation = -0"
|
|
line.long 0xC "PREAC4FSCOEF,Pre-Emphasis Filter Coefficient for 4 FS register 0. This register seclects the pre-emphasis filter coeffcient for the input channel when 4FS mode is used"
|
|
bitfld.long 0xC 0.--1. "COMP,Pre-emphasis filer coefficient for 4 FS mode. 0: Compensation = 0; 1: Compensation = -0.16; 2: Compensation = -0.15; 3: Compensation = -0.13." "0: Compensation = 0;,1: Compensation = -0,2: Compensation = -0,3: Compensation = -0"
|
|
line.long 0x10 "GAINSHIFT,Decimator Gain Shift register 0. This register adjusts the gain of the 4FS PCM data from the input filter."
|
|
hexmask.long.byte 0x10 0.--5. 1. "GAIN,Gain control as a positive or negative (two s complement) number of bits to shift."
|
|
group.long ($2+0x80)++0x13
|
|
line.long 0x0 "FIFO_CTRL,FIFO Control register 0. This register configures FIFO usage."
|
|
hexmask.long.byte 0x0 16.--20. 1. "TRIGLVL,FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so the FIFO level can wake up the device. 0: trigger when the FIFO has received one entry (is no longer empty). 1: trigger when the FIFO has.."
|
|
bitfld.long 0x0 3. "DMAEN,DMA enable. 0: DMA requests are not enabled. 1: DMA requests based on FIFO level are enabled." "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "INTEN,Interrupt enable. 0: FIFO level interrupts are not enabled. 1: FIFO level interrupts are enabled." "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
|
|
bitfld.long 0x0 1. "RESETN,FIFO reset. 0: Reset the FIFO. This bit must be cleared before resuming operation. 1: Normal operation." "0: Reset the FIFO,1: Normal operation"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,FIFO enable. 0: FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful in order to avoid a filter settling. delay when a channel is re-enabled after a period when the data was not needed. 1: FIFO is enabled. The FIFO.." "0: FIFO is not enabled,1: FIFO is enabled"
|
|
line.long 0x4 "FIFO_STATUS,FIFO Status register 0 . This register provides status information for the FIFO and also indicates an interrupt from the peripheral funcion."
|
|
bitfld.long 0x4 2. "UNDERRUN,Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag." "0,1"
|
|
bitfld.long 0x4 1. "OVERRUN,Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one to this bit clears the flag. This flag does not cause an interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "INT,Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC subsystem must be running in order for an interrupt to occur." "0,1"
|
|
line.long 0x8 "FIFO_DATA,FIFO Data Register 0. This register is used to read values that have been received via the PDM stream."
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data from the top of the input filter FIFO."
|
|
line.long 0xC "PHY_CTRL,PHY Control / PDM Source Configuration register 0. This register configures how the PDM source signals are interpreted."
|
|
bitfld.long 0xC 1. "PHY_HALF,Half rate sampling. 0: Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing. 1: Use half rate sampling. The PDM clock to DMIC is divided by 2. Each PDM data is sampled twice into the.." "0: Standard half rate sampling,1: Use half rate sampling"
|
|
bitfld.long 0xC 0. "PHY_FALL,Capture PDM_DATA. 0: Capture PDM_DATA on the rising edge of PDM_CLK. 1: Capture PDM_DATA on the falling edge of PDM_CLK." "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
|
|
line.long 0x10 "DC_CTRL,DC Control register 0. This register controls the DC filter."
|
|
bitfld.long 0x10 8. "SATURATEAT16BIT,Selects 16-bit saturation. 0:Results roll over if out range and do not saturate. 1:If the result overflows it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow." "0: Results roll over if out range and do not saturate,1: If the result overflows"
|
|
hexmask.long.byte 0x10 4.--7. 1. "DCGAIN,Fine gain adjustment in the form of a number of bits to downshift."
|
|
newline
|
|
bitfld.long 0x10 0.--1. "DCPOLE,DC block filter. 0: Flat response no filter. 1: 155 Hz. 2: 78 Hz. 3: 39 Hz. These frequencies assume a PCM output frequency of 16 MHz. If the actual PCM output frequency is 8 MHz for example the noted frequencies would be divided by 2." "0: Flat response,?,?,?"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4008A000
|
|
group.long 0xF00++0x3
|
|
line.long 0x0 "CHANEN,Channel Enable register. This register allows enabling either or both PDM channels."
|
|
bitfld.long 0x0 1. "EN_CH1,Enable channel 1. When 1 PDM channel 1 is enabled." "0,1"
|
|
bitfld.long 0x0 0. "EN_CH0,Enable channel 0. When 1 PDM channel 0 is enabled." "0,1"
|
|
group.long 0xF0C++0x7
|
|
line.long 0x0 "IOCFG,I/O Configuration register. This register configures the use of the PDM pins."
|
|
bitfld.long 0x0 2. "STEREO_DATA0,Stereo PDM select. When 1 PDM_DATA0 is routed to both PDM channels in a configuration that supports a single stereo digital microphone." "0,1"
|
|
bitfld.long 0x0 1. "CLK_BYPASS1,Bypass CLK1. When 1 PDM_DATA1 becomes the clock for PDM channel 1. This provides for the possibility of an external codec taking over the PDM bus." "0,1"
|
|
bitfld.long 0x0 0. "CLK_BYPASS0,Bypass CLK0. When 1 PDM_DATA1 becomes the clock for PDM channel 0. This provides for the possibility of an external codec taking over the PDM bus." "0,1"
|
|
line.long 0x4 "USE2FS,Use 2FS register. This register allow selecting 2FS output rather than 1FS output."
|
|
bitfld.long 0x4 0. "USE2FS,Use 2FS register. 0: Use 1FS output for PCM data. 1: Use 2FS output for PCM data." "0: Use 1FS output for PCM data,1: Use 2FS output for PCM data"
|
|
group.long 0xF80++0x17
|
|
line.long 0x0 "HWVADGAIN,HWVAD input gain register. This register controls the input gain of the HWVAD."
|
|
hexmask.long.byte 0x0 0.--3. 1. "INPUTGAIN,Shift value for input bits. 0x0: -10 bits; 0x1: -8 bits; 0x2: -6 bits; 0x3: -4 bits; 0x4: -2 bits; 0x5: 0 bits (default); 0x6: +2 bits; 0x7: +4 bits; 0x8: +6 bits; 0x9: +8 bits; 0xA: +10 bits; 0xB: +12 bits; 0xC: +14 bits; 0xD to 0xF: Reserved."
|
|
line.long 0x4 "HWVADHPFS,HWVAD filter control register. This register controls the HWVAD filter setting."
|
|
bitfld.long 0x4 0.--1. "HPFS,High pass filter. 0: First filter by-pass; 1: High pass filter with -3dB cut-off at 1750Hz; 2: High pass filter with -3dB cut-off at 215Hz.; 3: Reserved. This filter setting parameter can be used to optimize performance for different background.." "0: First filter by-pass;,1: High pass filter with -3dB cut-off at 1750Hz;,2: High pass filter with -3dB cut-off at 215Hz,3: Reserved"
|
|
line.long 0x8 "HWVADST10,HWVAD control register. This register controls the operation of the filter block and resets the internal interrut flag."
|
|
bitfld.long 0x8 0. "ST10,ST10. Once the HWVAD has triggered an interrupt a short '1' pulse on bit ST10 clears the interrupt. Alternatively keeping the bit on '1' level for some time has a special function for filter convergence. 0: Normal operation waiting for HWVAD.." "0: Normal operation,1: Reset internal interrupt flag by writing a 1 pulse"
|
|
line.long 0xC "HWVADRSTT,HWVAD filter reset register"
|
|
bitfld.long 0xC 0. "RSTT,HWVAD filter reset. Writing a 1 then writing a '0' resets all filter values. 0: Filters anr not held in reset. 1: Holds the filters in reset." "0: Filters anr not held in reset,1: Holds the filters in reset"
|
|
line.long 0x10 "HWVADTHGN,HWVAD noise estimator gain register"
|
|
hexmask.long.byte 0x10 0.--3. 1. "THGN,Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1. THGN and THGS are used within the hardware to determine when to assert the HWVAD result."
|
|
line.long 0x14 "HWVADTHGS,HWVAD signal estimator gain register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "THGS,Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1. THGN and THGS are used within the hardware to determine when to assert the HWVAD result."
|
|
rgroup.long 0xF98++0x3
|
|
line.long 0x0 "HWVADLOWZ,HWVAD noise envelope estimator register"
|
|
hexmask.long.word 0x0 0.--15. 1. "LOWZ,Noise envelope estimator value. This register contains 2 bytes of the output of filter stage z7. It can be used as an indication for the noise floor and must be evaluated by software. Note: For power saving reasons this register is not synchronized.."
|
|
rgroup.long 0xFFC++0x3
|
|
line.long 0x0 "ID,Module Identification register"
|
|
hexmask.long 0x0 0.--31. 1. "ID,Indicates module ID and the number of channels in this DMIC interface."
|
|
tree.end
|
|
tree "FLASH (Flash Controller)"
|
|
base ad:0x40009000
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "CMD,command register"
|
|
hexmask.long 0x0 0.--31. 1. "CMD,command register"
|
|
line.long 0x4 "EVENT,event register"
|
|
bitfld.long 0x4 2. "ABORT,When bit is set a running program/erase command is aborted." "0,1"
|
|
bitfld.long 0x4 1. "WAKEUP,When bit is set the controller wakes up from whatever low power or powerdown mode was active. If not in a powerdown mode this bit has no effect." "0,1"
|
|
bitfld.long 0x4 0. "RST,When bit is set the controller and flash are reset." "0,1"
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "AUTOPROG,specifies what commands are performed on AHB write"
|
|
bitfld.long 0x0 0.--1. "AUTOPROG,Auto programmings configuration. 00: auto programming switched off. 01: execute write word . 10: execute write word then if the last word in a page was written program page . 11: reserved for future use / no action." "0: auto programming switched off,1: execute write word,?,?"
|
|
line.long 0x4 "STARTA,start address for next flash command"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "STARTA,Address / Start address for commands that take an address (range) as a parameter. The address is in units of memory words not bytes."
|
|
line.long 0x8 "STOPA,end address for next flash command. if command operates on address ranges"
|
|
hexmask.long.tbyte 0x8 0.--17. 1. "STOPA,Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). The address is in units of memory words not bytes."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "DATAW[$1],data register. word 0-3; Memory data. or command parameter. or command result."
|
|
hexmask.long 0x0 0.--31. 1. "DATAW,data register word 0-3; Memory data or command parameter or command result."
|
|
repeat.end
|
|
wgroup.long 0xFD8++0x7
|
|
line.long 0x0 "INT_CLR_ENABLE,Clear interrupt enable bits"
|
|
bitfld.long 0x0 3. "ECC_ERR,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1"
|
|
bitfld.long 0x0 2. "DONE,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1"
|
|
bitfld.long 0x0 1. "ERR,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1"
|
|
bitfld.long 0x0 0. "FAIL,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1"
|
|
line.long 0x4 "INT_SET_ENABLE,Set interrupt enable bits"
|
|
bitfld.long 0x4 3. "ECC_ERR,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1"
|
|
bitfld.long 0x4 2. "DONE,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1"
|
|
bitfld.long 0x4 1. "ERR,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1"
|
|
bitfld.long 0x4 0. "FAIL,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1"
|
|
rgroup.long 0xFE0++0x7
|
|
line.long 0x0 "INT_STATUS,Interrupt status bits"
|
|
bitfld.long 0x0 3. "ECC_ERR,This status bit is set if during a memory read operation (either a user-requested read or a speculative read or reads performed by a controller command) a correctable or uncorrectable error is detected by ECC decoding logic." "0,1"
|
|
bitfld.long 0x0 2. "DONE,This status bit is set at the end of command execution" "0,1"
|
|
bitfld.long 0x0 1. "ERR,This status bit is set if execution of an illegal command is detected. A command is illegal if it is unknown or it is not allowed in the current mode or it is violating access restrictions or it has invalid parameters." "0,1"
|
|
bitfld.long 0x0 0. "FAIL,This status bit is set if execution of a (legal) command failed. The flag can be set at any time during command execution not just at the end." "0,1"
|
|
line.long 0x4 "INT_ENABLE,Interrupt enable bits"
|
|
bitfld.long 0x4 3. "ECC_ERR,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high." "0,1"
|
|
bitfld.long 0x4 2. "DONE,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high." "0,1"
|
|
bitfld.long 0x4 1. "ERR,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high." "0,1"
|
|
bitfld.long 0x4 0. "FAIL,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high." "0,1"
|
|
wgroup.long 0xFE8++0x7
|
|
line.long 0x0 "INT_CLR_STATUS,Clear interrupt status bits"
|
|
bitfld.long 0x0 3. "ECC_ERR,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1"
|
|
bitfld.long 0x0 2. "DONE,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1"
|
|
bitfld.long 0x0 1. "ERR,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1"
|
|
bitfld.long 0x0 0. "FAIL,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1"
|
|
line.long 0x4 "INT_SET_STATUS,Set interrupt status bits"
|
|
bitfld.long 0x4 3. "ECC_ERR,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1"
|
|
bitfld.long 0x4 2. "DONE,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1"
|
|
bitfld.long 0x4 1. "ERR,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1"
|
|
bitfld.long 0x4 0. "FAIL,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1"
|
|
rgroup.long 0xFFC++0x3
|
|
line.long 0x0 "MODULE_ID,Controller and Memory module identification"
|
|
hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision i.e. implies software modifications"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision i.e. with no software consequences"
|
|
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
|
|
tree.end
|
|
tree "FLEXCOMM (LPC5411x FLEXCOMM Serial Communication)"
|
|
base ad:0x0
|
|
tree "FLEXCOMM0"
|
|
base ad:0x4008B000
|
|
group.long 0xFF8++0x7
|
|
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
|
|
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
|
|
newline
|
|
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
|
|
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
|
|
newline
|
|
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
|
|
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
|
|
line.long 0x4 "PID,Peripheral identification register."
|
|
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
|
|
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
|
|
tree.end
|
|
tree "FLEXCOMM1"
|
|
base ad:0x4008C000
|
|
group.long 0xFF8++0x7
|
|
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
|
|
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
|
|
newline
|
|
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
|
|
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
|
|
newline
|
|
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
|
|
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
|
|
line.long 0x4 "PID,Peripheral identification register."
|
|
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
|
|
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
|
|
tree.end
|
|
tree "FLEXCOMM2"
|
|
base ad:0x40003000
|
|
group.long 0xFF8++0x7
|
|
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
|
|
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
|
|
newline
|
|
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
|
|
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
|
|
newline
|
|
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
|
|
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
|
|
line.long 0x4 "PID,Peripheral identification register."
|
|
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
|
|
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
|
|
tree.end
|
|
tree "FLEXCOMM3"
|
|
base ad:0x40004000
|
|
group.long 0xFF8++0x7
|
|
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
|
|
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
|
|
newline
|
|
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
|
|
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
|
|
newline
|
|
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
|
|
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
|
|
line.long 0x4 "PID,Peripheral identification register."
|
|
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
|
|
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
|
|
tree.end
|
|
tree "FLEXCOMM4"
|
|
base ad:0x4008D000
|
|
group.long 0xFF8++0x7
|
|
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
|
|
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
|
|
newline
|
|
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
|
|
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
|
|
newline
|
|
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
|
|
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
|
|
line.long 0x4 "PID,Peripheral identification register."
|
|
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
|
|
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
|
|
tree.end
|
|
tree "FLEXCOMM5"
|
|
base ad:0x4008E000
|
|
group.long 0xFF8++0x7
|
|
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
|
|
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
|
|
newline
|
|
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
|
|
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
|
|
newline
|
|
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
|
|
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
|
|
line.long 0x4 "PID,Peripheral identification register."
|
|
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
|
|
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
|
|
tree.end
|
|
tree "FLEXCOMM6"
|
|
base ad:0x40005000
|
|
group.long 0xFF8++0x7
|
|
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
|
|
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
|
|
newline
|
|
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
|
|
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
|
|
newline
|
|
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
|
|
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
|
|
line.long 0x4 "PID,Peripheral identification register."
|
|
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
|
|
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
|
|
tree.end
|
|
tree.end
|
|
tree "GINT (GPIO Group Interrupt)"
|
|
base ad:0x40011000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,GPIO Grouped interrupt control register"
|
|
bitfld.long 0x0 2. "TRIG,Group interrupt trigger. 0: Edge Triggered. 1: Level Triggered." "0: Edge Triggered,1: Level Triggered"
|
|
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt. 0: Or OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity) 1: And AND functionality: An interrupt is generated when all.." "0: Or,1: And"
|
|
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PORT_POL0,GPIO Grouped Interrupt polarity register. Configure the pin polarity of each PIO signal into the group interrupt function. If a bit is low then the corresponding PIO has an active low contribution into the group interrupt. If a bit is high then.."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "POL,Configure pin polarity of pin PIOn."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PORT_ENA0,GPIO Grouped Interrupt port enable register. When a bit is set then the corresponding PIO is enabled for the group interrupt function."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "ENA,Enable pin PIOn for group interrupt."
|
|
tree.end
|
|
tree "GPIO (General Purpose I/Os)"
|
|
base ad:0x40080000
|
|
repeat 22. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "B[$1],Byte pin registers. Read 0: pin PIOn is LOW. Read 0xFF: pin PIOn is HIGH. Only 0 or 0xFF can be read. Write 0: clear output bit. Write any value 0x01 to 0xFF: set output bit. Reset values reflects the state of pin given by the relevant bit of PIN.."
|
|
hexmask.byte 0x0 0.--7. 1. "B,Byte pin registers. Read 0: pin PIOn is LOW. Read 0xFF: pin PIOn is HIGH. Only 0 or 0xFF can be read. Write 0: clear output bit. Write any value 0x01 to 0xFF: set output bit. Reset values reflects the state of pin given by the relevant bit of PIN reset.."
|
|
repeat.end
|
|
repeat 22. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "W[$1],Word pin registers Read 0: pin PIOn is LOW. Read 0xFFFFFFFF: pin PIOn is HIGH. Only 0 or 0xFFFF FFFF can be read. Write 0: clear output bit. Write any value 0x00000001 to 0xFFFFFFFF: set output bit. Reset values reflects the state of pin given by.."
|
|
hexmask.long 0x0 0.--31. 1. "W,Word pin registers Read 0: pin PIOn is LOW. Read 0xFFFFFFFF: pin PIOn is HIGH. Only 0 or 0xFFFF FFFF can be read. Write 0: clear output bit. Write any value 0x00000001 to 0xFFFFFFFF: set output bit. Reset values reflects the state of pin given by the.."
|
|
repeat.end
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "DIR0,Direction register"
|
|
bitfld.long 0x0 21. "DIRP_PIO21,Selects pin direction for pin PIO21 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 20. "DIRP_PIO20,Selects pin direction for pin PIO20 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 19. "DIRP_PIO19,Selects pin direction for pin PIO19 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 18. "DIRP_PIO18,Selects pin direction for pin PIO18 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 17. "DIRP_PIO17,Selects pin direction for pin PIO17 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 16. "DIRP_PIO16,Selects pin direction for pin PIO16 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 15. "DIRP_PIO15,Selects pin direction for pin PIO15 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 14. "DIRP_PIO14,Selects pin direction for pin PIO14 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 13. "DIRP_PIO13,Selects pin direction for pin PIO13 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 12. "DIRP_PIO12,Selects pin direction for pin PIO12 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 11. "DIRP_PIO11,Selects pin direction for pin PIO11 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 10. "DIRP_PIO10,Selects pin direction for pin PIO10 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 9. "DIRP_PIO9,Selects pin direction for pin PIO9 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 8. "DIRP_PIO8,Selects pin direction for pin PIO8 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 7. "DIRP_PIO7,Selects pin direction for pin PIO7 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 6. "DIRP_PIO6,Selects pin direction for pin PIO6 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 5. "DIRP_PIO5,Selects pin direction for pin PIO5 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 4. "DIRP_PIO4,Selects pin direction for pin PIO4 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 3. "DIRP_PIO3,Selects pin direction for pin PIO3 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 2. "DIRP_PIO2,Selects pin direction for pin PIO2 . 0 = input. 1 = output." "0: input,1: output"
|
|
newline
|
|
bitfld.long 0x0 1. "DIRP_PIO1,Selects pin direction for pin PIO1 . 0 = input. 1 = output." "0: input,1: output"
|
|
bitfld.long 0x0 0. "DIRP_PIO0,Selects pin direction for pin PIO0 . 0 = input. 1 = output." "0: input,1: output"
|
|
group.long 0x2080++0x3
|
|
line.long 0x0 "MASK0,Mask register"
|
|
bitfld.long 0x0 21. "MASKP_PIO21,Controls if PIO21 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 20. "MASKP_PIO20,Controls if PIO20 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 19. "MASKP_PIO19,Controls if PIO19 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 18. "MASKP_PIO18,Controls if PIO18 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 17. "MASKP_PIO17,Controls if PIO17 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 16. "MASKP_PIO16,Controls if PIO16 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 15. "MASKP_PIO15,Controls if PIO150 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 14. "MASKP_PIO14,Controls if PIO14 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 13. "MASKP_PIO13,Controls if PIO13 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 12. "MASKP_PIO12,Controls if PIO12 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 11. "MASKP_PIO11,Controls if PIO11 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 10. "MASKP_PIO10,Controls if PIO10 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 9. "MASKP_PIO9,Controls if PIO9 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 8. "MASKP_PIO8,Controls if PIO8 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 7. "MASKP_PIO7,Controls if PIO7 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 6. "MASKP_PIO6,Controls if PIO6 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 5. "MASKP_PIO5,Controls if PIO5 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 4. "MASKP_PIO4,Controls if PIO4 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 3. "MASKP_PIO3,Controls if PIO3 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 2. "MASKP_PIO2,Controls if PIO2 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
newline
|
|
bitfld.long 0x0 1. "MASKP_PIO1,Controls if PIO1 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
bitfld.long 0x0 0. "MASKP_PIO0,Controls if PIO0 is active in MPIN register. 0 = Mask bit is clear the PIO will be active. 1 = Mask bit is set the PIO will not be active." "0: Mask bit is clear,1: Mask bit is set"
|
|
group.long 0x2100++0x3
|
|
line.long 0x0 "PIN0,Pin register"
|
|
bitfld.long 0x0 21. "PORT_PIO21,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 20. "PORT_PIO20,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
|
|
bitfld.long 0x0 19. "PORT_PIO19,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 18. "PORT_PIO18,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
|
|
bitfld.long 0x0 17. "PORT_PIO17,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 16. "PORT_PIO16,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
|
|
bitfld.long 0x0 15. "PORT_PIO15,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 14. "PORT_PIO14,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
|
|
bitfld.long 0x0 13. "PORT_PIO13,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 12. "PORT_PIO12,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
|
|
bitfld.long 0x0 11. "PORT_PIO11,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 10. "PORT_PIO10,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
|
|
bitfld.long 0x0 9. "PORT_PIO9,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 8. "PORT_PIO8,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
|
|
bitfld.long 0x0 7. "PORT_PIO7,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 6. "PORT_PIO6,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
|
|
bitfld.long 0x0 5. "PORT_PIO5,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
bitfld.long 0x0 4. "PORT_PIO4,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
|
|
newline
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bitfld.long 0x0 3. "PORT_PIO3,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
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bitfld.long 0x0 2. "PORT_PIO2,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
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newline
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bitfld.long 0x0 1. "PORT_PIO1,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
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bitfld.long 0x0 0. "PORT_PIO0,Reads pin states or loads output bits. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." "0: Read: pin is low; write: clear output bit,1: Read: pin is high; write: set output bit"
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group.long 0x2180++0x3
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line.long 0x0 "MPIN0,Masked Pin register"
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bitfld.long 0x0 21. "MPORT_PIO21,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 20. "MPORT_PIO20,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 19. "MPORT_PIO19,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 18. "MPORT_PIO18,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 17. "MPORT_PIO17,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 16. "MPORT_PIO16,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 15. "MPORT_PIO15,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 14. "MPORT_PIO14,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 13. "MPORT_PIO13,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 12. "MPORT_PIO12,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 11. "MPORT_PIO11,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 10. "MPORT_PIO10,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 9. "MPORT_PIO9,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 8. "MPORT_PIO8,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 7. "MPORT_PIO7,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 6. "MPORT_PIO6,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 5. "MPORT_PIO5,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 4. "MPORT_PIO4,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 3. "MPORT_PIO3,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 2. "MPORT_PIO2,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 1. "MPORT_PIO1,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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bitfld.long 0x0 0. "MPORT_PIO0,Masked pin register. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register.." "0: Read: pin is LOW and/or the corresponding bit in..,1: Read: pin is HIGH and the corresponding bit in.."
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group.long 0x2200++0x3
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line.long 0x0 "SET0,Write: Set Pin register bits Read: output bits"
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bitfld.long 0x0 21. "SETP_PIO21,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 20. "SETP_PIO20,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 19. "SETP_PIO19,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 18. "SETP_PIO18,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 17. "SETP_PIO17,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 16. "SETP_PIO16,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 15. "SETP_PIO15,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 14. "SETP_PIO14,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 13. "SETP_PIO13,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 12. "SETP_PIO12,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 11. "SETP_PIO11,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 10. "SETP_PIO10,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 9. "SETP_PIO9,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 8. "SETP_PIO8,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 7. "SETP_PIO7,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 6. "SETP_PIO6,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 5. "SETP_PIO5,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 4. "SETP_PIO4,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 3. "SETP_PIO3,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 2. "SETP_PIO2,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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newline
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bitfld.long 0x0 1. "SETP_PIO1,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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bitfld.long 0x0 0. "SETP_PIO0,Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." "0: Read: output bit: write: no operation,1: Read: output bit; write: set output bit"
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wgroup.long 0x2280++0x3
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line.long 0x0 "CLR0,Clear Pin register bits"
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bitfld.long 0x0 21. "CLRP_PIO21,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 20. "CLRP_PIO20,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 19. "CLRP_PIO19,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 18. "CLRP_PIO18,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 17. "CLRP_PIO17,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 16. "CLRP_PIO16,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 15. "CLRP_PIO15,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 14. "CLRP_PIO14,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 13. "CLRP_PIO13,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 12. "CLRP_PIO12,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 11. "CLRP_PIO11,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 10. "CLRP_PIO10,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 9. "CLRP_PIO9,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 8. "CLRP_PIO8,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 7. "CLRP_PIO7,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 6. "CLRP_PIO6,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 5. "CLRP_PIO5,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 4. "CLRP_PIO4,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 3. "CLRP_PIO3,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 2. "CLRP_PIO2,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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newline
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bitfld.long 0x0 1. "CLRP_PIO1,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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bitfld.long 0x0 0. "CLRP_PIO0,Clear output bits. 0 = No operation. 1 = Clear output bit." "0: No operation,1: Clear output bit"
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wgroup.long 0x2300++0x3
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line.long 0x0 "NOT0,Toggle Pin register bits"
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bitfld.long 0x0 21. "NOTP_PIO21,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 20. "NOTP_PIO20,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 19. "NOTP_PIO19,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 18. "NOTP_PIO18,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 17. "NOTP_PIO17,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 16. "NOTP_PIO16,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 15. "NOTP_PIO15,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 14. "NOTP_PIO14,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 13. "NOTP_PIO13,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 12. "NOTP_PIO12,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 11. "NOTP_PIO11,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 10. "NOTP_PIO10,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 9. "NOTP_PIO9,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 8. "NOTP_PIO8,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 7. "NOTP_PIO7,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 6. "NOTP_PIO6,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 5. "NOTP_PIO5,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 4. "NOTP_PIO4,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 3. "NOTP_PIO3,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 2. "NOTP_PIO2,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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newline
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bitfld.long 0x0 1. "NOTP_PIO1,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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bitfld.long 0x0 0. "NOTP_PIO0,Toggle output bits. 0 = no operation. 1 = Toggle output bit." "0: no operation,1: Toggle output bit"
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wgroup.long 0x2380++0x3
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line.long 0x0 "DIRSET0,Set pin direction bits"
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bitfld.long 0x0 21. "DIRSETP_PIO21,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 20. "DIRSETP_PIO20,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 19. "DIRSETP_PIO19,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 18. "DIRSETP_PIO18,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 17. "DIRSETP_PIO17,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 16. "DIRSETP_PIO16,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 15. "DIRSETP_PIO15,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 14. "DIRSETP_PIO14,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 13. "DIRSETP_PIO13,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 12. "DIRSETP_PIO12,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 11. "DIRSETP_PIO11,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 10. "DIRSETP_PIO10,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 9. "DIRSETP_PIO9,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 8. "DIRSETP_PIO8,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 7. "DIRSETP_PIO7,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 6. "DIRSETP_PIO6,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 5. "DIRSETP_PIO5,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 4. "DIRSETP_PIO4,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 3. "DIRSETP_PIO3,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 2. "DIRSETP_PIO2,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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newline
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bitfld.long 0x0 1. "DIRSETP_PIO1,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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bitfld.long 0x0 0. "DIRSETP_PIO0,Set direction bits. 0 = no operation. 1 = Set direction bit." "0: no operation,1: Set direction bit"
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wgroup.long 0x2400++0x3
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line.long 0x0 "DIRCLR0,Clear pin direction bits"
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bitfld.long 0x0 21. "DIRCLRP_PIO21,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 20. "DIRCLRP_PIO20,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 19. "DIRCLRP_PIO19,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 18. "DIRCLRP_PIO18,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 17. "DIRCLRP_PIO17,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 16. "DIRCLRP_PIO16,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 15. "DIRCLRP_PIO15,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 14. "DIRCLRP_PIO14,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 13. "DIRCLRP_PIO13,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 12. "DIRCLRP_PIO12,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 11. "DIRCLRP_PIO11,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 10. "DIRCLRP_PIO10,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 9. "DIRCLRP_PIO9,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 8. "DIRCLRP_PIO8,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 7. "DIRCLRP_PIO7,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 6. "DIRCLRP_PIO6,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 5. "DIRCLRP_PIO5,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 4. "DIRCLRP_PIO4,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 3. "DIRCLRP_PIO3,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 2. "DIRCLRP_PIO2,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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newline
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bitfld.long 0x0 1. "DIRCLRP_PIO1,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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bitfld.long 0x0 0. "DIRCLRP_PIO0,Clear direction bits. 0 = no operation. 1 = Clear direction bit." "0: no operation,1: Clear direction bit"
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wgroup.long 0x2480++0x3
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line.long 0x0 "DIRNOT0,Toggle pin direction bits"
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bitfld.long 0x0 21. "DIRNOTP_PIO21,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 20. "DIRNOTP_PIO20,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 19. "DIRNOTP_PIO19,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 18. "DIRNOTP_PIO18,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 17. "DIRNOTP_PIO17,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 16. "DIRNOTP_PIO16,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 15. "DIRNOTP_PIO15,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 14. "DIRNOTP_PIO14,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 13. "DIRNOTP_PIO13,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 12. "DIRNOTP_PIO12,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 11. "DIRNOTP_PIO11,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 10. "DIRNOTP_PIO10,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 9. "DIRNOTP_PIO9,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 8. "DIRNOTP_PIO8,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 7. "DIRNOTP_PIO7,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 6. "DIRNOTP_PIO6,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 5. "DIRNOTP_PIO5,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 4. "DIRNOTP_PIO4,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 3. "DIRNOTP_PIO3,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 2. "DIRNOTP_PIO2,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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newline
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bitfld.long 0x0 1. "DIRNOTP_PIO1,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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bitfld.long 0x0 0. "DIRNOTP_PIO0,Toggle direction bits. 0 = no operation. 1 = Toggle direction bit." "0: no operation,1: Toggle direction bit"
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tree.end
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tree "I2C (Inter-Integrated Circuit)"
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base ad:0x0
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tree "I2C0"
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base ad:0x40003000
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group.long 0x0++0xB
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line.long 0x0 "CFG,Configuration for shared functions."
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bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter as well as the timing for certain I2C signalling enabling High-speed mode applies to all functions: master slave and monitor." "0,1"
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bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0,1"
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newline
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bitfld.long 0x0 3. "TIMEOUT,I2C bus Time-out Enable. When disabled the time-out function is internally reset." "0,1"
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bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled configurations settings for the Monitor function are not changed but the Monitor function is internally reset." "0,1"
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newline
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled configurations settings for the Slave function are not changed but the Slave function is internally reset." "0,1"
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bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled configurations settings for the Master function are not changed but the Master function is internally reset." "0,1"
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line.long 0x4 "STAT,Status register for Master. Slave and Monitor functions."
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bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 0: No time-out. SCL low time has not caused a time-out. 1: Time-out. SCL.." "0: No time-out,1: Time-out"
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bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start Stop and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out,1: Event time-out"
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newline
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle,1: Idle"
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rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 0: Inactive. The Monitor function.." "0: Inactive,1: Active"
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newline
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag. 0: No overrun. Monitor data has not overrun 1: Overrun. A monitor data overrun has occurred. This can only happen when Monitor clock stretching is not enabled via the MOCCLKSTR bit in the CFG register. Writing 1 to this bit.." "0: No overrun,1: Overrun"
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rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read. 0: No data. The Monitor function does not currently have data available. 1: Data waiting. The Monitor function has data waiting to be read." "0: No data,1: Data waiting"
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newline
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 0: Not deselected. The slave function has not become deslected. This does not mean that it is.." "0: Not deselected,1: Deselected"
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bitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected,1: Selected"
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newline
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers and provides an identification of the.." "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
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rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: stretching,?"
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newline
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 393 for state values and actions. Remark: note that the occurrence of some states and how they are.." "0: Slave address,1: Slave receive,2: Slave transmit,?"
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rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress,1: Pending"
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newline
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 0: No start/stop Error has occurred. 1: The master function has experienced a.." "0: No start/stop Error has occurred,1: The master function has experienced a Start/Stop.."
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bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 0: No Arbitration Loss has occurred. 1: Arbitration Loss. The mater function has.." "0: No Arbitration Loss has occurred,1: Arbitration Loss"
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newline
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle,1: Receive ready,2: Transmit ready,3: NACK address,4: NACK data,?,?,?"
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rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress,1: Pending"
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line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
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bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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wgroup.long 0xC++0x3
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line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Writing a 1 to this bit clears the corresponding bit in the INTENSET register. disabling that interrupt. This is a Write-only register."
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bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
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bitfld.long 0x0 24. "EVCLRTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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newline
|
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
|
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bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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newline
|
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
|
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bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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newline
|
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
|
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bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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newline
|
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
|
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bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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newline
|
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bitfld.long 0x0 0. "MSTPCLRDINGCLR,Master Pending interrupt clear." "0,1"
|
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group.long 0x10++0x7
|
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line.long 0x0 "TIMEOUT,Time-out value register."
|
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hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks as defined by the CLKDIV register. To change this value while I2C is in operation disable all time-outs write a new value to TIMEOUT then re-enable.."
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hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
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line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register and controls some timing of the Slave function."
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hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the I2C clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. I2C block should be configured for 8MHz clock this will limit SCL master clock range from 444kHz to 2MHz. 0x0000 = FCLK is.."
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rgroup.long 0x18++0x3
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line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave and Monitor functions."
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bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out interrupt." "0,1"
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bitfld.long 0x0 24. "EVTTIMEOUT,Event time-out interrupt." "0,1"
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newline
|
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle interrupt." "0,1"
|
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bitfld.long 0x0 17. "MONOV,Monitor Overrun interrupt." "0,1"
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newline
|
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bitfld.long 0x0 16. "MONRDY,Monitor data Ready interrupt." "0,1"
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bitfld.long 0x0 15. "SLVDESEL,Slave Deselect interrupt." "0,1"
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newline
|
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching interrupt." "0,1"
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bitfld.long 0x0 8. "SLVPENDING,Slave Pending interrupt." "0,1"
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newline
|
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error interrupt." "0,1"
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bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss interrupt." "0,1"
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newline
|
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bitfld.long 0x0 0. "MSTPENDING,Master Pending interrupt." "0,1"
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group.long 0x20++0xB
|
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line.long 0x0 "MSTCTL,Master control register."
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bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start address Stop and address match must always be done with software typically via an interrupt. Address acknowledgement must also be.." "0: Disable,1: Enable"
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bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only. 0: No effect. 1. Stop. A stop will be generated on the I2C bus at the next allowed time preceded by a NACK to the slave if the master is receiving data from the salve (Master Receiver mode)." "0: No effect,?"
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newline
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only. 0: No effect. 1. Start. A start will be generated on the I2C bus at the next allowed time." "0: No effect,?"
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bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only. 0: No effect. 1: Continue. Informs the Master function to continue to the next operation. This must be done after writing transmit data reading received data or other housekeeping related to the next.." "0: No effect,1: Continue"
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line.long 0x4 "MSTTIME,Master timing configuration."
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bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus.." "0,1,2,3,4,5,6,7"
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line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
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hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
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group.long 0x40++0x7
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line.long 0x0 "SLVCTL,Slave control register."
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bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
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bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal,1: A header with matching SLVADR0 and matching.."
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newline
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable. 0: Slave DMA enable. 1: Enabled. DMA requests are issued for I2C slave data transmission and reception." "0: Slave DMA enable,1: Enabled"
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bitfld.long 0x0 1. "SLVNACK,Slave NACK. 0: No effect. 1: NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode)." "0: No effect,1: NACK"
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newline
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue. 0: no effect 1: Continue. Informs the Slave function to continue to the next operation by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data reading recevied data or any other.." "0: no effect,1: Continue"
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line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
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hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x48)++0x3
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line.long 0x0 "SLVADR[$1],Slave address 0."
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bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD allows software to ignore I2C traffic while handling previous I2C data or other operations. 0: Normal operation matching I2C addresses are not ignored. 1:.." "0: Normal operation,1: Automatic-only mode"
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hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled. The compare can be affected by the setting of the SLVQUAL0 register."
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newline
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bitfld.long 0x0 0. "SADISABLE,Slave Address 0 Disable. 0: Slave Address 0 is enabled. 1: Slave Address 0 is ignored." "0: Slave Address 0 is enabled,1: Slave Address 0 is ignored"
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repeat.end
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group.long 0x58++0x3
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line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
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hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is assuming that it is enabled. If QUALMODE0 = 0 any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
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bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0. 0: Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 1: Extend. The SLVQAL0 field is used to extend address 0 matching in a range of addresses." "0: Mask,1: Extend"
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rgroup.long 0x80++0x3
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line.long 0x0 "MONRXDAT,Monitor receiver data register."
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bitfld.long 0x0 10. "MONNACK,Monitor Received NACK. 0: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave recevier. 1: Not Acknowledged. The data currently being provided by the Monitor function was not.." "0: Acknowledged,1: Not Acknowledged"
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bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start. 0: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 1: Repeate start detected. The Monitor function has detected a Repeated Start event on the I2C bus." "0: No repeated start detected,1: Repeate start detected"
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newline
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start. 0: No start detected. The monitor function has not detected a Start event on the I2C bus. 1: Start detected. The Monitor function has detected a Start event on the I2C bus." "0: No start detected,1: Start detected"
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hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
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rgroup.long 0xFFC++0x3
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line.long 0x0 "ID,I2C Module Identifier"
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hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
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hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. there may be software incompatability between major revisions."
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newline
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hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
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hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
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tree.end
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tree "I2C1"
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base ad:0x40004000
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group.long 0x0++0xB
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line.long 0x0 "CFG,Configuration for shared functions."
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bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter as well as the timing for certain I2C signalling enabling High-speed mode applies to all functions: master slave and monitor." "0,1"
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bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0,1"
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newline
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bitfld.long 0x0 3. "TIMEOUT,I2C bus Time-out Enable. When disabled the time-out function is internally reset." "0,1"
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bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled configurations settings for the Monitor function are not changed but the Monitor function is internally reset." "0,1"
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newline
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled configurations settings for the Slave function are not changed but the Slave function is internally reset." "0,1"
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bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled configurations settings for the Master function are not changed but the Master function is internally reset." "0,1"
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line.long 0x4 "STAT,Status register for Master. Slave and Monitor functions."
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bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 0: No time-out. SCL low time has not caused a time-out. 1: Time-out. SCL.." "0: No time-out,1: Time-out"
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bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start Stop and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out,1: Event time-out"
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newline
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle,1: Idle"
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rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 0: Inactive. The Monitor function.." "0: Inactive,1: Active"
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newline
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag. 0: No overrun. Monitor data has not overrun 1: Overrun. A monitor data overrun has occurred. This can only happen when Monitor clock stretching is not enabled via the MOCCLKSTR bit in the CFG register. Writing 1 to this bit.." "0: No overrun,1: Overrun"
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rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read. 0: No data. The Monitor function does not currently have data available. 1: Data waiting. The Monitor function has data waiting to be read." "0: No data,1: Data waiting"
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newline
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 0: Not deselected. The slave function has not become deslected. This does not mean that it is.." "0: Not deselected,1: Deselected"
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bitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected,1: Selected"
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newline
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers and provides an identification of the.." "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
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rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: stretching,?"
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newline
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 393 for state values and actions. Remark: note that the occurrence of some states and how they are.." "0: Slave address,1: Slave receive,2: Slave transmit,?"
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rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress,1: Pending"
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newline
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 0: No start/stop Error has occurred. 1: The master function has experienced a.." "0: No start/stop Error has occurred,1: The master function has experienced a Start/Stop.."
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bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 0: No Arbitration Loss has occurred. 1: Arbitration Loss. The mater function has.." "0: No Arbitration Loss has occurred,1: Arbitration Loss"
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newline
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle,1: Receive ready,2: Transmit ready,3: NACK address,4: NACK data,?,?,?"
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rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress,1: Pending"
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line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
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bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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newline
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable. 0: interrupt is disabled. 1: interrupt is enabled." "0: interrupt is disabled,1: interrupt is enabled"
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wgroup.long 0xC++0x3
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line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Writing a 1 to this bit clears the corresponding bit in the INTENSET register. disabling that interrupt. This is a Write-only register."
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bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
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bitfld.long 0x0 24. "EVCLRTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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newline
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
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bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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newline
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
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bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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newline
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
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bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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newline
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
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bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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newline
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bitfld.long 0x0 0. "MSTPCLRDINGCLR,Master Pending interrupt clear." "0,1"
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group.long 0x10++0x7
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line.long 0x0 "TIMEOUT,Time-out value register."
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hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks as defined by the CLKDIV register. To change this value while I2C is in operation disable all time-outs write a new value to TIMEOUT then re-enable.."
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hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
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line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register and controls some timing of the Slave function."
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hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the I2C clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. I2C block should be configured for 8MHz clock this will limit SCL master clock range from 444kHz to 2MHz. 0x0000 = FCLK is.."
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rgroup.long 0x18++0x3
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line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave and Monitor functions."
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bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out interrupt." "0,1"
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bitfld.long 0x0 24. "EVTTIMEOUT,Event time-out interrupt." "0,1"
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newline
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle interrupt." "0,1"
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bitfld.long 0x0 17. "MONOV,Monitor Overrun interrupt." "0,1"
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newline
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bitfld.long 0x0 16. "MONRDY,Monitor data Ready interrupt." "0,1"
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bitfld.long 0x0 15. "SLVDESEL,Slave Deselect interrupt." "0,1"
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newline
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching interrupt." "0,1"
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bitfld.long 0x0 8. "SLVPENDING,Slave Pending interrupt." "0,1"
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newline
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error interrupt." "0,1"
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bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss interrupt." "0,1"
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newline
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bitfld.long 0x0 0. "MSTPENDING,Master Pending interrupt." "0,1"
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group.long 0x20++0xB
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line.long 0x0 "MSTCTL,Master control register."
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bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start address Stop and address match must always be done with software typically via an interrupt. Address acknowledgement must also be.." "0: Disable,1: Enable"
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bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only. 0: No effect. 1. Stop. A stop will be generated on the I2C bus at the next allowed time preceded by a NACK to the slave if the master is receiving data from the salve (Master Receiver mode)." "0: No effect,?"
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newline
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only. 0: No effect. 1. Start. A start will be generated on the I2C bus at the next allowed time." "0: No effect,?"
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bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only. 0: No effect. 1: Continue. Informs the Master function to continue to the next operation. This must be done after writing transmit data reading received data or other housekeeping related to the next.." "0: No effect,1: Continue"
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line.long 0x4 "MSTTIME,Master timing configuration."
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bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus.." "0,1,2,3,4,5,6,7"
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line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
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hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
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group.long 0x40++0x7
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line.long 0x0 "SLVCTL,Slave control register."
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bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
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bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal,1: A header with matching SLVADR0 and matching.."
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newline
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable. 0: Slave DMA enable. 1: Enabled. DMA requests are issued for I2C slave data transmission and reception." "0: Slave DMA enable,1: Enabled"
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bitfld.long 0x0 1. "SLVNACK,Slave NACK. 0: No effect. 1: NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode)." "0: No effect,1: NACK"
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newline
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue. 0: no effect 1: Continue. Informs the Slave function to continue to the next operation by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data reading recevied data or any other.." "0: no effect,1: Continue"
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line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
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hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x48)++0x3
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line.long 0x0 "SLVADR[$1],Slave address 0."
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bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD allows software to ignore I2C traffic while handling previous I2C data or other operations. 0: Normal operation matching I2C addresses are not ignored. 1:.." "0: Normal operation,1: Automatic-only mode"
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hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled. The compare can be affected by the setting of the SLVQUAL0 register."
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newline
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bitfld.long 0x0 0. "SADISABLE,Slave Address 0 Disable. 0: Slave Address 0 is enabled. 1: Slave Address 0 is ignored." "0: Slave Address 0 is enabled,1: Slave Address 0 is ignored"
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repeat.end
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group.long 0x58++0x3
|
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line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
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hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is assuming that it is enabled. If QUALMODE0 = 0 any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
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bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0. 0: Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 1: Extend. The SLVQAL0 field is used to extend address 0 matching in a range of addresses." "0: Mask,1: Extend"
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rgroup.long 0x80++0x3
|
|
line.long 0x0 "MONRXDAT,Monitor receiver data register."
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|
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK. 0: Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave recevier. 1: Not Acknowledged. The data currently being provided by the Monitor function was not.." "0: Acknowledged,1: Not Acknowledged"
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bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start. 0: No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 1: Repeate start detected. The Monitor function has detected a Repeated Start event on the I2C bus." "0: No repeated start detected,1: Repeate start detected"
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newline
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start. 0: No start detected. The monitor function has not detected a Start event on the I2C bus. 1: Start detected. The Monitor function has detected a Start event on the I2C bus." "0: No start detected,1: Start detected"
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hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
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rgroup.long 0xFFC++0x3
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line.long 0x0 "ID,I2C Module Identifier"
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hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
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|
hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. there may be software incompatability between major revisions."
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|
newline
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hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
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hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
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tree.end
|
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tree.end
|
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tree "INPUTMUX (Input Multiplexing)"
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base ad:0x4000E000
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repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0xC0)++0x3
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line.long 0x0 "PINTSEL[$1],Pin interrupt select register"
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hexmask.long.byte 0x0 0.--4. 1. "INTPIN,Pin number select for pin interrupt or pattern match engine input."
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repeat.end
|
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repeat 19. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0xE0)++0x3
|
|
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel. Configurable for each of the DMA channels."
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hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 17). 0: ADC0 Sequence A interrupt; 1: Reserved; 2: Timer CT32B0 Match 0; 3: Timer CT32B0 Match 1; 4: Timer CT32B1 Match 0; 5: Timer CT32B1 Match 1; 6: Pin interrupt 0; 7: Pin interrupt.."
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repeat.end
|
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2+0x160)++0x3
|
|
line.long 0x0 "DMA_OTRIG_INMUX[$1],DMA output trigger selection to become an input to the DMA trigger mux. Four selections can be made."
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hexmask.long.byte 0x0 0.--4. 1. "INP,DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19)."
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repeat.end
|
|
group.long 0x180++0x7
|
|
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
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|
hexmask.long.byte 0x0 0.--3. 1. "CLKIN,Clock source number (decimal value) for frequency measure function ref clock: 0: CLK_IN (must be enabled in functional mux); 1: XTAL 32 MHz (must be enabled in clock_ctrl); 2: FRO 1 MHz (must be enabled in clock_ctrl); 3: 32 kHz oscillator (either.."
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|
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
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hexmask.long.byte 0x4 0.--3. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0: CLK_IN (must be enabled in functional mux); 1: XTAL 32 MHz (must be enabled in clock_ctrl); 2: FRO 1 MHz (must be enabled in clock_ctrl); 3: 32 kHz oscillator.."
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|
tree.end
|
|
tree "IOCON (I/O Pin Configuration)"
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|
base ad:0x4000F000
|
|
group.long 0x0++0x57
|
|
line.long 0x0 "PIO0_0,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0x0 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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|
bitfld.long 0x0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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|
newline
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bitfld.long 0x0 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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|
bitfld.long 0x0 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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|
newline
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|
bitfld.long 0x0 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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|
bitfld.long 0x0 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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|
newline
|
|
bitfld.long 0x0 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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|
bitfld.long 0x0 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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|
newline
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bitfld.long 0x0 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x4 "PIO0_1,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0x4 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
|
|
bitfld.long 0x4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
|
|
newline
|
|
bitfld.long 0x4 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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|
bitfld.long 0x4 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
|
|
newline
|
|
bitfld.long 0x4 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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|
bitfld.long 0x4 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
|
|
newline
|
|
bitfld.long 0x4 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
|
|
bitfld.long 0x4 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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|
newline
|
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bitfld.long 0x4 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x8 "PIO0_2,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0x8 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
|
|
bitfld.long 0x8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
|
|
newline
|
|
bitfld.long 0x8 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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|
bitfld.long 0x8 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
|
|
newline
|
|
bitfld.long 0x8 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
|
|
bitfld.long 0x8 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
|
|
newline
|
|
bitfld.long 0x8 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
|
|
bitfld.long 0x8 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
|
|
newline
|
|
bitfld.long 0x8 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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|
line.long 0xC "PIO0_3,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0xC 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
|
|
bitfld.long 0xC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
|
|
newline
|
|
bitfld.long 0xC 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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|
bitfld.long 0xC 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
|
|
newline
|
|
bitfld.long 0xC 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
|
|
bitfld.long 0xC 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
|
|
newline
|
|
bitfld.long 0xC 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
|
|
bitfld.long 0xC 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
|
|
newline
|
|
bitfld.long 0xC 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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|
line.long 0x10 "PIO0_4,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0x10 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
|
|
bitfld.long 0x10 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
|
|
newline
|
|
bitfld.long 0x10 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
|
|
bitfld.long 0x10 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
|
|
newline
|
|
bitfld.long 0x10 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
|
|
bitfld.long 0x10 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
|
|
newline
|
|
bitfld.long 0x10 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
|
|
bitfld.long 0x10 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
|
|
newline
|
|
bitfld.long 0x10 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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|
line.long 0x14 "PIO0_5,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0x14 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
|
|
bitfld.long 0x14 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
|
|
newline
|
|
bitfld.long 0x14 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
|
|
bitfld.long 0x14 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
|
|
newline
|
|
bitfld.long 0x14 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
|
|
bitfld.long 0x14 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
|
|
newline
|
|
bitfld.long 0x14 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
|
|
bitfld.long 0x14 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
|
|
newline
|
|
bitfld.long 0x14 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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|
line.long 0x18 "PIO0_6,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0x18 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
|
|
bitfld.long 0x18 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
|
|
newline
|
|
bitfld.long 0x18 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
|
|
bitfld.long 0x18 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
|
|
newline
|
|
bitfld.long 0x18 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
|
|
bitfld.long 0x18 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
|
|
newline
|
|
bitfld.long 0x18 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
|
|
bitfld.long 0x18 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
|
|
newline
|
|
bitfld.long 0x18 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
|
|
line.long 0x1C "PIO0_7,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0x1C 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
|
|
bitfld.long 0x1C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
|
|
newline
|
|
bitfld.long 0x1C 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
|
|
bitfld.long 0x1C 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
|
|
newline
|
|
bitfld.long 0x1C 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
|
|
bitfld.long 0x1C 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
|
|
newline
|
|
bitfld.long 0x1C 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
|
|
bitfld.long 0x1C 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
|
|
newline
|
|
bitfld.long 0x1C 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
|
|
line.long 0x20 "PIO0_8,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
|
|
bitfld.long 0x20 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
|
|
bitfld.long 0x20 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
|
|
newline
|
|
bitfld.long 0x20 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
|
|
bitfld.long 0x20 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
|
|
newline
|
|
bitfld.long 0x20 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
|
|
bitfld.long 0x20 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
|
|
newline
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bitfld.long 0x20 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x20 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x20 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x24 "PIO0_9,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on whether.."
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bitfld.long 0x24 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x24 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x24 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x24 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x24 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x24 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x24 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x24 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x24 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x28 "PIO0_10,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x28 12. "IO_CLAMP,Assert to freeze the IO. Also needs SYSCON:RETENTIONCTRL set as well. Useful in power down mode. This mode is held through power down cycle. Before releasing this mode on a wake-up ensure the IO is set to the required direction and value using.." "0: IO_CLAMP is disabled.,1: IO_CLAMP is enabled."
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bitfld.long 0x28 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x28 9. "FSEL,Control Input Glitch Filter." "0: Noise pulses below approximately 50ns are..,1: Noise pulses below approximately 10 ns are.."
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bitfld.long 0x28 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x28 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x28 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x28 5. "EHS,Speed selection. When IO is in GPIO mode set 1 for high speed GPIO 0 for low speed GPIO. For IIC mode this bit has no effect and the IO is always in low speed." "0: low speed for GPIO mode or i2c mode.,1: High speed for GPIO mode."
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bitfld.long 0x28 4. "ECS,Pull-up current source enable when set. When IO is is IIC mode (EGP=0) and ECS is low the IO cell is an open drain cell." "0: Pull-up current source disabled.,1: Pull-up current source enabled."
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newline
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bitfld.long 0x28 3. "EGP,GPIO Mode of IO Cell." "0: IIC mode.,1: GPIO mode."
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bitfld.long 0x28 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x2C "PIO0_11,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x2C 12. "IO_CLAMP,Assert to freeze the IO. Also needs SYSCON:RETENTIONCTRL set as well. Useful in power down mode. This mode is held through power down cycle. Before releasing this mode on a wake-up ensure the IO is set to the required direction and value using.." "0: IO_CLAMP is disabled.,1: IO_CLAMP is enabled."
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bitfld.long 0x2C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x2C 9. "FSEL,Control Input Glitch Filter." "0: Noise pulses below approximately 50ns are..,1: Noise pulses below approximately 10 ns are.."
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bitfld.long 0x2C 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x2C 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x2C 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x2C 5. "EHS,Speed selection. When IO is in GPIO mode set 1 for high speed GPIO 0 for low speed GPIO. For IIC mode this bit has no effect and the IO is always in low speed." "0: low speed for GPIO mode or i2c mode.,1: High speed for GPIO mode."
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bitfld.long 0x2C 4. "ECS,Pull-up current source enable when set. When IO is is IIC mode (EGP=0) and ECS is low the IO cell is an open drain cell." "0: Pull-up current source disabled.,1: Pull-up current source enabled."
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newline
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bitfld.long 0x2C 3. "EGP,GPIO Mode of IO Cell." "0: IIC mode.,1: GPIO mode."
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bitfld.long 0x2C 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x30 "PIO0_12,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x30 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x30 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x30 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x30 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x30 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x30 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x30 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x30 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x30 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x34 "PIO0_13,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x34 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x34 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x34 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x34 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x34 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x34 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x34 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x34 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x34 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x38 "PIO0_14,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x38 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x38 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x38 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x38 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x38 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x38 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x38 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x38 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x38 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x3C "PIO0_15,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x3C 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x3C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x3C 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x3C 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x3C 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x3C 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x3C 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x3C 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x3C 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x40 "PIO0_16,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x40 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x40 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x40 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x40 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x40 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x40 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x40 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x40 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x40 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x44 "PIO0_17,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x44 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x44 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x44 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x44 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x44 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x44 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x44 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x44 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x44 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x48 "PIO0_18,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x48 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x48 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x48 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x48 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x48 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x48 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x48 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x48 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x48 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x4C "PIO0_19,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x4C 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x4C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x4C 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x4C 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x4C 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x4C 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x4C 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x4C 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x4C 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x50 "PIO0_20,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x50 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x50 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x50 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x50 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x50 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x50 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x50 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x50 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x50 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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line.long 0x54 "PIO0_21,Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use a different IO cell type to the other PIO pins and so there are some differences in the bit field descriptions of the PIO register for these Ios. Reset values vary depending on.."
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bitfld.long 0x54 11. "SSEL,IO Clamping Function" "0: This bit controls the IO clamping function is..,1: This bit controls the IO clamping function is.."
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bitfld.long 0x54 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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newline
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bitfld.long 0x54 9. "SLEW1,Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1 SLEW0] the quicker the slew rate." "0: Driver slew1 rate is disabled.,1: Driver slew1 rate is enabled."
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bitfld.long 0x54 8. "FILTEROFF,Controls Input Glitch Filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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newline
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bitfld.long 0x54 7. "DIGIMODE,Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode the receiver path in the IO cell is disabled. In this mode it is essential that the digital function (e.g. GPIO) is not configured as an output. Otherwise it may.." "0: Analog mode digital input is disabled.,1: Digital mode digital input is enabled."
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bitfld.long 0x54 6. "INVERT,Input Polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input function is inverted."
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newline
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bitfld.long 0x54 5. "SLEW0,This bit field is used in combination with SLEW1. The higher [SLEW1 SLEW0] the quicker the IO cell slew rate." "0: Driver slew0 rate is disabled.,1: Driver slew0 rate is enabled."
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bitfld.long 0x54 3.--4. "MODE,Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor.." "0: Pull-up,1: Repeater mode,2: Plain Input 0x3 : Pull-down,3: Pull-down. Pull-down resistor enabled."
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newline
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bitfld.long 0x54 0.--2. "FUNC,Select digital function assigned to this pin." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
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tree.end
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tree "ISO7816 (ISO 7816 Smart Card Interface)"
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base ad:0x40006000
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group.long 0x0++0x37
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line.long 0x0 "SSR,Slot Select Register"
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bitfld.long 0x0 1. "SEQ_EN,Set this bit to enable the sequencer. If this field is 0b the sequencer will not respond to the Start control bit." "0,1"
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bitfld.long 0x0 0. "SOFTRESETN,When set to logic 0 this bit resets the whole Contact UART (software reset) sets to logic 1 automatically by hardware after after one clock cycle if slot 1 is not activated else after one clock cycle after slot 1 has been automatically.." "0,1"
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line.long 0x4 "PDR1_LSB,Programmable Divider Register (LSB) slot 1. Least significant byte of a 16-bit counter defining the ETU. The ETU counter counts a number of cycles of the Contact Interface clock. this defines the ETU. The minimum acceptable value is 0001 0000b."
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hexmask.long 0x4 0.--31. 1. "PDR1_LSB,Programmable Divider Register (LSB) slot 1. Least significant byte of a 16-bit counter defining the ETU. The ETU counter counts a number of cycles of the Contact Interface clock this defines the ETU. The minimum acceptable value is 0001 0000b."
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line.long 0x8 "PDR1_MSB,Programmable Divider Register (MSB) slot 1. Most significant byte of a 16-bit counter defining the ETU. The ETU counter counts a number of cycles of the Contact Interface clock. this defines the ETU"
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hexmask.long 0x8 0.--31. 1. "PDR1_MSB,Programmable Divider Register (MSB) slot 1. Most significant byte of a 16-bit counter defining the ETU. The ETU counter counts a number of cycles of the Contact Interface clock this defines the ETU"
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line.long 0xC "FCR,FIFO Control Register"
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bitfld.long 0xC 5.--7. "PEC,Parity Error Count [For protocol T = 0] Set the number of allowed repetitions in reception or transmission mode before setting pe in ct_usr1_reg. The value 000 indicates that if only one parity error has occurred bit pe is set at logic 1; the value.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 0.--4. 1. "FTC,FIFO Threshold Configuration: Define the number of received or transmitted characters in the FIFO triggering the ft bit in USR1. The FIFO depth is 32 bytes. In reception mode it enables to know that a number equals to ftc(4:0) + 1 bytes have been.."
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line.long 0x10 "GTR1,Guard Time Register slot 1. Value used by the Contact UART notably in transmission mode. The Contact UART will wait this number of ETUs before transmitting the character. In protocol T=1. gtr = FFh means operation at 11 ETUs. In protocol T=0. gtr =.."
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hexmask.long 0x10 0.--31. 1. "GTR1,Guard Time Register slot 1. Value used by the Contact UART notably in transmission mode. The Contact UART will wait this number of ETUs before transmitting the character. In protocol T=1 gtr = FFh means operation at 11 ETUs. In protocol T=0 gtr =.."
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line.long 0x14 "UCR11,UART Configuration Register 1 slot 1"
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bitfld.long 0x14 5. "FIP,Force Inverse Parity: If bit FIP is set to logic 1 the Contact UART will NAK a correctly received character and will transmit characters with wrong parity bits." "0,1"
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bitfld.long 0x14 4. "FC,Described in a separated document." "0,1"
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bitfld.long 0x14 3. "PROT,PROTocol: Selects the protocol: logic 1 means T=1 and logic 0 T=0." "0,1"
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bitfld.long 0x14 2. "T_R,Transmit/Receive: Defines the mode: logic 1 means transmission and logic 0 reception. Bit T/R is set by software for transmission mode. Bit T/R is automatically reset to logic 0 by hardware if bit LCT has been used before transmitting the last.." "0,1"
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newline
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bitfld.long 0x14 1. "LCT,Last Character to Transmit: Bit LCT is set to logic 1 by software before writing the last character to be transmitted in register ct_utr_reg. It allows automatic change to reception mode. It is reset to logic 0 by hardware at the end of a successful.." "0,1"
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bitfld.long 0x14 0. "CONV,CONVention: Bit CONV is set to logic 1 if the convention is direct. Bit CONV is either automatically written by hardware according to the convention detected during ATR or by software if the bit AUTOCONV in register ct_ucr1_reg is set to logic 1." "0,1"
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line.long 0x18 "UCR21,UART Configuration Register 2 slot 1"
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bitfld.long 0x18 7. "WRDACC,FIFO WoRD ACCess: When set to logic 1 the FIFO supports word (4 bytes) access (read and write) access failure is indicated by bit wrdaccerr in register USR2. When set to logic 0 the FIFO supports byte access (read and write)." "0,1"
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bitfld.long 0x18 6. "FIFOFLUSH,FIFO flush: When set to logic 1 the FIFO is flushed whatever the mode (reception or transmission) is. It can be used before any reception or transmission of characters but not while receiving or transmitting a character. It is reset to logic 0.." "0,1"
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bitfld.long 0x18 4. "DISATRCOUNTER,DISable ATR counter: [For Slot 1 only] When set to logic 1 the bits EARLY and MUTE in register ct_usr1_reg will not generate interrupt. This bit should be set before activating." "0,1"
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bitfld.long 0x18 3. "DISPE,DISable Parity Error interrupt bit: When set to logic 1 the parity is not checked in both reception and transmission modes the bit pe in register ct_usr1_reg will not generate interrupt." "0,1"
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newline
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bitfld.long 0x18 2. "DISFT,DISable Fifo Threshold interrupt bit: When set to logic 1 the bit ft in register ct_usr1_reg will not generate interrupt." "0,1"
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bitfld.long 0x18 1. "MANBGT,MANual BGT: When set to logic 1 BGT is managed by software else by hardware." "0,1"
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bitfld.long 0x18 0. "AUTOCONVN,AUTOmatically detected CONVention: If bit AUTOCONV = 1 then the convention is set by software using bit CONV in register ct_ucr1_reg. If the bit is reset to logic 0 then the configuration is automatically detected on the first received.." "0,1"
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line.long 0x1C "CCR1,Clock Configuration Register slot 1"
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bitfld.long 0x1C 5. "SHL,Stop HIGH or LOW: - Slot 1: If bits SAN = 0 and CST = 1 then the clock is stopped at LOW level. If bit SHL = 0 and at HIGH level if bit SHL = 1. I+I10f bit SAN = 1 then contact CLK is the copy of the value of bit SHL." "?,1: If bits SAN = 0 and CST = 1"
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bitfld.long 0x1C 4. "CST,Clock STop: [For Slot 1]: In the case of an asynchronous card bit CST defines whether the clock to the card is stopped or not; if bit CST is reset to logic 0 then the clock is determined by bits ACC0 ACC1 and ACC2. [For Slot AUX]+I40: This bit is.." "0,1"
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bitfld.long 0x1C 3. "SAN,Synchronous/Asynchronous Card: [For Slot 1]: When set to logic 1 the Contact UART supports synchronous card. The Contact UART is then bypassed only bit 0 of registers ct_urr_reg and ct_utr_reg is connected to pin I/O. In this case the card clock.." "0,1"
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bitfld.long 0x1C 0.--2. "ACC,Asynchronous Card Clock: Defines the card clock frequency: 000: card clock frequency = fclk_ip; 001: card clock frequency = fclk_ip /2; 010: card clock frequency = fclk_ip /3; 011: card clock frequency = fclk_ip /4; 100: card clock frequency =.." "0: card clock frequency = fclk_ip;,1: card clock frequency = fclk_ip /2;,?,?,?,?,?,?"
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line.long 0x20 "PCR,Power Control Register"
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hexmask.long 0x20 0.--31. 1. "PCR,Power Control Register"
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line.long 0x24 "ECR,Early answer Counter register"
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hexmask.long 0x24 0.--31. 1. "ECR,Early answer Counter register"
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line.long 0x28 "MCRL_LSB,Mute card Counter RST Low register (LSB)"
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hexmask.long 0x28 0.--31. 1. "MCRL_LSB,Mute card Counter RST Low register (LSB)"
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line.long 0x2C "MCRL_MSB,Mute card Counter RST Low register (MSB)"
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hexmask.long 0x2C 0.--31. 1. "MCRL_MSB,Mute card Counter RST Low register (MSB)"
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line.long 0x30 "MCRH_LSB,Mute card Counter RST High register (LSB)"
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hexmask.long 0x30 0.--31. 1. "MCRH_LSB,Mute card Counter RST High register (LSB)"
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line.long 0x34 "MCRH_MSB,Mute card Counter RST High register (MSB)"
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hexmask.long 0x34 0.--31. 1. "MCRH_MSB,Mute card Counter RST High register (MSB)"
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group.long 0x3C++0x3
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line.long 0x0 "URR_UTR,UART Receive Register / UART Transmit Register"
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hexmask.long 0x0 0.--31. 1. "URR_UTR,UART Receive Register / UART Transmit Register"
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wgroup.long 0x4C++0xB
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line.long 0x0 "TOR1,Time-Out Register 1"
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hexmask.long 0x0 0.--31. 1. "TOR1,Time-Out Register 1"
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line.long 0x4 "TOR2,Time-Out Register 2"
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hexmask.long 0x4 0.--31. 1. "TOR2,Time-Out Register 2"
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line.long 0x8 "TOR3,Time-Out Register 3"
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hexmask.long 0x8 0.--31. 1. "TOR3,Time-Out Register 3"
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group.long 0x58++0x3
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line.long 0x0 "TOC,Time-Out Configuration register"
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hexmask.long 0x0 0.--31. 1. "TOC,Time-Out Configuration register"
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rgroup.long 0x5C++0xF
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line.long 0x0 "FSR,FIFO Status Register"
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hexmask.long 0x0 0.--31. 1. "FSR,FIFO Status Register"
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line.long 0x4 "MSR,Mixed Status Register"
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hexmask.long 0x4 0.--31. 1. "MSR,Mixed Status Register"
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line.long 0x8 "USR1,UART Status Register 1"
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hexmask.long 0x8 0.--31. 1. "USR1,UART Status Register 1"
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line.long 0xC "USR2,UART Status Register 2"
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hexmask.long 0xC 0.--31. 1. "USR2,UART Status Register 2"
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tree.end
|
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tree "OTPC (One Time Programmable Memory)"
|
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base ad:0x40002000
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group.long 0x0++0x3
|
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line.long 0x0 "ADDR,Address register for reading the E-Fuse OTP"
|
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hexmask.long.word 0x0 0.--11. 1. "ADDR,Address of OTP value to be read"
|
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wgroup.long 0x8++0x3
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line.long 0x0 "READ,Register for reading the E-Fuse OTP."
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hexmask.long.word 0x0 16.--31. 1. "SEQ,Read unlock sequence: only when 0x7F12 is written is the Read command accepted."
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bitfld.long 0x0 0. "READ,When 1 is written the OTP is read. Note this operation only occurs if correct SEQ value is also written." "0,1"
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rgroup.long 0x14++0x3
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line.long 0x0 "RDATA,Register for the OTP read back data."
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bitfld.long 0x0 31. "VALID,Valid bit. This bit will be cleared when a Read command has been given and will be set when the sequencer has successfully captured the E-Fuse OTP data." "0,1"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Read back data from the E-Fuse OTP."
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tree.end
|
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tree "PINT (Pin Interrupt and Pattern Match)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x7
|
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line.long 0x0 "ISEL,Pin Interrupt Mode register (only interrupts 0 to 3 supported to processor)"
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bitfld.long 0x0 7. "PMODE_PIN7,Selects the interrupt mode for pin interrupt 7 (selected in PINTSEL7). [Note interrupt not supported to processor] 0: Edge sensitive. 1: Level sensitive." "0: Edge sensitive,1: Level sensitive"
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bitfld.long 0x0 6. "PMODE_PIN6,Selects the interrupt mode for pin interrupt 6 (selected in PINTSEL6). [Note interrupt not supported to processor] 0: Edge sensitive. 1: Level sensitive." "0: Edge sensitive,1: Level sensitive"
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newline
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bitfld.long 0x0 5. "PMODE_PIN5,Selects the interrupt mode for pin interrupt 5 (selected in PINTSEL5). [Note interrupt not supported to processor] 0: Edge sensitive 1: Level sensitive" "0: Edge sensitive,1: Level sensitive"
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bitfld.long 0x0 4. "PMODE_PIN4,Selects the interrupt mode for pin interrupt 4 (selected in PINTSEL4). [Note interrupt not supported to processor] 0: Edge sensitive. 1: Level sensitive." "0: Edge sensitive,1: Level sensitive"
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newline
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bitfld.long 0x0 3. "PMODE_PIN3,Selects the interrupt mode for pin interrupt 3 (selected in PINTSEL3). 0: Edge sensitive. 1: Level sensitive." "0: Edge sensitive,1: Level sensitive"
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bitfld.long 0x0 2. "PMODE_PIN2,Selects the interrupt mode for pin interrupt 2 (selected in PINTSEL2). 0: Edge sensitive. 1: Level sensitive." "0: Edge sensitive,1: Level sensitive"
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newline
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bitfld.long 0x0 1. "PMODE_PIN1,Selects the interrupt mode for pin interrupt 1 (selected in PINTSEL1). 0: Edge sensitive. 1: Level sensitive." "0: Edge sensitive,1: Level sensitive"
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bitfld.long 0x0 0. "PMODE_PIN0,Selects the interrupt mode for pin interrupt 0 (selected in PINTSEL0). 0: Edge sensitive. 1: Level sensitive." "0: Edge sensitive,1: Level sensitive"
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line.long 0x4 "IENR,Pin interrupt level or rising edge interrupt enable register (only interrupts 0 to 3 supported to processor)"
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bitfld.long 0x4 7. "ENRL_PIN7,Enables the rising edge or level interrupt for pin interrupt 7 (selected in PINTSEL7). [Note interrupt not supported to processor] 0: Disable rising edge or level interrupt. 1: Enable rising edge or level interrupt." "0: Disable rising edge or level interrupt,1: Enable rising edge or level interrupt"
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bitfld.long 0x4 6. "ENRL_PIN6,Enables the rising edge or level interrupt for pin interrupt 6 (selected in PINTSEL6). [Note interrupt not supported to processor] 0: Disable rising edge or level interrupt. 1: Enable rising edge or level interrupt." "0: Disable rising edge or level interrupt,1: Enable rising edge or level interrupt"
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newline
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bitfld.long 0x4 5. "ENRL_PIN5,Enables the rising edge or level interrupt for pin interrupt 5 (selected in PINTSEL5). [Note interrupt not supported to processor] 0: Disable rising edge or level interrupt. 1: Enable rising edge or level interrupt." "0: Disable rising edge or level interrupt,1: Enable rising edge or level interrupt"
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bitfld.long 0x4 4. "ENRL_PIN4,Enables the rising edge or level interrupt for pin interrupt 4 (selected in PINTSEL4). [Note interrupt not supported to processor] 0: Disable rising edge or level interrupt. 1: Enable rising edge or level interrupt." "0: Disable rising edge or level interrupt,1: Enable rising edge or level interrupt"
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newline
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bitfld.long 0x4 3. "ENRL_PIN3,Enables the rising edge or level interrupt for pin interrupt 3 (selected in PINTSEL3). 0: Disable rising edge or level interrupt. 1: Enable rising edge or level interrupt." "0: Disable rising edge or level interrupt,1: Enable rising edge or level interrupt"
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bitfld.long 0x4 2. "ENRL_PIN2,Enables the rising edge or level interrupt for pin interrupt 2 (selected in PINTSEL2). 0: Disable rising edge or level interrupt. 1: Enable rising edge or level interrupt." "0: Disable rising edge or level interrupt,1: Enable rising edge or level interrupt"
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newline
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bitfld.long 0x4 1. "ENRL_PIN1,Enables the rising edge or level interrupt for pin interrupt 1 (selected in PINTSEL1). 0: Disable rising edge or level interrupt. 1: Enable rising edge or level interrupt." "0: Disable rising edge or level interrupt,1: Enable rising edge or level interrupt"
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bitfld.long 0x4 0. "ENRL_PIN0,Enables the rising edge or level interrupt for pin interrupt 0 (selected in PINTSEL0). 0: Disable rising edge or level interrupt. 1: Enable rising edge or level interrupt." "0: Disable rising edge or level interrupt,1: Enable rising edge or level interrupt"
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|
wgroup.long 0x8++0x7
|
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line.long 0x0 "SIENR,Pin interrupt level or rising edge interrupt set register (only interrupts 0 to 3 supported to processor)"
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bitfld.long 0x0 7. "SETENRL_PIN7,Ones written to this address set bits in the IENR thus enabling interrupts. Bit 7 sets bit 7 in the IENR register. [Note interrupt not supported to processor] 0: No operation. 1: Enable rising edge or level interrupt." "0: No operation,1: Enable rising edge or level interrupt"
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bitfld.long 0x0 6. "SETENRL_PIN6,Ones written to this address set bits in the IENR thus enabling interrupts. Bit 6 sets bit 6 in the IENR register. [Note interrupt not supported to processor] 0: No operation. 1: Enable rising edge or level interrupt." "0: No operation,1: Enable rising edge or level interrupt"
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newline
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bitfld.long 0x0 5. "SETENRL_PIN5,Ones written to this address set bits in the IENR thus enabling interrupts. Bit 5 sets bit 5 in the IENR register. [Note interrupt not supported to processor] 0: No operation. 1: Enable rising edge or level interrupt." "0: No operation,1: Enable rising edge or level interrupt"
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bitfld.long 0x0 4. "SETENRL_PIN4,Ones written to this address set bits in the IENR thus enabling interrupts. Bit 4 sets bit 4 in the IENR register. [Note interrupt not supported to processor] 0: No operation. 1: Enable rising edge or level interrupt." "0: No operation,1: Enable rising edge or level interrupt"
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bitfld.long 0x0 3. "SETENRL_PIN3,Ones written to this address set bits in the IENR thus enabling interrupts. Bit 3 sets bit 3 in the IENR register. 0: No operation. 1: Enable rising edge or level interrupt." "0: No operation,1: Enable rising edge or level interrupt"
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bitfld.long 0x0 2. "SETENRL_PIN2,Ones written to this address set bits in the IENR thus enabling interrupts. Bit 2 sets bit 2 in the IENR register. 0: No operation. 1: Enable rising edge or level interrupt." "0: No operation,1: Enable rising edge or level interrupt"
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bitfld.long 0x0 1. "SETENRL_PIN1,Ones written to this address set bits in the IENR thus enabling interrupts. Bit 1 sets bit 1 in the IENR register. 0: No operation. 1: Enable rising edge or level interrupt." "0: No operation,1: Enable rising edge or level interrupt"
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bitfld.long 0x0 0. "SETENRL_PIN0,Ones written to this address set bits in the IENR thus enabling interrupts. Bit 0 sets bit 0 in the IENR register. 0: No operation. 1: Enable rising edge or level interrupt." "0: No operation,1: Enable rising edge or level interrupt"
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line.long 0x4 "CIENR,Pin interrupt level (rising edge interrupt) clear register (only interrupts 0 to 3 supported to processor)"
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bitfld.long 0x4 7. "CLRENRL_PIN7,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit 7 clears bit 7 in the IENR register. [Note interrupt not supported to processor] 0: No operation. 1: Disable rising edge or level interrupt." "0: No operation,1: Disable rising edge or level interrupt"
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bitfld.long 0x4 6. "CLRENRL_PIN6,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit 6 clears bit 6 in the IENR register. [Note interrupt not supported to processor] 0: No operation. 1: Disable rising edge or level interrupt." "0: No operation,1: Disable rising edge or level interrupt"
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bitfld.long 0x4 5. "CLRENRL_PIN5,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit 5 clears bit 5 in the IENR register. [Note interrupt not supported to processor] 0: No operation. 1: Disable rising edge or level interrupt." "0: No operation,1: Disable rising edge or level interrupt"
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bitfld.long 0x4 4. "CLRENRL_PIN4,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit 4 clears bit 4 in the IENR register. [Note interrupt not supported to processor] 0: No operation. 1: Disable rising edge or level interrupt." "0: No operation,1: Disable rising edge or level interrupt"
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bitfld.long 0x4 3. "CLRENRL_PIN3,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit 3 clears bit 3 in the IENR register. 0: No operation. 1: Disable rising edge or level interrupt." "0: No operation,1: Disable rising edge or level interrupt"
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bitfld.long 0x4 2. "CLRENRL_PIN2,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit 2 clears bit 2 in the IENR register. 0: No operation. 1: Disable rising edge or level interrupt." "0: No operation,1: Disable rising edge or level interrupt"
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bitfld.long 0x4 1. "CLRENRL_PIN1,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit 1 clears bit 1 in the IENR register. 0: No operation. 1: Disable rising edge or level interrupt." "0: No operation,1: Disable rising edge or level interrupt"
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bitfld.long 0x4 0. "CLRENRL_PIN0,Ones written to this address clear bits in the IENR thus disabling the interrupts. Bit 0 clears bit 0 in the IENR register. 0: No operation. 1: Disable rising edge or level interrupt." "0: No operation,1: Disable rising edge or level interrupt"
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group.long 0x10++0x3
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line.long 0x0 "IENF,Pin interrupt active level or falling edge interrupt enable register"
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bitfld.long 0x0 7. "ENAF_PIN7,Enables the falling edge or configures the active level interrupt for pin interrupt 7 (selected in PINTSEL7). [Note interrupt not supported to processor] 0: Disable falling edge interrupt or set active interrupt level LOW. 1: Enable falling.." "0: Disable falling edge interrupt or set active..,1: Enable falling edge interrupt enabled or set.."
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bitfld.long 0x0 6. "ENAF_PIN6,Enables the falling edge or configures the active level interrupt for pin interrupt 6 (selected in PINTSEL6). [Note interrupt not supported to processor] 0: Disable falling edge interrupt or set active interrupt level LOW. 1: Enable falling.." "0: Disable falling edge interrupt or set active..,1: Enable falling edge interrupt enabled or set.."
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bitfld.long 0x0 5. "ENAF_PIN5,Enables the falling edge or configures the active level interrupt for pin interrupt 5 (selected in PINTSEL5). [Note interrupt not supported to processor] 0: Disable falling edge interrupt or set active interrupt level LOW. 1: Enable falling.." "0: Disable falling edge interrupt or set active..,1: Enable falling edge interrupt enabled or set.."
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bitfld.long 0x0 4. "ENAF_PIN4,Enables the falling edge or configures the active level interrupt for pin interrupt 4 (selected in PINTSEL4). [Note interrupt not supported to processor] 0: Disable falling edge interrupt or set active interrupt level LOW. 1: Enable falling.." "0: Disable falling edge interrupt or set active..,1: Enable falling edge interrupt enabled or set.."
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bitfld.long 0x0 3. "ENAF_PIN3,Enables the falling edge or configures the active level interrupt for pin interrupt 3 (selected in PINTSEL3). 0: Disable falling edge interrupt or set active interrupt level LOW. 1: Enable falling edge interrupt enabled or set active interrupt.." "0: Disable falling edge interrupt or set active..,1: Enable falling edge interrupt enabled or set.."
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bitfld.long 0x0 2. "ENAF_PIN2,Enables the falling edge or configures the active level interrupt for pin interrupt 2 (selected in PINTSEL2). 0: Disable falling edge interrupt or set active interrupt level LOW. 1: Enable falling edge interrupt enabled or set active interrupt.." "0: Disable falling edge interrupt or set active..,1: Enable falling edge interrupt enabled or set.."
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bitfld.long 0x0 1. "ENAF_PIN1,Enables the falling edge or configures the active level interrupt for pin interrupt 1 (selected in PINTSEL1). 0: Disable falling edge interrupt or set active interrupt level LOW. 1: Enable falling edge interrupt enabled or set active interrupt.." "0: Disable falling edge interrupt or set active..,1: Enable falling edge interrupt enabled or set.."
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bitfld.long 0x0 0. "ENAF_PIN0,Enables the falling edge or configures the active level interrupt for pin interrupt 0 (selected in PINTSEL0). 0: Disable falling edge interrupt or set active interrupt level LOW. 1: Enable falling edge interrupt enabled or set active interrupt.." "0: Disable falling edge interrupt or set active..,1: Enable falling edge interrupt enabled or set.."
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wgroup.long 0x14++0x7
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line.long 0x0 "SIENF,Pin interrupt active level or falling edge interrupt set register"
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bitfld.long 0x0 7. "SETENAF_PIN7,Ones written to this address set bits in the IENF thus enabling interrupts. Bit 7 sets bit 7 in the IENF register. 0: No operation. 1: Select HIGH-active interrupt or enable falling edge interrupt." "0: No operation,1: Select HIGH-active interrupt or enable falling.."
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bitfld.long 0x0 6. "SETENAF_PIN6,Ones written to this address set bits in the IENF thus enabling interrupts. Bit 6 sets bit 6 in the IENF register. 0: No operation. 1: Select HIGH-active interrupt or enable falling edge interrupt." "0: No operation,1: Select HIGH-active interrupt or enable falling.."
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bitfld.long 0x0 5. "SETENAF_PIN5,Ones written to this address set bits in the IENF thus enabling interrupts. Bit 5 sets bit 5 in the IENF register. 0: No operation. 1: Select HIGH-active interrupt or enable falling edge interrupt." "0: No operation,1: Select HIGH-active interrupt or enable falling.."
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bitfld.long 0x0 4. "SETENAF_PIN4,Ones written to this address set bits in the IENF thus enabling interrupts. Bit 4 sets bit 4 in the IENF register. 0: No operation. 1: Select HIGH-active interrupt or enable falling edge interrupt." "0: No operation,1: Select HIGH-active interrupt or enable falling.."
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bitfld.long 0x0 3. "SETENAF_PIN3,Ones written to this address set bits in the IENF thus enabling interrupts. Bit 3 sets bit 3 in the IENF register. 0: No operation. 1: Select HIGH-active interrupt or enable falling edge interrupt." "0: No operation,1: Select HIGH-active interrupt or enable falling.."
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bitfld.long 0x0 2. "SETENAF_PIN2,Ones written to this address set bits in the IENF thus enabling interrupts. Bit 2 sets bit 2 in the IENF register. 0: No operation. 1: Select HIGH-active interrupt or enable falling edge interrupt." "0: No operation,1: Select HIGH-active interrupt or enable falling.."
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bitfld.long 0x0 1. "SETENAF_PIN1,Ones written to this address set bits in the IENF thus enabling interrupts. Bit 1 sets bit 1 in the IENF register. 0: No operation. 1: Select HIGH-active interrupt or enable falling edge interrupt." "0: No operation,1: Select HIGH-active interrupt or enable falling.."
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bitfld.long 0x0 0. "SETENAF_PIN0,Ones written to this address set bits in the IENF thus enabling interrupts. Bit 0 sets bit 0 in the IENF register. 0: No operation. 1: Select HIGH-active interrupt or enable falling edge interrupt." "0: No operation,1: Select HIGH-active interrupt or enable falling.."
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line.long 0x4 "CIENF,Pin interrupt active level or falling edge interrupt clear register"
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bitfld.long 0x4 7. "CLRENAF_PIN7,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit 7 clears bit 7 in the IENF register. 0: No operation. 1: LOW-active interrupt selected or falling edge interrupt disabled." "0: No operation,1: LOW-active interrupt selected or falling edge.."
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bitfld.long 0x4 6. "CLRENAF_PIN6,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit 6 clears bit 6 in the IENF register. 0: No operation. 1: LOW-active interrupt selected or falling edge interrupt disabled." "0: No operation,1: LOW-active interrupt selected or falling edge.."
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bitfld.long 0x4 5. "CLRENAF_PIN5,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit 5 clears bit 5 in the IENF register. 0: No operation. 1: LOW-active interrupt selected or falling edge interrupt disabled." "0: No operation,1: LOW-active interrupt selected or falling edge.."
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bitfld.long 0x4 4. "CLRENAF_PIN4,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit 4 clears bit 4 in the IENF register. 0: No operation. 1: LOW-active interrupt selected or falling edge interrupt disabled." "0: No operation,1: LOW-active interrupt selected or falling edge.."
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bitfld.long 0x4 3. "CLRENAF_PIN3,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit 3 clears bit 3 in the IENF register. 0: No operation. 1: LOW-active interrupt selected or falling edge interrupt disabled." "0: No operation,1: LOW-active interrupt selected or falling edge.."
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bitfld.long 0x4 2. "CLRENAF_PIN2,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit 2 clears bit 2 in the IENF register. 0: No operation. 1: LOW-active interrupt selected or falling edge interrupt disabled." "0: No operation,1: LOW-active interrupt selected or falling edge.."
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bitfld.long 0x4 1. "CLRENAF_PIN1,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit 1 clears bit 1 in the IENF register. 0: No operation. 1: LOW-active interrupt selected or falling edge interrupt disabled." "0: No operation,1: LOW-active interrupt selected or falling edge.."
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bitfld.long 0x4 0. "CLRENAF_PIN0,Ones written to this address clears bits in the IENF thus disabling interrupts. Bit 0 clears bit 0 in the IENF register. 0: No operation. 1: LOW-active interrupt selected or falling edge interrupt disabled." "0: No operation,1: LOW-active interrupt selected or falling edge.."
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group.long 0x1C++0x17
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line.long 0x0 "RISE,Pin interrupt rising edge register"
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hexmask.long.byte 0x0 0.--7. 1. "RDET,Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been.."
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line.long 0x4 "FALL,Pin interrupt falling edge register"
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hexmask.long.byte 0x4 0.--7. 1. "FDET,Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has.."
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line.long 0x8 "IST,Pin interrupt status register. For bits in this regsiter the following functionality occurs for the corresponding PIN bit: Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested.."
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bitfld.long 0x8 7. "PSTAT_PIN7,Pin interrupt status. Bit 7 returns the status clears the edge interrupt or inverts the active level of the pin 7 (selected in PINTSEL7)." "0,1"
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bitfld.long 0x8 6. "PSTAT_PIN6,Pin interrupt status. Bit 6 returns the status clears the edge interrupt or inverts the active level of the pin 6 (selected in PINTSEL6)." "0,1"
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bitfld.long 0x8 5. "PSTAT_PIN5,Pin interrupt status. Bit 5 returns the status clears the edge interrupt or inverts the active level of the pin 5 (selected in PINTSEL5)." "0,1"
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bitfld.long 0x8 4. "PSTAT_PIN4,Pin interrupt status. Bit 4 returns the status clears the edge interrupt or inverts the active level of the pin 4 (selected in PINTSEL4)." "0,1"
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bitfld.long 0x8 3. "PSTAT_PIN3,Pin interrupt status. Bit 3 returns the status clears the edge interrupt or inverts the active level of the pin 3 (selected in PINTSEL3)." "0,1"
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bitfld.long 0x8 2. "PSTAT_PIN2,Pin interrupt status. Bit 2 returns the status clears the edge interrupt or inverts the active level of the pin 2 (selected in PINTSEL2)." "0,1"
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bitfld.long 0x8 1. "PSTAT_PIN1,Pin interrupt status. Bit 1 returns the status clears the edge interrupt or inverts the active level of the pin 1 (selected in PINTSEL0)." "0,1"
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bitfld.long 0x8 0. "PSTAT_PIN0,Pin interrupt status. Bit 0 returns the status clears the edge interrupt or inverts the active level of the pin 0 (selected in PINTSEL0)." "0,1"
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line.long 0xC "PMCTRL,Pattern match interrupt control register"
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hexmask.long.byte 0xC 24.--31. 1. "PMAT,This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs."
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bitfld.long 0xC 1. "ENA_RXEV,Enables the RXEV output to the CPU when the specified boolean expression evaluates to true. 0: Disabled. RXEV output to the CPU is disabled. 1: Enabled. RXEV output to the CPU is enabled." "0: Disabled,1: Enabled"
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bitfld.long 0xC 0. "SEL_PMATCH,Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 0: Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. 1: Pattern match. Interrupts are.." "0: Pin interrupt,1: Pattern match"
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line.long 0x10 "PMSRC,Pattern match interrupt bit-slice source register"
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bitfld.long 0x10 29.--31. "SRC7,Selects the input source for bit slice 7. Value X selects the pin selected in the PINTSELX register as the source to this bit slice. For example 3 selects the pin selected in PINTSEL3 regsiter." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 26.--28. "SRC6,Selects the input source for bit slice 6. Value X selects the pin selected in the PINTSELX register as the source to this bit slice. For example 3 selects the pin selected in PINTSEL3 regsiter." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 23.--25. "SRC5,Selects the input source for bit slice 5. Value X selects the pin selected in the PINTSELX register as the source to this bit slice. For example 3 selects the pin selected in PINTSEL3 regsiter." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 20.--22. "SRC4,Selects the input source for bit slice 4. Value X selects the pin selected in the PINTSELX register as the source to this bit slice. For example 3 selects the pin selected in PINTSEL3 regsiter." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 17.--19. "SRC3,Selects the input source for bit slice 3. Value X selects the pin selected in the PINTSELX register as the source to this bit slice. For example 3 selects the pin selected in PINTSEL3 regsiter." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 14.--16. "SRC2,Selects the input source for bit slice 2. Value X selects the pin selected in the PINTSELX register as the source to this bit slice. For example 3 selects the pin selected in PINTSEL3 regsiter." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 11.--13. "SRC1,Selects the input source for bit slice 1. Value X selects the pin selected in the PINTSELX register as the source to this bit slice. For example 3 selects the pin selected in PINTSEL3 regsiter." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8.--10. "SRC0,Selects the input source for bit slice 0. Value X selects the pin selected in the PINTSELX register as the source to this bit slice. For example 3 selects the pin selected in PINTSEL3 regsiter." "0,1,2,3,4,5,6,7"
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line.long 0x14 "PMCFG,Pattern match interrupt bit slice configuration register"
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bitfld.long 0x14 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7. See CFG0 for the modes available." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6. See CFG0 for the modes available." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5. See CFG0 for the modes available." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4. See CFG0 for the modes available." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3. See CFG0 for the modes available." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2. See CFG0 for the modes available." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1. See CFG0 for the modes available." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0. 0x0: Constant HIGH. This bit slice always contributes to a product term match. 0x1: Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time.." "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
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bitfld.long 0x14 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint. 0: No effect. Slice 6 is not an endpoint. 1: endpoint. Slice 6 is the endpoint of a product term (minterm). No NVIC interrupt is assocaited with this." "0: No effect,1: endpoint"
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bitfld.long 0x14 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint. 0 No effect. Slice 5 is not an endpoint. 1: endpoint. Slice 5 is the endpoint of a product term (minterm). No NVIC interrupt is assocaited with this." "?,1: endpoint"
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bitfld.long 0x14 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint. 0: No effect. Slice 4 is not an endpoint. 1: endpoint. Slice 4 is the endpoint of a product term (minterm). No NVIC interrupt is assocaited with this." "0: No effect,1: endpoint"
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bitfld.long 0x14 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint. 0: No effect. Slice 3 is not an endpoint. 1: endpoint. Slice 3 is the endpoint of a product term (minterm). Interrupt PINT3 in the NVIC is raised if the minterm evaluates as true." "0: No effect,1: endpoint"
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bitfld.long 0x14 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint. 0: No effect. Slice 2 is not an endpoint. 1: endpoint. Slice 2 is the endpoint of a product term (minterm). Interrupt PINT2 in the NVIC is raised if the minterm evaluates as true." "0: No effect,1: endpoint"
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bitfld.long 0x14 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint. 0: No effect. Slice 1 is not an endpoint. 1: endpoint. Slice 1 is the endpoint of a product term (minterm). Interrupt PINT1 in the NVIC is raised if the minterm evaluates as true." "0: No effect,1: endpoint"
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bitfld.long 0x14 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint. 0: No effect. Slice 0 is not an endpoint. 1: endpoint. Slice 0 is the endpoint of a product term (minterm). Interrupt PINT0 in the NVIC is raised if the minterm evaluates as true." "0: No effect,1: endpoint"
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tree.end
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tree "PMC (Power Management Controller)"
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base ad:0x40012000
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group.long 0x0++0x27
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line.long 0x0 "CTRL,Power Management Control [Reset by POR. RSTN. WDT ]"
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bitfld.long 0x0 9. "SWRRESETENABLE,Software reset enable. If set enables the software reset to affect the system." "0,1"
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bitfld.long 0x0 8. "SELLDOVOLTAGE,0 = all LDOs current output levels are determined by their associated VADJ bitfield. 1 = all LDOs current output levels are determined by their associated VADJ_2 bitfield." "0: all LDOs current output levels are determined by..,1: all LDOs current output levels are determined by.."
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bitfld.long 0x0 4. "WAKUPRESETENABLE,Wake-up I/Os reset enable. When set the I/O power domain is not shutoff in deep powerdown mode." "0,1"
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bitfld.long 0x0 3. "WDTRESETENABLE,Watchdog Timer reset enable. If set allow a watchdog timer reset event to affect the system." "0,1"
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bitfld.long 0x0 2. "SYSTEMRESETENABLE,ARM system reset request enable. If set enables the ARM system reset to affect the system." "0,1"
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bitfld.long 0x0 0.--1. "LPMODE,Power Mode Control. 00: Active; 01: Deep Sleep; 10: Power Down; 11: Deep Power Down." "0: Active;,1: Deep Sleep;,?,?"
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line.long 0x4 "DCDC0,DCDC control register (1st). This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources. except ARM SystemReset]"
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hexmask.long 0x4 0.--31. 1. "DCDC0,DCDC control register (1st). This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources except ARM SystemReset]"
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line.long 0x8 "DCDC1,DCDC control register (2nd). This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources. except ARM SystemReset]"
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hexmask.long 0x8 0.--31. 1. "DCDC1,DCDC control register (2nd). This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources except ARM SystemReset]"
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line.long 0xC "BIAS,Bias current source control register. This reigster is controlled by the boot code and the Low power API software. [Reset by POR. RSTN. WDT ]"
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hexmask.long 0xC 0.--31. 1. "BIAS,Bias current source control register. This reigster is controlled by the boot code and the Low power API software. [Reset by POR RSTN WDT ]"
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line.long 0x10 "LDOPMU,PMU & Always On domains LDO control. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources. except ARM SystemReset]"
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hexmask.long 0x10 0.--31. 1. "LDOPMU,PMU & Always On domains LDO control. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources except ARM SystemReset]"
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line.long 0x14 "LDOMEM,Memories LDO control register. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources. except ARM SystemReset]"
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hexmask.long 0x14 0.--31. 1. "LDOMEM,Memories LDO control register. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources except ARM SystemReset]"
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line.long 0x18 "LDOCORE,Digital Core LDO control register. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources. except ARM SystemReset]"
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hexmask.long 0x18 0.--31. 1. "LDOCORE,Digital Core LDO control register. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources except ARM SystemReset]"
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line.long 0x1C "LDOFLASHNV,Flash LDO control register. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources. except ARM SystemReset]"
|
|
hexmask.long 0x1C 0.--31. 1. "LDOFLASHNV,Flash LDO control register. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources except ARM SystemReset]"
|
|
line.long 0x20 "LDOFLASHCORE,Flash Core LDO control register. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources. except ARM SystemReset]"
|
|
hexmask.long 0x20 0.--31. 1. "LDOFLASHCORE,Flash Core LDO control register. This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources except ARM SystemReset]"
|
|
line.long 0x24 "LDOADC,General Purpose ADC LDO control register This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources. except ARM SystemReset]"
|
|
hexmask.long 0x24 0.--31. 1. "LDOADC,General Purpose ADC LDO control register This reigster is controlled by the boot code and the Low power API software. [Reset by all reset sources except ARM SystemReset]"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "BODVBAT,VBAT Brown Out Dectector control register This reigster is controlled by the boot code and the Low power API software. [Reset by POR. RSTN. WDT ]"
|
|
bitfld.long 0x0 5.--6. "HYST,BOD Hysteresis control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "TRIGLVL,BOD trigger level"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "FRO192M,High Speed FRO control register This reigster is controlled by the boot code and the Low power API software. [Reset by POR. RSTN. WDT ]"
|
|
hexmask.long.byte 0x0 20.--24. 1. "DIVSEL,Mode of operation (which clock to output). Each bit enables a clocks as shown. Enables are additive meaning that two or more clocks can be enabled together. xxxx1: 12MHz enabled; xxx1x: 32MHz enabled; xx1xx: 48MHz enabled; x1xxx: Not applicable;.."
|
|
line.long 0x4 "FRO1M,1 MHz Free Running Oscillator control register. [Reset by all reset sources. except ARM SystemReset]"
|
|
hexmask.long.byte 0x4 9.--13. 1. "DIVSEL,Divider selection bits."
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|
newline
|
|
bitfld.long 0x4 7.--8. "ATBCTRL,Debug control bits to set the analog/digital test modes; only required for test purposes." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "FREQSEL,Frequency trimming bits. This field is used to give accurate frequency for each device. The required setting is based upon calibration data sotred in flash during device test. This setting is applied by the clock driver function."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "ANAMUXCOMP,Analog Comparator and Analog Mux control register. [Reset by all reset sources. except ARM SystemReset]"
|
|
bitfld.long 0x0 4. "COMP_INPUTSWAP,Input swap is enabled when set. Comparator{ _p _n} ports are connected to {ACM ACP}. Otherwsie normal configuration occurs {_p _n} is connected to {ACP ACM} ." "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "COMP_LOWPOWER,Comparator Low power mode enabled when set." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "COMP_INNINT,Voltage reference inn_int input is selected for _n comparator input when sel_inn_int = 1 . This setting also requires PMU_BIASING to be active. Also flash biasing and DCDC converter needs to be enabled. If this setting = '0' then _n input.." "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "COMP_HYST,Hysteris enabled in comparator when hyst = '1' no hysteresis when = '0'." "0,1"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "PWRSWACK,Power Switch acknowledge. [Reset by all reset sources. except ARM SystemReset]"
|
|
bitfld.long 0x0 3. "PDMCURETENTION,MCU Retention Power Domain power switch status." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "PDSYSTEM,System Power Domain power switch status." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PDCOMM0,Comm0 (USART0 I2C0 SPI0) Power Domain power switch status." "0,1"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "DPDWKSRC,Power Down and Deep Power Down wake-up source. [Reset by POR. RSTN. WDT ]"
|
|
bitfld.long 0x0 21. "PIO21,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO21: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 20. "PIO20,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO20: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 19. "PIO19,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO19: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 18. "PIO18,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO18: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 17. "PIO17,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO17: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 16. "PIO16,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO16: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 15. "PIO15,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO15: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 14. "PIO14,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO14: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 13. "PIO13,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO13: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 12. "PIO12,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO12: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 11. "PIO11,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO11: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 10. "PIO10,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO10: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 9. "PIO9,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO9: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 8. "PIO8,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO8: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 7. "PIO7,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO7: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 6. "PIO6,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO6: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 5. "PIO5,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO5: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 4. "PIO4,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO4: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 3. "PIO3,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO3: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 2. "PIO2,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO2: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 1. "PIO1,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO1: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 0. "PIO0,Enable / disable wakeup from Power down and Deep Power Down modes by GPIO0: 0: Disable; 1: Enable." "0: Disable;,1: Enable"
|
|
rgroup.long 0x68++0x7
|
|
line.long 0x0 "STATUSPWR,Power OK and Ready signals from various analog modules (DCDC. LDO. ). [Reset by all reset sources. except ARM SystemReset]"
|
|
bitfld.long 0x0 5. "LDOADC1V1PWROK,General Purpose ADC LDO power OK. Max switch on time is 8us." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LDOFLASHCOREPWROK,Flash Core LDO power OK Max switch on time should be considered as 10us." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LDOFLASHNVPWROK,Flash NV LDO power OK Max switch on time 20us." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LDOCOREPWROK,CORE LDO power OK. Max switch on time 2us." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DCDCVXCTRLMON,Picture of the DCDC output state." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DCDCPWROK,DCDC converter power OK" "0,1"
|
|
line.long 0x4 "STATUSCLK,FRO and XTAL status register. [Reset by all reset sources. except ARM SystemReset]"
|
|
bitfld.long 0x4 2. "FRO1MCLKVALID,FRO 1 MHz CCO voltage detector output." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "XTAL32KOK,XTAL oscillator 32KHz OK signal. When the XTAL is stable then a transition from 1 to 0 will indicate a clock issue. Can not be used to identify a stable clock during XTAL start." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FRO192MCLKVALID,High Speed FRO (FRO 192 MHz) clock valid signal. The FRO192M clock generator also generates the FRO12M FRO32M and FRO48M clock signals. These will also be valid when this flag is assertetd." "0,1"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "RESETCAUSE,Reset Cause register. [Reset by POR]"
|
|
bitfld.long 0x0 7. "SWRRESET,1 : The last chip reset was caused by a Software. Write '1' to clear this bit." "?,1: The last chip reset was caused by a Software"
|
|
newline
|
|
bitfld.long 0x0 6. "WAKEUPPWDNRESET,1 : The last CPU reset was caused by a Wake-up from Power down (many sources possible: timer IO ...). Write '1' to clear this bit. Check NVIC register if not waken-up by IO (NVIC_GetPendingIRQ)." "?,1: The last CPU reset was caused by a Wake-up from.."
|
|
newline
|
|
bitfld.long 0x0 5. "WAKEUPIORESET,1 : The last chip reset was caused by a Wake-up I/O (GPIO). Write '1' to clear this bit." "?,1: The last chip reset was caused by a Wake-up I/O"
|
|
newline
|
|
bitfld.long 0x0 4. "WDTRESET,1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit." "?,1: The last chip reset was caused by the Watchdog.."
|
|
newline
|
|
bitfld.long 0x0 3. "SYSTEMRESET,1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit." "?,1: The last chip reset was caused by a System Reset.."
|
|
newline
|
|
bitfld.long 0x0 2. "BODRESET,1 : The last chip reset was caused by a Brown Out Detector. Write '1' to clear this bit." "?,1: The last chip reset was caused by a Brown Out.."
|
|
newline
|
|
bitfld.long 0x0 1. "PADRESET,1 : The last chip reset was caused by a Pad Reset. Write '1' to clear this bit." "?,1: The last chip reset was caused by a Pad Reset"
|
|
newline
|
|
bitfld.long 0x0 0. "POR,1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit." "?,1: The last chip reset was caused by a Power On Reset"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "AOREG0,General purpose always on domain data storage. [Reset by all reset sources. except ARM SystemReset]"
|
|
hexmask.long 0x0 0.--31. 1. "DATA31_0,General purpose always on domain data storage. Only writable 1 time after any chip reset. After the 1st write any further writes are blocked. After any chip reset the write block is disabled until after next write. The chip reset includes POR .."
|
|
line.long 0x4 "AOREG1,General purpose always on domain data storage. [Reset by POR. RSTN]"
|
|
hexmask.long 0x4 0.--31. 1. "DATA31_0,Reserved for use by NXP system software. General purpose always on domain data storage. Only reinitialized on Power On Reset and RSTIN Pin reset."
|
|
line.long 0x8 "AOREG2,General purpose always on domain data storage. [Reset by POR. RSTN]"
|
|
hexmask.long 0x8 0.--31. 1. "DATA31_0,General purpose always on domain data storage. Only reinitialized on Power On Reset and RSTIN Pin reset."
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "DPDCTRL,Configuration parameters for Power Down and Deep Power Down mode. [Reset by POR. RSTN. WDT ]"
|
|
bitfld.long 0x0 1.--2. "XTAL32MSTARTDLY,Delay between xtal ldo enable and release of reset to xtal 0:16us 1:32us 2:48us 3:64us. LSB reset value set by efuse (wake-up by I/O only). This delay is applied within PMC for Efuse controlled XTAL start and also BLE link layer for BLE.." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0. "XTAL32MSTARTENA,Enable XTAL32MHz automatic start-up at power up & wake up from power down or deep power down. Reset value is set by eFuse content. This register field will overwrite option selected by eFuse content only if power-up or wake-up is NOT.." "0,1"
|
|
rgroup.long 0x9C++0x7
|
|
line.long 0x0 "PIOPORCAP,The PIOPORCAP register captures the state of GPIO at power-on-reset or pin reset. Each bit represents the power-on reset state of one GPIO pin. [Reset by POR. RSTN]"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "GPIO,Capture of GPIO values at power-on-reset and pin reset."
|
|
line.long 0x4 "PIORESCAP,The PIORESCAP0 register captures the state of GPIO port 0 when a reset other than a power-on reset or pin reset occurs. Each bit represents the reset state of one GPIO pin. [Reset by WDT. BOD. WAKEUP IO. ARM System reset ]"
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "GPIO,Capture of GPIO values."
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "PDSLEEPCFG,Controls the power to various modules in Low Power modes. [Reset by all reset sources. except ARM SystemReset]"
|
|
bitfld.long 0x0 21. "PDEN_PD_MEM11,Enable Power Down mode of SRAM 11 when entering in Powerdown mode. Automatically switched off in deep power down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PDEN_PD_MEM10,Enable Power Down mode of SRAM 10 when entering in Powerdown mode. Automatically switched off in deep power down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PDEN_PD_MEM9,Enable Power Down mode of SRAM 9 when entering in Powerdown mode. Automatically switched off in deep power down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PDEN_PD_MEM8,Enable Power Down mode of SRAM 8 when entering in Powerdown mode. Automatically switched off in deep power down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PDEN_PD_MEM7,Enable Power Down mode of SRAM 7 when entering in Powerdown mode. Automatically switched off in deep power down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PDEN_PD_MEM6,Enable Power Down mode of SRAM 6 when entering in Powerdown mode. Automatically switched off in deep power down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "PDEN_PD_MEM5,Enable Power Down mode of SRAM 5 when entering in Powerdown mode. Automatically switched off in deep power down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PDEN_PD_MEM4,Enable Power Down mode of SRAM 4 when entering in Powerdown mode. Automatically switched off in deep power down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PDEN_PD_MEM3,Enable Power Down mode of SRAM 3 when entering in Powerdown mode. Automatically switched off in deep power down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PDEN_PD_MEM2,Enable Power Down mode of SRAM 2 when entering in Powerdown mode. Automatically switched off in deep power down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PDEN_PD_MEM1,Enable Power Down mode of SRAM 1 when entering in Powerdown mode. Automatically switched off in deep power down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PDEN_PD_MEM0,Enable Power Down mode of SRAM 0 when entering in Powerdown mode. Automatically switched off in deep power down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EN_PDMCU_RETENTION,Enable MCU Power Domain state retention when entering in 'Powerdown' mode for modem and radio cal values" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PDEN_PD_COMM0,Enable Comm0 power domain (USART0 I2C0 SPI0) Power Down mode when entering in Powerdown mode. In Deep power down it is disabled by hardware. In deep sleep it is always enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "PDEN_PD_FLASH,Enable Flash power domain Power Down mode (power shutoff) when entering in DeepSleep. In PowerDown modes this domain is automatically powered off." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PDEN_FRO1M,Controls FRO1M power in Deep Sleep Power down and Deep Power down modes. This should be disabled before entering power down (unless needed for low power timers) or deep power down mode. 0: FRO1M is disabled; 1: FRO1M is enabled." "0: FRO1M is disabled;,1: FRO1M is enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "PDEN_FRO192M,Controls FRO192M power in Deep Sleep Power down and Deep Power down modes. This should be disabled before entering power down or deep power down mode. 0: FRO192M is disabled; 1: FRO192M is enabled." "0: FRO192M is disabled;,1: FRO192M is enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "PDEN_VBAT_BOD,Controls VBAT BOD power in Power down and Deep Power down modes. 0: VBAT BOD is disabled in Power down and Deep Power down modes; 1: VBAT BOD is enabled in Power down and Deep Power down modes." "0: VBAT BOD is disabled in Power down and Deep..,1: VBAT BOD is enabled in Power down and Deep Power.."
|
|
newline
|
|
bitfld.long 0x0 2. "PDEN_LDO_MEM,Controls LDO memories power in Power down mode. Automatically switched off in deep power down 0: LDO is disabled in Power down mode; 1: LDO is enabled in Power down mode." "0: LDO is disabled in Power down mode;,1: LDO is enabled in Power down mode"
|
|
newline
|
|
bitfld.long 0x0 1. "PDEN_BIAS,Controls Bias power in Power down and Deep Power down modes. 0: Bias is disabled in Power down and Deep Power down modes; 1: Bias is enabled in Power down and Deep Power down modes." "0: Bias is disabled in Power down and Deep Power..,1: Bias is enabled in Power down and Deep Power.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDEN_DCDC,Controls DCDC power in Power down and Deep Power down modes. Automatically switched off in deep power down. 0: DCDC is disabled in Power down and Deep Power down modes; 1: DCDC is enabled in Power down and Deep Power down modes." "0: DCDC is disabled in Power down and Deep Power..,1: DCDC is enabled in Power down and Deep Power.."
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PDRUNCFG,Controls the power to various analog blocks. [Reset by all reset sources. except ARM SystemReset]"
|
|
bitfld.long 0x0 27. "ENA_ANA_COMP,Analog Comparator enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "ENA_XTAL32K,XTAL32K enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "ENA_FRO32K,FRO32K enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ENA_BOD_CORE,BOD CORE enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "ENA_BOD_MEM,BOD MEM enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "ENA_LDO_ADC,LDO ADC enabled. See STATUSPWR.LDOADC1V1PWROK for when the power domain is ready." "0,1"
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "WAKEIOCAUSE,Wake-up source from Power Down and Deep Power Down modes. Allow to identify the Wake-up source from Power-Down mode or Deep Power Down mode.[Reset by POR. RSTN. WDT ]"
|
|
bitfld.long 0x0 21. "GPIO21,Wake up was triggered by GPIO 21" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "GPIO20,Wake up was triggered by GPIO 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GPIO19,Wake up was triggered by GPIO 19" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "GPIO18,Wake up was triggered by GPIO 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GPIO17,Wake up was triggered by GPIO 17" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "GPIO16,Wake up was triggered by GPIO 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "GPIO15,Wake up was triggered by GPIO 15" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "GPIO14,Wake up was triggered by GPIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "GPIO13,Wake up was triggered by GPIO 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "GPIO12,Wake up was triggered by GPIO 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO11,Wake up was triggered by GPIO 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "GPIO10,Wake up was triggered by GPIO 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "GPIO09,Wake up was triggered by GPIO 09" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "GPIO08,Wake up was triggered by GPIO 08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GPIO07,Wake up was triggered by GPIO 07" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "GPIO06,Wake up was triggered by GPIO 06" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GPIO05,Wake up was triggered by GPIO 05" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "GPIO04,Wake up was triggered by GPIO 04" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "GPIO03,Wake up was triggered by GPIO 03" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "GPIO02,Wake up was triggered by GPIO 02" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "GPIO01,Wake up was triggered by GPIO 01" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "GPIO00,Wake up was triggered by GPIO 00" "0,1"
|
|
group.long 0xCC++0x3
|
|
line.long 0x0 "CTRLNORST,Extension of CTRL register. but never reset except by POR"
|
|
bitfld.long 0x0 0.--2. "FASTLDOENABLE,Fast LDO wake-up enable. 3 bits for the different wake-up sources: {generic async wake up event as selected by SLEEPCON/STARTER0&1 IO wake-up event RSTN pad event}. If required this field should only be managed by the Low power driver.." "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation)"
|
|
base ad:0x4000C000
|
|
group.long 0x0++0x57
|
|
line.long 0x0 "CTRL0,PWM 1st Control Register (Channel 0 to Channel 10) for channel enables and interrupt enables. Note if all interrupts are enabled with short period timings it will not be possible to manage all the interrupts."
|
|
bitfld.long 0x0 26. "INT_EN_10,PWM channel 10 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 25. "INT_EN_9,PWM channel 9 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 24. "INT_EN_8,PWM channel 8 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EN_7,PWM channel 7 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 22. "INT_EN_6,PWM channel 6 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 21. "INT_EN_5,PWM channel 5 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EN_4,PWM channel 4 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 19. "INT_EN_3,PWM channel 3 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 18. "INT_EN_2,PWM channel 2 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EN_1,PWM channel 1 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 16. "INT_EN_0,PWM channel 0 interrupt enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 10. "PWM_EN_10,PWM channel 10 enable. 0 = Disable / 1 = Enable. Note this enables the common PWM mode where PWM10 will be routed to all PWM channels." "0: Disable /,1: Enable"
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|
newline
|
|
bitfld.long 0x0 9. "PWM_EN_9,PWM channel 9 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 8. "PWM_EN_8,PWM channel 8 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 7. "PWM_EN_7,PWM channel 7 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 6. "PWM_EN_6,PWM channel 6 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 5. "PWM_EN_5,PWM channel 5 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 4. "PWM_EN_4,PWM channel 4 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 3. "PWM_EN_3,PWM channel 3 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 2. "PWM_EN_2,PWM channel 2 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
bitfld.long 0x0 1. "PWM_EN_1,PWM channel 1 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 0. "PWM_EN_0,PWM channel 0 enable. 0 = Disable / 1 = Enable." "0: Disable /,1: Enable"
|
|
line.long 0x4 "CTRL1,PWM 2nd Control Register (Channel 0 to Channel 10) for channel polarity and output state for a disabled channel."
|
|
bitfld.long 0x4 25. "DIS_LEVEL_9,PWM channel 9 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
bitfld.long 0x4 24. "DIS_LEVEL_8,PWM channel 8 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
bitfld.long 0x4 23. "DIS_LEVEL_7,PWM channel 7 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
newline
|
|
bitfld.long 0x4 22. "DIS_LEVEL_6,PWM channel 6 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
bitfld.long 0x4 21. "DIS_LEVEL_5,PWM channel 5 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
bitfld.long 0x4 20. "DIS_LEVEL_4,PWM channel 4 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
newline
|
|
bitfld.long 0x4 19. "DIS_LEVEL_3,PWM channel 3 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
bitfld.long 0x4 18. "DIS_LEVEL_2,PWM channel 2 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
bitfld.long 0x4 17. "DIS_LEVEL_1,PWM channel 1 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
newline
|
|
bitfld.long 0x4 16. "DIS_LEVEL_0,PWM channel 0 output level when PWM channel 0 is disable. 0 = Low Level / 1 = High Level." "0: Low Level /,1: High Level"
|
|
bitfld.long 0x4 10. "POL_10,PWM channel 10 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
bitfld.long 0x4 9. "POL_9,PWM channel 9 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
newline
|
|
bitfld.long 0x4 8. "POL_8,PWM channel 8 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
bitfld.long 0x4 7. "POL_7,PWM channel 7 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
bitfld.long 0x4 6. "POL_6,PWM channel 6 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
newline
|
|
bitfld.long 0x4 5. "POL_5,PWM channel 5 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
bitfld.long 0x4 4. "POL_4,PWM channel 4 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
bitfld.long 0x4 3. "POL_3,PWM channel 3 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
newline
|
|
bitfld.long 0x4 2. "POL_2,PWM channel 2 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
bitfld.long 0x4 1. "POL_1,PWM channel 1 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
bitfld.long 0x4 0. "POL_0,PWM channel 0 waveform Polarity control. 0: Set high on compare match set low at the end of PWM period. 1: Set low on compare match set high at the end of PWM period" "0: Set high on compare match,1: Set low on compare match"
|
|
line.long 0x8 "PSCL01,PWM Channels 0 & 1 prescalers"
|
|
hexmask.long.word 0x8 16.--25. 1. "PSCL_1,PWM channel 1 prescaler. The output frequency equals to clk/(PSCL_1 + 1)"
|
|
hexmask.long.word 0x8 0.--9. 1. "PSCL_0,PWM channel 0 prescaler. The output frequency equals to clk/(PSCL_0 + 1)"
|
|
line.long 0xC "PSCL23,PWM Channels 2 & 3 prescalers"
|
|
hexmask.long.word 0xC 16.--25. 1. "PSCL_3,PWM channel 3 prescaler. The output frequency equals to clk/(PSCL_3 + 1)"
|
|
hexmask.long.word 0xC 0.--9. 1. "PSCL_2,PWM channel 2 prescaler. The output frequency equals to clk/(PSCL_2 + 1)"
|
|
line.long 0x10 "PSCL45,PWM Channels 4 & 5 prescalers"
|
|
hexmask.long.word 0x10 16.--25. 1. "PSCL_5,PWM channel 5 prescaler. The output frequency equals to clk/(PSCL_5 + 1)"
|
|
hexmask.long.word 0x10 0.--9. 1. "PSCL_4,PWM channel 4 prescaler. The output frequency equals to clk/(PSCL_4 + 1)"
|
|
line.long 0x14 "PSCL67,PWM Channels 6 & 7 prescalers"
|
|
hexmask.long.word 0x14 16.--25. 1. "PSCL_7,PWM channel 7 prescaler. The output frequency equals to clk/(PSCL_7 + 1)"
|
|
hexmask.long.word 0x14 0.--9. 1. "PSCL_6,PWM channel 6 prescaler. The output frequency equals to clk/(PSCL_6 + 1)"
|
|
line.long 0x18 "PSCL89,PWM Channels 8 & 9 prescalers"
|
|
hexmask.long.word 0x18 16.--25. 1. "PSCL_9,PWM channel 9 prescaler. The output frequency equals to clk/(PSCL_9 + 1)"
|
|
hexmask.long.word 0x18 0.--9. 1. "PSCL_8,PWM channel 8 prescaler. The output frequency equals to clk/(PSCL_8 + 1)"
|
|
line.long 0x1C "PSCL1011,PWM Channel 10 prescaler"
|
|
hexmask.long.word 0x1C 0.--9. 1. "PSCL_10,PWM channel 10 prescaler. The output frequency equals to clk/(PSCL_10 + 1)"
|
|
line.long 0x20 "PCP0,PWM Channel 0 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x20 16.--31. 1. "COMPARE,PWM channel 0 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x20 0.--15. 1. "PERIOD,PWM channel 0 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x24 "PCP1,PWM Channel 1 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x24 16.--31. 1. "COMPARE,PWM channel 1 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x24 0.--15. 1. "PERIOD,PWM channel 1 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x28 "PCP2,PWM Channel 2 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x28 16.--31. 1. "COMPARE,PWM channel 2 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x28 0.--15. 1. "PERIOD,PWM channel 2 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x2C "PCP3,PWM Channel 3 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x2C 16.--31. 1. "COMPARE,PWM channel 3 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x2C 0.--15. 1. "PERIOD,PWM channel 3 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x30 "PCP4,PWM Channel 4 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x30 16.--31. 1. "COMPARE,PWM channel 4 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x30 0.--15. 1. "PERIOD,PWM channel 4 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x34 "PCP5,PWM Channel 5 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x34 16.--31. 1. "COMPARE,PWM channel 5 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x34 0.--15. 1. "PERIOD,PWM channel 5 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x38 "PCP6,PWM Channel 6 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x38 16.--31. 1. "COMPARE,PWM channel 6 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x38 0.--15. 1. "PERIOD,PWM channel 6 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x3C "PCP7,PWM Channel 7 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x3C 16.--31. 1. "COMPARE,PWM channel 7 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x3C 0.--15. 1. "PERIOD,PWM channel 7 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x40 "PCP8,PWM Channel 8 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x40 16.--31. 1. "COMPARE,PWM channel 8 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x40 0.--15. 1. "PERIOD,PWM channel 8 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x44 "PCP9,PWM Channel 9 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached PWM output will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x44 16.--31. 1. "COMPARE,PWM channel 9 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x44 0.--15. 1. "PERIOD,PWM channel 9 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x48 "PCP10,PWM Channel 10 Period and Compare register. Counter will count down from period to zero. When Comapre value is reached all PWM outputs will change on next counter decrement and be stable from 'Compare-1' to 0."
|
|
hexmask.long.word 0x48 16.--31. 1. "COMPARE,PWM channel 10 compare register. 'COMPARE' must not be 0x0."
|
|
hexmask.long.word 0x48 0.--15. 1. "PERIOD,PWM channel 10 period register. The actual period equals to [PERIOD + 1]. 'PERIOD' must not be 0x0."
|
|
line.long 0x4C "PST0,PWM 1st Status Register (Channel 0 to Channel 3)"
|
|
bitfld.long 0x4C 24. "INT_FLG_3,PWM channel 3 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
bitfld.long 0x4C 16. "INT_FLG_2,PWM channel 2 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
bitfld.long 0x4C 8. "INT_FLG_1,PWM channel 1 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x4C 0. "INT_FLG_0,PWM channel 0 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
line.long 0x50 "PST1,PWM 2nd Status Register (Channel 4 to Channel 7)"
|
|
bitfld.long 0x50 24. "INT_FLG_7,PWM channel 7 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
bitfld.long 0x50 16. "INT_FLG_6,PWM channel 6 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
bitfld.long 0x50 8. "INT_FLG_5,PWM channel 5 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x50 0. "INT_FLG_4,PWM channel 4 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
line.long 0x54 "PST2,PWM 3rd Status Register (Channel 8 to Channel 10)"
|
|
bitfld.long 0x54 16. "INT_FLG_10,PWM channel 10 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
bitfld.long 0x54 8. "INT_FLG_9,PWM channel 9 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
bitfld.long 0x54 0. "INT_FLG_8,PWM channel 8 interrupt flag. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear the interrupt." "0: No interrupt pending,1: Interrupt pending"
|
|
rgroup.long 0xFFC++0x3
|
|
line.long 0x0 "MODULE_ID,PWM Module Identifier ('PW' in ASCII)"
|
|
hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. implies software modifications"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
|
|
tree.end
|
|
tree "RNG (True Random Number Generator)"
|
|
base ad:0x4000D000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RANDOM_NUMBER,Random number"
|
|
hexmask.long 0x0 0.--31. 1. "RAND_NUM,This register contains a random 32 bit number which is computed on demand at each time it is read. Weak cryptographic post-processing is used to maximize throughput. The block will start computing before the first register access and so the.."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "COUNTER_VAL,Counter values to show information about the random process"
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFRESH_CNT,Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. This gives an indication on 'entropy refill'. Note that there is no linear accumulation of entropy: as implemented today entropy refill.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CLK_RATIO,Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes. Internal clock frequencies are half the incoming ones: COUNTER_VAL = round[.."
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "COUNTER_CFG,Register linked to the comupting of statistics. not required for normal operation."
|
|
bitfld.long 0x0 5.--7. "SHIFT4X,To be used to add precision to clock_ratio and determine 'entropy refill'. Supported range is 0..4 Used as well for ONLINE_TEST" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--4. "CLOCK_SEL,Selects the internal clock on which to compute statistics. 1 is for first one 2 for second one . And 0 is for a XOR of results from all clocks" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MODE,00: disabled 01: update once. Will return to 00 once done 10: free running: updates countinuously 11: reserved" "0: disabled,1: update once,?,?"
|
|
line.long 0x4 "ONLINE_TEST_CFG,Configuration for the online test features"
|
|
bitfld.long 0x4 1.--2. "DATA_SEL,Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy (do not use) 10: RANDOM_NUMBER 11: not valid 'activate' should be set.." "0: LSB of COUNTER: raw data from one or all sources..,1: MSB of COUNTER: raw data from one or all sources..,?,?"
|
|
bitfld.long 0x4 0. "ACTIVATE,0: disabled 1: activated Update rhythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. Otherwise VAL is updated each time RANDOM_NUMBER is read" "0: disabled,1: activated Update rhythm for VAL depends on.."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "ONLINE_TEST_VAL,Online test results"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAX_CHI_SQUARED,Maximum value of LIVE_CHI_SQUARED since the last reset of this field. This field is reset when 'activate'=0"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MIN_CHI_SQUARED,Minimum value of LIVE_CHI_SQUARED since the last reset of this field. This field is reset when 'activate'=0"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LIVE_CHI_SQUARED,This value is updated as described in field 'activate'. This value is a statistic value that indicates the quality of entropy generation. Low value means good high value means no good. If 'data_sel'<10 increase 'shift4x' till 'chi' is.."
|
|
group.long 0xFF4++0x3
|
|
line.long 0x0 "POWERDOWN,Powerdown mode and reset control. generally use of this register is not necessary"
|
|
bitfld.long 0x0 31. "POWERDOWN,When set all accesses to standard registers are blocked" "0,1"
|
|
bitfld.long 0x0 1. "FORCE_SOFT_RESET,When used with softreset it forces CORE_RESETN to low on acknowledge from CORE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOFT_RESET,Request softreset that will go low automaticaly after acknowledge from CORE" "0,1"
|
|
rgroup.long 0xFFC++0x3
|
|
line.long 0x0 "MODULEID,IP identifier"
|
|
hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. implies software modifications"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
|
|
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x4000B000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRL,RTC control register"
|
|
bitfld.long 0x0 7. "RTC_EN,RTC enable. 0: Disable. The RTC 32-bit timer and 16-bit timer clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. 1: Enable. The 32-bit RTC clock is running and RTC.." "0: Disable,1: Enable"
|
|
bitfld.long 0x0 6. "RTC1KHZ_EN,RTC 16-bit timer clock enable. This bit can be set to 0 to conserve power if the 16-bit timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). 0: Disable. A match on the 16-bit RTC timer will not.." "0: Disable,1: Enable"
|
|
bitfld.long 0x0 5. "WAKEDPD_EN,RTC 16-bit timer wake-up enable for power-down modes. 0: Disable. A match on the 16-bit RTC timer will not bring the part out of power-down modes. 1: Enable. A match on the 16-bit RTC timer will bring the part out of power-down modes." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 4. "ALARMDPD_EN,RTC 32-bit timer alarm enable for Low power mode. 0: Disable. A match on the 32-bit RTC timer will not bring the part out of power-down modes. 1: Enable. A match on the 32-bit RTC timer will bring the part out of power-down modes." "0: Disable,1: Enable"
|
|
bitfld.long 0x0 3. "WAKE1KHZ,RTC 16-bit timer wake-up flag status. 0: The RTC 16-bit timer is running. Writing a 0 has no effect. 1: The 16-bit timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from low power.." "0: The RTC 16-bit timer is running,1: The 16-bit timer has timed out"
|
|
bitfld.long 0x0 2. "ALARM1HZ,RTC 32-bit timer alarm flag status. 0: No match has occurred on the 32-bit RTC timer. Writing a 0 has no effect. 1: A match condition has occurred on the 32-bit RTC timer. This flag generates an RTC alarm interrupt request. RTC_ALARM which can.." "0: No match has occurred on the 32-bit RTC timer,1: A match condition has occurred on the 32-bit RTC.."
|
|
newline
|
|
bitfld.long 0x0 0. "SWRESET,Software reset control. 0: Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. 1: In reset. The RTC is held in reset. All register bits within the RTC will be forced to.." "0: Not in reset,1: In reset"
|
|
line.long 0x4 "MATCH,RTC 32-bit counter match register"
|
|
hexmask.long 0x4 0.--31. 1. "MATVAL,Contains the match value against which the 1 Hz RTC timer will be compared to generate the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled."
|
|
line.long 0x8 "COUNT,RTC 32-bit counter register"
|
|
hexmask.long 0x8 0.--31. 1. "VAL,A read reflects the current value of the main 32-bit RTC timer. A write loads a new initial value into the timer. The RTC 32-bit counter will count up continuously at the 32-bit timer clock rate once the RTC Software Reset is removed (by clearing.."
|
|
line.long 0xC "WAKE,16-bit RTC timer register"
|
|
hexmask.long.word 0xC 0.--15. 1. "VAL,A read reflects the current value of 16-bit timer. A write pre-loads a start count value into the 16-bit timer and initializes a count-down sequence. Do not write to this register while counting is in progress."
|
|
tree.end
|
|
tree "SHA"
|
|
base ad:0x4008F000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control register"
|
|
bitfld.long 0x0 12. "HASHSWPB,If 1 will swap bytes in the word for SHA hashing. The default is byte order (so LSB is first byte) but this allows swapping to MSB is first." "0,1"
|
|
bitfld.long 0x0 9. "DMA_O,Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set the DMA has to know to switch direction and the locations. If written to 0 the DMA is not used and the processor has to read the digest/output in response to the.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DMA_I,Written with 1 to use DMA to fill INDATA. For Hash will request from DMA for 16 words and then will process the Hash. Normal model is that the DMA interrupts the processor when its length expires." "0,1"
|
|
bitfld.long 0x0 4. "NEW,Written with 1 when starting a new Hash. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. Digest/Result is initialized when New is set to 1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "MODE,Operational mode: 0: Disabled; 1: SHA1; 2: SHA2-256; 3: SHA2-512; 4-7: Not valid" "0: Disabled;,1: SHA1;,2: SHA2-256;,3: SHA2-512; 4-7: Not valid,?,?,?,?"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status Regsiter"
|
|
bitfld.long 0x0 5. "NEEDIV,Indicates the block wants an IV/NONE to be written in (set along with WAITING). 0: no IV is needed either because written already or because not needed. 1: IV needed and INDATA will be accepted as IV." "0: no IV is needed,1: IV needed and INDATA will be accepted as IV"
|
|
bitfld.long 0x0 4. "NEEDKEY,Indicates the block wants the key to be written in (set along with WAITING). 0: no key is needed and writes will not be treated as Key. 1: key is needed and INDATA will be accepted as key. Will also set WAITING." "0: no key is needed and writes will not be treated..,1: key is needed and INDATA will be accepted as key"
|
|
newline
|
|
bitfld.long 0x0 2. "ERROR,If 1 an error occurred. For normal uses this is due to an attempted overrun: INDATA was written when it was not appropriate. Write 1 to clear." "0,1"
|
|
bitfld.long 0x0 1. "DIGEST,If 1 then a DIGEST is ready and waiting and there is no active next block already started. This is cleared when any data is written when New is written or when the block is disabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAITING,Waiting Status 0: Not waiting for data may be disabled or may be busy. Note that for cryptographic uses this is not set if IsLast is set nor will it set until at least 1 word is read of the output. 1: Waiting for data to be written in (16 words)" "0: Not waiting for data may be disabled or may be..,1: Waiting for data to be written in"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "INTENSET,Interrupt Enable and Interrupt enable set function"
|
|
bitfld.long 0x0 2. "ERROR,0: Will not interrupt on Error. 1: Will interrupt on Error. Write 1 to set this bit." "0: Will not interrupt on Error,1: Will interrupt on Error"
|
|
bitfld.long 0x0 1. "DIGEST,0: Will not interrupt when Digest is ready. 1: Will interrupt when Digest is ready. Write 1 to set this bit." "0: Will not interrupt when Digest is ready,1: Will interrupt when Digest is ready"
|
|
newline
|
|
bitfld.long 0x0 0. "WAITING,0: Will not interrupt when waiting. 1: Will interrupt when waiting. Write 1 to set this bit." "0: Will not interrupt when waiting,1: Will interrupt when waiting"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "INTENCLR,Interrupt Clear Register"
|
|
bitfld.long 0x0 2. "ERROR,Write 1 to clear correspnding bit in INTENSET." "0,1"
|
|
bitfld.long 0x0 1. "DIGEST,Write 1 to clear correspnding bit in INTENSET." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAITING,Write 1 to clear correspnding bit in INTENSET." "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "MEMCTRL,Setup Master to access memory"
|
|
hexmask.long.word 0x0 16.--26. 1. "COUNT,Number of 512-bit blocks to copy starting at MEMADDR. This register will decrement after each block is copied ending in 0. For Hash the DIGEST interrupt will occur when it reaches 0. If a bus error occurs it will stop with this field set to the.."
|
|
bitfld.long 0x0 0. "MASTER,Enables Mastering. 0: Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. 1: Mastering is enabled and DMA and INDATA should not be used." "0: Mastering is not used and the normal DMA or..,1: Mastering is enabled and DMA and INDATA should.."
|
|
line.long 0x4 "MEMADDR,Address to start memory access from"
|
|
hexmask.long 0x4 0.--31. 1. "BASEADDR,This field indicates the base address in Internal Flash SRAM0 SRAMX or SPIFI to start copying from."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INDATA[$1],Input Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,In this field the next word is written in little-endian format."
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "DIGEST[$1],DIGEST or OUTD0. 5 or 8 bytes of output data. depending upon mode"
|
|
hexmask.long 0x0 0.--31. 1. "DIGEST,This field contains one word of the Digest."
|
|
repeat.end
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "MASK,Mask register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Mask register"
|
|
rgroup.long 0xFFC++0x3
|
|
line.long 0x0 "ID,IP identifier"
|
|
hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. implies software modifications"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
|
|
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "SPI0"
|
|
base ad:0x4008D000
|
|
group.long 0x400++0x13
|
|
line.long 0x0 "CFG,SPI Configuration register"
|
|
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select. Valid only for SPI-1" "0,1"
|
|
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select. Valid only for SPI-1" "0,1"
|
|
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0,1"
|
|
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode and connects transmit and receive data connected together to allow simple software testing." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0,1"
|
|
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0,1"
|
|
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0,1"
|
|
bitfld.long 0x0 2. "MASTER,Master mode select." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,SPI enable." "0,1"
|
|
line.long 0x4 "DLY,SPI Delay register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
|
|
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOFR flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOTR). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted."
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
|
|
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
|
|
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
|
|
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress as if the EOTR flag had been set prior to the last transmission. This capability is.." "0,1"
|
|
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
|
|
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy and allows waking up the device from.." "0,1"
|
|
bitfld.long 0x8 3. "TXUR,Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter.." "0,1"
|
|
bitfld.long 0x8 2. "RXOV,Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs the receiver buffer contents are.." "0,1"
|
|
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
|
|
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0,1"
|
|
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0,1"
|
|
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0,1"
|
|
bitfld.long 0xC 3. "TXUREN,TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "RXOVEN,RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The.." "0,1"
|
|
line.long 0x10 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
|
|
bitfld.long 0x10 8. "MSTIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
|
|
bitfld.long 0x10 5. "SSDCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
|
|
bitfld.long 0x10 4. "SSACLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
|
|
bitfld.long 0x10 3. "TXURCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "RXOVCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
|
|
group.long 0x420++0x7
|
|
line.long 0x0 "TXCTL,SPI Transmit Control. If Transmit FIFO is enabled. in FIFOCFG. then values read in this register are affected values in FIFO."
|
|
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data transfer Length."
|
|
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore." "0,1"
|
|
bitfld.long 0x0 21. "EOFR,End of Frame." "0,1"
|
|
bitfld.long 0x0 20. "EOTR,End of Transfer." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXSSEL3_N,[Reserved] Transmit Slave Select 3." "0,1"
|
|
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select 2. Valid only for SPI-1" "0,1"
|
|
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select 1. Valid only for SPI-1" "0,1"
|
|
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select 0." "0,1"
|
|
line.long 0x4 "DIV,SPI clock Divider"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the SPI Module clock is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in SPICLK/1 the value 1 results in SPICLK/2 up to the maximum possible divide.."
|
|
rgroup.long 0x428++0x3
|
|
line.long 0x0 "INTSTAT,SPI Interrupt Status"
|
|
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
|
|
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
|
|
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
|
|
bitfld.long 0x0 3. "TXUR,Transmitter Underrun interrupt flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXOV,Receiver Overrun interrupt flag." "0,1"
|
|
group.long 0xE00++0xB
|
|
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
|
|
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0,1"
|
|
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
|
|
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
|
|
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0,1"
|
|
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = Reset value. 0x1 = FIFO is configured as 4 entries of 16bits. This value is read after PSELID.PERSEL=2 for SPI functionlaity. 0x2 0x3 = not applicable." "0: Reset value,1: FIFO is configured as 4 entries of 16bits,?,3: not applicable"
|
|
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO. This is automatically enabled when PSELID.PERSEL is set to 2 to configure for SPI functionality" "0,1"
|
|
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO. This is automatically enabled when PSELID.PERSEL is set to 2 to configure for SPI functionality" "0,1"
|
|
line.long 0x4 "FIFOSTAT,FIFO status register."
|
|
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full the RXFULL.."
|
|
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full the TXEMPTY.."
|
|
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1 the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
|
|
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1 the receive FIFO is not empty so data can be read. When 0 the receive FIFO is empty." "0,1"
|
|
newline
|
|
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1 the transmit FIFO is not full so more data can be written. When 0 the transmit FIFO is full and another write would cause it to overflow." "0,1"
|
|
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1 the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
|
|
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1 this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral s STAT register." "0,1"
|
|
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
|
|
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
|
|
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO.."
|
|
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. ... 7 = 1 = trigger when the TX FIFO level decreases to 7 entries.."
|
|
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET or a DMA trigger if DMARX in FIFOCFG is set." "0,1"
|
|
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET or a DMA trigger if DMATX in FIFOCFG is set." "0,1"
|
|
group.long 0xE10++0x7
|
|
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
|
|
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0,1"
|
|
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0,1"
|
|
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register." "0,1"
|
|
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register." "0,1"
|
|
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
|
|
bitfld.long 0x4 3. "RXLVL,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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|
bitfld.long 0x4 2. "TXLVL,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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|
bitfld.long 0x4 1. "RXERR,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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|
bitfld.long 0x4 0. "TXERR,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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|
rgroup.long 0xE18++0x3
|
|
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
|
|
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
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|
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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|
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
|
|
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
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|
wgroup.long 0xE20++0x3
|
|
line.long 0x0 "FIFOWR,FIFO write data. FIFO data not reset by block reset"
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|
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. Note: when LEN = 0 the underrun status is.."
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|
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA." "0,1"
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|
bitfld.long 0x0 21. "EOF,End of Frame. Between frames a delay may be inserted as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0,1"
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|
bitfld.long 0x0 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0,1"
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|
newline
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|
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register." "0,1"
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|
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register." "0,1"
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|
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register." "0,1"
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|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
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|
rgroup.long 0xE30++0x3
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|
line.long 0x0 "FIFORD,FIFO read data."
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|
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e. any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
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|
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
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|
rgroup.long 0xE40++0x3
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|
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
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|
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e. any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
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|
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
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|
group.long 0xFF8++0x3
|
|
line.long 0x0 "PSELID,Peripheral function select and ID register"
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|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Peripheral Select ID."
|
|
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only and has value 0x1 to indicate SPI function is present." "0,1"
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|
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software. 0 Peripheral select can be changed by software. 1 Peripheral select is locked and cannot be changed until this peripheral or the entire device is reset." "0,1"
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bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software. Reset value is 0x0 showing that no peripheral is selected. Write 0x2 to select the SPI function. All other values are not valid." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0xFFC++0x3
|
|
line.long 0x0 "ID,SPI Module Identifier"
|
|
hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. implies software modifications"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
|
|
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
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|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x4008E000
|
|
group.long 0x400++0x13
|
|
line.long 0x0 "CFG,SPI Configuration register"
|
|
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select. Valid only for SPI-1" "0,1"
|
|
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select. Valid only for SPI-1" "0,1"
|
|
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0,1"
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|
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode and connects transmit and receive data connected together to allow simple software testing." "0,1"
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newline
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|
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0,1"
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|
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0,1"
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|
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0,1"
|
|
bitfld.long 0x0 2. "MASTER,Master mode select." "0,1"
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|
newline
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|
bitfld.long 0x0 0. "ENABLE,SPI enable." "0,1"
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|
line.long 0x4 "DLY,SPI Delay register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
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|
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOFR flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOTR). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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|
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted."
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|
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
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|
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
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|
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
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|
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress as if the EOTR flag had been set prior to the last transmission. This capability is.." "0,1"
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|
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
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|
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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|
newline
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy and allows waking up the device from.." "0,1"
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bitfld.long 0x8 3. "TXUR,Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter.." "0,1"
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|
bitfld.long 0x8 2. "RXOV,Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs the receiver buffer contents are.." "0,1"
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line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
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|
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0,1"
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|
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0,1"
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|
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0,1"
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bitfld.long 0xC 3. "TXUREN,TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available." "0,1"
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newline
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bitfld.long 0xC 2. "RXOVEN,RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The.." "0,1"
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line.long 0x10 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
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bitfld.long 0x10 8. "MSTIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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|
bitfld.long 0x10 5. "SSDCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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|
bitfld.long 0x10 4. "SSACLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x10 3. "TXURCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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newline
|
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bitfld.long 0x10 2. "RXOVCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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group.long 0x420++0x7
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line.long 0x0 "TXCTL,SPI Transmit Control. If Transmit FIFO is enabled. in FIFOCFG. then values read in this register are affected values in FIFO."
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hexmask.long.byte 0x0 24.--27. 1. "LEN,Data transfer Length."
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bitfld.long 0x0 22. "RXIGNORE,Receive Ignore." "0,1"
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|
bitfld.long 0x0 21. "EOFR,End of Frame." "0,1"
|
|
bitfld.long 0x0 20. "EOTR,End of Transfer." "0,1"
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|
newline
|
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bitfld.long 0x0 19. "TXSSEL3_N,[Reserved] Transmit Slave Select 3." "0,1"
|
|
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select 2. Valid only for SPI-1" "0,1"
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|
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select 1. Valid only for SPI-1" "0,1"
|
|
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select 0." "0,1"
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line.long 0x4 "DIV,SPI clock Divider"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the SPI Module clock is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in SPICLK/1 the value 1 results in SPICLK/2 up to the maximum possible divide.."
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|
rgroup.long 0x428++0x3
|
|
line.long 0x0 "INTSTAT,SPI Interrupt Status"
|
|
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
|
|
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
|
|
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
|
|
bitfld.long 0x0 3. "TXUR,Transmitter Underrun interrupt flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXOV,Receiver Overrun interrupt flag." "0,1"
|
|
group.long 0xE00++0xB
|
|
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
|
|
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0,1"
|
|
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
|
|
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
|
|
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0,1"
|
|
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = Reset value. 0x1 = FIFO is configured as 4 entries of 16bits. This value is read after PSELID.PERSEL=2 for SPI functionlaity. 0x2 0x3 = not applicable." "0: Reset value,1: FIFO is configured as 4 entries of 16bits,?,3: not applicable"
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|
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO. This is automatically enabled when PSELID.PERSEL is set to 2 to configure for SPI functionality" "0,1"
|
|
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO. This is automatically enabled when PSELID.PERSEL is set to 2 to configure for SPI functionality" "0,1"
|
|
line.long 0x4 "FIFOSTAT,FIFO status register."
|
|
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full the RXFULL.."
|
|
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full the TXEMPTY.."
|
|
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1 the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
|
|
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1 the receive FIFO is not empty so data can be read. When 0 the receive FIFO is empty." "0,1"
|
|
newline
|
|
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1 the transmit FIFO is not full so more data can be written. When 0 the transmit FIFO is full and another write would cause it to overflow." "0,1"
|
|
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1 the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
|
|
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1 this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral s STAT register." "0,1"
|
|
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
|
|
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
|
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hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO.."
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hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. ... 7 = 1 = trigger when the TX FIFO level decreases to 7 entries.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET or a DMA trigger if DMARX in FIFOCFG is set." "0,1"
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bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET or a DMA trigger if DMATX in FIFOCFG is set." "0,1"
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group.long 0xE10++0x7
|
|
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
|
|
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0,1"
|
|
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0,1"
|
|
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register." "0,1"
|
|
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register." "0,1"
|
|
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
|
|
bitfld.long 0x4 3. "RXLVL,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
|
|
bitfld.long 0x4 2. "TXLVL,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
|
|
bitfld.long 0x4 1. "RXERR,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
|
|
bitfld.long 0x4 0. "TXERR,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
|
|
rgroup.long 0xE18++0x3
|
|
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
|
|
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
|
|
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
|
|
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
|
|
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
|
|
wgroup.long 0xE20++0x3
|
|
line.long 0x0 "FIFOWR,FIFO write data. FIFO data not reset by block reset"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. Note: when LEN = 0 the underrun status is.."
|
|
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA." "0,1"
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|
bitfld.long 0x0 21. "EOF,End of Frame. Between frames a delay may be inserted as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0,1"
|
|
bitfld.long 0x0 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register." "0,1"
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|
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register." "0,1"
|
|
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
|
|
rgroup.long 0xE30++0x3
|
|
line.long 0x0 "FIFORD,FIFO read data."
|
|
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e. any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
|
|
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
|
|
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
newline
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
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|
rgroup.long 0xE40++0x3
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|
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
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|
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e. any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
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|
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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|
newline
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
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|
group.long 0xFF8++0x3
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|
line.long 0x0 "PSELID,Peripheral function select and ID register"
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|
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Peripheral Select ID."
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rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only and has value 0x1 to indicate SPI function is present." "0,1"
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bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software. 0 Peripheral select can be changed by software. 1 Peripheral select is locked and cannot be changed until this peripheral or the entire device is reset." "0,1"
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bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software. Reset value is 0x0 showing that no peripheral is selected. Write 0x2 to select the SPI function. All other values are not valid." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0xFFC++0x3
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|
line.long 0x0 "ID,SPI Module Identifier"
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|
hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
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|
hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. implies software modifications"
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|
hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
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hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
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|
tree.end
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tree.end
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|
tree "SPIFI (SPI Flash Interface)"
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base ad:0x40084000
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group.long 0x0++0x1F
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line.long 0x0 "CTRL,SPIFI control register"
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|
bitfld.long 0x0 31. "DMAEN,A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory.." "0,1"
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bitfld.long 0x0 30. "FBCLK,Feedback clock select. 0: Internal clock. The SPIFI samples read data using an internal clock. 1: Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. Remark: MODE3 .." "0: Internal clock,1: Feedback clock"
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bitfld.long 0x0 29. "RFCLK,Select active clock edge for input data. 0: Rising edge. Read data is sampled on rising edges on the clock as in classic SPI operation. 1: Falling edge. Read data is sampled on falling edges of the clock allowing a full serial clock of of time in.." "0: Rising edge,1: Falling edge"
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bitfld.long 0x0 28. "DUAL,Select dual protocol. 0: Quad protocol. This protocol uses IO3:0. 1: Dual protocol. This protocol uses IO1:0." "0: Quad protocol,1: Dual protocol"
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|
newline
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|
bitfld.long 0x0 27. "PRFTCH_DIS,Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. 0: Enable. Cache prefetching enabled. 1: Disable. Disables prefetching of cache lines." "0: Enable,1: Disable"
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bitfld.long 0x0 23. "MODE3,SPI Mode 3 select. 0: SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured and keeps it low while CS is HIGH. 1: SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each.." "0: SCK LOW,1: SCK HIGH"
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bitfld.long 0x0 22. "INTEN,If this bit is 1 when a command ends the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." "0,1"
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|
bitfld.long 0x0 21. "D_PRFTCH_DIS,This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." "0,1"
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|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "CSHIGH,This field controls the minimum CS high time expressed as a number of serial clock periods minus one."
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|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,This field contains the number of serial clock periods without the processor reading data in memory mode which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register."
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|
line.long 0x4 "CMD,SPIFI command register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "OPCODE,The opcode of the command (not used for some FRAMEFORM values)."
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bitfld.long 0x4 21.--23. "FRAMEFORM,This field controls the opcode and address fields. 0x0: Reserved. 0x1: Opcode. Opcode only no address. 0x2: Opcode one byte. Opcode least significant byte of address. 0x3: Opcode two bytes. Opcode two least significant bytes of address. 0x4:.." "0: Reserved,1: Opcode,2: Opcode one byte,3: Opcode two bytes,4: Opcode three bytes,5: Opcode four bytes,6: No opcode three bytes,7: No opcode four bytes"
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|
bitfld.long 0x4 19.--20. "FIELDFORM,This field controls how the fields of the command are sent. 0x0: All serial. All fields of the command are serial. 0x1: Quad/dual data. Data field is quad/dual other fields are serial. 0x2: Serial opcode. Opcode field is serial. Other fields.." "0: All serial,1: Quad/dual data,2: Serial opcode,3: All quad/dual"
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bitfld.long 0x4 16.--18. "INTLEN,This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles depending on whether the intermediate field is in serial 2-bit or 4-bit format.) Intermediate bytes are output by the SPIFI and.." "?,?,2: bit,?,4: bit format,?,?,?"
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newline
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bitfld.long 0x4 15. "DOUT,If the DATALEN field is not zero this bit controls the direction of the data: 0: Input from serial flash. 1: Output to serial flash." "0: Input from serial flash,1: Output to serial flash"
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bitfld.long 0x4 14. "POLL,This bit should be written as 1 only with an opcode that a) contains an input data field and b) causes the serial flash device to return byte status repetitively (e.g. a Read Status command). When this bit is 1 the SPIFI hardware continues to.." "0,1"
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hexmask.long.word 0x4 0.--13. 1. "DATALEN,Except when the POLL bit in this register is 1 this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field."
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|
line.long 0x8 "ADDR,SPIFI address register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,SPIFI address register"
|
|
line.long 0xC "IDATA,SPIFI intermediate data register"
|
|
hexmask.long 0xC 0.--31. 1. "IDATA,SPIFI intermediate data register"
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|
line.long 0x10 "CLIMIT,SPIFI limit register"
|
|
hexmask.long 0x10 0.--31. 1. "CLIMIT,SPIFI limit register"
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|
line.long 0x14 "DATA,SPIFI data register. Input or output data"
|
|
hexmask.long 0x14 0.--31. 1. "DATA,SPIFI data register. Input or output data"
|
|
line.long 0x18 "MCMD,SPIFI memory command register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "OPCODE,The opcode of the command (not used for some FRAMEFORM values)."
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|
bitfld.long 0x18 21.--23. "FRAMEFORM,This field controls the opcode and address fields. 0x0: Reserved. 0x1: Opcode. Opcode only no address. 0x2: Opcode one byte. Opcode least-significant byte of address. 0x3: Opcode two bytes. Opcode 2 least-significant bytes of address. 0x4:.." "0: Reserved,1: Opcode,2: Opcode one byte,3: Opcode two bytes,4: Opcode three bytes,5: Opcode four bytes,6: No opcode three bytes,7: No opcode"
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bitfld.long 0x18 19.--20. "FIELDFORM,This field controls how the fields of the command are sent. 0x0 All serial. All fields of the command are serial. 0x1 Quad/dual data. Data field is quad/dual other fields are serial. 0x2 Serial opcode. Opcode field is serial. Other fields are.." "0,1,2,3"
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bitfld.long 0x18 16.--18. "INTLEN,This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles depending on whether the intermediate field is in serial 2-bit or 4-bit format.) Intermediate bytes are output by the SPIFI and.." "?,?,2: bit,?,4: bit format,?,?,?"
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|
newline
|
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bitfld.long 0x18 15. "DOUT,This bit should be written as 0." "0,1"
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|
bitfld.long 0x18 14. "POLL,This bit should be written as 0." "0,1"
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|
line.long 0x1C "STAT,SPIFI status register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "VERSION,no description available"
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|
bitfld.long 0x1C 5. "INTRQ,This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." "0,1"
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bitfld.long 0x1C 4. "RESET,Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." "0,1"
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bitfld.long 0x1C 1. "CMD,This bit is 1 when the Command register is written. It is cleared by a hardware reset a write to the RESET bit in this register or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." "0,1"
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|
newline
|
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bitfld.long 0x1C 0. "MCINIT,This bit is set when software successfully writes the Memory Command register and is cleared by Reset or by writing a 1 to the RESET bit in this register." "0,1"
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|
tree.end
|
|
tree "SYSCON (System Configuration)"
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|
base ad:0x40000000
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group.long 0x0++0x3
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line.long 0x0 "MEMORYREMAP,Memory Remap control register"
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|
bitfld.long 0x0 26.--27. "QSPI_REMAP_APP_3,Address bits to use when QSPI Flash address [19:18] = 3 (256-KB unit page). Setting 11 gives no remapping." "0,1,2,3"
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|
newline
|
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bitfld.long 0x0 24.--25. "QSPI_REMAP_APP_2,Address bits to use when QSPI Flash address [19:18] = 2 (256-KB unit page). Setting 10 gives no remapping." "0,1,2,3"
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|
newline
|
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bitfld.long 0x0 22.--23. "QSPI_REMAP_APP_1,Address bits to use when QSPI Flash address [19:18] = 1 (256-KB unit page). Setting 01 gives no remapping." "0,1,2,3"
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newline
|
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bitfld.long 0x0 20.--21. "QSPI_REMAP_APP_0,Address bits to use when QSPI Flash address [19:18] = 0 (256-KB unit page). Setting 00 gives no remapping." "0,1,2,3"
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newline
|
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bitfld.long 0x0 0.--1. "MAP,Select the location of the vector table : 0: Vector Table in ROM. 1: Vector Table in RAM. 2: Vector Table in Flash. 3: Vector Table in Flash." "0: Vector Table in ROM,1: Vector Table in RAM,2: Vector Table in Flash,3: Vector Table in Flash"
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|
group.long 0x10++0x3
|
|
line.long 0x0 "AHBMATPRIO,AHB Matrix priority control register"
|
|
hexmask.long 0x0 0.--31. 1. "AHBMATPRIO,AHB Matrix priority control register"
|
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group.long 0x40++0x3
|
|
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
|
|
bitfld.long 0x0 25. "NOREF,Cortex System tick timer SYST_CALIB.NOREF setting. When 0 a separate reference clock is available. When 1 a separate reference clock is not available." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SKEW,Cortex System tick timer SYST_CALIB.SKEW setting. When 0 the value of SYST_CALIB.TENMS field is considered to be precise. When 1 the value of TENMS is not considered to be precise." "0,1"
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|
newline
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,Cortex System tick timer calibration value readable from Cortex SYST_CALIB.TENMS register field. Set this value to be the number of clock periods to give 10ms period. SYSTICK freq is a function of the mainclk and SYSTICKCLKDIV register. If the tick.."
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|
group.long 0x48++0x7
|
|
line.long 0x0 "NMISRC,NMI Source Select"
|
|
bitfld.long 0x0 31. "NMIENM40,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM40. The NMI Interrupt should be disabled before changing the source selection (IRQM40)" "0,1"
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|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "IRQM40,The number of the interrupt source within the interrupt array that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4 if enabled by NMIENM40. This can also cause the device to wakeup from sleep."
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line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
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bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem" "0,1"
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|
group.long 0x100++0x3
|
|
line.long 0x0 "PRESETCTRL0,Peripheral reset control 0"
|
|
bitfld.long 0x0 27. "ADC_RST,ADC reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 25. "WAKE_UP_TIMERS_RST,Wake up Timers reset control. 0: Clear reset to this function. 1: Assert reset to this function. This will clear interrupt status flag. However configuration for wake timers that is in SYSCON will not be reset these should be managed.." "0: Clear reset to this function,1: Assert reset to this function"
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|
newline
|
|
bitfld.long 0x0 24. "ANA_INT_CTRL_RST,Analog Modules Interrupt Controller reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
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|
newline
|
|
bitfld.long 0x0 23. "RTC_RST,Real Time Clock (RTC) reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 22. "WWDT_RST,Watchdog Timer reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 21. "ISO7816_RST,ISO7816 reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 20. "DMA_RST,DMA reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 19. "GINT_RST,Group interrupt (GINT) reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 14. "GPIO_RST,GPIO reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 13. "IOCON_RST,I/O controller reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 12. "BLE_TIMING_GEN_RST,BLE Low Power Control module reset. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 11. "MUX_RST,Input Mux reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x0 10. "SPIFI_RST,Quad SPI Flash controller reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "PRESETCTRLS0,Pin assign register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
line.long 0x4 "PRESETCTRL1,Peripheral reset control 1"
|
|
bitfld.long 0x4 27. "HASH_RST,HASH reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 26. "DMIC_RST,DMIC Reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 25. "RFP_RST,RFP (Radio controller) reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 24. "AES_RST,AES256 reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 23. "MODEM_MASTER_RST,MODEM AHB Master Interface reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 22. "BLE_RST,BLE reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 21. "ZIGBEE_RST,Zigbee reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 19. "RNG_RST,Random Number Generator reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 18. "PWM_RST,PWM reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 17. "IR_RST,Infra Red reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 16. "SPI1_RST,SPI1 reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 15. "SPI0_RST,SPI0 reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 14. "I2C1_RST,I2C1 reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 13. "I2C0_RST,I2C0 reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 12. "USART1_RST,UART1 reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
newline
|
|
bitfld.long 0x4 11. "USART0_RST,UART0 reset control. 0: Clear reset to this function. 1: Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "PRESETCTRLS1,Pin assign register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PRESETCTRLSET0,Set bits in PRESETCTRL0. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers."
|
|
bitfld.long 0x0 27. "ADC_RST_SET,Writing one to this register sets the ADC_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "WAKE_UP_TIMERS_RST_SET,Writing one to this register sets the WAKE_UP_TIMERS bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ANA_INT_CTRL_RST_SET,Writing one to this register sets the ANA_INT_CTRL_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RTC_RST_SET,Writing one to this register sets the RTC_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "WWDT_RST_SET,Writing one to this register sets the WWDT_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ISO7816_RST_SET,Writing one to this register sets the ISO7816_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DMA_RST_SET,Writing one to this register sets the DMA_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GINT_RST_SET,Writing one to this register sets the GINT_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PINT_RST_SET,Writing one to this register sets the PINT_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "GPIO_RST_SET,Writing one to this register sets the GPIO_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IOCON_RST_SET,Writing one to this register sets the IOCON_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BLE_TIMING_GEN_RST_SET,Writing one to this register sets the BLE_TIMING_GEN_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MUX_RST_SET,Writing one to this register sets the MUX_RST bit in the PRESETCTRL0 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPIFI_RST_SET,Writing one to this register sets the SPIFI_RST bit in the PRESETCTRL0 register" "0,1"
|
|
group.long 0x120++0x3
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line.long 0x0 "PRESETCTRLSETS0,Pin assign register"
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|
hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
wgroup.long 0x124++0x3
|
|
line.long 0x0 "PRESETCTRLSET1,Set bits in PRESETCTRL1. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers."
|
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bitfld.long 0x0 27. "HASH_RST_SET,Writing one to this register sets the HASH_RST bit in the PRESETCTRL1 register" "0,1"
|
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bitfld.long 0x0 26. "DMIC_RST_SET,Writing one to this register sets the DMIC_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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|
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bitfld.long 0x0 25. "RFP_RST_SET,Writing one to this register sets the RFP_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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|
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bitfld.long 0x0 24. "AES_RST_SET,Writing one to this register sets the AES_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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bitfld.long 0x0 23. "MODEM_MASTER_RST_SET,Writing one to this register sets the MODEM_MASTER_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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bitfld.long 0x0 22. "BLE_RST_SET,Writing one to this register sets the BLE_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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|
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bitfld.long 0x0 21. "ZIGBEE_RST_SET,Writing one to this register sets the ZIGBEE_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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|
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bitfld.long 0x0 19. "RNG_RST_SET,Writing one to this register sets the RNG_RST bit in the PRESETCTRL1 register" "0,1"
|
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bitfld.long 0x0 18. "PWM_RST_SET,Writing one to this register sets the PWM_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 17. "IR_RST_SET,Writing one to this register sets the IR_RST bit in the PRESETCTRL1 register" "0,1"
|
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bitfld.long 0x0 16. "SPI1_RST_SET,Writing one to this register sets the SPI1_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 15. "SPI0_RST_SET,Writing one to this register sets the SPI0_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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bitfld.long 0x0 14. "I2C1_RST_SET,Writing one to this register sets the I2C1_RST bit in the PRESETCTRL1 register" "0,1"
|
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bitfld.long 0x0 13. "I2C0_RST_SET,Writing one to this register sets the I2C0_RST bit in the PRESETCTRL1 register" "0,1"
|
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bitfld.long 0x0 12. "USART1_RST_SET,Writing one to this register sets the UART1_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 11. "USART0_RST_SET,Writing one to this register sets the UART0_RST bit in the PRESETCTRL1 register" "0,1"
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group.long 0x124++0x3
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line.long 0x0 "PRESETCTRLSETS1,Pin assign register"
|
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
wgroup.long 0x140++0x3
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line.long 0x0 "PRESETCTRLCLR0,Clear bits in PRESETCTRL0. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers."
|
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bitfld.long 0x0 27. "ADC_RST_CLR,Writing one to this register clears the ADC_RST bit in the PRESETCTRL0 register" "0,1"
|
|
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bitfld.long 0x0 25. "WAKE_UP_TIMERS_RST_CLR,Writing one to this register clears the WAKE_UP_TIMERS_RST bit in the PRESETCTRL0 register" "0,1"
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bitfld.long 0x0 24. "ANA_INT_CTRL_RST_CLR,Writing one to this register clears the ANA_INT_CTRL_RST bit in the PRESETCTRL0 register" "0,1"
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bitfld.long 0x0 23. "RTC_RST_CLR,Writing one to this register clears the RTC_RST bit in the PRESETCTRL0 register" "0,1"
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bitfld.long 0x0 22. "WWDT_RST_CLR,Writing one to this register clears the WWDT_RST bit in the PRESETCTRL0 register" "0,1"
|
|
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bitfld.long 0x0 21. "ISO7816_RST_CLR,Writing one to this register clears the ISO7816_RST bit in the PRESETCTRL0 register" "0,1"
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|
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|
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bitfld.long 0x0 20. "DMA_RST_CLR,Writing one to this register clears the DMA_RST bit in the PRESETCTRL0 register" "0,1"
|
|
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bitfld.long 0x0 19. "GINT_RST_CLR,Writing one to this register clears the GINT_RST bit in the PRESETCTRL0 register" "0,1"
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bitfld.long 0x0 18. "PINT_RST_CLR,Writing one to this register clears the PINT_RST bit in the PRESETCTRL0 register" "0,1"
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bitfld.long 0x0 14. "GPIO_RST_CLR,Writing one to this register clears the GPIO_RST bit in the PRESETCTRL0 register" "0,1"
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bitfld.long 0x0 13. "IOCON_RST_CLR,Writing one to this register clears the IOCON_RST bit in the PRESETCTRL0 register" "0,1"
|
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bitfld.long 0x0 12. "BLE_TIMING_GEN_RST_CLR,Writing one to this register clears the BLE_TIMING_GEN_RST bit in the PRESETCTRL0 register" "0,1"
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bitfld.long 0x0 11. "MUX_RST_CLR,Writing one to this register clears the MUX_RST bit in the PRESETCTRL0 register" "0,1"
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bitfld.long 0x0 10. "SPIFI_RST_CLR,Writing one to this register clears the SPIFI_RST bit in the PRESETCTRL0 register" "0,1"
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group.long 0x140++0x3
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line.long 0x0 "PRESETCTRLCLRS0,Pin assign register"
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
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wgroup.long 0x144++0x3
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line.long 0x0 "PRESETCTRLCLR1,Clear bits in PRESETCTRL1. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers."
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bitfld.long 0x0 27. "HASH_RST_CLR,Writing one to this register clears the HASH_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 26. "DMIC_RST_CLR,Writing one to this register clears the DMIC_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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|
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bitfld.long 0x0 25. "RFP_RST_CLR,Writing one to this register clears the RFP_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 24. "AES_RST_CLR,Writing one to this register clears the AES_RST bit in the PRESETCTRL1 register" "0,1"
|
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bitfld.long 0x0 23. "MODEM_MASTER_RST_CLR,Writing one to this register clears the MODEM_MASTER_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 22. "BLE_RST_CLR,Writing one to this register clears the BLE_RST bit in the PRESETCTRL1 register" "0,1"
|
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bitfld.long 0x0 21. "ZIGBEE_RST_CLR,Writing one to this register clears the ZIGBEE_RST bit in the PRESETCTRL1 register" "0,1"
|
|
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|
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bitfld.long 0x0 19. "RNG_RST_CLR,Writing one to this register clears the RNG_RST bit in the PRESETCTRL1 register" "0,1"
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|
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bitfld.long 0x0 18. "PWM_RST_CLR,Writing one to this register clears the PWM_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 17. "IR_RST_CLR,Writing one to this register clears the IR_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 16. "SPI1_RST_CLR,Writing one to this register clears the SPI1_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 15. "SPI0_RST_CLR,Writing one to this register clears the SPI0_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 14. "I2C1_RST_CLR,Writing one to this register clears the I2C1_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 13. "I2C0_RST_CLR,Writing one to this register clears the I2C0_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 12. "USART1_RST_CLR,Writing one to this register clears the UART1_RST bit in the PRESETCTRL1 register" "0,1"
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bitfld.long 0x0 11. "USART0_RST_CLR,Writing one to this register clears the UART0_RST bit in the PRESETCTRL1 register" "0,1"
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group.long 0x144++0x3
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line.long 0x0 "PRESETCTRLCLRS1,Pin assign register"
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
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group.long 0x200++0x3
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line.long 0x0 "AHBCLKCTRL0,AHB Clock control 0"
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bitfld.long 0x0 27. "ADC,Enables the clock for the ADC Controller. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x0 25. "WAKE_UP_TIMERS,Enables the clock for the Wake up Timers. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x0 24. "ANA_INT_CTRL,Enables the clock for the Analog Interrupt Control module (for BOD and comparator status and interrupt control). 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x0 23. "RTC,Enables the clock for the RTC. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x0 21. "ISO7816,Enables the clock for the ISO7816 smart card interface. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x0 19. "GINT,Enables the clock for the Group interrupt block (GINT). 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x0 18. "PINT,Enables the clock for the Pin interrupt block (PINT). 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x0 14. "GPIO,Enables the clock for the GPIO. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x0 13. "IOCON,Enables the clock for the I/O controller block. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x0 11. "MUX,Enables the clock for the Input Mux. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x0 10. "SPIFI,Enables the clock for the Quad SPI Flash controller [Note: SPIFI IOs need configuring for high drive]. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x0 4. "SRAM_CTRL1,Enables the clock for the SRAM Controller 1 (SRAM 8 to SRAM 11). 0: Disable. 1: Enable." "0: Disable,1: Enable"
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bitfld.long 0x0 3. "SRAM_CTRL0,Enables the clock for the SRAM Controller 0 (SRAM 0 to SRAM 7). 0: Disable. 1: Enable." "0: Disable,1: Enable"
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group.long 0x200++0x7
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line.long 0x0 "AHBCLKCTRLS0,Pin assign register"
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
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line.long 0x4 "AHBCLKCTRL1,AHB Clock control 1"
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bitfld.long 0x4 27. "HASH,Enable the clock for the Hash. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x4 26. "DMIC,Enable the clock for the DMIC. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 25. "RFP,Enable the clock for the RFP (Radio Front End controller). 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 24. "AES,Enable the clock for the AES. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 23. "MODEM_MASTER,Enable the clock for the Modem AHB Master Interface. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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bitfld.long 0x4 22. "BLE,Enable the clock for the BLE Modem. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 21. "ZIGBEE,Enable the clock for the Zigbee Modem . 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 19. "RNG,Enable the clock for the Random Number Generator. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x4 18. "PWM,Enable the clock for the PWM. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x4 17. "IR,Enable the clock for the Infra Red. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 16. "SPI1,Enable the clock for the SPI1. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 15. "SPI0,Enable the clock for the SPI0. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x4 14. "I2C1,Enable the clock for the I2C1. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x4 13. "I2C0,Enable the clock for the I2C0. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 12. "USART1,Enable the clock for the UART1. 0: Disable. 1: Enable." "0: Disable,1: Enable"
|
|
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|
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bitfld.long 0x4 11. "USART0,Enable the clock for the UART0. 0: Disable. 1: Enable." "0: Disable,1: Enable"
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group.long 0x204++0x3
|
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line.long 0x0 "AHBCLKCTRLS1,Pin assign register"
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
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wgroup.long 0x220++0x3
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line.long 0x0 "AHBCLKCTRLSET0,Set bits in AHBCLKCTRL0"
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bitfld.long 0x0 27. "ADC_CLK_SET,Writing one to this register sets the ADC bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 25. "WAKE_UP_TIMERS_CLK_SET,Writing one to this register sets the WAKE_UP_TIMERS bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 24. "ANA_INT_CTRL_CLK_SET,Writing one to this register sets the ANA_INT_CTRL bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 23. "RTC_CLK_SET,Writing one to this register sets the RTC bit in the AHBCLKCTRL0 register." "0,1"
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|
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bitfld.long 0x0 22. "WWDT_CLK_SET,Writing one to this register sets the WWDT bit in the AHBCLKCTRL0 register." "0,1"
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|
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|
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bitfld.long 0x0 21. "ISO7816_CLK_SET,Writing one to this register sets the ISO7816 bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 20. "DMA_CLK_SET,Writing one to this register sets the DMA bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 19. "GINT_CLK_SET,Writing one to this register sets the GINT bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 18. "PINT_CLK_SET,Writing one to this register sets the PINT bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 14. "GPIO_CLK_SET,Writing one to this register sets the GPIO bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 13. "IOCON_CLK_SET,Writing one to this register sets the IOCON bit in the AHBCLKCTRL0 register." "0,1"
|
|
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|
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bitfld.long 0x0 11. "MUX_CLK_SET,Writing one to this register sets the MUX bit in the AHBCLKCTRL0 register." "0,1"
|
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|
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bitfld.long 0x0 10. "SPIFI_CLK_SET,Writing one to this register sets the SPIFI bit in the AHBCLKCTRL0 register." "0,1"
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|
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bitfld.long 0x0 4. "SRAM_CTRL1_CLK_SET,Writing one to this register sets the SRAM_CTRL1 bit in the AHBCLKCTRL0 register." "0,1"
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|
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bitfld.long 0x0 3. "SRAM_CTRL0_CLK_SET,Writing one to this register sets the SRAM_CTRL0 bit in the AHBCLKCTRL0 register." "0,1"
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group.long 0x220++0x3
|
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line.long 0x0 "AHBCLKCTRLSETS0,Pin assign register"
|
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
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wgroup.long 0x224++0x3
|
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line.long 0x0 "AHBCLKCTRLSET1,Set bits in AHBCLKCTRL1"
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bitfld.long 0x0 27. "HASH_CLK_SET,Writing one to this register sets the HASH bit in the AHBCLKCTRL1 register." "0,1"
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bitfld.long 0x0 26. "DMIC_CLK_SET,Writing one to this register sets the DMIC bit in the AHBCLKCTRL1 register." "0,1"
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|
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bitfld.long 0x0 25. "RFP_CLK_SET,Writing one to this register sets the RFP bit in the AHBCLKCTRL1 register." "0,1"
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bitfld.long 0x0 24. "AES_CLK_SET,Writing one to this register sets the AES bit in the AHBCLKCTRL1 register." "0,1"
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|
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bitfld.long 0x0 23. "MODEM_MASTER_CLK_SET,Writing one to this register sets the MODEM_MASTER bit in the AHBCLKCTRL1 register." "0,1"
|
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|
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bitfld.long 0x0 22. "BLE_CLK_SET,Writing one to this register sets the BLE bit in the AHBCLKCTRL1 register." "0,1"
|
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|
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bitfld.long 0x0 21. "ZIGBEE_CLK_SET,Writing one to this register sets the ZIGBEE bit in the AHBCLKCTRL1 register." "0,1"
|
|
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|
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bitfld.long 0x0 19. "RNG_CLK_SET,Writing one to this register sets the RNG bit in the AHBCLKCTRL1 register." "0,1"
|
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bitfld.long 0x0 18. "PWM_CLK_SET,Writing one to this register sets the PWM bit in the AHBCLKCTRL1 register." "0,1"
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|
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bitfld.long 0x0 17. "IR_CLK_SET,Writing one to this register sets the IR bit in the AHBCLKCTRL1 register." "0,1"
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|
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bitfld.long 0x0 16. "SPI1_CLK_SET,Writing one to this register sets the SPI1 bit in the AHBCLKCTRL1 register." "0,1"
|
|
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|
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bitfld.long 0x0 15. "SPI0_CLK_SET,Writing one to this register sets the SPI0 bit in the AHBCLKCTRL1 register." "0,1"
|
|
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|
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bitfld.long 0x0 14. "I2C1_CLK_SET,Writing one to this register sets the I2C1 bit in the AHBCLKCTRL1 register." "0,1"
|
|
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|
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bitfld.long 0x0 13. "I2C0_CLK_SET,Writing one to this register sets the I2C0 bit in the AHBCLKCTRL1 register." "0,1"
|
|
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|
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bitfld.long 0x0 12. "USART1_CLK_SET,Writing one to this register sets the UART1 bit in the AHBCLKCTRL1 register." "0,1"
|
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|
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bitfld.long 0x0 11. "USART0_CLK_SET,Writing one to this register sets the UART0 bit in the AHBCLKCTRL1 register." "0,1"
|
|
group.long 0x224++0x3
|
|
line.long 0x0 "AHBCLKCTRLSETS1,Pin assign register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "AHBCLKCTRLCLR0,Clear bits in AHBCLKCTRL0"
|
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bitfld.long 0x0 28. "EFUSE_CLK_CLR,Writing one to this register clears the EFUSE bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 27. "ADC_CLK_CLR,Writing one to this register clears the ADC bit in the AHBCLKCTRL0 register." "0,1"
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bitfld.long 0x0 25. "WAKE_UP_TIMERS_CLK_SET,Writing one to this register clears the WAKE_UP_TIMERS bit in the AHBCLKCTRL0 register." "0,1"
|
|
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|
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bitfld.long 0x0 24. "ANA_INT_CTRL_CLK_SET,Writing one to this register clears the ANA_INT_CTRL bit in the AHBCLKCTRL0 register." "0,1"
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|
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|
|
bitfld.long 0x0 23. "RTC_CLK_CLR,Writing one to this register clears the RTC bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "WWDT_CLK_CLR,Writing one to this register clears the WWDT bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ISO7816_CLK_CLR,Writing one to this register clears the ISO7816 bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DMA_CLK_CLR,Writing one to this register clears the DMA bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GINT_CLK_CLR,Writing one to this register clears the GINT bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PINT_CLK_CLR,Writing one to this register clears the PINT bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "GPIO_CLK_CLR,Writing one to this register clears the GPIO bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IOCON_CLK_CLR,Writing one to this register clears the IOCON bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MUX_CLK_CLR,Writing one to this register clears the MUX bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPIFI_CLK_CLR,Writing one to this register clears the SPIFI bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FLASH_CLK_CLR,Writing one to this register clears the FLASH bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SRAM_CTRL1_CLK_CLR,Writing one to this register clears the SRAM_CTRL1 bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SRAM_CTRL0_CLK_CLR,Writing one to this register clears the SRAM_CTRL0 bit in the AHBCLKCTRL0 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ROM_CLK_CLR,Writing one to this register clears the ROM bit in the AHBCLKCTRL0 register." "0,1"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "AHBCLKCTRLCLRS0,Pin assign register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
wgroup.long 0x244++0x3
|
|
line.long 0x0 "AHBCLKCTRLCLR1,Clear bits in AHBCLKCTRL1"
|
|
bitfld.long 0x0 27. "HASH_CLK_CLR,Writing one to this register clears the HASH bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "DMIC_CLK_CLR,Writing one to this register clears the DMIC bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RFP_CLK_CLR,Writing one to this register clears the RFP bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "AES_CLK_CLR,Writing one to this register clears the AES bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MODEM_MASTER_CLK_CLR,Writing one to this register clears the MODEM_MASTER bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "BLE_CLK_CLR,Writing one to this register clears the BLE bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ZIGBEE_CLK_CLR,Writing one to this register clears the ZIGBEE bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RNG_CLK_CLR,Writing one to this register clears the RNG bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PWM_CLK_CLR,Writing one to this register clears the PWM bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "IR_CLK_CLR,Writing one to this register clears the IR bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPI1_CLK_CLR,Writing one to this register clears the SPI1 bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SPI0_CLK_CLR,Writing one to this register clears the SPI0 bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "I2C1_CLK_CLR,Writing one to this register clears the I2C1 bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I2C0_CLK_CLR,Writing one to this register clears the I2C0 bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "USART1_CLK_CLR,Writing one to this register clears the UART1 bit in the AHBCLKCTRL1 register." "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "USART0_CLK_CLR,Writing one to this register clears the UART0 bit in the AHBCLKCTRL1 register." "0,1"
|
|
group.long 0x244++0x3
|
|
line.long 0x0 "AHBCLKCTRLCLRS1,Pin assign register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
group.long 0x280++0xB
|
|
line.long 0x0 "MAINCLKSEL,Main clock source select"
|
|
bitfld.long 0x0 0.--2. "SEL,Main clock source selection:" "0: 12 MHz free running oscillator (FRO),?,2: 32 MHz crystal oscillator (XTAL),3: 32 MHz free running oscillator (FRO),4: 48 MHz free running oscillator (FRO),?,?,?"
|
|
line.long 0x4 "OSC32CLKSEL,OSC32KCLK and OSC32MCLK clock sources select. Note: this register is not locked by CLOCKGENUPDATELOCKOUT"
|
|
bitfld.long 0x4 1. "SEL32KHZ,OSC32KCLK clock source selection" "0: 32 KHz free running oscillator (FRO),1: 32 KHz crystal oscillator"
|
|
newline
|
|
bitfld.long 0x4 0. "SEL32MHZ,OSC32MCLK clock source selection" "0: 32 MHz free running oscillator (FRO),1: 32 MHz crystal oscillator"
|
|
line.long 0x8 "CLKOUTSEL,CLKOUT clock source select"
|
|
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: CPU & System Bus clock,1: 32 KHz crystal oscillator (XTAL),2: 32 KHz free running oscillator (FRO),3: 32 MHz crystal oscillator (XTAL),?,5: 48 MHz free running oscillator (FRO),6: 1 MHz free running oscillator (FRO),7: No clock"
|
|
group.long 0x2A0++0x7
|
|
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
|
|
bitfld.long 0x0 0.--2. "SEL,SPIFICLK clock source selection" "0: CPU & System Bus clock,1: 32 MHz crystal oscillator (XTAL),2: No clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock"
|
|
line.long 0x4 "ADCCLKSEL,ADC clock source select"
|
|
bitfld.long 0x4 0.--1. "SEL,ADCCLK clock source selection" "0: 32 MHz crystal oscillator (XTAL),1: FRO 12 MHz,?,3: No clock"
|
|
group.long 0x2B0++0x17
|
|
line.long 0x0 "USARTCLKSEL,USART0 & 1 clock source select"
|
|
bitfld.long 0x0 0.--1. "SEL,USARTCLK (USART0 & 1) clock source selection" "0: Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL),1: 48 MHz free running oscillator (FRO),2: Fractional Rate Generator clock (see FRGCLKSEL),3: No clock"
|
|
line.long 0x4 "I2CCLKSEL,I2C0. 1 and 2 clock source select"
|
|
bitfld.long 0x4 0.--1. "SEL,I2CCLK (I2C0 & 1) clock source selection" "0: Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL),1: 48 MHz free running oscillator (FRO),?,3: No clock"
|
|
line.long 0x8 "SPICLKSEL,SPI0 & 1 clock source select"
|
|
bitfld.long 0x8 0.--1. "SEL,SPICLK (SPI0 & 1) clock source selection" "0: Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL),1: 48 MHz free running oscillator (FRO),?,3: No clock"
|
|
line.long 0xC "IRCLKSEL,Infra Red clock source select"
|
|
bitfld.long 0xC 0.--1. "SEL,IRCLK (IR Blaster) clock source selection" "0: Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL),1: 48 MHz free running oscillator (FRO),?,3: No clock"
|
|
line.long 0x10 "PWMCLKSEL,PWM clock source select"
|
|
bitfld.long 0x10 0.--1. "SEL,PWMCLK (PWM) clock source selection" "0: Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL),1: 48 MHz free running oscillator (FRO),?,3: No Clock"
|
|
line.long 0x14 "WDTCLKSEL,Watchdog Timer clock source select"
|
|
bitfld.long 0x14 0.--1. "SEL,WDTCLK (Watchdog Timer) clock source selection" "0: Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL),1: Either 32 KHz FRO or 32 KHz XTAL (see OSC32CLKSEL),2: 1 MHz FRO,3: No Clock"
|
|
group.long 0x2CC++0x3
|
|
line.long 0x0 "MODEMCLKSEL,Modem clock source select"
|
|
bitfld.long 0x0 1. "SEL_BLE,BLE 32 MHz clock source selection" "0: 32 MHz XTAL,1: No Clock"
|
|
newline
|
|
bitfld.long 0x0 0. "SEL_ZIGBEE,Zigbee Modem clock source selection" "0: 32 MHz XTAL,1: No Clock"
|
|
group.long 0x2E8++0xB
|
|
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator (FRG) clock source select. The FRG is one of the USART clocking options."
|
|
bitfld.long 0x0 0.--1. "SEL,Fractional Rate Generator clock source selection" "0: System Bus clock,1: Either 32 MHz FRO or 32 MHz XTAL (see OSC32CLKSEL),2: 48 MHz free running oscillator (FRO),3: No Clock"
|
|
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
|
|
bitfld.long 0x4 0.--2. "SEL,DMIC clock source selection" "0: System Bus clock,1: Either 32 KHz FRO or 32 KHz XTAL (see OSC32CLKSEL),2: 48 MHz free running oscillator (FRO),3: External clock,4: 1 MHz free running oscillator (FRO),5: 12 MHz free running oscillator (FRO),?,7: No Clock"
|
|
line.long 0x8 "WKTCLKSEL,Wake-up Timer clock select"
|
|
bitfld.long 0x8 0.--1. "SEL,Wake-up Timers clock source selection" "0: Either 32 KHz FRO or 32 KHz XTAL (see OSC32CLKSEL),?,?,3: No Clock"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider. The SYSTICK clock can drive the SYSTICK function within the processor."
|
|
rbitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256."
|
|
line.long 0x4 "TRACECLKDIV,TRACE clock divider. used for part of the Serial debugger (SWD) feature."
|
|
rbitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256."
|
|
group.long 0x36C++0x3
|
|
line.long 0x0 "WDTCLKDIV,Watchdog Timer clock divider"
|
|
rbitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256."
|
|
group.long 0x378++0x3
|
|
line.long 0x0 "IRCLKDIV,Infra Red clock divider"
|
|
rbitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 15: Divide by 16."
|
|
group.long 0x380++0x7
|
|
line.long 0x0 "AHBCLKDIV,System clock divider"
|
|
rbitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256."
|
|
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
|
|
rbitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 15: Divide by 16."
|
|
group.long 0x390++0xB
|
|
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
|
|
rbitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 3: Divide by 4." "0: Divide by 1 and,?,?,3: Divide by 4"
|
|
line.long 0x4 "ADCCLKDIV,ADC clock divider"
|
|
rbitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 7: Divide by 8." "0: Divide by 1 and,?,?,?,?,?,?,7: Divide by 8"
|
|
line.long 0x8 "RTCCLKDIV,Real Time Clock divider (1 KHz clock generation)"
|
|
rbitfld.long 0x8 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x8 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 31: Divide by 32."
|
|
group.long 0x3A0++0x3
|
|
line.long 0x0 "FRGCTRL,Fractional rate generator divider. The FRG is one of the USART clocking options."
|
|
hexmask.long.byte 0x0 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV,Denominator of the fractional divider is equal to the (DIV+1). Always set to 0xFF to use with the fractional baud rate generator : fout = fin / (1 + MULT/(DIV+1))"
|
|
group.long 0x3A8++0x7
|
|
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
|
|
rbitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider setting divider ratio is (DIV+1). E.g. 0: Divide by 1 and 255: Divide by 256."
|
|
line.long 0x4 "RTC1HZCLKDIV,Real Time Clock divider (1 Hz clock generation. The divider is fixed to 32768)"
|
|
rbitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider s clock source to be changed without the risk of a glitch at the output." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
|
|
group.long 0x3FC++0x3
|
|
line.long 0x0 "CLOCKGENUPDATELOCKOUT,Control clock configuration registers access (like xxxDIV. xxxSEL)"
|
|
bitfld.long 0x0 0. "LOCK,When set disables access to clock control registers (like xxxDIV xxxSEL). Affects all clock control registers except OSC32CLKSEL." "0,1"
|
|
group.long 0x59C++0x7
|
|
line.long 0x0 "RNGCLKCTRL,Random Number Generator Clocks control"
|
|
bitfld.long 0x0 0. "ENABLE,Enable the clocks used by the Random Number Generator (RNG)" "0,1"
|
|
line.long 0x4 "SRAMCTRL,All SRAMs common control signals"
|
|
bitfld.long 0x4 0.--1. "SMB,SMB" "0,1,2,3"
|
|
group.long 0x5CC++0x3
|
|
line.long 0x0 "MODEMCTRL,Modem (Bluetooth) control and 32K clock enable"
|
|
bitfld.long 0x0 9. "BLE_LP_OSC32K_EN,1 = enable the 32K clock to the BLE Low power wake up counter USART 0 & 1 LSPI0 & 1 PMC and the frequency measure block" "?,1: enable the 32K clock to the BLE Low power wake.."
|
|
newline
|
|
bitfld.long 0x0 8. "BLE_ISO_ENABLE,Control isolation of BLE Low Power Control module. When the BLE low power controller/timers is being used then the isolation must be enabled before entering power down state. Must not be set before MODEMSTATUS.BLE_LL_CLK_STATUS is high.." "0: isolation is disabled,1: isolation is enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "BLE_PHASE_MATCH_1,For normal BLE operation set to 0. BLE operation with this bit set to 1 is not supported." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "BLE_HCLK_BLE_EN,For normal BLE operation set to 1 to enable the register interface clock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BLE_AHB_DIV1,For normal BLE operation set to 0. BLE operation with this bit set to 1 is not supported." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "BLE_AHB_DIV0,For normal BLE operation set to 0. BLE operation with this bit set to 1 is not supported." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BLE_CLK32M_SEL,For normal BLE operation set to 0. BLE operation with this bit set to 1 is not supported." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BLE_DP_DIV_EN,For normal BLE operation set to 1. BLE operation with this bit set to 0 is not supported." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BLE_FREQ_SEL,For normal BLE operation set to 1. BLE operation with this bit set to 0 is not supported. 1 = 16 MHz ; 0 = 8 MHz" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BLE_LP_SLEEP_TRIG,For normal operation leave at 0. If set to 1 will cause the load of register in the BLE low power timing block as if going into deep sleep. This is not needed for the standard method to enter power down modes." "0,1"
|
|
rgroup.long 0x5D0++0x3
|
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line.long 0x0 "MODEMSTATUS,Modem (Bluetooth) status"
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bitfld.long 0x0 2. "BLE_LP_RADIO_EN,BLE low power timing block can be configured to start the radio early; this is not supoorted in this device. However that control signal can be observed here." "0,1"
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bitfld.long 0x0 1. "BLE_LP_OSC_EN,BLE low power timing block can be configured to start the wake-up sequence from power down. This status bit indicates the value of that control bit." "0,1"
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bitfld.long 0x0 0. "BLE_LL_CLK_STATUS,Status bit to indicate the clocking status from the link layer. 1 = BLE IP in deep sleep using low power clock; 0 BLE IP active using 32M clocks" "?,1: BLE IP in deep sleep using low power clock; 0.."
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group.long 0x5D4++0x7
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line.long 0x0 "XTAL32KCAP,XTAL 32 KHz oscillator Capacitor control"
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hexmask.long.byte 0x0 7.--13. 1. "XO_OSC_CAP_OUT,Internal Capacitor setting for XTAL_32K_N. This setting selects the internal capacitance to ground that is connected to this XTAL pin. During device testing the capacitor banks are calibrated so accurate setting of the capacitance can be.."
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hexmask.long.byte 0x0 0.--6. 1. "XO_OSC_CAP_IN,Internal Capacitor setting for XTAL_32K_P. This setting selects the internal capacitance to ground that is connected to this XTAL pin. During device testing the capacitor banks are calibrated so accurate setting of the capacitance can be.."
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line.long 0x4 "XTAL32MCTRL,XTAL 32 MHz oscillator control register"
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bitfld.long 0x4 1. "DEACTIVATE_BLE_CTRL,In order to have XTAL ready for BLE after a low power cycle the XTAL must be started early by the BLE low power module; this can be deactivated. 0: Enable XTAL 32 MHz controls coming from BLE Low Power Control module. 1: Disable XTAL.." "0: Enable XTAL 32 MHz controls coming from BLE Low..,1: Disable XTAL 32 MHz controls coming from BLE Low.."
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bitfld.long 0x4 0. "DEACTIVATE_PMC_CTRL,The 32MHz XTAL is enabled whenever the device is active due to internal control signals from the PMC. This control bit can deactivate this. 0: Enable XTAL 32 MHz controls coming from PMC. 1: Disable XTAL 32 MHz controls coming from PMC." "0: Enable XTAL 32 MHz controls coming from PMC,1: Disable XTAL 32 MHz controls coming from PMC"
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group.long 0x680++0x3
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line.long 0x0 "STARTER0,Start logic 0 wake-up enable register. Enable an interrupt for wake-up from deep-sleep mode. Some bits can also control wake-up from powerdown mode"
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bitfld.long 0x0 29. "RTC,Real Time Clock (RTC) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 27. "PWM10,PWM10 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 26. "PWM9,PWM9 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 25. "PWM8,PWM8 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 24. "PWM7,PWM7 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 23. "PWM6,PWM6 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 22. "PWM5,PWM5 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 21. "PWM4,PWM4 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 20. "PWM3,PWM3 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 19. "PWM2,PWM2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 18. "PWM1,PWM1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 17. "PWM0,PWM0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 16. "SPI1,SPI1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 15. "SPI0,SPI0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 14. "I2C1,I2C1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 13. "I2C0,I2C0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 12. "USART1,USART1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 11. "USART0,USART0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 10. "TIMER1,Counter/Timer1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 9. "TIMER0,Counter/Timer0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 8. "SPIFI,SPI Flash Interface (SPIFI) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 7. "PINT3,Pattern Interupt 3 (PINT3) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 6. "PINT2,Pattern Interupt 2 (PINT2) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 5. "PINT1,Pattern Interupt 1 (PINT1) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 4. "PINT0,Pattern Interupt 0 (PINT0) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 3. "IRBLASTER,Infra Red Blaster interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 2. "GINT,Group Interrupt 0 (GINT0) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x0 1. "DMA,DMA Operation in Deep-Sleep and Powerdown not supported. Leave set to 0." "0,1"
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bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD Interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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group.long 0x680++0x7
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line.long 0x0 "STARTERS0,Pin assign register"
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
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line.long 0x4 "STARTER1,Start logic 1 wake-up enable register. Enable an interrupt for wake-up from deep-sleep mode. Some bits can also control wake-up from powerdown mode"
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bitfld.long 0x4 31. "GPIO,GPIO interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Set this bit to allow GPIO to cause a wake-up in Deep-Sleep and Power-down mode." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 23. "BLE_OSC_EN,BLE Oscillator Enable interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown. Used as early wake-up trigger to allow 32M XTAL to be started and ready for BLE timeslot" "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 22. "BLE_WAKE_UP_TIMER,BLE Wake-up Timer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 17. "WAKE_UP_TIMER1,Wake-up Timer1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 16. "WAKE_UP_TIMER0,Wake-up Timer0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 15. "ANA_COMP,Analog Comparator interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 14. "ISO7816,ISO7816 Smart Card interface interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 13. "RFP_AGC,Radio Control AGC (RFP AGC) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 12. "RFP_TMU,Radio Controller Timing Controller (RFP TMU) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 11. "ZIGBEE_MODEM,Zigbee Modem interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 10. "ZIGBEE_MAC,Zigbee MAC interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 9. "BLE_LL_ALL,BLE Link Layer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 8. "BLE_DP2,BLE Datapath 2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 7. "BLE_DP1,BLE Datapath 1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 6. "BLE_DP0,BLE Datapath 0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 5. "BLE_DP,BLE Datapath interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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newline
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bitfld.long 0x4 4. "HWVAD,Hardware Voice Activity Detector (HWVAD) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 3. "DMIC,Digital Microphone (DMIC) interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 2. "ADC_THCMP_OVR,ADC threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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bitfld.long 0x4 0. "ADC_SEQA,ADC Sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep." "0: Wake-up disabled,1: Wake-up enabled"
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group.long 0x684++0x3
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line.long 0x0 "STARTERS1,Pin assign register"
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
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wgroup.long 0x6A0++0x3
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line.long 0x0 "STARTERSET0,Set bits in STARTER0"
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bitfld.long 0x0 29. "RTC_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 27. "PWM10_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 26. "PWM9_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 25. "PWM8_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 24. "PWM7_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 23. "PWM6_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 22. "PWM5_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 21. "PWM4_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 20. "PWM3_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 19. "PWM2_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 18. "PWM1_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 17. "PWM0_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 16. "SPI1_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 15. "SPI0_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 14. "I2C1_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 13. "I2C0_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 12. "USART1_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 11. "USART0_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 10. "TIMER1_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 9. "TIMER0_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 8. "SPIFI_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 7. "PINT3_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 6. "PINT2_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 5. "PINT1_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 4. "PINT0_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 3. "IRBLASTER_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 2. "GINT_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 1. "DMA_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 0. "WDT_BOD_SET,Writing one to this bit sets the corresponding bit in the STARTER0 register" "0,1"
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group.long 0x6A0++0x3
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line.long 0x0 "STARTERSETS0,Pin assign register"
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
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wgroup.long 0x6A4++0x3
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line.long 0x0 "STARTERSET1,Set bits in STARTER1"
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bitfld.long 0x0 31. "GPIO_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 23. "BLE_OSC_EN_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 22. "BLE_WAKE_UP_TIMER_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 17. "WAKE_UP_TIMER1_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 16. "WAKE_UP_TIMER0_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 15. "ANA_COMP_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 14. "ISO7816_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 13. "RFP_AGC_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 12. "RFP_TMU_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 11. "ZIGBEE_MODEM_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 10. "ZIGBEE_MAC_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 9. "BLE_LL_ALL_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 8. "BLE_DP2_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 7. "BLE_DP1_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 6. "BLE_DP0_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 5. "BLE_DP_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 4. "HWVAD_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 3. "DMIC_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 2. "ADC_THCMP_OVR_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 0. "ADC_SEQA_SET,Writing one to this bit sets the corresponding bit in the STARTER1 register" "0,1"
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group.long 0x6A4++0x3
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line.long 0x0 "STARTERSETS1,Pin assign register"
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hexmask.long 0x0 0.--31. 1. "DATA,no description available"
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wgroup.long 0x6C0++0x3
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line.long 0x0 "STARTERCLR0,Clear bits in STARTER0"
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bitfld.long 0x0 29. "RTC_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 27. "PWM10_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 26. "PWM9_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
|
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bitfld.long 0x0 25. "PWM8_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "PWM7_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "PWM6_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
|
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bitfld.long 0x0 22. "PWM5_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "PWM4_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
|
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bitfld.long 0x0 20. "PWM3_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "PWM2_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
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bitfld.long 0x0 18. "PWM1_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
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newline
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bitfld.long 0x0 17. "PWM0_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
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bitfld.long 0x0 16. "SPI1_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "SPI0_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "I2C1_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
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bitfld.long 0x0 13. "I2C0_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
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bitfld.long 0x0 12. "USART1_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
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bitfld.long 0x0 11. "USART0_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
|
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bitfld.long 0x0 10. "TIMER1_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
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bitfld.long 0x0 9. "TIMER0_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "SPIFI_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
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bitfld.long 0x0 7. "PINT3_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
|
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bitfld.long 0x0 6. "PINT2_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
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bitfld.long 0x0 5. "PINT1_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "PINT0_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
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bitfld.long 0x0 3. "IRBLASTER_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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newline
|
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bitfld.long 0x0 2. "GINT_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "DMA_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
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bitfld.long 0x0 0. "WDT_BOD_CLR,Writing one to this bit clears the corresponding bit in the STARTER0 register" "0,1"
|
|
group.long 0x6C0++0x3
|
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line.long 0x0 "STARTERCLRS0,Pin assign register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
wgroup.long 0x6C4++0x3
|
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line.long 0x0 "STARTERCLR1,Clear bits in STARTER1"
|
|
bitfld.long 0x0 31. "GPIO_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
|
|
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bitfld.long 0x0 23. "BLE_OSC_EN_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 22. "BLE_WAKE_UP_TIMER_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
|
|
newline
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bitfld.long 0x0 17. "WAKE_UP_TIMER1_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 16. "WAKE_UP_TIMER0_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 15. "ANA_COMP_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 14. "ISO7816_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 13. "RFP_AGC_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 12. "RFP_TMU_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
|
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newline
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bitfld.long 0x0 11. "ZIGBEE_MODEM_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 10. "ZIGBEE_MAC_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 9. "BLE_LL_ALL_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 8. "BLE_DP2_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 7. "BLE_DP1_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 6. "BLE_DP0_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
|
|
newline
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bitfld.long 0x0 5. "BLE_DP_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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bitfld.long 0x0 4. "HWVAD_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 3. "DMIC_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 2. "ADC_THCMP_OVR_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
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newline
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bitfld.long 0x0 0. "ADC_SEQA_CLR,Writing one to this bit clears the corresponding bit in the STARTER1 register" "0,1"
|
|
group.long 0x6C4++0x3
|
|
line.long 0x0 "STARTERCLRS1,Pin assign register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,no description available"
|
|
group.long 0x708++0x3
|
|
line.long 0x0 "RETENTIONCTRL,I/O retention control register"
|
|
bitfld.long 0x0 0. "IOCLAMP,Global control of activation of I/O clamps to allow IOs to hold a value during a power mode cycle. To use enable before the power down and then disable after a wake up. Note that each I/O clamp must also be enabled/disabled individually in IOCON.." "0: I/O clamp is disable,1: I/O clamp is enable"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CPSTACK,CPSTACK"
|
|
hexmask.long 0x0 0.--31. 1. "CPSTACK,CPSTACK"
|
|
group.long 0xA00++0x3
|
|
line.long 0x0 "ANACTRL_CTRL,Analog Interrupt control register. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set."
|
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bitfld.long 0x0 1.--2. "COMPINTRPOL,Analog Comparator interrupt Polarity: When COMPINTRLVL = 0 (edge sensitive): 00: rising edge. 01: falling edge. 10: both edges (rising and falling). 11: both edges (rising and falling). When COMPINTRLVL = 1 (level sensitive): 00: Low level.." "0: Low level,1: Low level,?,?"
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|
newline
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bitfld.long 0x0 0. "COMPINTRLVL,Analog Comparator interrupt type: 0: Analog Comparator interrupt is edge sensitive. 1: Analog Comparator interrupt is level sensitive." "0: Analog Comparator interrupt is edge sensitive,1: Analog Comparator interrupt is level sensitive"
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|
rgroup.long 0xA04++0x3
|
|
line.long 0x0 "ANACTRL_VAL,Analog modules (BOD and Analog Comparator) outputs current values (BOD 'Power OK' and Analog comparator out). Requires AHBCLKCTRL0.ANA_INT_CTRL to be set."
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bitfld.long 0x0 4. "BODVBATHIGH,Not(BOD VBAT). Inverse of BOD VBAT. 0 = Power OK; 1 = Power not OK" "0: Power OK;,1: Power not OK"
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newline
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bitfld.long 0x0 3. "ANACOMP,Analog comparator Status : 0 = Comparator in 0 < in 1 ; 1 = Comparator in 0 > in 1." "0: in 1,1: Comparator in"
|
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newline
|
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bitfld.long 0x0 0. "BODVBAT,BOD VBAT Status : 0 = Power not OK ; 1 = Power OK" "0: Power not OK ;,1: Power OK"
|
|
group.long 0xA08++0x7
|
|
line.long 0x0 "ANACTRL_STAT,Analog modules (BOD and Analog Comparator) interrupt status. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set."
|
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bitfld.long 0x0 4. "BODVBATHIGH,NOT(BOD VBAT) interrupt status. Will be set when BOD VBAT goes high. Write 1 to clear." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "ANACOMP,Analog comparator Interrupt status. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear." "0: No interrupt pending,1: Interrupt pending"
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newline
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bitfld.long 0x0 0. "BODVBAT,BOD VBAT Interrupt status. 0: No interrupt pending. 1: Interrupt pending. Write 1 to clear." "0: No interrupt pending,1: Interrupt pending"
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line.long 0x4 "ANACTRL_INTENSET,Analog modules (BOD and Analog Comparator) Interrupt Enable Read and Set register. Read value indicates which interrupts are enabled. Writing ones sets the corresponding interrupt enable bits. Note. interrupt enable bits are cleared.."
|
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bitfld.long 0x4 4. "BODVBATHIGH,NOT(BOD VBAT) Interrupt Enable Read and Set register" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "ANACOMP,Analog comparator Interrupt Enable Read and Set register" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "BODVBAT,BOD VBAT Interrupt Enable Read and Set register" "0,1"
|
|
wgroup.long 0xA10++0x3
|
|
line.long 0x0 "ANACTRL_INTENCLR,Analog modules (BOD and Analog Comparator) Interrupt Enable Clear register. Writing ones clears the corresponding interrupt enable bits. Note. interrupt enable bits are set in ANACTRL_INTENSET. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set.."
|
|
bitfld.long 0x0 4. "BODVBATHIGH,NOT(BOD VBAT) Interrupt Enable Clear register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ANACOMP,Analog comparator Interrupt Enable Clear register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BODVBAT,BOD VBAT Interrupt Enable Clear register" "0,1"
|
|
rgroup.long 0xA14++0x3
|
|
line.long 0x0 "ANACTRL_INTSTAT,Analog modules (BOD and Analog Comparator) Interrupt Status register (masked with interrupt enable). Requires AHBCLKCTRL0.ANA_INT_CTRL to be set to use this register. Interrupt status bit are cleared using ANACTRL_STAT."
|
|
bitfld.long 0x0 4. "BODVBATHIGH,NOT(BOD VBAT) Interrupt (after interrupt mask). 0 = No interrupt pending. 1 = Interrupt pending. Only set when BODVBATHIGH is enabled in INTENSET" "0: No interrupt pending,1: Interrupt pending"
|
|
newline
|
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bitfld.long 0x0 3. "ANACOMP,Analog comparator Interrupt (after interrupt mask). 0 = No interrupt pending. 1 = Interrupt pending. Only set when ANACOMP is enabled in INTENSET" "0: No interrupt pending,1: Interrupt pending"
|
|
newline
|
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bitfld.long 0x0 0. "BODVBAT,BOD VBAT Interrupt (after interrupt mask). 0 = No interrupt pending. 1 = Interrupt pending. Only set when BODVBAT is enabled in INTENSET" "0: No interrupt pending,1: Interrupt pending"
|
|
group.long 0xA18++0x3
|
|
line.long 0x0 "CLOCK_CTRL,Various system clock controls : Flash clock (48 MHz) control. clocks to Frequency Measure function"
|
|
bitfld.long 0x0 2. "FRO1MHZ_FREQM_ENA,Enable FRO 1MHz clock for Frequency Measure module. 0 = Disabled. 1 = Enabled." "0: Disabled,1: Enabled"
|
|
newline
|
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bitfld.long 0x0 1. "XTAL32MHZ_FREQM_ENA,Enable XTAL32MHz clock for Frequency Measure module. 0 = Disabled. 1 = Enabled." "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "FLASH48MHZ_ENA,Enable Flash 48 MHz clock. 0 = Disabled. 1 = Enabled." "0: Disabled,1: Enabled"
|
|
group.long 0xA20++0xF
|
|
line.long 0x0 "WKT_CTRL,Wake-up timers control"
|
|
bitfld.long 0x0 3. "WKT1_CLK_ENA,Enable wake-up timer 1 clock: 0 = Disabled. 1 = Enabled." "0: Disabled,1: Enabled"
|
|
newline
|
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bitfld.long 0x0 2. "WKT0_CLK_ENA,Enable wake-up timer 0 clock: 0 = Disabled. 1 = Enabled." "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "WKT1_ENA,Enable wake-up timer 1: 0 = Disabled. 1 = Enabled (counter is running)." "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "WKT0_ENA,Enable wake-up timer 0: 0 = Disabled. 1 = Enabled (counter is running)." "0: Disabled,1: Enabled"
|
|
line.long 0x4 "WKT_LOAD_WKT0_LSB,Wake-up timer 0 reload value least significant bits ([31:0])."
|
|
hexmask.long 0x4 0.--31. 1. "WKT0_LOAD_LSB,Wake-up timer 0 reload value least significant bits ([31:0]). Write when timer is not enabled"
|
|
line.long 0x8 "WKT_LOAD_WKT0_MSB,Wake-up timer 0 reload value most significant bits ([8:0])."
|
|
hexmask.long.word 0x8 0.--8. 1. "WKT0_LOAD_MSB,Wake-up timer 0 reload value most significant bits ([8:0]). Write when timer is not enabled"
|
|
line.long 0xC "WKT_LOAD_WKT1,Wake-up timer 1 reload value."
|
|
hexmask.long 0xC 0.--27. 1. "WKT1_LOAD,Wake-up timer 1 reload value. Write when timer is not enabled"
|
|
rgroup.long 0xA30++0xB
|
|
line.long 0x0 "WKT_VAL_WKT0_LSB,Wake-up timer 0 current value least significant bits ([31:0]). WARNING : reading not reliable: read this register several times until you get a stable value."
|
|
hexmask.long 0x0 0.--31. 1. "WKT0_VAL_LSB,Wake-up timer 0 value least significant bits ([31:0]). Reread until stable value seen."
|
|
line.long 0x4 "WKT_VAL_WKT0_MSB,Wake-up timer 0 current value most significant bits ([8:0]). WARNING : reading not reliable: read this register several times until you get a stable value."
|
|
hexmask.long.word 0x4 0.--8. 1. "WKT0_VAL_MSB,Wake-up timer 0 value most significant bits ([8:0]). Reread until stable value seen."
|
|
line.long 0x8 "WKT_VAL_WKT1,Wake-up timer 1 current value. WARNING : reading not reliable: read this register several times until you get a stable value."
|
|
hexmask.long 0x8 0.--27. 1. "WKT1_VAL,Wake-up timer 1 value. Reread until stable value seen."
|
|
group.long 0xA3C++0x7
|
|
line.long 0x0 "WKT_STAT,Wake-up timers status"
|
|
rbitfld.long 0x0 3. "WKT1_RUNNING,Running Status of Wake-up timer 1 : 0 = not running ; 1 = running" "0: not running ;,1: running"
|
|
newline
|
|
rbitfld.long 0x0 2. "WKT0_RUNNING,Running Status of Wake-up timer 0 : 0 = not running ; 1 = running" "0: not running ;,1: running"
|
|
newline
|
|
bitfld.long 0x0 1. "WKT1_TIMEOUT,Timeout Status of Wake-up timer 1 : 0 = timeout not reached ; 1 = timeout reached. Write 1 to clear." "0: timeout not reached ;,1: timeout reached"
|
|
newline
|
|
bitfld.long 0x0 0. "WKT0_TIMEOUT,Timeout Status of Wake-up timer 0 : 0 = timeout not reached ; 1 = timeout reached. Write 1 to clear." "0: timeout not reached ;,1: timeout reached"
|
|
line.long 0x4 "WKT_INTENSET,Interrupt Enable Read and Set register"
|
|
bitfld.long 0x4 1. "WKT1_TIMEOUT,Wake-up Timer 1 Timeout Interrupt Enable Read and Set register. Read value of '1' indicates that the interrupt is enabled. Set this bit to enable the interrupt. Use WKT_INTENCLR to disable the interrupt." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "WKT0_TIMEOUT,Wake-up Timer 0 Timeout Interrupt Enable Read and Set register. Read value of '1' indicates that the interrupt is enabled. Set this bit to enable the interrupt. Use WKT_INTENCLR to disable the interrupt." "0,1"
|
|
wgroup.long 0xA44++0x3
|
|
line.long 0x0 "WKT_INTENCLR,Interrupt Enable Clear register"
|
|
bitfld.long 0x0 1. "WKT1_TIMEOUT,Wake-up Timer 1 Timeout Interrupt Enable Clear register. Set this bit to disable the interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WKT0_TIMEOUT,Wake-up Timer 0 Timeout Interrupt Enable Clear register. Set this bit to disable the interrupt." "0,1"
|
|
rgroup.long 0xA48++0x3
|
|
line.long 0x0 "WKT_INTSTAT,Interrupt Status register"
|
|
bitfld.long 0x0 1. "WKT1_TIMEOUT,Wake-up Timer 1 Timeout Interrupt. 0: No interrupt pending. 1: Interrupt pending. Only set when WKT1_TIMEOUT is enable in INTENSET" "0: No interrupt pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 0. "WKT0_TIMEOUT,Wake-up Timer 0 Timeout Interrupt. 0: No interrupt pending. 1: Interrupt pending. Only set when WKT0_TIMEOUT is enable in INTENSET" "0: No interrupt pending,1: Interrupt pending"
|
|
group.long 0xE08++0x3
|
|
line.long 0x0 "GPIOPSYNC,Enable bypass of the first stage of synchonization inside GPIO_INT module."
|
|
bitfld.long 0x0 0. "PSYNC,Enable bypass of the first stage of synchonization inside GPIO_INT module." "0,1"
|
|
rgroup.long 0xFB0++0x3
|
|
line.long 0x0 "DIEID,Chip revision ID & Number"
|
|
hexmask.long.tbyte 0x0 4.--23. 1. "MCO_NUM_IN_DIE_ID,Chip Number"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "REV_ID,Chip Revision ID"
|
|
wgroup.long 0xFF0++0x3
|
|
line.long 0x0 "CODESECURITYPROT,Security code to allow test access via SWD/JTAG. Reset with POR. SW reset or BOD"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_CODE,Security code to allow debug via SWD and JTAG access in test mode. Write once register value 0x87654321 disables the access and therefore prevents any chance to enable it. Writing any other value enables the access and locks the mode. In some.."
|
|
tree.end
|
|
tree "USART (Universal Synchronous/Asynchronous Receiver Transmitter)"
|
|
base ad:0x0
|
|
tree "USART0"
|
|
base ad:0x4008B000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
|
|
bitfld.long 0x0 23. "TXPOL,Transmit data polarity. 0: Standard. The TX signal is sent out without change. This means that the TX rest value is 1 start bit is 0 data is not inverted and the stop bit is 1. 1: Inverted. The TX signal is inverted by the USART before being.." "0: Standard,1: Inverted"
|
|
bitfld.long 0x0 22. "RXPOL,Receive data polarity. 0: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1 start bit is 0 data is not inverted and the stop bit is 1. 1: Inverted. The RX signal is inverted before being used by.." "0: Standard,1: Inverted"
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|
newline
|
|
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity. 0: Low. If selected by OESEL the output enable is active low. 1: High. If selected by OESEL the output enable is active high." "0: Low,1: High"
|
|
bitfld.long 0x0 20. "OESEL,Output Enable Select. 0: Standard. The RTS signal is used as the standard flow control function. 1: RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver." "0: Standard,1: RS-485"
|
|
newline
|
|
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable. 0: Disabled. When addressing is enabled by ADDRDET address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). 1: Enabled. When.." "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation. 0: Disabled. If selected by OESEL the Output Enable signal deasserted at the end of the last stop bit of a transmission. 1: Enabled. If selected by OESEL the Output Enable signal remains.." "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "LOOP,Selects data loopback mode. 0: Normal operaetion. 1: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive.." "0: Normal operaetion,1: Loopback mode"
|
|
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select. 0: Slave. When synchronous mode is enabled the USART is a slave. 1: Master. When synchronous mode is enabled the USART is a master." "0: Slave,1: Master"
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|
newline
|
|
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode. 0: Falling edge. Un_RXD is sampled on the falling edge of SCLK. 1: Rising edge. Un_RXD is sampled on the rising edge of SCLK." "0: Falling edge,1: Rising edge"
|
|
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation. 0: Asynchronous mode. 1: Synchronous mode." "0: Asynchronous mode,1: Synchronous mode"
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|
newline
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin or from the USART s own RTS if loopback mode is enabled. 0 : No flow control. The transmitter does not receive any automatic flow control signal. 1: Flow.." "0: No flow control,1: Flow control enabled"
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bitfld.long 0x0 8. "LINMODE,LIN bus break mode enable. 0: Disabled. Break detect and generate is configured for normal operation. 1: Enabled. Break detect and generate is configured for LIN bus operation." "0: Disabled,1: Enabled"
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode. 0: Disabled. USART uses standard clocking. 1: Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG and uses a special bit clocking scheme." "0: Disabled,1: Enabled"
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 0: 1 stop bit; 1: 2 stop bits. This setting should only be used for asynchronous communication." "0,1"
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART. 0: No parity; 1: Reserved; 2: Even Parity. Adds a bit to each character such that the number of 1s in a transmitted character is even and the number of 1s in a received character is expected to.." "0: No parity;,1: Reserved;,2: Even Parity,3: Odd parity"
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART. 0: 7 bit Data Length; 1: 8 bit data length; 2: 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTRL regsiter. 3: Reserved." "?,?,?,3: Reserved"
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bitfld.long 0x0 0. "ENABLE,USART Enable. 0: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0 all USART interrupts and DMA transfers are disabled. When Enable is set again CFG and most other control bits remain.." "0: Disabled,1: Eanbled"
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line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
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bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable. 0: Disabled. USART is in normal operating mode. 1: Enabled. USART is in auto-baud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to.." "0: Disabled,1: Enabled"
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bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock. 0: No effect. No effect on the CC bit. 1: Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." "0: No effect,1: Auto-clear"
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default SCLK is only output while data is being transmitted in synchronous mode. 0: Clock on character. In synchronous mode SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is.." "0: Clock on character,1: Continuous clock"
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bitfld.long 0x4 6. "TXDIS,Transmit Disable. 0: Not disabled. USART transmitter is not disabled. 1: Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." "0: Not disabled,1: Disabled"
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode. 0: Disabled. The USART presents all incoming data. 1: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1 .." "0: Disabled,1: Enabled"
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bitfld.long 0x4 1. "TXBRKEN,Break Enable. 0: Normal Operation. 1: Continuous break. Continuous break is sent immediately when this bit is set and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the.." "0: Normal Operation,1: Continuous break"
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line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
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bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured essentially an auto baud time-out." "0,1"
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bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
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bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
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rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1 this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
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rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. Hence reset value not applicable." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0 indicates that the transmitter is currently in the process of sending data.When 1 indicate that the transmitter is not currently in the process of sending data." "0,1"
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rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0 indicates that the receiver is currently in the process of receiving data. When 1 indicates that the receiver is not currently in the process of receiving data." "0,1"
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line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
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bitfld.long 0xC 16. "ABERREN,When 1 enables an interrupt when an auto baud error occurs." "0,1"
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bitfld.long 0xC 15. "RXNOISEEN,When 1 enables an interrupt when noise is detected." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1 enables an interrupt when a parity error has been detected." "0,1"
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bitfld.long 0xC 13. "FRAMERREN,When 1 enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1 enables an interrupt when a received start bit has been detected." "0,1"
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bitfld.long 0xC 11. "DELTARXBRKEN,When 1 enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1 enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
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bitfld.long 0xC 5. "DELTACTSEN,Transmitter Idle. When 0 indicates that the transmitter is currently in the process of sending data.When 1 indicate that the transmitter is not currently in the process of sending data." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1 enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
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bitfld.long 0xC 2. "TXRDTEN,When 1 enables an interrupt when TX becomes ready" "0,1"
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bitfld.long 0xC 0. "RXRDYEN,When 1 enables an interrupt when RX becomes ready" "0,1"
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wgroup.long 0x10++0x3
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line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
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bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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group.long 0x20++0x3
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line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
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hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate based on the input clock from the FRG. 0: FCLK is used directly by the USART function. 1: FCLK is divided by 2 before use by the USART function. 2: FCLK is divided by 3.."
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rgroup.long 0x24++0x3
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line.long 0x0 "INTSTAT,Interrupt status register. Reflects the status of interrupts that are currently enabled."
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bitfld.long 0x0 16. "ABERR,Auto baud Error Interrupt flag." "0,1"
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bitfld.long 0x0 15. "RXNOISE,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERR,Parity Error interrupt flag." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
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bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDIS,Transmitter Disabled Interrupt flag." "0,1"
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bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
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bitfld.long 0x0 2. "TX_RDY,Transmitter Ready Status" "0,1"
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bitfld.long 0x0 1. "RXIDLE,Receiver Idle Status" "0,1"
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bitfld.long 0x0 0. "RX_RDY,Receiver Ready Status" "0,1"
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group.long 0x28++0x7
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line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
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hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3: not supported. 0x4: 5 function clocks are used to transmit and receive each data bit. 0x5: 6 function clocks are used to transmit and receive each data bit. ... 0xF: 16 function clocks are used to transmit and.."
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line.long 0x4 "ADDR,Address register for automatic address matching."
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hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
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group.long 0xE00++0xB
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line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
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bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0,1"
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bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wakeup for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up processes data and.." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wakeup for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive. 0: DMA is not used for the receive function. 1: Generate a DMA request for the receive function if the FIFO is not empty. Generally data interrupts would be disabled if DMA is enabled." "0: DMA is not used for the receive function,1: Generate a DMA request for the receive function.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit. 0: DMA is not used for the transmit function. 1: Generate a DMA request for the transmit function if the FIFO is not full. Generally data interrupts would be disabled if DMA is enabled" "0: DMA is not used for the transmit function,1: Generate a DMA request for the transmit function.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 4 entries of 8 bits. 0x1 0x2 0x3 = not applicable." "0: FIFO is configured as 4 entries of 8 bits,?,?,3: not applicable"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO. 0: The receive FIFO is not enabled. 1: The receive FIFO is enabled. This is automatically enabled when PSELID.PERSEL is set to 1 to configure the USART functionality." "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO. 0: The transmit FIFO is not enabled. 1: The transmit FIFO is enabled. This is automatically enabled when PSELID.PERSEL is set to 1 to configure the USART functionality." "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
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line.long 0x4 "FIFOSTAT,FIFO status register."
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hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full the RXFULL.."
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hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1 the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
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rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1 the receive FIFO is not empty so data can be read. When 0 the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1 the transmit FIFO is not full so more data can be written. When 0 the transmit FIFO is full and another write would cause it to overflow." "0,1"
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rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1 the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1 this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral s STAT register." "0,1"
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bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
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line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
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hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. 0: trigger when the RX FIFO has received one entry (is no longer empty). 1: trigger when the RX FIFO has.."
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hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. 0: trigger when the TX FIFO becomes empty. 1: trigger when the TX FIFO level decreases to one entry. ... 3: trigger when the TX FIFO level decreases to 3 entries (is no.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET or a DMA trigger if DMARX in FIFOCFG is set. 0: Receive FIFO level does not generate a FIFO level trigger. 1: An interrupt will be generated if.." "0: Receive FIFO level does not generate a FIFO..,1: An interrupt will be generated if the receive.."
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bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET or a DMA trigger if DMATX in FIFOCFG is set. 0: Transmit FIFO level does not generate a FIFO level trigger. 1: An interrupt will be generated.." "0: Transmit FIFO level does not generate a FIFO..,1: An interrupt will be generated if the transmit.."
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group.long 0xE10++0x3
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line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
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bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 0: No interrupt will be generated based on the RX FIFO level. 1: If RXLVLENA in the FIFOTRIG register = 1 an.." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1"
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bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 0: No interrupt will be generated based on the TX FIFO level. 1: TXLVLENA in the FIFOTRIG register = 1 an.." "0: No interrupt will be generated based on the TX..,1: TXLVLENA in the FIFOTRIG register = 1"
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register. 0: No interrupt will be generated for a receive error. 1: An interrupt will be generated when a receive error occurs." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive.."
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bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register. 0: No interrupt will be generated for a transmit error. 1: An interrupt will be generated when a transmit error occurs." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
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wgroup.long 0xE14++0x3
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line.long 0x0 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
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bitfld.long 0x0 3. "RXLVL,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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bitfld.long 0x0 2. "TXLVL,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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bitfld.long 0x0 1. "RXERR,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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bitfld.long 0x0 0. "TXERR,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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rgroup.long 0xE18++0x3
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line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register. Reflects the status of interrupts that are currently enabled."
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bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
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bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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newline
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
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bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
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wgroup.long 0xE20++0x3
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line.long 0x0 "FIFOWR,FIFO write data. Used to write values to be transmitted to the FIFO."
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hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on the DATALEN"
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rgroup.long 0xE30++0x3
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line.long 0x0 "FIFORD,FIFO read data. Used to read values that have been received."
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bitfld.long 0x0 15. "RXNOISE,Received Noise flag." "0,1"
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bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
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rgroup.long 0xE40++0x3
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line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop. This register acts in exactly the same way as FIFORD. except that it supplies data from the top of the FIFO without popping the FIFO (i.e. leaving the FIFO state unchanged). This could be used to allow system.."
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bitfld.long 0x0 15. "RXNOISE,Received Noise flag." "0,1"
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bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
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group.long 0xFF8++0x3
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line.long 0x0 "PSELID,Flexcomm ID and peripheral function select register"
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hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
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rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only. 0: This Flexcomm does not include the USART function. 1: This Flexcomm includes the USART function." "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
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bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software. 0: Peripheral select can be changed by software. 1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset." "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.."
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bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software. 0x0: No peripheral selected. 0x1: USART function selected. 0x2 - 0x7: Reserved." "0: No peripheral selected,1: USART function selected,?,?,?,?,?,7: Reserved"
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rgroup.long 0xFFC++0x3
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line.long 0x0 "ID,USART Module Identifier"
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hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
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hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. implies software modifications"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
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hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
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tree.end
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tree "USART1"
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base ad:0x4008C000
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group.long 0x0++0xF
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line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
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bitfld.long 0x0 23. "TXPOL,Transmit data polarity. 0: Standard. The TX signal is sent out without change. This means that the TX rest value is 1 start bit is 0 data is not inverted and the stop bit is 1. 1: Inverted. The TX signal is inverted by the USART before being.." "0: Standard,1: Inverted"
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bitfld.long 0x0 22. "RXPOL,Receive data polarity. 0: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1 start bit is 0 data is not inverted and the stop bit is 1. 1: Inverted. The RX signal is inverted before being used by.." "0: Standard,1: Inverted"
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity. 0: Low. If selected by OESEL the output enable is active low. 1: High. If selected by OESEL the output enable is active high." "0: Low,1: High"
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bitfld.long 0x0 20. "OESEL,Output Enable Select. 0: Standard. The RTS signal is used as the standard flow control function. 1: RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver." "0: Standard,1: RS-485"
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable. 0: Disabled. When addressing is enabled by ADDRDET address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). 1: Enabled. When.." "0: Disabled,1: Enabled"
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bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation. 0: Disabled. If selected by OESEL the Output Enable signal deasserted at the end of the last stop bit of a transmission. 1: Enabled. If selected by OESEL the Output Enable signal remains.." "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode. 0: Normal operaetion. 1: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive.." "0: Normal operaetion,1: Loopback mode"
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select. 0: Slave. When synchronous mode is enabled the USART is a slave. 1: Master. When synchronous mode is enabled the USART is a master." "0: Slave,1: Master"
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode. 0: Falling edge. Un_RXD is sampled on the falling edge of SCLK. 1: Rising edge. Un_RXD is sampled on the rising edge of SCLK." "0: Falling edge,1: Rising edge"
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation. 0: Asynchronous mode. 1: Synchronous mode." "0: Asynchronous mode,1: Synchronous mode"
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin or from the USART s own RTS if loopback mode is enabled. 0 : No flow control. The transmitter does not receive any automatic flow control signal. 1: Flow.." "0: No flow control,1: Flow control enabled"
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bitfld.long 0x0 8. "LINMODE,LIN bus break mode enable. 0: Disabled. Break detect and generate is configured for normal operation. 1: Enabled. Break detect and generate is configured for LIN bus operation." "0: Disabled,1: Enabled"
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode. 0: Disabled. USART uses standard clocking. 1: Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG and uses a special bit clocking scheme." "0: Disabled,1: Enabled"
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 0: 1 stop bit; 1: 2 stop bits. This setting should only be used for asynchronous communication." "0,1"
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newline
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART. 0: No parity; 1: Reserved; 2: Even Parity. Adds a bit to each character such that the number of 1s in a transmitted character is even and the number of 1s in a received character is expected to.." "0: No parity;,1: Reserved;,2: Even Parity,3: Odd parity"
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART. 0: 7 bit Data Length; 1: 8 bit data length; 2: 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTRL regsiter. 3: Reserved." "?,?,?,3: Reserved"
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newline
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bitfld.long 0x0 0. "ENABLE,USART Enable. 0: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0 all USART interrupts and DMA transfers are disabled. When Enable is set again CFG and most other control bits remain.." "0: Disabled,1: Eanbled"
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line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
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bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable. 0: Disabled. USART is in normal operating mode. 1: Enabled. USART is in auto-baud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to.." "0: Disabled,1: Enabled"
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bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock. 0: No effect. No effect on the CC bit. 1: Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." "0: No effect,1: Auto-clear"
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newline
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default SCLK is only output while data is being transmitted in synchronous mode. 0: Clock on character. In synchronous mode SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is.." "0: Clock on character,1: Continuous clock"
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bitfld.long 0x4 6. "TXDIS,Transmit Disable. 0: Not disabled. USART transmitter is not disabled. 1: Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." "0: Not disabled,1: Disabled"
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newline
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode. 0: Disabled. The USART presents all incoming data. 1: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1 .." "0: Disabled,1: Enabled"
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bitfld.long 0x4 1. "TXBRKEN,Break Enable. 0: Normal Operation. 1: Continuous break. Continuous break is sent immediately when this bit is set and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the.." "0: Normal Operation,1: Continuous break"
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line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
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bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured essentially an auto baud time-out." "0,1"
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bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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newline
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
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bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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newline
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
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rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1 this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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newline
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
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rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. Hence reset value not applicable." "0,1"
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newline
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0 indicates that the transmitter is currently in the process of sending data.When 1 indicate that the transmitter is not currently in the process of sending data." "0,1"
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rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0 indicates that the receiver is currently in the process of receiving data. When 1 indicates that the receiver is not currently in the process of receiving data." "0,1"
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line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
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bitfld.long 0xC 16. "ABERREN,When 1 enables an interrupt when an auto baud error occurs." "0,1"
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bitfld.long 0xC 15. "RXNOISEEN,When 1 enables an interrupt when noise is detected." "0,1"
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newline
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bitfld.long 0xC 14. "PARITYERREN,When 1 enables an interrupt when a parity error has been detected." "0,1"
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bitfld.long 0xC 13. "FRAMERREN,When 1 enables an interrupt when a framing error has been detected." "0,1"
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newline
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bitfld.long 0xC 12. "STARTEN,When 1 enables an interrupt when a received start bit has been detected." "0,1"
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bitfld.long 0xC 11. "DELTARXBRKEN,When 1 enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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newline
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bitfld.long 0xC 6. "TXDISEN,When 1 enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
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bitfld.long 0xC 5. "DELTACTSEN,Transmitter Idle. When 0 indicates that the transmitter is currently in the process of sending data.When 1 indicate that the transmitter is not currently in the process of sending data." "0,1"
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newline
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bitfld.long 0xC 3. "TXIDLEEN,When 1 enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
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bitfld.long 0xC 2. "TXRDTEN,When 1 enables an interrupt when TX becomes ready" "0,1"
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newline
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bitfld.long 0xC 0. "RXRDYEN,When 1 enables an interrupt when RX becomes ready" "0,1"
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wgroup.long 0x10++0x3
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line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
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bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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newline
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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newline
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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newline
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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newline
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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newline
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bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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group.long 0x20++0x3
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line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
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hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate based on the input clock from the FRG. 0: FCLK is used directly by the USART function. 1: FCLK is divided by 2 before use by the USART function. 2: FCLK is divided by 3.."
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rgroup.long 0x24++0x3
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line.long 0x0 "INTSTAT,Interrupt status register. Reflects the status of interrupts that are currently enabled."
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bitfld.long 0x0 16. "ABERR,Auto baud Error Interrupt flag." "0,1"
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bitfld.long 0x0 15. "RXNOISE,Received Noise interrupt flag." "0,1"
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newline
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bitfld.long 0x0 14. "PARITYERR,Parity Error interrupt flag." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error interrupt flag." "0,1"
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newline
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
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bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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newline
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bitfld.long 0x0 6. "TXDIS,Transmitter Disabled Interrupt flag." "0,1"
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bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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newline
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
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bitfld.long 0x0 2. "TX_RDY,Transmitter Ready Status" "0,1"
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newline
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bitfld.long 0x0 1. "RXIDLE,Receiver Idle Status" "0,1"
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bitfld.long 0x0 0. "RX_RDY,Receiver Ready Status" "0,1"
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group.long 0x28++0x7
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line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
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hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3: not supported. 0x4: 5 function clocks are used to transmit and receive each data bit. 0x5: 6 function clocks are used to transmit and receive each data bit. ... 0xF: 16 function clocks are used to transmit and.."
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line.long 0x4 "ADDR,Address register for automatic address matching."
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hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
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group.long 0xE00++0xB
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line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
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bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0,1"
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bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
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newline
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wakeup for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up processes data and.." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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newline
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bitfld.long 0x0 14. "WAKETX,Wakeup for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive. 0: DMA is not used for the receive function. 1: Generate a DMA request for the receive function if the FIFO is not empty. Generally data interrupts would be disabled if DMA is enabled." "0: DMA is not used for the receive function,1: Generate a DMA request for the receive function.."
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newline
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit. 0: DMA is not used for the transmit function. 1: Generate a DMA request for the transmit function if the FIFO is not full. Generally data interrupts would be disabled if DMA is enabled" "0: DMA is not used for the transmit function,1: Generate a DMA request for the transmit function.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 4 entries of 8 bits. 0x1 0x2 0x3 = not applicable." "0: FIFO is configured as 4 entries of 8 bits,?,?,3: not applicable"
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newline
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO. 0: The receive FIFO is not enabled. 1: The receive FIFO is enabled. This is automatically enabled when PSELID.PERSEL is set to 1 to configure the USART functionality." "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO. 0: The transmit FIFO is not enabled. 1: The transmit FIFO is enabled. This is automatically enabled when PSELID.PERSEL is set to 1 to configure the USART functionality." "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
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line.long 0x4 "FIFOSTAT,FIFO status register."
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hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full the RXFULL.."
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hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full the TXEMPTY.."
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newline
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1 the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
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rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1 the receive FIFO is not empty so data can be read. When 0 the receive FIFO is empty." "0,1"
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newline
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1 the transmit FIFO is not full so more data can be written. When 0 the transmit FIFO is full and another write would cause it to overflow." "0,1"
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rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1 the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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newline
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1 this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral s STAT register." "0,1"
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bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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newline
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
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line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
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hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. 0: trigger when the RX FIFO has received one entry (is no longer empty). 1: trigger when the RX FIFO has.."
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hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. 0: trigger when the TX FIFO becomes empty. 1: trigger when the TX FIFO level decreases to one entry. ... 3: trigger when the TX FIFO level decreases to 3 entries (is no.."
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newline
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET or a DMA trigger if DMARX in FIFOCFG is set. 0: Receive FIFO level does not generate a FIFO level trigger. 1: An interrupt will be generated if.." "0: Receive FIFO level does not generate a FIFO..,1: An interrupt will be generated if the receive.."
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bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET or a DMA trigger if DMATX in FIFOCFG is set. 0: Transmit FIFO level does not generate a FIFO level trigger. 1: An interrupt will be generated.." "0: Transmit FIFO level does not generate a FIFO..,1: An interrupt will be generated if the transmit.."
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group.long 0xE10++0x3
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line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
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bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 0: No interrupt will be generated based on the RX FIFO level. 1: If RXLVLENA in the FIFOTRIG register = 1 an.." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1"
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bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 0: No interrupt will be generated based on the TX FIFO level. 1: TXLVLENA in the FIFOTRIG register = 1 an.." "0: No interrupt will be generated based on the TX..,1: TXLVLENA in the FIFOTRIG register = 1"
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newline
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register. 0: No interrupt will be generated for a receive error. 1: An interrupt will be generated when a receive error occurs." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive.."
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bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register. 0: No interrupt will be generated for a transmit error. 1: An interrupt will be generated when a transmit error occurs." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
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wgroup.long 0xE14++0x3
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line.long 0x0 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
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bitfld.long 0x0 3. "RXLVL,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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bitfld.long 0x0 2. "TXLVL,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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newline
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bitfld.long 0x0 1. "RXERR,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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bitfld.long 0x0 0. "TXERR,Writing 1 clears the corresponding bit in the FIFOINTENSET register" "0,1"
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rgroup.long 0xE18++0x3
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line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register. Reflects the status of interrupts that are currently enabled."
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bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
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bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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newline
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
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bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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newline
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
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wgroup.long 0xE20++0x3
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line.long 0x0 "FIFOWR,FIFO write data. Used to write values to be transmitted to the FIFO."
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hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on the DATALEN"
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rgroup.long 0xE30++0x3
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line.long 0x0 "FIFORD,FIFO read data. Used to read values that have been received."
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bitfld.long 0x0 15. "RXNOISE,Received Noise flag." "0,1"
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bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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newline
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
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rgroup.long 0xE40++0x3
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line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop. This register acts in exactly the same way as FIFORD. except that it supplies data from the top of the FIFO without popping the FIFO (i.e. leaving the FIFO state unchanged). This could be used to allow system.."
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bitfld.long 0x0 15. "RXNOISE,Received Noise flag." "0,1"
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bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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newline
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
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group.long 0xFF8++0x3
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line.long 0x0 "PSELID,Flexcomm ID and peripheral function select register"
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hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
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rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only. 0: This Flexcomm does not include the USART function. 1: This Flexcomm includes the USART function." "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
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newline
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bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software. 0: Peripheral select can be changed by software. 1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset." "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.."
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bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software. 0x0: No peripheral selected. 0x1: USART function selected. 0x2 - 0x7: Reserved." "0: No peripheral selected,1: USART function selected,?,?,?,?,?,7: Reserved"
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rgroup.long 0xFFC++0x3
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line.long 0x0 "ID,USART Module Identifier"
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hexmask.long.word 0x0 16.--31. 1. "ID,Identifier. This is the unique identifier of the module"
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hexmask.long.byte 0x0 12.--15. 1. "MAJ_REV,Major revision i.e. implies software modifications"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "MIN_REV,Minor revision i.e. with no software consequences"
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hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP"
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tree.end
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tree.end
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tree "WWDT (Windowed Watchdog Timer)"
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base ad:0x4000A000
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group.long 0x0++0x7
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line.long 0x0 "MOD,Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer."
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bitfld.long 0x0 4. "WDPROTECT,Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 0: Flexible. A feed sequence can be performed at any time; ie. the watchdog timer can be reloaded with time-out value (TC) at any time. 1: Threshold. A.." "0: Flexible,1: Threshold"
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bitfld.long 0x0 3. "WDINT,Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur.." "0,1"
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bitfld.long 0x0 2. "WDTOF,Watchdog time-out flag. Set when the watchdog timer times out by a feed error or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1." "0,1"
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bitfld.long 0x0 1. "WDRESET,Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 0: Interrupt. A watchdog time-out will not cause a chip reset. It will cause an interrupt of the watchdog. 1: Reset. A watchdog time-out will.." "0: Interrupt,1: Reset"
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bitfld.long 0x0 0. "WDEN,Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed the watchdog timer will run permanently. 0: The watchdog timer is stopped. 1: The watchdog timer is running." "0: The watchdog timer is stopped,1: The watchdog timer is running"
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line.long 0x4 "TC,Watchdog timer constant register. This 24-bit register determines the time-out value."
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hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Watchdog time-out value. If MOD.WDPROTECT is set then changing this value may cause an error."
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wgroup.long 0x8++0x3
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line.long 0x0 "FEED,Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC."
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hexmask.long.byte 0x0 0.--7. 1. "FEED,Feed value should be 0xAA followed by 0x55. Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the TC value. This operation will also start the Watchdog if it is enabled via the WDMOD register. Setting the WDEN bit in.."
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rgroup.long 0xC++0x3
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line.long 0x0 "TV,Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer."
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hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter timer value. The TV register is used to read the current value of Watchdog timer counter."
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group.long 0x14++0x7
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line.long 0x0 "WARNINT,Watchdog Warning Interrupt compare value."
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hexmask.long.word 0x0 0.--9. 1. "WARNINT,Watchdog warning interrupt compare value.A match of the watchdog timer counter to WARNINT occurs when the bottom 10 bits of the counter have the same value as the 10 bits of WARNINT and the remaining upper bits of the counter are all 0. This.."
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line.long 0x4 "WINDOW,Watchdog Window compare value."
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hexmask.long.tbyte 0x4 0.--23. 1. "WINDOW,Watchdog window value. The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. If a feed sequence occurs when TV is greater than the value in WINDOW a watchdog event will occur"
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tree.end
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AUTOINDENT.OFF
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