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Gen4_R-Car_Trace32/2_Trunk/perimxrt5xx.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: IMXRT5xx On-Chip Peripherals
; @Props: Released
; @Author: KWI, PIW
; @Changelog: 2021-03-19 KWI
; 2022-03-01 PIW
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: SVD generated, based on: MIMXRT533S.svd (Ver. 1.0)
; MIMXRT555S.svd (Ver. 1.0)
; MIMXRT595S_cm33.svd (Ver. 1.0)
; @Core: Cortex-M33F
; @Chip: IMXRT533, IMXRT555, IMXRT595-CM33
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perimxrt5xx.per 17736 2024-04-08 09:26:07Z kwisniewski $
tree.close "Core Registers (Cortex-M33F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
textline " "
bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
textline " "
bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
textline " "
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline " "
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline " "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
textline " "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline " "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
textline " "
bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
textline " "
bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
textline " "
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
textline " "
bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
textline " "
eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
textline " "
eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
textline " "
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
textline " "
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
textline " "
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline " "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
textline " "
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline " "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline " "
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline " "
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline " "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline " "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline " "
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline " "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline " "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline " "
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline " "
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline " "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ACMP (CMP)"
base ad:0x40139000
rgroup.long 0x00++0x03
line.long 0x00 "VERID,Version ID Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
rgroup.long 0x04++0x03
line.long 0x00 "PARAM,Parameter Register"
hexmask.long 0x00 0.--31. 1. "PARAM,Parameter Registers"
group.long 0x08++0x03
line.long 0x00 "C0,CMP Control Register 0"
bitfld.long 0x00 31. "LINKEN,CMP to DAC link enable" "0: CMP to DAC link is disabled,1: CMP to DAC link is enabled"
bitfld.long 0x00 30. "DMAEN,DMA Enable" "0: DMA is disabled,1: DMA is enabled"
newline
bitfld.long 0x00 28. "IER,Comparator Interrupt Enable Rising" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 27. "IEF,Comparator Interrupt Enable Falling" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
eventfld.long 0x00 26. "CFR,Analog Comparator Flag Rising" "0: A rising edge has not been detected on COUT,1: A rising edge on COUT has occurred"
eventfld.long 0x00 25. "CFF,Analog Comparator Flag Falling" "0: A falling edge has not been detected on COUT,1: A falling edge on COUT has occurred"
newline
rbitfld.long 0x00 24. "COUT,Analog Comparator Output" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "FPR,Filter Sample Period"
newline
bitfld.long 0x00 15. "SE,Sample Enable" "0: Sampling mode is not selected,1: Sampling mode is selected"
bitfld.long 0x00 14. "WE,Windowing Enable" "0: Windowing mode is not selected,1: Windowing mode is selected"
newline
bitfld.long 0x00 12. "PMODE,Power Mode Select" "0: Low Speed (LS) comparison mode is selected,1: High Speed (HS) comparison mode is selected"
bitfld.long 0x00 11. "INVT,Comparator invert" "0: Does not invert the comparator output,1: Inverts the comparator output"
newline
bitfld.long 0x00 10. "COS,Comparator Output Select" "0: Set CMPO to equal COUT (filtered comparator..,1: Set CMPO to equal COUTA (unfiltered.."
bitfld.long 0x00 9. "OPE,Comparator Output Pin Enable" "0: When OPE is 0 the comparator output (after..,1: When OPE is 1 and if the software has.."
newline
bitfld.long 0x00 8. "EN,Comparator Module Enable" "0: Analog Comparator is disabled,1: Analog Comparator is enabled"
bitfld.long 0x00 4.--6. "FILTER_CNT,Filter Sample Count" "0: Filter is disabled,1: 1 consecutive sample must agree (comparator..,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
newline
bitfld.long 0x00 0.--1. "HYSTCTR,Comparator hard block hysteresis control" "0: The hard block output has level 0 hysteresis..,1: The hard block output has level 1 hysteresis..,2: The hard block output has level 2 hysteresis..,3: The hard block output has level 3 hysteresis.."
group.long 0x0C++0x03
line.long 0x00 "C1,CMP Control Register 1"
bitfld.long 0x00 28.--30. "PSEL,Plus Input MUX Control" "0: Internal Posivite Input 0 for Plus Channel --..,1: External Input 1 for Plus Channel --..,2: External Input 2 for Plus Channel --..,3: External Input 3 for Plus Channel --..,4: External Input 4 for Plus Channel --..,5: External Input 4 for Plus Channel --..,6: External Input 4 for Plus Channel --..,7: Internal 8b DAC output"
bitfld.long 0x00 24.--26. "MSEL,Minus Input MUX Control" "0: Internal Negative Input 0 for Minus Channel..,1: External Input 1 for Minus Channel --..,2: External Input 2 for Minus Channel --..,3: External Input 3 for Minus Channel --..,4: External Input 4 for Minus Channel --..,5: External Input 5 for Minus Channel --..,6: External Input 6 for Minus Channel --..,7: Internal 8b DAC output"
newline
bitfld.long 0x00 21. "CHN5,Channel 5 input enable" "0,1"
bitfld.long 0x00 20. "CHN4,Channel 4 input enable" "0,1"
newline
bitfld.long 0x00 19. "CHN3,Channel 3 input enable" "0,1"
bitfld.long 0x00 18. "CHN2,Channel 2 input enable" "0,1"
newline
bitfld.long 0x00 17. "CHN1,Channel 1 input enable" "0,1"
bitfld.long 0x00 16. "CHN0,Channel 0 input enable" "0,1"
newline
bitfld.long 0x00 12.--14. "PSEL_SEC,Secondary Plus channel select" "0: Input 0 for Plus Channel,1: Input 1 for Plus Channel,2: Input 2 for Plus Channel,3: Input 3 for Plus Channel,4: Input 4 for Plus Channel,5: Input 5 for Plus Channel,6: Input 6 for Plus Channel,7: Internal 8b DAC output for Plus Channel"
bitfld.long 0x00 10. "DACEN,DAC Enable" "0: DAC is disabled,1: DAC is enabled"
newline
bitfld.long 0x00 9. "VRSEL,Supply Voltage Reference Source Select" "0: Vin1 is selected as resistor ladder network..,1: Vin2 is selected as resistor ladder network.."
bitfld.long 0x00 8. "DMODE,DAC Mode Selection" "0: DAC is selected to work in low speed and low..,1: DAC is selected to work in high speed high.."
newline
hexmask.long.byte 0x00 0.--7. 1. "VOSEL,DAC Output Voltage Select"
group.long 0x10++0x03
line.long 0x00 "C2,CMP Control Register 2"
bitfld.long 0x00 30. "RRIE,Round-Robin interrupt enable" "0: The round-robin interrupt is disabled,1: The round-robin interrupt is enabled when a.."
bitfld.long 0x00 29. "FXMP,Fixed MUX Port" "0: The Plus port is fixed,1: The Minus port is fixed"
newline
bitfld.long 0x00 25.--27. "FXMXCH,Fixed channel selection" "0: External Reference Input 0 is selected as the..,1: External Reference Input 1 is selected as the..,2: External Reference Input 2 is selected as the..,3: External Reference Input 3 is selected as the..,4: External Reference Input 4 is selected as the..,5: External Reference Input 5 is selected as the..,?,7: The 8bit DAC is selected as the fixed.."
eventfld.long 0x00 21. "CH5F,CH5F" "0,1"
newline
eventfld.long 0x00 20. "CH4F,CH4F" "0,1"
eventfld.long 0x00 19. "CH3F,CH3F" "0,1"
newline
eventfld.long 0x00 18. "CH2F,CH2F" "0,1"
eventfld.long 0x00 17. "CH1F,CH1F" "0,1"
newline
eventfld.long 0x00 16. "CH0F,CH0F" "0,1"
bitfld.long 0x00 14.--15. "NSAM,Number of sample clocks" "0: The comparison result is sampled as soon as..,1: The sampling takes place 1 round-robin clock..,2: The sampling takes place 2 round-robin clock..,3: The sampling takes place 3 round-robin clock.."
newline
bitfld.long 0x00 8.--13. "INITMOD,Comparator and DAC initialization delay modulus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ACOn,ACOn" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x03
line.long 0x00 "C3,CMP Control Register 3"
bitfld.long 0x00 28. "PCHCTEN,Positive Channel Continuous Mode Enable" "0: Positive channel is in Discrete Mode and..,1: Positive channel is in Continuous Mode and no.."
bitfld.long 0x00 24. "NCHCTEN,Negative Channel Continuous Mode Enable" "0: Negative channel is in Discrete Mode and..,1: Negative channel is in Continuous Mode and no.."
newline
bitfld.long 0x00 20. "RDIVE,Resistor Divider Enable" "0: The resistor is not enabled even when either..,1: The resistor is enabled because the inputs.."
bitfld.long 0x00 16. "DMCS,Discrete Mode Clock Selection" "0: Slow clock is selected for the timing..,1: Fast clock is selected for the timing.."
newline
bitfld.long 0x00 12.--14. "ACSAT,Analog Comparator Sampling Time control" "0: The sampling time equals to T,1: The sampling time equasl to 2*T,2: The sampling time equasl to 4*T,3: The sampling time equasl to 8*T,4: The sampling time equasl to 16*T,5: The sampling time equasl to 32*T,6: The sampling time equasl to 64*T,7: The sampling time equasl to 256*T"
bitfld.long 0x00 8.--10. "ACPH1TC,Analog Comparator Phase1 Timing Control" "0: Phase1 active time in one sampling period..,1: Phase1 active time in one sampling period..,2: Phase1 active time in one sampling period..,3: Phase1 active time in one sampling period..,4: Phase1 active time in one sampling period..,5: Phase1 active time in one sampling period..,6: Phase1 active time in one sampling period..,7: Phase1 active time in one sampling period.."
newline
bitfld.long 0x00 4.--6. "ACPH2TC,Analog Comparator Phase2 Timing Control" "0: Phase2 active time in one sampling period..,1: Phase2 active time in one sampling period..,2: Phase2 active time in one sampling period..,3: Phase2 active time in one sampling period..,4: Phase2 active time in one sampling period..,5: Phase2 active time in one sampling period..,6: Phase2 active time in one sampling period..,7: Phase2 active time in one sampling period.."
group.long 0x18++0x03
line.long 0x00 "RR_TIMER_CR,Round-Robin Timer Control Register"
bitfld.long 0x00 31. "RR_TIMER_ENA,RR_TIMER enable" "0,1"
hexmask.long 0x00 0.--27. 1. "RR_TIMER_RELOAD,This field establishes the repetitive count rate for the timer"
tree.end
tree "ADC"
base ad:0x4013A000
rgroup.long 0x00++0x03
line.long 0x00 "VERID,Version ID Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
bitfld.long 0x00 12.--14. "NUM_FIFO,Number of FIFOs" "0: NUM_FIFO_0,1: This design supports one result FIFO,2: This design supports two result FIFOs,3: This design supports three result FIFOs,4: This design supports four result FIFOs,?..."
bitfld.long 0x00 11. "NUM_SEC,Number of Single Ended Outputs Supported" "0: This design supports one single ended..,1: This design supports two simultanious single.."
newline
bitfld.long 0x00 10. "CALOFSI,Calibration Function Implemented" "0: Calibration Not Implemented,1: Calibration Implemented"
bitfld.long 0x00 9. "IADCKI,Internal ADC Clock implemented" "0: Internal clock source not implemented,1: Internal clock source (and CFG[ADCKEN]).."
newline
bitfld.long 0x00 8. "VR1RNGI,Voltage Reference 1 Range Control Bit Implemented" "0: Range control not required,1: Range control required"
bitfld.long 0x00 4.--6. "CSW,Channel Scale Width" "0: Channel scaling not supported,1: Channel scaling supported,?,?,?,?,6: Channel scaling supported,?..."
newline
bitfld.long 0x00 3. "MVI,Multi Vref Implemented" "0: Single voltage reference high (VREFH) input..,1: Multiple voltage reference high (VREFH).."
bitfld.long 0x00 1. "DIFFEN,Differential Supported" "0: Differential operation not supported,1: Differential operation supported"
newline
bitfld.long 0x00 0. "RES,Resolution" "0: Up to 13-bit differential/12-bit single ended..,1: Up to 16-bit differential/15-bit single ended.."
rgroup.long 0x04++0x03
line.long 0x00 "PARAM,Parameter Register"
hexmask.long.byte 0x00 24.--31. 1. "CMD_NUM,Command Buffer Number"
hexmask.long.byte 0x00 16.--23. 1. "CV_NUM,Compare Value Number"
newline
hexmask.long.byte 0x00 8.--15. 1. "FIFOSIZE,Result FIFO Depth"
hexmask.long.byte 0x00 0.--7. 1. "TRIG_NUM,Trigger Number"
group.long 0x10++0x03
line.long 0x00 "CTRL,ADC Control Register"
bitfld.long 0x00 9. "RSTFIFO1,Reset FIFO 1" "0: RSTFIFO1_0,1: FIFO 1 is reset"
bitfld.long 0x00 8. "RSTFIFO0,Reset FIFO 0" "0: RSTFIFO0_0,1: FIFO 0 is reset"
newline
bitfld.long 0x00 2. "DOZEN,Doze Enable" "0: ADC is enabled in Doze mode,1: ADC is disabled in Doze mode"
bitfld.long 0x00 1. "RST,Software Reset" "0: ADC logic is not reset,1: ADC logic is reset"
newline
bitfld.long 0x00 0. "ADCEN,ADC Enable" "0: ADC is disabled,1: ADC is enabled"
group.long 0x14++0x03
line.long 0x00 "STAT,ADC Status Register"
rbitfld.long 0x00 24.--27. "CMDACT,Command Active" "0: No command is currently in progress,1: Command 1 currently being executed,2: Command 2 currently being executed,3: Associated command number is currently being..,4: Associated command number is currently being..,5: Associated command number is currently being..,6: Associated command number is currently being..,7: Associated command number is currently being..,8: Associated command number is currently being..,9: Associated command number is currently being..,?..."
rbitfld.long 0x00 16.--19. "TRGACT,Trigger Active" "0: Command (sequence) associated with Trigger 0..,1: Command (sequence) associated with Trigger 1..,2: Command (sequence) associated with Trigger 2..,3: Command (sequence) from the associated..,4: Command (sequence) from the associated..,5: Command (sequence) from the associated..,6: Command (sequence) from the associated..,7: Command (sequence) from the associated..,8: Command (sequence) from the associated..,9: Command (sequence) from the associated..,?..."
newline
rbitfld.long 0x00 11. "ADC_ACTIVE,ADC Active" "0: The ADC is IDLE,1: The ADC is processing a conversion running.."
eventfld.long 0x00 9. "TCOMP_INT,Interrupt Flag For Trigger Completion" "0: Either IE[TCOMP_IE] is set to 0 or no trigger..,1: Trigger sequence has been completed and all.."
newline
eventfld.long 0x00 8. "TEXC_INT,Interrupt Flag For High Priority Trigger Exception" "0: No trigger exceptions have occurred,1: A trigger exception has occurred and is.."
eventfld.long 0x00 3. "FOF1,Result FIFO1 Overflow Flag" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.."
newline
rbitfld.long 0x00 2. "RDY1,Result FIFO1 Ready Flag" "0: Result FIFO1 data level not above watermark..,1: Result FIFO1 holding data above watermark level"
eventfld.long 0x00 1. "FOF0,Result FIFO 0 Overflow Flag" "0: No result FIFO 0 overflow has occurred since..,1: At least one result FIFO 0 overflow has.."
newline
rbitfld.long 0x00 0. "RDY0,Result FIFO 0 Ready Flag" "0: Result FIFO 0 data level not above watermark..,1: Result FIFO 0 holding data above watermark.."
group.long 0x18++0x03
line.long 0x00 "IE,Interrupt Enable Register"
hexmask.long.word 0x00 16.--31. 1. "TCOMP_IE,Trigger Completion Interrupt Enable"
bitfld.long 0x00 8. "TEXC_IE,Trigger Exception Interrupt Enable" "0: Trigger exception interrupts are disabled,1: Trigger exception interrupts are enabled"
newline
bitfld.long 0x00 3. "FOFIE1,Result FIFO1 Overflow Interrupt Enable" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.."
bitfld.long 0x00 2. "FWMIE1,FIFO1 Watermark Interrupt Enable" "0: FIFO1 watermark interrupts are not enabled,1: FIFO1 watermark interrupts are enabled"
newline
bitfld.long 0x00 1. "FOFIE0,Result FIFO 0 Overflow Interrupt Enable" "0: FIFO 0 overflow interrupts are not enabled,1: FIFO 0 overflow interrupts are enabled"
bitfld.long 0x00 0. "FWMIE0,FIFO 0 Watermark Interrupt Enable" "0: FIFO 0 watermark interrupts are not enabled,1: FIFO 0 watermark interrupts are enabled"
group.long 0x1C++0x03
line.long 0x00 "DE,DMA Enable Register"
bitfld.long 0x00 1. "FWMDE1,FIFO1 Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled"
bitfld.long 0x00 0. "FWMDE0,FIFO 0 Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled"
group.long 0x20++0x03
line.long 0x00 "CFG,ADC Configuration Register"
bitfld.long 0x00 28. "PWREN,ADC Analog Pre-Enable" "0: ADC analog circuits are only enabled while..,1: ADC analog circuits are pre-enabled and ready.."
hexmask.long.byte 0x00 16.--23. 1. "PUDLY,Power Up Delay"
newline
bitfld.long 0x00 10. "HPT_EXDI,High Priority Trigger Exception Disable" "0: High priority trigger exceptions are enabled,1: High priority trigger exceptions are disabled"
bitfld.long 0x00 9. "TCMDRES,Trigger Command Resume" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.."
newline
bitfld.long 0x00 8. "TRES,Trigger Resume Enable" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.."
bitfld.long 0x00 6.--7. "REFSEL,Voltage Reference Selection" "0: (Default) Option 1 setting,1: Option 2 setting,2: Option 3 setting,?..."
newline
bitfld.long 0x00 4.--5. "PWRSEL,Power Configuration Select" "0: Lowest power setting,1: Higher power setting than 0b0,2: Higher power setting than 0b1,3: Highest power setting"
bitfld.long 0x00 0.--1. "TPRICTRL,ADC trigger priority control" "0: If a higher priority trigger is detected..,1: If a higher priority trigger is received..,2: If a higher priority trigger is received..,?..."
group.long 0x24++0x03
line.long 0x00 "PAUSE,ADC Pause Register"
bitfld.long 0x00 31. "PAUSEEN,PAUSE Option Enable" "0: Pause operation disabled,1: Pause operation enabled"
hexmask.long.word 0x00 0.--8. 1. "PAUSEDLY,Pause Delay"
group.long 0x34++0x03
line.long 0x00 "SWTRIG,Software Trigger Register"
bitfld.long 0x00 15. "SWT15,Software trigger 15 event" "0: No trigger 15 event generated,1: Trigger 15 event generated"
bitfld.long 0x00 14. "SWT14,Software trigger 14 event" "0: No trigger 14 event generated,1: Trigger 14 event generated"
newline
bitfld.long 0x00 13. "SWT13,Software trigger 13 event" "0: No trigger 13 event generated,1: Trigger 13 event generated"
bitfld.long 0x00 12. "SWT12,Software trigger 12 event" "0: No trigger 12 event generated,1: Trigger 12 event generated"
newline
bitfld.long 0x00 11. "SWT11,Software trigger 11 event" "0: No trigger 11 event generated,1: Trigger 11 event generated"
bitfld.long 0x00 10. "SWT10,Software trigger 10 event" "0: No trigger 10 event generated,1: Trigger 10 event generated"
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bitfld.long 0x00 9. "SWT9,Software trigger 9 event" "0: No trigger 9 event generated,1: Trigger 9 event generated"
bitfld.long 0x00 8. "SWT8,Software trigger 8 event" "0: No trigger 8 event generated,1: Trigger 8 event generated"
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bitfld.long 0x00 7. "SWT7,Software trigger 7 event" "0: No trigger 7 event generated,1: Trigger 7 event generated"
bitfld.long 0x00 6. "SWT6,Software trigger 6 event" "0: No trigger 6 event generated,1: Trigger 6 event generated"
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bitfld.long 0x00 5. "SWT5,Software trigger 5 event" "0: No trigger 5 event generated,1: Trigger 5 event generated"
bitfld.long 0x00 4. "SWT4,Software trigger 4 event" "0: No trigger 4 event generated,1: Trigger 4 event generated"
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bitfld.long 0x00 3. "SWT3,Software trigger 3 event" "0: No trigger 3 event generated,1: Trigger 3 event generated"
bitfld.long 0x00 2. "SWT2,Software trigger 2 event" "0: No trigger 2 event generated,1: Trigger 2 event generated"
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bitfld.long 0x00 1. "SWT1,Software trigger 1 event" "0: No trigger 1 event generated,1: Trigger 1 event generated"
bitfld.long 0x00 0. "SWT0,Software trigger 0 event" "0: No trigger 0 event generated,1: Trigger 0 event generated"
group.long 0x38++0x03
line.long 0x00 "TSTAT,Trigger Status Register"
hexmask.long.word 0x00 16.--31. 1. "TCOMP_FLAG,Trigger Completion Flag"
hexmask.long.word 0x00 0.--15. 1. "TEXC_NUM,Trigger Exception Number"
repeat 16. (increment 0 1) (increment 0 0x4)
group.long ($2+0xA0)++0x03
line.long 0x00 "TCTRL[$1],Trigger Control Register $1"
bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed"
bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1"
bitfld.long 0x00 8.--11. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,?,?,?,?,?,15: Set to lowest priority Level 16"
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bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1"
bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0xE0)++0x03
line.long 0x00 "FCTRL[$1],FIFO Control Register $1"
bitfld.long 0x00 16.--19. "FWMARK,Watermark level selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--4. "FCOUNT,Result FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
group.long 0x100++0x03
line.long 0x00 "CMDL1,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x104++0x03
line.long 0x00 "CMDH1,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
group.long 0x108++0x03
line.long 0x00 "CMDL2,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x10C++0x03
line.long 0x00 "CMDH2,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
group.long 0x110++0x03
line.long 0x00 "CMDL3,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x114++0x03
line.long 0x00 "CMDH3,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
group.long 0x118++0x03
line.long 0x00 "CMDL4,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x11C++0x03
line.long 0x00 "CMDH4,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
group.long 0x120++0x03
line.long 0x00 "CMDL5,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x124++0x03
line.long 0x00 "CMDH5,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x128++0x03
line.long 0x00 "CMDL6,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x12C++0x03
line.long 0x00 "CMDH6,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x130++0x03
line.long 0x00 "CMDL7,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x134++0x03
line.long 0x00 "CMDH7,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x138++0x03
line.long 0x00 "CMDL8,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x13C++0x03
line.long 0x00 "CMDH8,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x140++0x03
line.long 0x00 "CMDL9,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x144++0x03
line.long 0x00 "CMDH9,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x148++0x03
line.long 0x00 "CMDL10,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x14C++0x03
line.long 0x00 "CMDH10,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x150++0x03
line.long 0x00 "CMDL11,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x154++0x03
line.long 0x00 "CMDH11,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x158++0x03
line.long 0x00 "CMDL12,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x15C++0x03
line.long 0x00 "CMDH12,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x160++0x03
line.long 0x00 "CMDL13,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x164++0x03
line.long 0x00 "CMDH13,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x168++0x03
line.long 0x00 "CMDL14,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x16C++0x03
line.long 0x00 "CMDH14,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x170++0x03
line.long 0x00 "CMDL15,ADC Command Low Buffer Register"
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x174++0x03
line.long 0x00 "CMDH15,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
newline
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
repeat 4. (strings "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x200)++0x03
line.long 0x00 "CV$1,Compare Value Register"
hexmask.long.word 0x00 16.--31. 1. "CVH,Compare Value High"
hexmask.long.word 0x00 0.--15. 1. "CVL,Compare Value Low"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x300)++0x03
line.long 0x00 "RESFIFO[$1],ADC Data Result FIFO Register $1"
bitfld.long 0x00 31. "VALID,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid"
bitfld.long 0x00 24.--27. "CMDSRC,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword..,1: CMD1 buffer used as control settings for this..,2: Corresponding command buffer used as control..,3: Corresponding command buffer used as control..,4: Corresponding command buffer used as control..,5: Corresponding command buffer used as control..,6: Corresponding command buffer used as control..,7: Corresponding command buffer used as control..,8: Corresponding command buffer used as control..,9: Corresponding command buffer used as control..,?,?,?,?,?,15: CMD15 buffer used as control settings for.."
newline
bitfld.long 0x00 20.--23. "LOOPCNT,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,?,?,?,?,?,15: Result is from 16th conversion in command"
bitfld.long 0x00 16.--19. "TSRC,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Corresponding trigger source initiated this..,3: Corresponding trigger source initiated this..,4: Corresponding trigger source initiated this..,5: Corresponding trigger source initiated this..,6: Corresponding trigger source initiated this..,7: Corresponding trigger source initiated this..,8: Corresponding trigger source initiated this..,9: Corresponding trigger source initiated this..,?,?,?,?,?,15: Trigger source 15 initiated this conversion"
newline
hexmask.long.word 0x00 0.--15. 1. "D,Data result"
repeat.end
tree.end
tree "AHB_SECURE_CTRL"
base ad:0x40148000
sif cpuis("IMXRT595-CM33")
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x10)++0x03
line.long 0x00 "ROM_MEM_RULE[$1],Memory ROM Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x30)++0x03
line.long 0x00 "FLEXSPI0_REGION0_RULE[$1],FLEXSPI0 Region 0 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x90)++0x03
line.long 0x00 "RAM00_RULE[$1],SRAM Partition 00 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xA0)++0x03
line.long 0x00 "RAM01_RULE[$1],SRAM Partition 01 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xC0)++0x03
line.long 0x00 "RAM02_RULE[$1],SRAM Partition 02 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xD0)++0x03
line.long 0x00 "RAM03_RULE[$1],SRAM Partition 03 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xF0)++0x03
line.long 0x00 "RAM04_RULE[$1],SRAM Partition 04 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "RAM05_RULE[$1],SRAM Partition 05 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x110)++0x03
line.long 0x00 "RAM06_RULE[$1],SRAM Partition 06 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x120)++0x03
line.long 0x00 "RAM07_RULE[$1],SRAM Partition 07 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x140)++0x03
line.long 0x00 "RAM08_RULE[$1],SRAM Partition 08 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x150)++0x03
line.long 0x00 "RAM09_RULE[$1],SRAM Partition 09 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x160)++0x03
line.long 0x00 "RAM10_RULE[$1],SRAM Partition 10 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x170)++0x03
line.long 0x00 "RAM11_RULE[$1],SRAM Partition 11 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x190)++0x03
line.long 0x00 "RAM12_RULE[$1],SRAM Partition 12 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1A0)++0x03
line.long 0x00 "RAM13_RULE[$1],SRAM Partition 13 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1B0)++0x03
line.long 0x00 "RAM14_RULE[$1],SRAM Partition 14 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1C0)++0x03
line.long 0x00 "RAM15_RULE[$1],SRAM Partition 15 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1E0)++0x03
line.long 0x00 "RAM16_RULE[$1],SRAM Partition 16 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1F0)++0x03
line.long 0x00 "RAM17_RULE[$1],SRAM Partition 17 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "RAM18_RULE[$1],SRAM Partition 18 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x210)++0x03
line.long 0x00 "RAM19_RULE[$1],SRAM Partition 19 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x230)++0x03
line.long 0x00 "RAM20_RULE[$1],SRAM Partition 20 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x240)++0x03
line.long 0x00 "RAM21_RULE[$1],SRAM Partition 21 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x250)++0x03
line.long 0x00 "RAM22_RULE[$1],SRAM Partition 22 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x260)++0x03
line.long 0x00 "RAM23_RULE[$1],SRAM Partition 23 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x280)++0x03
line.long 0x00 "RAM24_RULE[$1],SRAM Partition 24 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x290)++0x03
line.long 0x00 "RAM25_RULE[$1],SRAM Partition 25 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2A0)++0x03
line.long 0x00 "RAM26_RULE[$1],SRAM Partition 26 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2B0)++0x03
line.long 0x00 "RAM27_RULE[$1],SRAM Partition 27 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2D0)++0x03
line.long 0x00 "RAM28_RULE[$1],SRAM Partition 28 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2E0)++0x03
line.long 0x00 "RAM29_RULE[$1],SRAM Partition 29 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2F0)++0x03
line.long 0x00 "RAM30_RULE[$1],SRAM Partition 30 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x300)++0x03
line.long 0x00 "RAM31_RULE[$1],SRAM Partition 31 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x320)++0x03
line.long 0x00 "SDMA_RAM_RULE[$1],Smart DMA (SDMA) RAM Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x340)++0x03
line.long 0x00 "FLEXSPI1_REGION0_RULE[$1],FlexSPI1 Region 0 Rule(n) Register $1"
bitfld.long 0x00 28.--29. "RULE7,Rule 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,Rule 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,Rule 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,Rule 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat.end
group.long 0x3A0++0x03
line.long 0x00 "APB_BRIDGE_PER0_RULE0,APB Bridge Peripheral 0 Rule 0 Register"
bitfld.long 0x00 24.--25. "PUF,PUF" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "IOCON,IOCON" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "PVT,PVT" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "SYSCTL_A,SYSCTL_A" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "CLKCTL_A,CLKCTL_A" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RSTCTL_A,RSTCTL_A" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3A4++0x03
line.long 0x00 "APB_BRIDGE_PER0_RULE1,APB Bridge Peripheral 0 Rule 1 Register"
bitfld.long 0x00 28.--29. "MICRO_TICK,MICRO_TICK" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "WWDT0,WWDT0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3AC++0x03
line.long 0x00 "APB_BRIDGE_PER0_RULE3,APB Bridge Peripheral 0 Rule 3 Register"
bitfld.long 0x00 28.--29. "PROBE_IS_XVC,PROBE_IS (XVC)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "PROBE_IS_SYNC,PROBE_IS (SYNC)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3B0++0x03
line.long 0x00 "APB_BRIDGE_PER1_RULE0,APB Bridge Peripheral 1 Rule 0 Register"
bitfld.long 0x00 28.--29. "SDMA,Smart DMA (SDMA)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "PERIPHERAL_MUXES,Peripheral Muxes" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "GPIO_INT,GPIO_INT" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "SYSCTL_B,SYSCTL_B" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "CLKCTL_B,CLKCTL_B" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RSTCTL_B,RSTCTL_B" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3B4++0x03
line.long 0x00 "APB_BRIDGE_PER1_RULE1,APB Bridge Peripheral 1 Rule 1 Register"
bitfld.long 0x00 28.--29. "FREQMEASURE,FREQMEASURE" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "WWDT1,WWDT1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "MRT0,MRT0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "CT32B4,CT32B4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "CT32B3,CT32B3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "CT32B2,CT32B2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "CT32B1,CT32B1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "CT32B0,CT32B0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3B8++0x03
line.long 0x00 "APB_BRIDGE_PER1_RULE2,APB Bridge Peripheral 1 Rule 2 Register"
bitfld.long 0x00 28.--29. "I3C1,I3C1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "I3C0,I3C0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "CACHE_CONTROL_1_REGS,Cache Control 1 Registers" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "CACHE_CONTROL_0_REGS,Cache Control 0 Registers" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "FLEXIO_REGISTERS,FLEXIO Registers" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "DSI_HOST_CONTROLLER,DSI Host Controller" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RTC_WAKEUP,RTC Wakeup" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3BC++0x03
line.long 0x00 "APB_BRIDGE_PER1_RULE3,APB Bridge Peripheral 1 Rule 3 Register"
bitfld.long 0x00 28.--29. "MRT1,MRT1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3C0++0x03
line.long 0x00 "AHB_PERIPH0_SLAVE_RULE0,AHB Peripheral 0 Slave Rule 0 Register"
bitfld.long 0x00 28.--29. "DEBUG_MAILBOX,DEBUG_MAILBOX" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "FLEXCOMM3,FLEXCOMM 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "FLEXCOMM2,FLEXCOMM 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "FLEXCOMM1,FLEXCOMM 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "FLEXCOMM0,FLEXCOMM 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "DMA1,DMA 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "DMA0,DMA 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "HSGPIO,HSGPIO" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3D0++0x03
line.long 0x00 "AIPS_BRIDGE0_PER_RULE0,AIPS Bridge Peripheral 0 Rule 0 Register"
bitfld.long 0x00 20.--21. "ROM,ROM" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "OS_EVENT_TIMER_DSP_PORT,OS_EVENT TIMER (DSP PORT)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "OS_EVENT_TIMER_M33_PORT,OS_EVENT TIMER (M33 PORT)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "SEMAPHORE,Semaphore" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "MU1,MU1 (DSP PORT)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "MU0,MU0 (M33 PORT)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3E0++0x03
line.long 0x00 "AHB_PERIPH1_SLAVE_RULE0,AHB Peripheral 1 Slave Rule 0 Register"
bitfld.long 0x00 28.--29. "FLEXCOMM15,FLEXCOMM 15" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "FLEXCOMM14,FLEXCOMM 14" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "FLEXCOMM7,FLEXCOMM 7" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "FLEXCOMM6,FLEXCOMM 6" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "FLEXCOMM5,FLEXCOMM 5" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "FLEXCOMM4,FLEXCOMM 4" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "DMIC0,DMIC0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "CRC,CRC" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3E4++0x03
line.long 0x00 "AHB_PERIPH1_SLAVE_RULE1,AHB Peripheral 1 Slave Rule 1 Register"
bitfld.long 0x00 0.--1. "FLEXCOMM16,FLEXCOMM 16" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x400++0x03
line.long 0x00 "AIPS_BRIDGE1_PER_RULE0,AIPS Bridge Peripheral 1 Rule 0 Register"
bitfld.long 0x00 28.--29. "SDIO1_REGISTERS,SDIO 1 Registers" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "SDIO0_REGISTERS,SDIO 0 Registers" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "PMC_PMU_CONTROL,PMC (PMU CONTROL)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "FLEXSPI0_REGISTERS,FLEXSPI0 Registers" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "OTP_CONTROLLER_3,OTP Controller 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "OTP_CONTROLLER_2,OTP Controller 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "OTP_CONTROLLER_1,OTP Controller 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "OTP_CONTROLLER_0,OTP Controller 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x404++0x03
line.long 0x00 "AIPS_BRIDGE1_PER_RULE1,AIPS Bridge Peripheral 1 Rule 1 Register"
bitfld.long 0x00 16.--17. "FLEXSPI1_REGISTERS,FLEXSPI1 Registers" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "HS_USB_PHY,HS USB PHY" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "ADC0,ADC 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "ACMP0,ACMP 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RNG,RNG (Random Number Generator)" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x410++0x03
line.long 0x00 "AHB_PERIPH2_SLAVE_RULE0,AHB Peripheral 2 Slave Rule 0 Register"
bitfld.long 0x00 12.--13. "SCT,SCT" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "USB_HS_HOST,USB HS HOST" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "USB_HS_DEV,USB HS DEV" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "USB_HS_RAM,USB HS RAM" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x420++0x03
line.long 0x00 "AHB_SECURE_CTRL_PERIPH_RULE0,AHB Secure Control Peripheral Rule 0 Register"
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x430++0x03
line.long 0x00 "AHB_PERIPH3_SLAVE_RULE0,AHB Peripheral 3 Slave Rule 0 Register"
bitfld.long 0x00 28.--29. "FLEXCOMM10,FLEXCOMM 10" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 24.--25. "FLEXCOMM9,FLEXCOMM 9" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 20.--21. "FLEXCOMM8,FLEXCOMM 8" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "HASH,HASH" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "SECURE_GPIO,Secure GPIO" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "CASPER_RAM,CASPER RAM" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "CASPER,CASPER" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "POWERQUAD,POWERQUAD" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x434++0x03
line.long 0x00 "AHB_PERIPH3_SLAVE_RULE1,AHB Peripheral 3 Slave Rule 1 Register"
bitfld.long 0x00 20.--21. "AXI_SWITCH,AXI Switch" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 16.--17. "GPU,GPU" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 12.--13. "DCNANO,DCNANO" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "FLEXCOMM13,FLEXCOMM 13" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "FLEXCOMM12,FLEXCOMM 12" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "FLEXCOMM11,FLEXCOMM 11" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
repeat 18. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE00)++0x03
line.long 0x00 "SEC_VIO_ADDR[$1],Security Violation Address(n) Register $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_INFO_WRITE,Security violation access read/write indicator"
repeat.end
repeat 18. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE80)++0x03
line.long 0x00 "SEC_VIO_MISC_INFO[$1],Security Violation Miscellaneous Information at Address(n) Register $1"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,Security violation master number" "0: M33_CODE,1: M33 System,2: Powerquad,3: DSP,4: DMA0,5: DMA1,6: SDMA Instruction,7: SDMA_DATA,8: SDIO0,9: SDIO1,10: HASH,11: GPU,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,Security Violation Info Master Security Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,Security Violation Info Data Access" "0: CODE,1: DATA"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,Security violation access read/write indicator" "0: Read access,1: Write access"
repeat.end
group.long 0xF00++0x03
line.long 0x00 "SEC_VIO_INFO_VALID,Security Violation Info Validity for Address(n) Register"
eventfld.long 0x00 18. "VIO_INFO_VALID18,Violation information valid flag for AHB port 18" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 17. "VIO_INFO_VALID17,Violation information valid flag for AHB port 17" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 16. "VIO_INFO_VALID16,Violation information valid flag for AHB port 16" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 15. "VIO_INFO_VALID15,Violation information valid flag for AHB port 15" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 14. "VIO_INFO_VALID14,Violation information valid flag for AHB port 14" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 13. "VIO_INFO_VALID13,Violation information valid flag for AHB port 13" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 12. "VIO_INFO_VALID12,Violation information valid flag for AHB port 12" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 11. "VIO_INFO_VALID11,Violation information valid flag for AHB port 11" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 10. "VIO_INFO_VALID10,Violation information valid flag for AHB port 10" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 9. "VIO_INFO_VALID9,Violation information valid flag for AHB port 9" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 8. "VIO_INFO_VALID8,Violation information valid flag for AHB port 8" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 7. "VIO_INFO_VALID7,Violation information valid flag for AHB port 7" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 6. "VIO_INFO_VALID6,Violation information valid flag for AHB port 6" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 5. "VIO_INFO_VALID5,Violation information valid flag for AHB port 5" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 4. "VIO_INFO_VALID4,Violation information valid flag for AHB port 4" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 3. "VIO_INFO_VALID3,Violation information valid flag for AHB port 3" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 2. "VIO_INFO_VALID2,Violation information valid flag for AHB port 2" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 1. "VIO_INFO_VALID1,Violation information valid flag for AHB port 1" "0: NOT_VALID,1: VALID"
newline
eventfld.long 0x00 0. "VIO_INFO_VALID0,Violation information valid flag for AHB port 0" "0: NOT_VALID,1: VALID"
repeat 3. (increment 0 1) (increment 0 0x04)
group.long ($2+0xF80)++0x03
line.long 0x00 "SEC_GPIO_MASK[$1],GPIO Mask for Port index Register $1"
bitfld.long 0x00 31. "PIO0_PIN31_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 30. "PIO0_PIN30_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 29. "PIO0_PIN29_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 28. "PIO0_PIN28_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 27. "PIO0_PIN27_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 26. "PIO0_PIN26_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 25. "PIO0_PIN25_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 24. "PIO0_PIN24_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 23. "PIO0_PIN23_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 22. "PIO0_PIN22_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 21. "PIO0_PIN21_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 20. "PIO0_PIN20_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 19. "PIO0_PIN19_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 18. "PIO0_PIN18_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 17. "PIO0_PIN17_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 16. "PIO0_PIN16_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 15. "PIO0_PIN15_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 14. "PIO0_PIN14_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 13. "PIO0_PIN13_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 12. "PIO0_PIN12_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 11. "PIO0_PIN11_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 10. "PIO0_PIN10_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 9. "PIO0_PIN9_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 8. "PIO0_PIN8_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 7. "PIO0_PIN7_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 6. "PIO0_PIN6_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 5. "PIO0_PIN5_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 4. "PIO0_PIN4_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 3. "PIO0_PIN3_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 2. "PIO0_PIN2_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 1. "PIO0_PIN1_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 0. "PIO0_PIN0_SEC_MASK,Mask bit" "0: MASKED,1: NOT_MASKED"
repeat.end
group.long 0xFA0++0x03
line.long 0x00 "DSP_INT_MASK0,Secure Interrupt Mask for DSP Register"
bitfld.long 0x00 31. "PMUX_OUT26,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 30. "PMUX_OUT25,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 29. "PMUX_OUT24,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 28. "PMUX_OUT23,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 27. "PMUX_OUT22,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 26. "PMUX_OUT21,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 25. "PMUX_OUT20,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 24. "PMUX_OUT19,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 23. "PMUX_OUT18,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 22. "PMUX_OUT17,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 21. "PMUX_OUT16,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 20. "PMUX_OUT15,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 19. "PMUX_OUT14,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 18. "PMUX_OUT13,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 17. "PMUX_OUT12,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 16. "PMUX_OUT11,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 15. "PMUX_OUT10,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 14. "PMUX_OUT9,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 13. "PMUX_OUT8,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 12. "PMUX_OUT7,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 11. "PMUX_OUT6,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 10. "PMUX_OUT5,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 9. "PMUX_OUT4,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 8. "PMUX_OUT3,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 7. "PMUX_OUT2,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 6. "PMUX_OUT1,Mask bit" "0: MASKED,1: NOT_MASKED"
newline
bitfld.long 0x00 5. "PMUX_OUT0,Mask bit" "0: MASKED,1: NOT_MASKED"
group.long 0xFBC++0x03
line.long 0x00 "SEC_MASK_LOCK,Secure Mask Lock Register"
newline
bitfld.long 0x00 16.--17. "SEC_DSP_INT_MASK_LOCK,SEC_DSP_INT_MASK Lock" "?,1: SEC_DSP_INT_MASK cannot be written,2: SEC_DSP_INT_MASK can be written,?..."
newline
bitfld.long 0x00 14.--15. "SEC_GPIO_MASK7_LOCK,SEC_GPIO_MASK7 Lock" "?,1: SEC_GPIO_MASK7 cannot be written,2: SEC_GPIO_MASK7 can be written,?..."
newline
bitfld.long 0x00 12.--13. "SEC_GPIO_MASK6_LOCK,SEC_GPIO_MASK6 Lock" "?,1: SEC_GPIO_MASK6 cannot be written,2: SEC_GPIO_MASK6 can be written,?..."
newline
bitfld.long 0x00 10.--11. "SEC_GPIO_MASK5_LOCK,SEC_GPIO_MASK5 Lock" "?,1: SEC_GPIO_MASK5 cannot be written,2: SEC_GPIO_MASK5 can be written,?..."
newline
bitfld.long 0x00 8.--9. "SEC_GPIO_MASK4_LOCK,SEC_GPIO_MASK4 Lock" "?,1: SEC_GPIO_MASK4_LOCK cannot be written,2: SEC_GPIO_MASK4_LOCK can be written,?..."
newline
bitfld.long 0x00 6.--7. "SEC_GPIO_MASK3_LOCK,Secure GPIO _MASK3 Lock" "?,1: SEC_GPIO_MASK3 cannot be written,2: SEC_GPIO_MASK3 can be written,?..."
newline
bitfld.long 0x00 4.--5. "SEC_GPIO_MASK2_LOCK,Secure GPIO _MASK2 Lock" "?,1: SEC_GPIO_MASK2 cannot be written,2: SEC_GPIO_MASK2 can be written,?..."
newline
bitfld.long 0x00 2.--3. "SEC_GPIO_MASK1_LOCK,Secure GPIO _MASK1 Lock" "?,1: SEC_GPIO_MASK1 cannot be written,2: SEC_GPIO_MASK1 can be written,?..."
newline
bitfld.long 0x00 0.--1. "SEC_GPIO_MASK0_LOCK,Secure GPIO _MASK0 Lock" "?,1: SEC_GPIO_MASK0 cannot be written,2: SEC_GPIO_MASK0 can be written,?..."
group.long 0xFD0++0x03
line.long 0x00 "MASTER_SEC_LEVEL,Master Secure Level Register"
bitfld.long 0x00 30.--31. "MASTER_SEC_LEVEL_LOCK,Master Security Level Lock" "?,1: Lock writing to this register including these..,2: MASTER_SEC_LEVEL_LOCK_CAN_BE_WRITTEN,?..."
newline
bitfld.long 0x00 20.--21. "GPU,GPU" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
newline
bitfld.long 0x00 18.--19. "SDIO1,SDIO 1" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
newline
bitfld.long 0x00 16.--17. "SDIO0,SDIO 0" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
newline
bitfld.long 0x00 14.--15. "SDMA_D,Smart DMA (SDMA) Data" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
newline
bitfld.long 0x00 12.--13. "SDMA_I,Smart DMA (SDMA) Instruction" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
newline
bitfld.long 0x00 10.--11. "DMA1,DMA 1" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
newline
bitfld.long 0x00 8.--9. "DMA0,DMA 0" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
newline
bitfld.long 0x00 6.--7. "DSP,DSP" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
newline
bitfld.long 0x00 4.--5. "PQ,Power Quad" "0: Non-secure and non-privileged Master,1: Non-secure and privileged Master,2: Secure and non-privileged Master,3: Secure and privileged Master"
group.long 0xFD4++0x03
line.long 0x00 "MASTER_SEC_ANTI_POL_REG,Master Secure Level Register"
bitfld.long 0x00 30.--31. "MASTER_SEC_LEVEL_ANTIPOL_LOCK,Master Security Level Antipole Lock" "?,1: Lock writing to this register including these..,2: MASTER_SEC_LEVEL_ANTIPOL_LOCK_CAN_BE_WRITTEN,?..."
newline
bitfld.long 0x00 20.--21. "GPU,GPU" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "SDIO1,SDIO 1" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "SDIO0,SDIO 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "SDMA_D,Smart DMA (SDMA) Data" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "SDMA_I,Smart DMA (SDMA) Instruction" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "DMA1,DMA 1" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "DMA0,DMA 0" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "DSP,DSP" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "PQ,Power Quad" "0,1,2,3"
group.long 0xFEC++0x03
line.long 0x00 "CM33_LOCK_REG,Miscellaneous CPU0 Control Signals Register"
bitfld.long 0x00 30.--31. "CM33_LOCK_REG_LOCK,Lock CM33 Lock Register" "?,1: Does not allow writing to this register,2: Allows writing to this register,?..."
newline
bitfld.long 0x00 8.--9. "LOCK_SAU,Lock SAU" "?,1: SAU is locked,2: SAU can be used,?..."
newline
bitfld.long 0x00 6.--7. "LOCK_S_MPU,Lock Secure MPU" "?,1: Locks Secure MPU,2: Secure MPU can be used,?..."
newline
bitfld.long 0x00 4.--5. "LOCK_S_VTOR,Lock Secure VTOR" "?,1: Locks Secure VTOR,2: Secure VTOR can be used,?..."
newline
bitfld.long 0x00 2.--3. "LOCK_NS_MPU,Lock Non-Secure MPU" "?,1: Locks Non-Secure MPU,2: Non-Secure MPU can be used,?..."
newline
bitfld.long 0x00 0.--1. "LOCK_NS_VTOR,Lock Non-Secure VTOR" "?,1: Locks Non-Secure VTOR,2: Non-Secure VTOR can be used,?..."
group.long 0xFF8++0x03
line.long 0x00 "MISC_CTRL_DP_REG,Secure Control Duplicate Register"
bitfld.long 0x00 14.--15. "IDAU_ALL_NS,IDAU All Non-Secure" "?,1: IDAU is disabled which means that all..,2: IDAU is enabled (restrictive mode),?..."
newline
bitfld.long 0x00 12.--13. "DISABLE_SMART_MASTER_STRICT_MODE,Disable Smart Master Strict Mode" "?,1: Can access memories and peripherals at the..,2: Can access memories and peripherals at same..,?..."
newline
bitfld.long 0x00 10.--11. "DISABLE_SIMPLE_MASTER_STRICT_MODE,Disable Simple Master Strict Mode" "?,1: Can access memories and peripherals at the..,2: Can access memories and peripherals at same..,?..."
newline
bitfld.long 0x00 8.--9. "DISABLE_VIOLATION_ABORT,Disable Violation Abort" "?,1: The violation detected by the secure checker..,2: The violation detected by the secure checker..,?..."
newline
bitfld.long 0x00 6.--7. "ENABLE_NS_PRIV_CHECK,Enable Non-Secure Privilege Checking" "?,1: Enabled (restrictive mode),2: DISABLED,?..."
newline
bitfld.long 0x00 4.--5. "ENABLE_S_PRIV_CHECK,Enable Secure Privilege Checking" "?,1: Enabled (restrictive mode),2: DISABLED,?..."
newline
bitfld.long 0x00 2.--3. "ENABLE_SECURE_CHECKING,Enable Secure Checking" "?,1: Enabled (restrictive mode),2: DISABLED,?..."
newline
bitfld.long 0x00 0.--1. "WRITE_LOCK,Write Lock" "?,1: Writes to this register and to the Memory and..,2: Writes to this register and to the Memory and..,?..."
group.long 0xFFC++0x03
line.long 0x00 "MISC_CTRL_REG,Secure Control Register"
bitfld.long 0x00 14.--15. "IDAU_ALL_NS,IDAU All Non-Secure" "?,1: IDAU is disabled which means that all..,2: IDAU is enabled (restrictive mode),?..."
newline
bitfld.long 0x00 12.--13. "DISABLE_SMART_MASTER_STRICT_MODE,Disable Smart Master Strict Mode" "?,1: Can access memories and peripherals at the..,2: Can access memories and peripherals at same..,?..."
newline
bitfld.long 0x00 10.--11. "DISABLE_SIMPLE_MASTER_STRICT_MODE,Disable Simple Master Strict Mode" "?,1: Can access memories and peripherals at the..,2: Can access memories and peripherals at same..,?..."
newline
bitfld.long 0x00 8.--9. "DISABLE_VIOLATION_ABORT,Disable Violation Abort" "?,1: The violation detected by the secure checker..,2: The violation detected by the secure checker..,?..."
newline
bitfld.long 0x00 6.--7. "ENABLE_NS_PRIV_CHECK,Enable Non-Secure Privilege Checking" "?,1: Enabled (restrictive mode),2: DISABLED,?..."
newline
bitfld.long 0x00 4.--5. "ENABLE_S_PRIV_CHECK,Enable Secure Privilege Checking" "?,1: Enabled (restrictive mode),2: DISABLED,?..."
newline
bitfld.long 0x00 2.--3. "ENABLE_SECURE_CHECKING,Enable Secure Checking" "?,1: Enabled (restrictive mode),2: DISABLED,?..."
newline
bitfld.long 0x00 0.--1. "WRITE_LOCK,Write Lock" "?,1: Writes to this register and to the Memory and..,2: Writes to this register and to the Memory and..,?..."
endif
repeat 4. (increment 0 1)(increment 0 0x10)
tree "FLEXSPI0_REGION1_4_RULE[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0x40)++0x03
line.long 0x00 "FLEXSPI0_REGION_RULE0,FLEXSPI0 Region index Rule 0 Register"
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
endif
tree.end
repeat.end
repeat 4. (increment 0 1)(increment 0 0x320)
tree "FLEXSPI1_REGIONn_RULE[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0x350)++0x03
line.long 0x00 "FLEXSPI1_REGION_RULE0,FlexSPI1 Region index Rule 0 Register"
bitfld.long 0x00 12.--13. "RULE3,Rule 3" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,Rule 2" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,Rule 1" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,Rule 0" "0: Non-secure and non-privilege user access..,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
endif
tree.end
repeat.end
tree.end
tree "AXI_SWITCH_AMIB"
base ad:0x40282000
group.long 0x08++0x03
line.long 0x00 "FN_MOD_BM_ISS,Bus Matrix Issuing Functionality Modification"
bitfld.long 0x00 0.--1. "FN_MOD_BM_ISS,Read channel QoS value" "0,1,2,3"
group.long 0x24++0x03
line.long 0x00 "FN_MOD2,Bypass Merge"
bitfld.long 0x00 0. "FN_MOD2,Bypass Merge" "0,1"
group.long 0x108++0x03
line.long 0x00 "FN_MOD,Issuing Functionality Modification"
bitfld.long 0x00 0.--1. "FN_MOD,Bypass Merge" "0,1,2,3"
tree.end
tree "AXI_SWITCH_ASIB"
base ad:0x402C2000
group.long 0x100++0x03
line.long 0x00 "READ_QOS,Read channel QoS value"
bitfld.long 0x00 0.--3. "READ_QOS,Read channel QoS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x104++0x03
line.long 0x00 "WRITE_QOS,WRITE channel QoS value"
bitfld.long 0x00 0.--3. "WRITE_QOS,Write channel QoS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x108++0x03
line.long 0x00 "FN_MOD,Issuing Functionality Modification"
bitfld.long 0x00 0.--1. "WRITE_QOS,Write channel QoS value" "0,1,2,3"
tree.end
tree "CACHE64_CTRL (CACHE64)"
repeat 2. (list 0. 1.) (list ad:0x40033000 ad:0x40034000)
tree "CACHE64_CTRL$1"
base $2
group.long 0x800++0x03
line.long 0x00 "CCR,Cache control register"
bitfld.long 0x00 31. "GO,Initiate Cache Command" "0: Write: no effect,1: Write: initiate command indicated by bits 27-24"
bitfld.long 0x00 27. "PUSHW1,Push Way 1" "0: no_operation,1: When setting the GO bit push all modified.."
newline
bitfld.long 0x00 26. "INVW1,Invalidate Way 1" "0: no_operation,1: When setting the GO bit invalidate all lines.."
bitfld.long 0x00 25. "PUSHW0,Push Way 0" "0: no_operation,1: When setting the GO bit push all modified.."
newline
bitfld.long 0x00 24. "INVW0,Invalidate Way 0" "0: no_operation,1: When setting the GO bit invalidate all lines.."
bitfld.long 0x00 1. "ENWRBUF,Enable Write Buffer" "0: Write buffer disabled,1: Write buffer enabled"
newline
bitfld.long 0x00 0. "ENCACHE,Cache enable" "0: Cache disabled,1: Cache enabled"
group.long 0x804++0x03
line.long 0x00 "CLCR,Cache line control register"
bitfld.long 0x00 27. "LACC,Line access type" "0: read,1: write"
bitfld.long 0x00 26. "LADSEL,Line Address Select" "0: Cache address,1: Physical address"
newline
bitfld.long 0x00 24.--25. "LCMD,Line Command" "0: Search and read or write,1: invalidate,2: push,3: clear"
bitfld.long 0x00 22. "LCWAY,Line Command Way" "0,1"
newline
bitfld.long 0x00 21. "LCIMB,Line Command Initial Modified Bit" "0,1"
bitfld.long 0x00 20. "LCIVB,Line Command Initial Valid Bit" "0,1"
newline
bitfld.long 0x00 16. "TDSEL,Tag/Data Select" "0: data,1: tag"
bitfld.long 0x00 14. "WSEL,Way select" "0: Way 0,1: Way 1"
newline
hexmask.long.word 0x00 2.--13. 1. "CACHEADDR,Cache address"
bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.."
group.long 0x808++0x03
line.long 0x00 "CSAR,Cache search address register"
bitfld.long 0x00 29.--31. "PHYADDR31_29,Physical Address" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 1.--27. 1. "PHYADDR27_1,Physical Address"
newline
bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.."
group.long 0x80C++0x03
line.long 0x00 "CCVR,Cache read/write value register"
hexmask.long 0x00 0.--31. 1. "DATA,Cache read/write Data"
tree.end
repeat.end
tree.end
tree "CACHE64_POLSEL"
repeat 2. (list 0. 1.) (list ad:0x40033000 ad:0x40034000)
tree "CACHE64_POLSEL$1"
base $2
group.long 0x14++0x03
line.long 0x00 "REG0_TOP,Region 0 Top Boundary"
hexmask.long.tbyte 0x00 10.--26. 1. "REG0_TOP,Upper limit of Region 0"
group.long 0x18++0x03
line.long 0x00 "REG1_TOP,Region 1 Top Boundary"
hexmask.long.tbyte 0x00 10.--26. 1. "REG1_TOP,Upper limit of Region 1"
group.long 0x1C++0x03
line.long 0x00 "POLSEL,Policy Select"
bitfld.long 0x00 4.--5. "REG02_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG2_11"
bitfld.long 0x00 2.--3. "REG1_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG1_11"
newline
bitfld.long 0x00 0.--1. "REG0_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG0_11"
tree.end
repeat.end
tree.end
tree "CASPER"
base ad:0x40201000
group.long 0x00++0x03
line.long 0x00 "CTRL0,Control 0"
hexmask.long.word 0x00 18.--28. 1. "CDOFF,CD Offset"
bitfld.long 0x00 16. "CDBPAIR,CDOFF Bank Pair" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
newline
bitfld.long 0x00 2. "ABOFF,AB Offset" "0,1"
bitfld.long 0x00 0. "ABBPAIR,ABOFF Bank Pair" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
group.long 0x04++0x03
line.long 0x00 "CTRL1,Control 1"
bitfld.long 0x00 30.--31. "CSKIP,Skip Rules on Carry" "0: NO_SKIP,1: Skip if Carry is 1,2: Skip if Carry is 0,3: Set CTRLOFF to CDOFF and Skip"
hexmask.long.word 0x00 18.--28. 1. "RESOFF,Result Offset"
newline
bitfld.long 0x00 16. "RESBPAIR,RESOFF Bank Pair" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
hexmask.long.byte 0x00 8.--15. 1. "MODE,Mode"
newline
hexmask.long.byte 0x00 0.--7. 1. "ITER,Interation Counter"
group.long 0x0C++0x03
line.long 0x00 "STATUS,Status"
rbitfld.long 0x00 5. "BUSY,Busy" "0: Not busy - is idle,1: Is busy"
rbitfld.long 0x00 4. "CARRY,Carry" "0: Carry was 0 or no carry,1: Carry was 1"
newline
bitfld.long 0x00 0. "DONE,Done" "0: Busy or just cleared,1: Completed last operation"
group.long 0x10++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set"
bitfld.long 0x00 0. "DONE,Done" "0: Do not interrupt when done,1: Interrupt when done"
group.long 0x14++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear"
eventfld.long 0x00 0. "DONE,Done" "0: If written 0 ignored,1: If written 1 do not interrupt when done"
rgroup.long 0x18++0x03
line.long 0x00 "INTSTAT,Interrupt status"
bitfld.long 0x00 0. "DONE,If set interrupt is caused by accelerator being done" "0: Not caused by accelerator being done,1: Caused by accelerator being done"
group.long 0x20++0x03
line.long 0x00 "AREG,A Register"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register Value"
group.long 0x24++0x03
line.long 0x00 "BREG,B Register"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register Value"
group.long 0x28++0x03
line.long 0x00 "CREG,C Register"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register Value"
group.long 0x2C++0x03
line.long 0x00 "DREG,D Register"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register Value"
group.long 0x30++0x03
line.long 0x00 "RES0,Result Register 0"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register Value"
group.long 0x34++0x03
line.long 0x00 "RES1,Result Register 1"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register to hold working result (from multiplier adder/xor etc)"
group.long 0x38++0x03
line.long 0x00 "RES2,Result Register 2"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register Value"
group.long 0x3C++0x03
line.long 0x00 "RES3,Result Register 3"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register to hold working result (from multiplier adder/xor etc)"
group.long 0x60++0x03
line.long 0x00 "MASK,Mask"
hexmask.long 0x00 0.--31. 1. "MASK,Mask"
group.long 0x64++0x03
line.long 0x00 "REMASK,Remask"
hexmask.long 0x00 0.--31. 1. "MASK,Mask"
group.long 0x80++0x03
line.long 0x00 "LOCK,Lock"
hexmask.long.word 0x00 4.--16. 1. "KEY,Key"
bitfld.long 0x00 0. "LOCK,Lock" "0: UNLOCK,1: Lock to current security level"
tree.end
tree "CLKCTL (Clock Controller 0)"
tree "CLKCTL0"
base ad:0x40001000
group.long 0x10++0x03
line.long 0x00 "PSCCTL0,Clock Control 0"
bitfld.long 0x00 30. "SMARTDMA_CLK,Smart DMA clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 28. "MIPI_DSI_CTLR_CLK,MIPI-DSI Controller clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 27. "DISPLAY_CTLR_CLK,Display Controller clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 26. "GPU_CLK,GPU clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 24. "SCT_CLK,SCT clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 23. "USBHS_SRAM_CLK,USB HS SRAM clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 22. "USBHS_HOST_CLK,USB HS Host clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 21. "USBHS_DEVICE_CLK,USB HS Device clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 20. "USBHS_PHY_CLK,USB HS PHY clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 18. "FLEXSPI1_CLK,FLEXSPI1 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 17. "OTP_CTLR_CLK,OTP Controller clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 16. "FLEXSPI0_OTFAD_CLK,FLEXSPI0 / OTFAD clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 12. "RNG_CLK,Random Number Generator (RNG) clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 11. "PUF_CLK,PUF clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 10. "HASHCRYPT_CLK,HASHCRYPT clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 9. "CASPER_CLK,CASPER clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 8. "POWERQUAD_CLK,POWERQUAD clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 4. "AXI_CTLR_CLK,AXI Controller clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 3. "AXI_SWITCH_CLK,AXI Switch clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 2. "ROM_CTRLR_CLK,128KB ROM Controller clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 1. "DSP_CLK,DSP clock control" "0: Disable clock,1: Enable clock"
group.long 0x14++0x03
line.long 0x00 "PSCCTL1,Clock Control 1"
bitfld.long 0x00 24. "SHSGPIO0_CLK,SHSGPIO0 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 16. "ADC0_CLK,ADC0 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 15. "ACMP0_CLK,ACMP0 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 3. "SDIO1_CLK,SDIO1 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 2. "SDIO0_CLK,SDIO0 clock control" "0: Disable clock,1: Enable clock"
group.long 0x18++0x03
line.long 0x00 "PSCCTL2,Clock Control 2"
bitfld.long 0x00 29. "PMC_CLK,Power Management Controller clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 1. "WWDT0_CLK,Watchdog Timer 0 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 0. "UTICK0_CLK,Micro-Tick Timer 0 clock control" "0: Disable clock,1: Enable clock"
wgroup.long 0x40++0x03
line.long 0x00 "PSCCTL0_SET,Clock Control 0 Set"
bitfld.long 0x00 30. "SMARTDMA_CLK,Smart DMA clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 28. "MIPI_DSI_CTLR_CLK,MIPI-DSI Controller clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 27. "DISPLAY_CTLR_CLK,Display Controller clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 26. "GPU_CLK,GPU clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 24. "SCT_CLK,SCT clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 23. "USBHS_SRAM_CLK,USB HS SRAM clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 22. "USBHS_HOST_CLK,USB HS Host clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 21. "USBHS_DEVICE_CLK,USB HS Device clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 20. "USBHS_PHY_CLK,USB HS PHY clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 18. "FLEXSPI1_CLK,FLEXSPI1 clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 17. "OTP_CTLR_CLK,OTP Controller clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 16. "FLEXSPI0_OTFAD_CLK,FLEXSPI0 / OTFAD clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 12. "RNG_CLK,Random Number Generator (RNG) clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 11. "PUF_CLK,PUF clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 10. "HASHCRYPT_CLK,HASHCRYPT clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 9. "CASPER_CLK,CASPER clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 8. "POWERQUAD_CLK,POWERQUAD clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 4. "AXI_CTLR_CLK,AXI Controller clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 3. "AXI_SWITCH_CLK,AXI Switch clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
bitfld.long 0x00 2. "ROM_CTRLR_CLK,128KB ROM Controller clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
newline
bitfld.long 0x00 1. "DSP_CLK,DSP clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL0 register"
wgroup.long 0x44++0x03
line.long 0x00 "PSCCTL1_SET,Clock Control 1 Set"
bitfld.long 0x00 24. "SHSGPIO0_CLK,SHSGPIO0 clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL1 register"
bitfld.long 0x00 16. "ADC0_CLK,ADC0 clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL1 register"
newline
bitfld.long 0x00 15. "ACMP0_CLK,ACMP0 clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL1 register"
bitfld.long 0x00 3. "SDIO1_CLK,SDIO1 clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL1 register"
newline
bitfld.long 0x00 2. "SDIO0_CLK,SDIO0 clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL1 register"
wgroup.long 0x48++0x03
line.long 0x00 "PSCCTL2_SET,Clock Control 2 Set"
bitfld.long 0x00 29. "PMC,Power Management Controller clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL2 register"
bitfld.long 0x00 1. "WWDT0_CLK,Watchdog Timer 0 clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL2 register"
newline
bitfld.long 0x00 0. "UTICK0_CLK,Micro-Tick Timer 0 clock set" "0: NO_EFFECT,1: Sets the corresponding bit in PSCCTL2 register"
wgroup.long 0x70++0x03
line.long 0x00 "PSCCTL0_CLR,Clock Control 0 Clear"
bitfld.long 0x00 30. "SMARTDMA_CLK,Smart DMA clock set" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 28. "MIPI_DSI_CTLR_CLK,MIPI-DSI Controller clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 27. "DISPLAY_CTLR_CLK,Display Controller clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 26. "GPU_CLK,GPU clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 24. "SCT_CLK,SCT clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 23. "USBHS_SRAM_CLK,USB HS SRAM clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 22. "USBHS_HOST_CLK,USB HS Host clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 21. "USBHS_DEVICE_CLK,USB HS Device clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 20. "USBHS_PHY_CLK,USB HS PHY clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 18. "FLEXSPI1_CLK,FLEXSPI1 clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 17. "OTP_CTLR_CLK,OTP Controller clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 16. "FLEXSPI0_OTFAD_CLK,FLEXSPI0 / OTFAD clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 12. "RNG_CLK,RNG clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 11. "PUF_CLK,PUF clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 10. "HASHCRYPT_CLK,HASHCRYPT clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 9. "CASPER_CLK,CASPER clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 8. "POWERQUAD_CLK,POWERQUAD clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 4. "AXI_CTLR_CLK,AXI Controller clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 3. "AXI_SWITCH_CLK,AXI Switch clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
bitfld.long 0x00 2. "ROM_CTRLR_CLK,128KB ROM Controller clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
newline
bitfld.long 0x00 1. "DSP_CLK,DSP clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL0.."
wgroup.long 0x74++0x03
line.long 0x00 "PSCCTL1_CLR,Clock Control 1 Clear"
bitfld.long 0x00 24. "SHSGPIO0_CLK,SHSGPIO0 clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL1.."
bitfld.long 0x00 16. "ADC0_CLK,ADC0 clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL1.."
newline
bitfld.long 0x00 15. "ACMP0_CLK,ACMP0 clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL1.."
bitfld.long 0x00 3. "SDIO1_CLK,SDIO1 clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL1.."
newline
bitfld.long 0x00 2. "SDIO0_CLK,SDIO0 clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL1.."
wgroup.long 0x78++0x03
line.long 0x00 "PSCCTL2_CLR,Clock Control 2 Clear"
bitfld.long 0x00 29. "PMC_CLK,Power Management Controller clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL2.."
bitfld.long 0x00 1. "WWDT0_CLK,Watchdog Timer 0 clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL2.."
newline
bitfld.long 0x00 0. "UTICK0_CLK,Micro-Tick Timer 0 clock clear" "0: NO_EFFECT,1: Clears the corresponding bit in PSCCTL2.."
group.long 0x80++0x03
line.long 0x00 "FRO_CONTROL,Free Running Oscillator Control"
bitfld.long 0x00 31. "ENA_TUNE,Enable Tuning" "0: ENA_TUNE_CLEAR,1: ENA_TUNE_START"
bitfld.long 0x00 21.--25. "THRESH_RANGE_LOW,Threshold Range Lower Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "THRESH_RANGE_UP,Threshold Range Upper Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "EXP_COUNT,Expected Count"
rgroup.long 0x84++0x03
line.long 0x00 "FRO_CAPVAL,Free Running Oscillator Captured Value"
bitfld.long 0x00 31. "DATA_VALID,Data Valid" "0: CAPVAL data is not valid,1: CAPVAL data is valid"
hexmask.long.word 0x00 0.--15. 1. "CAPVAL,Captured Value"
group.long 0x8C++0x03
line.long 0x00 "FRO_RDTRIM,Free Running Oscillator Trim"
hexmask.long.word 0x00 0.--10. 1. "TRIM,It is the trim value supplied to the oscillator"
group.long 0x90++0x03
line.long 0x00 "FRO_SCTRIM,Free Running OscillatorSC Trim"
hexmask.long.word 0x00 0.--10. 1. "TRIM,sc_trim value for the oscillator"
group.long 0x108++0x03
line.long 0x00 "FRODIVSEL,FRO Clock Divider"
bitfld.long 0x00 0.--1. "SEL,Select clock" "0: DIVIDEBY2,1: DIVIDEBY4,2: DIVIDEBY8,3: DIVIDEBY16"
rgroup.long 0x10C++0x03
line.long 0x00 "FROCLKSTATUS,FRO Clock Status"
bitfld.long 0x00 0. "CLK_OK,FRO Clock OK" "0: FRO clock has not yet reached its final..,1: FRO clock has reached its final frequency"
group.long 0x110++0x03
line.long 0x00 "FRODIVOEN,FRO Enable Register"
bitfld.long 0x00 4. "FRO_DIV16_O_EN,FRO Divided-by-16 Clock Enable" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 3. "FRO_DIV8_O_EN,FRO Divided-by-8 Clock Enable" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 2. "FRO_DIV4_O_EN,FRO Divided-by-4 Clock Enable" "0: Disable clock,1: Enable clock"
bitfld.long 0x00 1. "FRO_DIV2_O_EN,FRO Divided-by-2 Clock Enable" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x00 0. "FRO_DIV1_O_EN,FRO Divided-by-1 Clock Enable" "0: Disable clock,1: Enable clock"
group.long 0x130++0x03
line.long 0x00 "LOWFREQCLKDIV,Low Frequency Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Low Frequency Clock Divider Value"
group.long 0x160++0x03
line.long 0x00 "SYSOSCCTL0,System Oscillator Control 0"
bitfld.long 0x00 1. "BYPASS_ENABLE,Bypass Enable" "0: Enable Normal mode,1: Enable Bypass mode"
bitfld.long 0x00 0. "LP_ENABLE,Low Power Mode Enable" "0: Enable High Gain Mode (HP),1: Enable Low Power mode (LP)"
group.long 0x168++0x03
line.long 0x00 "SYSOSCBYPASS,OSC Clock Source Select"
bitfld.long 0x00 0.--2. "SEL,Select SYSOSC Bypass" "0: Select OSC Clock,1: Select Clock IN clock,?,?,?,?,?,7: None this may be selected to reduce power.."
group.long 0x190++0x03
line.long 0x00 "LPOSCCTL0,Low Power Oscillator Control 0"
bitfld.long 0x00 31. "CLKRDY,LPOSC Clock Ready" "0: LPOSC clock is not ready,1: LPOSC clock is ready"
group.long 0x1C0++0x03
line.long 0x00 "OSC32KHZCTL0,32 KHz Oscillator Control 0"
bitfld.long 0x00 0. "ENA32KHZ,32 KHz Oscillator Enable" "0: Disable oscillator,1: Enable oscillator"
group.long 0x200++0x03
line.long 0x00 "SYSPLL0CLKSEL,System PLL 0 Clock Select"
bitfld.long 0x00 0.--2. "SEL,System PLL0 Reference Input Clock Source" "0: FRO_DIV8 Clock,1: OSC_CLK clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x204++0x03
line.long 0x00 "SYSPLL0CTL0,System PLL0 Control 0"
hexmask.long.byte 0x00 16.--23. 1. "MULT,Multiplication Factor"
bitfld.long 0x00 13. "HOLDRINGOFF_ENA,Hold Ring Off Control" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "RESET,SYSPLL0 Reset" "0: SYSPLL0 reset is removed,1: SYSPLL0 is placed into reset"
bitfld.long 0x00 0. "BYPASS,SYSPLL0 BYPASS Mode" "0: PFD outputs are PFD-programmed clocks,1: Bypass Mode"
group.long 0x20C++0x03
line.long 0x00 "SYSPLL0LOCKTIMEDIV2,System PLL0 Lock Time Div2"
hexmask.long.word 0x00 0.--15. 1. "LOCKTIMEDIV2,SYSPLL0 Lock Time Divide-by-2"
group.long 0x210++0x03
line.long 0x00 "SYSPLL0NUM,System PLL0 Numerator"
hexmask.long 0x00 0.--29. 1. "NUM,Numerator of the SYSPLL0 fractional loop divider"
group.long 0x214++0x03
line.long 0x00 "SYSPLL0DENOM,System PLL0 Denominator"
hexmask.long 0x00 0.--29. 1. "DENOM,Denominator of the SYSPLL0 fractional loop divider"
group.long 0x218++0x03
line.long 0x00 "SYSPLL0PFD,System PLL0 PFD"
bitfld.long 0x00 31. "PFD3_CLKGATE,PFD3 Clock Gate" "0: PFD3 clock is not gated,1: PFD3 clock is gated"
bitfld.long 0x00 30. "PFD3_CLKRDY,PFD3 Clock Ready Status Flag" "0: PFD3 clock is not ready,1: PFD3 clock is ready"
newline
bitfld.long 0x00 24.--29. "PFD3,PLL Fractional Divider 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. "PFD2_CLKGATE,PFD2 Clock Gate" "0: PFD2 clock is not gated,1: PFD2 clock is gated"
newline
bitfld.long 0x00 22. "PFD2_CLKRDY,PFD2 Clock Ready Status Flag" "0: PFD2 clock is not ready,1: PFD2 clock is ready"
bitfld.long 0x00 16.--21. "PFD2,PLL Fractional Divider 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15. "PFD1_CLKGATE,PFD1 Clock Gate" "0: PFD1 clock is not gated,1: PFD1 clock is gated"
bitfld.long 0x00 14. "PFD1_CLKRDY,PFD1 Clock Ready Status Flag" "0: PFD1 clock is not ready,1: PFD1 clock is ready"
newline
bitfld.long 0x00 8.--13. "PFD1,PLL Fractional Divider 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "PFD0_CLKGATE,PFD0 Clock Gate" "0: PFD0 clock is not gated,1: PFD0 clock is gated"
newline
bitfld.long 0x00 6. "PFD0_CLKRDY,PFD0 Clock Ready Status Flag" "0: PFD0 clock is not ready,1: PFD0 clock is ready"
bitfld.long 0x00 0.--5. "PFD0,PLL Fractional Divider 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x240++0x03
line.long 0x00 "MAINPLLCLKDIV,Main PLL Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0,1"
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0,1"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Low Frequency Clock Divider Value"
group.long 0x244++0x03
line.long 0x00 "DSPPLLCLKDIV,DSP PLL Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0,1"
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0,1"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Low Frequency Clock Divider Value"
group.long 0x248++0x03
line.long 0x00 "AUX0PLLCLKDIV,AUX0 PLL Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0,1"
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0,1"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Low Frequency Clock Divider Value"
group.long 0x24C++0x03
line.long 0x00 "AUX1PLLCLKDIV,AUX1 PLL Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0,1"
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0,1"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Low Frequency Clock Divider Value"
group.long 0x400++0x03
line.long 0x00 "SYSCPUAHBCLKDIV,System CPU AHB Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x430++0x03
line.long 0x00 "MAINCLKSELA,Main Clock Select A"
bitfld.long 0x00 0.--1. "SEL,Control Main 1st Stage Control Clock Source" "0: Low Power Oscillator Clock (LPOSC),1: FRODIV which is the output of the FRODIVSEL mux,2: OSC_CLK clock,3: FRO_DIV1 clock"
group.long 0x434++0x03
line.long 0x00 "MAINCLKSELB,Main Clock Select B"
bitfld.long 0x00 0.--1. "SEL,Main Clock Source Selection" "0: MAINCLKSELA 1st Stage Clock,1: Main System PLL Clock,2: RTC 32 KHz Clock,?..."
group.long 0x500++0x03
line.long 0x00 "PFC0DIV,PFC divider 0 (trace clock)"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x504++0x03
line.long 0x00 "PFC1DIV,PFC divider 1 (USB HS PHY bus clock)"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x620++0x03
line.long 0x00 "FLEXSPI0FCLKSEL,FlexSPI0 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Main Clock,1: Main System PLL Clock,2: SYSPLL0 AUX0_PLL_Clock,3: FRO_DIV1 Clock,4: SYSPLL0 AUX1_PLL_Clock,?,?,7: None this may be selected to reduce power.."
group.long 0x624++0x03
line.long 0x00 "FLEXSPI0FCLKDIV,FlexSPI0 Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x630++0x03
line.long 0x00 "FLEXSPI1FCLKSEL,FlexSPI1 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Main Clock,1: Main System PLL Clock,2: SYSPLL0 AUX0_PLL_Clock,3: FRO_DIV1 Clock,4: SYSPLL0 AUX1_PLL_Clock,?,?,7: None this may be selected to reduce power.."
group.long 0x634++0x03
line.long 0x00 "FLEXSPI1FCLKDIV,FlexSPI1 Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x640++0x03
line.long 0x00 "SCTFCLKSEL,SCT Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Main Clock,1: Main System PLL Clock,2: SYSPLL0 AUX0_PLL_Clock,3: FRO_DIV1 Clock,4: SYSPLL0 AUX1_PLL_Clock,5: AUDIO PLL Clock,?,7: None this may be selected to reduce power.."
group.long 0x644++0x03
line.long 0x00 "SCTIN7CLKDIV,SCT Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x660++0x03
line.long 0x00 "USBHSFCLKSEL,High Speed USB Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: OSC_CLK Clock,1: Main Clock,?,3: AUX0_PLL_CLOCK,?,?,?,7: None this may be selected to reduce power.."
group.long 0x664++0x03
line.long 0x00 "USBHSFCLKDIV,High Speed USB Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x680++0x03
line.long 0x00 "SDIO0FCLKSEL,SDIO0 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Main Clock,1: System PLL Clock,2: SYSPLL0 AUX0_PLL_Clock,3: FRO_DIV2,4: SYSPLL0 AUX1_PLL_Clock,?,?,7: None this may be selected to reduce power.."
group.long 0x684++0x03
line.long 0x00 "SDIO0FCLKDIV,SDIO0 Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x690++0x03
line.long 0x00 "SDIO1FCLKSEL,SDIO1 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Main Clock,1: Main System PLL Clock,2: SYSPLL0 AUX0_PLL_Clock,3: FRO_DIV2,4: SYSPLL0 AUX1_PLL_Clock,?,?,7: None this may be selected to reduce power.."
group.long 0x694++0x03
line.long 0x00 "SDIO1FCLKDIV,SDIO1 Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x6D0++0x03
line.long 0x00 "ADC0FCLKSEL0,ADC0 Functional Clock Select 0"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: OSC_CLK Clock,1: Low Power Oscillator Clock (LPOSC),2: FRO_DIV4,?,?,?,?,7: None this may be selected to reduce power.."
group.long 0x6D4++0x03
line.long 0x00 "ADC0FCLKSEL1,ADC0 Functional Clock Select 1"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: ADC0FCLKSEL0 Multiplexed Output,1: SYSPLL0 MAIN_CLK (PFD0 Output),2: SYSPLL0 AUX0_PLL_Clock,3: SYSPLL0 AUX1_PLL_Clock,?,?,?,7: None this may be selected to reduce power.."
group.long 0x6D8++0x03
line.long 0x00 "ADC0FCLKDIV,ADC0 Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x700++0x03
line.long 0x00 "UTICKFCLKSEL,UTICK Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Low Power Oscillator Clock (LPOSC),?,?,?,?,?,?,7: None this may be selected to reduce power.."
group.long 0x720++0x03
line.long 0x00 "WDT0FCLKSEL,WDT0 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Low Power Oscillator Clock (LPOSC),?,?,?,?,?,?,7: None this may be selected to reduce power.."
group.long 0x730++0x03
line.long 0x00 "A32KHZWAKECLKSEL,32 KHz Wake Clock Source Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: A32KHZ,1: Low Power Oscillator Clock (LPOSC) divided by..,?,?,?,?,?,7: None this may be selected to reduce power.."
group.long 0x734++0x03
line.long 0x00 "A32KHZWAKECLKDIV,32 KHz Wake Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x760++0x03
line.long 0x00 "SYSTICKFCLKSEL,SYSTICK Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Systick Divider Output Clock,1: Low Power Oscillator Clock (LPOSC),2: 32 KHz RTC Clock,?,?,?,?,7: None this may be selected to reduce power.."
group.long 0x764++0x03
line.long 0x00 "SYSTICKFCLKDIV,SYSTICK Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x770++0x03
line.long 0x00 "DPHYCLKSEL,MIPI-DSI PHY Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: FRO_DIV1 Clock,1: SYSPLL0 MAIN_CLK (PFD0 Output),2: SYSPLL0 AUX0_PLL_Clock,3: SYSPLL0 AUX1_PLL_Clock,?,?,?,7: None this may be selected to reduce power.."
group.long 0x774++0x03
line.long 0x00 "DPHYCLKDIV,MIPI-DSI PHY Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x778++0x03
line.long 0x00 "DPHYESCCLKSEL,MIPI-DSI DPHY Escape Mode Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: FRO_DIV1 clock,1: FRO_DIV16 Clock,?,?,?,?,?,7: None this may be selected to reduce power.."
group.long 0x77C++0x03
line.long 0x00 "DPHYESCRXCLKDIV,MIPI-DSI DPHY Escape Mode Receive Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x780++0x03
line.long 0x00 "DPHYESCTXCLKDIV,MIPI-DSI DPHY Escape Mode Tramsmit Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x790++0x03
line.long 0x00 "GPUCLKSEL,GPU Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: Main Clock,1: FRO_DIV1 clock,2: SYSPLL0 MAIN_CLK (PFD0 Output),3: SYSPLL0 AUX0_PLL_Clock,4: SYSPLL0 AUX1_PLL_Clock,?,?,7: None this may be selected to reduce power.."
group.long 0x794++0x03
line.long 0x00 "GPUCLKDIV,GPU Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
group.long 0x7A0++0x03
line.long 0x00 "DCPIXELCLKSEL,LCDIF Pixel Clock Select"
bitfld.long 0x00 0.--2. "SEL,Select Clock Source" "0: MIPI-DSI PHY Clock,1: Main Clock,2: FRO_DIV1 Clock,3: SYSPLL0 MAIN_CLK (PFD0 Output),4: SYSPLL0 AUX0_PLL_Clock,5: SYSPLL0 AUX1_PLL_Clock,?,7: None this may be selected to reduce power.."
group.long 0x7A4++0x03
line.long 0x00 "DCPIXELCLKDIV,LCDIF Pixel Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: The change to the divider value has finished,1: A change is being made to the divider value"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Divider Value Selection"
tree.end
tree "CLKCTL1"
base ad:0x40021000
group.long 0x10++0x03
line.long 0x00 "PSCCTL0,Clock Control 0"
bitfld.long 0x00 29. "FlexIO,FlexIO clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 27. "OSEVENT_TIMER,OS event timer bus clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 25. "FC16_SPI_CLK,Flexcomm Interface 16 SPI clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 24. "DMIC0,DMIC0 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 23. "FC15_I2C_CLK,Flexcomm Interface 15 I2C clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 22. "FC14_SPI_CLK,Flexcomm Interface 14 SPI clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 21. "FC13_CLK,Flexcomm Interface 13 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 20. "FC12_CLK,Flexcomm Interface 12 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 19. "FC11_CLK,Flexcomm Interface 11 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 18. "FC10_CLK,Flexcomm Interface 10 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 17. "FC9_CLK,Flexcomm Interface 9 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 16. "FC8_CLK,Flexcomm Interface 8 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 15. "FC7_CLK,Flexcomm Interface 7 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 14. "FC6_CLK,Flexcomm Interface 6 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 13. "FC5_CLK,Flexcomm Interface 5 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 12. "FC4_CLK,Flexcomm Interface 4 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 11. "FC3_CLK,Flexcomm Interface 3 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 10. "FC2_CLK,Flexcomm Interface 2 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 9. "FC1_CLK,Flexcomm Interface 1 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 8. "FC0_CLK,Flexcomm Interface 0 clock control" "0: Disable Clock,1: Enable Clock"
group.long 0x14++0x03
line.long 0x00 "PSCCTL1,Clock Control 1"
bitfld.long 0x00 31. "FREQME_CLK,Frequency Measurement clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 29. "SEMA_CLK,Semaphore clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 28. "MU_CLK,Messaging Unit clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 24. "DMAC1_CLK,DMAC1 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 23. "DMAC0_CLK,DMAC0 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 16. "CRC_CLK,CRC clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 7. "HSGPIO7_CLK,Non-secure GPIO7 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 6. "HSGPIO6_CLK,Non-secure GPIO6 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 5. "HSGPIO5_CLK,Non-secure GPIO5 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 4. "HSGPIO4_CLK,Non-secure GPIO4 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 3. "HSGPIO3_CLK,Non-secure GPIO3 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 2. "HSGPIO2_CLK,Non-secure GPIO2 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 1. "HSGPIO1_CLK,Non-secure GPIO1 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 0. "HSGPIO0_CLK,Non-secure GPIO0 clock control" "0: Disable Clock,1: Enable Clock"
group.long 0x18++0x03
line.long 0x00 "PSCCTL2,Clock Control 2"
bitfld.long 0x00 31. "PIMCTL_CLK,INPUTMUX clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 30. "GPIOINTCTL_CLK,PINT clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 17. "I3C1_CLK,I3C1 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 16. "I3C0_CLK,I3C0 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 10. "WWDT1_CLK,Watchdog Timer 1 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 8. "MRT0_CLK,Multi-Rate Timer 0 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 7. "RTCLITE_CLK,RTC clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 4. "CT32BIT4_CLK,CT32BIT bit timer 4 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 3. "CT32BIT3_CLK,CT32BIT bit timer 3 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 2. "CT32BIT2_CLK,CT32BIT bit timer 2 clock control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 1. "CT32BIT1_CLK,CT32BIT bit timer 1 clock control" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 0. "CT32BIT0_CLK,CT32BIT bit timer 0 clock control" "0: Disable Clock,1: Enable Clock"
group.long 0x40++0x03
line.long 0x00 "PSCCTL0_SET,Clock Set 0"
bitfld.long 0x00 29. "FlexIO,FlexIO clock control" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 27. "OSEVENT_TIMER,OS event timer bus clock control" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 25. "FC16_SPI_CLK,Flexcomm Interface 16 SPI clock control" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 24. "DMIC0,DMIC0 clock control" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 23. "FC15_I2C_CLK,Flexcomm Interface 15 I2C clock control" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 22. "FC14_SPI_CLK,Flexcomm Interface 14 SPI clock control" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 21. "FC13_CLK,Flexcomm Interface 13 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 20. "FC12_CLK,Flexcomm Interface 12 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 19. "FC11_CLK,Flexcomm Interface 11 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 18. "FC10_CLK,Flexcomm Interface 10 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 17. "FC9_CLK,Flexcomm Interface 9 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 16. "FC8_CLK,Flexcomm Interface 8 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 15. "FC7_CLK,Flexcomm Interface 7 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 14. "FC6_CLK,Flexcomm Interface 6 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 13. "FC5_CLK,Flexcomm Interface 5 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 12. "FC4_CLK,Flexcomm Interface 4 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 11. "FC3_CLK,Flexcomm Interface 3 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 10. "FC2_CLK,Flexcomm Interface 2 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
newline
bitfld.long 0x00 9. "FC1_CLK,Flexcomm Interface 1 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
bitfld.long 0x00 8. "FC0_CLK,Flexcomm Interface 0 clock set" "0: No effect,1: Sets the PSCCTL0 bit"
group.long 0x44++0x03
line.long 0x00 "PSCCTL1_SET,Clock Set 1"
bitfld.long 0x00 31. "FREQME_CLK,Frequency Measurement clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
bitfld.long 0x00 29. "SEMA_CLK,Semaphore clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
newline
bitfld.long 0x00 28. "MU_CLK,Messaging Unit clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
bitfld.long 0x00 24. "DMAC1_CLK,DMAC1 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
newline
bitfld.long 0x00 23. "DMAC0_CLK,DMAC0 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
bitfld.long 0x00 16. "CRC_CLK,CRC clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
newline
bitfld.long 0x00 7. "HSGPIO7_CLK,Non-secure GPIO7 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
bitfld.long 0x00 6. "HSGPIO6_CLK,Non-secure GPIO6 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
newline
bitfld.long 0x00 5. "HSGPIO5_CLK,Non-secure GPIO5 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
bitfld.long 0x00 4. "HSGPIO4_CLK,Non-secure GPIO4 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
newline
bitfld.long 0x00 3. "HSGPIO3_CLK,Non-secure GPIO3 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
bitfld.long 0x00 2. "HSGPIO2_CLK,Non-secure GPIO2 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
newline
bitfld.long 0x00 1. "HSGPIO1_CLK,Non-secure GPIO1 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
bitfld.long 0x00 0. "HSGPIO0_CLK,Non-secure GPIO0 clock control set" "0: No effect,1: Sets the PSCCTL1 bit"
group.long 0x48++0x03
line.long 0x00 "PSCCTL2_SET,Clock Set 2"
bitfld.long 0x00 31. "PIMCTL_CLK,INPUTMUX clock control set" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 30. "GPIOINTCTL_CLK,PINT clock control set" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 17. "I3C1_CLK,I3C1 clock control set" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 16. "I3C0_CLK,I3C0 clock control set" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 10. "WWDT1_CLK,Watchdog Timer 1 clock control set" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 8. "MRT0_CLK,Multi-Rate Timer 0 clock control set" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 7. "RTCLITE_CLK,RTC clock control set" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 4. "CT32BIT4_CLK,CT32BIT bit timer 4 clock set" "0: NO_EFFECT,1: SET_BIT"
newline
bitfld.long 0x00 3. "CT32BIT3_CLK,CT32BIT bit timer 3 clock set" "0: NO_EFFECT,1: SET_BIT"
bitfld.long 0x00 2. "CT32BIT2_CLK,CT32BIT bit timer 2 clock set" "0: NO_EFFECT,1: SET_BIT"
newline
bitfld.long 0x00 1. "CT32BIT1_CLK,CT32BIT bit timer 1 clock set" "0: NO_EFFECT,1: SET_BIT"
bitfld.long 0x00 0. "CT32BIT0_CLK,CT32BIT bit timer 0 clock set" "0: NO_EFFECT,1: SET_BIT"
group.long 0x70++0x03
line.long 0x00 "PSCCTL0_CLR,Clock Clear 0"
bitfld.long 0x00 29. "FlexIO,FlexIO clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 27. "OSEVENT_TIMER,OS event timer bus clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 25. "FC16_SPI_CLK,Flexcomm Interface 16 SPI clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 24. "DMIC0,DMIC0 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 23. "FC15_I2C_CLK,Flexcomm Interface 15 I2C clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 22. "FC14_SPI_CLK,Flexcomm Interface 14 SPI clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 21. "FC13_CLK,Flexcomm Interface 13 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 20. "FC12_CLK,Flexcomm Interface 12 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 19. "FC11_CLK,Flexcomm Interface 11 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 18. "FC10_CLK,Flexcomm Interface 10 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 17. "FC9_CLK,Flexcomm Interface 9 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 16. "FC8_CLK,Flexcomm Interface 8 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 15. "FC7_CLK,Flexcomm Interface 7 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 14. "FC6_CLK,Flexcomm Interface 6 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 13. "FC5_CLK,Flexcomm Interface 5 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 12. "FC4_CLK,Flexcomm Interface 4 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 11. "FC3_CLK,Flexcomm Interface 3 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 10. "FC2_CLK,Flexcomm Interface 2 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
newline
bitfld.long 0x00 9. "FC1_CLK,Flexcomm Interface 1 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
bitfld.long 0x00 8. "FC0_CLK,Flexcomm Interface 0 clock control clear" "0: No effect,1: Clears the PSCCTL0 bit"
group.long 0x74++0x03
line.long 0x00 "PSCCTL1_CLR,Clock Clear 1"
bitfld.long 0x00 31. "FREQME_CLK,Frequency Measurement clock control" "0: No effect,1: Clears the PSCCTL1 bit"
bitfld.long 0x00 29. "SEMA_CLK,Semaphore clock control" "0: No effect,1: Clears the PSCCTL1 bit"
newline
bitfld.long 0x00 28. "MU_CLK,Messaging Unit clock control" "0: No effect,1: Clears the PSCCTL1 bit"
bitfld.long 0x00 24. "DMAC1_CLK,DMAC1 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
newline
bitfld.long 0x00 23. "DMAC0_CLK,DMAC0 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
bitfld.long 0x00 16. "CRC_CLK,CRC clock control" "0: No effect,1: Clears the PSCCTL1 bit"
newline
bitfld.long 0x00 7. "HSGPIO7_CLK,Non-secure GPIO7 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
bitfld.long 0x00 6. "HSGPIO6_CLK,Non-secure GPIO6 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
newline
bitfld.long 0x00 5. "HSGPIO5_CLK,Non-secure GPIO5 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
bitfld.long 0x00 4. "HSGPIO4_CLK,Non-secure GPIO4 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
newline
bitfld.long 0x00 3. "HSGPIO3_CLK,Non-secure GPIO3 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
bitfld.long 0x00 2. "HSGPIO2_CLK,Non-secure GPIO2 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
newline
bitfld.long 0x00 1. "HSGPIO1_CLK,Non-secure GPIO1 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
bitfld.long 0x00 0. "HSGPIO0_CLK,Non-secure GPIO0 clock control" "0: No effect,1: Clears the PSCCTL1 bit"
group.long 0x78++0x03
line.long 0x00 "PSCCTL2_CLR,Clock Clear 2"
bitfld.long 0x00 31. "PIMCTL_CLK,INPUTMUX clock control clear" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 30. "GPIOINTCTL_CLK,PINT clock control clear" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 17. "I3C1_CLK,I3C1 clock control clear" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 16. "I3C0_CLK,I3C0 clock control clear" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 10. "WWDT1_CLK,Watchdog Timer 1 clock control clear" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 8. "MRT0_CLK,Multi-Rate Timer 0 clock control clear" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 7. "RTCLITE_CLK,RTC clock control clear" "0: Disable Clock,1: Enable Clock"
bitfld.long 0x00 4. "CT32BIT4_CLK,CT32BIT bit timer 4 clock clear" "0: NO_EFFECT,1: SET_BIT"
newline
bitfld.long 0x00 3. "CT32BIT3_CLK,CT32BIT bit timer 3 clock clear" "0: NO_EFFECT,1: SET_BIT"
bitfld.long 0x00 2. "CT32BIT2_CLK,CT32BIT bit timer 2 clock clear" "0: NO_EFFECT,1: SET_BIT"
newline
bitfld.long 0x00 1. "CT32BIT1_CLK,CT32BIT bit timer 1 clock clear" "0: NO_EFFECT,1: SET_BIT"
bitfld.long 0x00 0. "CT32BIT0_CLK,CT32BIT bit timer 0 clock clear" "0: NO_EFFECT,1: SET_BIT"
group.long 0x200++0x03
line.long 0x00 "AUDIOPLL0CLKSEL,Audio PLL0 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Audio PLL0 Clock Select" "0: FRRO_DIV8,1: OSC_CLK clock (User-Selectable),?,?,?,?,?,7: None output gated to reduce power"
group.long 0x204++0x03
line.long 0x00 "AUDIOPLL0CTL0,Audio PLL0 Control 0"
hexmask.long.byte 0x00 16.--23. 1. "MULT,Multiplication Factor"
bitfld.long 0x00 13. "HOLDRINGOFF_ENA,Hold Ring Off Control" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "RESET,AUDIOPLL0 Reset" "0: AUDIOPLL0 reset is removed,1: AUDIOPLL0 is placed into reset"
bitfld.long 0x00 0. "BYPASS,AUDIOPLL0 BYPASS Mode" "0: PFD outputs are PFD-programmed clocks,1: Bypass Mode"
group.long 0x20C++0x03
line.long 0x00 "AUDIOPLL0LOCKTIMEDIV2,Audio PLL0 Lock Time Divide-by-2"
hexmask.long.word 0x00 0.--15. 1. "LOCKTIMEDIV2,AUDIOPLL0 Lock Time Divide-by-2"
group.long 0x210++0x03
line.long 0x00 "AUDIOPLL0NUM,Audio PLL0 Numerator"
hexmask.long 0x00 0.--29. 1. "NUM,Numerator"
group.long 0x214++0x03
line.long 0x00 "AUDIOPLL0DENOM,Audio PLL0 Denominator"
hexmask.long 0x00 0.--29. 1. "DENOM,Denominator"
group.long 0x218++0x03
line.long 0x00 "AUDIOPLL0PFD,Audio PLL0 PFD"
bitfld.long 0x00 31. "PFD3_CLKGATE,PFD3 Clock Gate" "0: PFD3 clock is not gated,1: PFD3 clock is gated"
bitfld.long 0x00 30. "PFD3_CLKRDY,PFD3 Clock Ready Status Flag" "0: NOT_READY,1: READY"
newline
bitfld.long 0x00 24.--29. "PFD3,PLL Fractional Divider 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. "PFD2_CLKGATE,PFD2 Clock Gate" "0: PFD2 clock is not gated,1: PFD2 clock is gated"
newline
bitfld.long 0x00 22. "PFD2_CLKRDY,PFD2 Clock Ready Status Flag" "0: NOT_READY,1: READY"
bitfld.long 0x00 16.--21. "PFD2,PLL Fractional Divider 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15. "PFD1_CLKGATE,PFD1 Clock Gate" "0: PFD1 clock is not gated,1: PFD1 clock is gated"
bitfld.long 0x00 14. "PFD1_CLKRDY,PFD1 Clock Ready Status Flag" "0: NOT_READY,1: READY"
newline
bitfld.long 0x00 8.--13. "PFD1,PLL Fractional Divider 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "PFD0_CLKGATE,PFD0 Clock Gate" "0: PFD0 clock is not gated,1: PFD0 clock is gated"
newline
bitfld.long 0x00 6. "PFD0_CLKRDY,PFD0 Clock Ready Status Flag" "0: NOT_READY,1: READY"
bitfld.long 0x00 0.--5. "PFD0,PLL Fractional Divider 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x240++0x03
line.long 0x00 "AUDIOPLLCLKDIV,Audio PLL Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,32 KHz Wake Clock Divider Value"
group.long 0x400++0x03
line.long 0x00 "DSPCPUCLKDIV,DSP CPU Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,DSP Clock Divider Value"
group.long 0x430++0x03
line.long 0x00 "DSPCPUCLKSELA,DSP CPU Clock Select A"
bitfld.long 0x00 0.--1. "SEL,DSP Main 1st Stage Control Clock Source" "0: FRO_DIV1 Clock,1: OSC_CLK Clock,2: Low Power Oscillator Clock (LPOSC),?..."
group.long 0x434++0x03
line.long 0x00 "DSPCPUCLKSELB,DSP CPU Clock Select B"
bitfld.long 0x00 0.--1. "SEL,Main Clock Source" "0: MAINCLKSELA 1st Stage Clock,1: Main System PLL Clock,2: DSP System PLL Clock,3: RTC 32 KHz Clock"
group.long 0x480++0x03
line.long 0x00 "OSEVENTTFCLKSEL,OS Event Timer Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,OS Event Timer Functional Clock Source" "0: Low Power Oscillator Clock (LPOSC),1: RTC 32 KHz Clock,2: HCLK Free-Running Clock (Global Time Stamping),?,?,?,?,7: None output gated to reduce power"
group.long 0x500++0x03
line.long 0x00 "FRG0CLKSEL,Fractional Rate Generator 0 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 0 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x504++0x03
line.long 0x00 "FRG0CTL,Fractional Rate Generator 0 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x508++0x03
line.long 0x00 "FC0FCLKSEL,Flexcomm0 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x520++0x03
line.long 0x00 "FRG1CLKSEL,Fractional Rate Generator 1 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 1 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x524++0x03
line.long 0x00 "FRG1CTL,Fractional Rate Generator 1 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x528++0x03
line.long 0x00 "FC1FCLKSEL,Flexcomm1 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x540++0x03
line.long 0x00 "FRG2CLKSEL,Fractional Rate Generator 2 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 2 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x544++0x03
line.long 0x00 "FRG2CTL,Fractional Rate Generator 2 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x548++0x03
line.long 0x00 "FC2FCLKSEL,Flexcomm2 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x560++0x03
line.long 0x00 "FRG3CLKSEL,Fractional Rate Generator 3 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 3 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x564++0x03
line.long 0x00 "FRG3CTL,Fractional Rate Generator 3 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x568++0x03
line.long 0x00 "FC3FCLKSEL,Flexcomm3 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x580++0x03
line.long 0x00 "FRG4CLKSEL,Fractional Rate Generator 4 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 4 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x584++0x03
line.long 0x00 "FRG4CTL,Fractional Rate Generator 4 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x588++0x03
line.long 0x00 "FC4FCLKSEL,Flexcomm4 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x5A0++0x03
line.long 0x00 "FRG5CLKSEL,Fractional Rate Generator 5 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 5 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x5A4++0x03
line.long 0x00 "FRG5CTL,Fractional Rate Generator 5 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x5A8++0x03
line.long 0x00 "FC5FCLKSEL,Flexcomm5 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x5C0++0x03
line.long 0x00 "FRG6CLKSEL,Fractional Rate Generator 6 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 6 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x5C4++0x03
line.long 0x00 "FRG6CTL,Fractional Rate Generator 6 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x5C8++0x03
line.long 0x00 "FC6FCLKSEL,Flexcomm6 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x5E0++0x03
line.long 0x00 "FRG7CLKSEL,Fractional Rate Generator 7 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 7 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x5E4++0x03
line.long 0x00 "FRG7CTL,Fractional Rate Generator 7 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x5E8++0x03
line.long 0x00 "FC7FCLKSEL,Flexcomm7 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x600++0x03
line.long 0x00 "FRG8CLKSEL,Fractional Rate Generator 8 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 8 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x604++0x03
line.long 0x00 "FRG8CTL,Fractional Rate Generator 8 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x608++0x03
line.long 0x00 "FC8FCLKSEL,Flexcomm8 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x620++0x03
line.long 0x00 "FRG9CLKSEL,Fractional Rate Generator 9 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 9 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x624++0x03
line.long 0x00 "FRG9CTL,Fractional Rate Generator 9 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x628++0x03
line.long 0x00 "FC9FCLKSEL,Flexcomm9 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x640++0x03
line.long 0x00 "FRG10CLKSEL,Fractional Rate Generator 10 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 10 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x644++0x03
line.long 0x00 "FRG10CTL,Fractional Rate Generator 10 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x648++0x03
line.long 0x00 "FC10FCLKSEL,Flexcomm10 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x660++0x03
line.long 0x00 "FRG11CLKSEL,Fractional Rate Generator 11 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 11 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x664++0x03
line.long 0x00 "FRG11CTL,Fractional Rate Generator 11 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x668++0x03
line.long 0x00 "FC11FCLKSEL,Flexcomm11 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x680++0x03
line.long 0x00 "FRG12CLKSEL,Fractional Rate Generator 12 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 12 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x684++0x03
line.long 0x00 "FRG12CTL,Fractional Rate Generator 12 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x688++0x03
line.long 0x00 "FC12FCLKSEL,Flexcomm12 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x6A0++0x03
line.long 0x00 "FRG13CLKSEL,Fractional Rate Generator 13 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 13 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x6A4++0x03
line.long 0x00 "FRG13CTL,Fractional Rate Generator 13 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x6A8++0x03
line.long 0x00 "FC13FCLKSEL,Flexcomm13 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x6C0++0x03
line.long 0x00 "FRG14CLKSEL,Fractional Rate Generator 14 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 14 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x6C4++0x03
line.long 0x00 "FRG14CTL,Fractional Rate Generator 14 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x6C8++0x03
line.long 0x00 "FC14FCLKSEL,Flexcomm14 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x6E0++0x03
line.long 0x00 "FRG15CLKSEL,Fractional Rate Generator 15 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 15 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x6E4++0x03
line.long 0x00 "FRG15CTL,Fractional Rate Generator 15 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x6E8++0x03
line.long 0x00 "FC15FCLKSEL,Flexcomm15 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x700++0x03
line.long 0x00 "FRG16CLKSEL,Fractional Rate Generator 16 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 16 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x704++0x03
line.long 0x00 "FRG16CTL,Fractional Rate Generator 16 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x708++0x03
line.long 0x00 "FC16FCLKSEL,Flexcomm16 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Functional Clock Source" "0: FRO_DIV4 clock,1: Audio PLL Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x720++0x03
line.long 0x00 "FRG17CLKSEL,Fractional Rate Generator 17 Clock Select"
bitfld.long 0x00 0.--2. "SEL,Fractional Generator 17 Clock Source" "0: Main Clock,1: FRG PLL Clock,2: FRO_DIV4 clock,?,?,?,?,7: None output gated to reduce power"
group.long 0x724++0x03
line.long 0x00 "FRG17CTL,Fractional Rate Generator 17 Control"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional divider: MULT is equal to the programmed value"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional divider: DIV is equal to the programmed value +1"
group.long 0x728++0x03
line.long 0x00 "FLEXIOCLKSEL,FlexIO Clock Select"
bitfld.long 0x00 0.--2. "SEL,FlexIO Functional Clock Source" "0: FRO_DIV4 Clock,1: Audio PLL Clock,2: Master Clock In,3: FC17 FRG Clock,?,?,?,7: None output gated to reduce power"
group.long 0x740++0x03
line.long 0x00 "FLEXIOCLKDIV,FlexIO Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,FLEXIO Clock Divider Value"
group.long 0x760++0x03
line.long 0x00 "FRGPLLCLKDIV,Fractional Rate Generator PLL Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,FRG PLL Clock Divider Value"
group.long 0x780++0x03
line.long 0x00 "DMIC0FCLKSEL,DMIC0 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,DMIC Functional Clock Source" "0: FRO Clock (Divided-by-4 selection),1: Audio PLL Clock,2: Master Clock In,3: Low Power Oscillator Clock (LPOSC),4: 32 KHz Wake Clock,?,?,7: None output gated to reduce power"
group.long 0x784++0x03
line.long 0x00 "DMIC0FCLKDIV,DMIC0 Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,32 KHz Wake Clock Divider Value"
repeat 5. (increment 0 1) (increment 0 0x04)
group.long ($2+0x7A0)++0x03
line.long 0x00 "CT32BITFCLKSEL[$1],CT32BIT bit timer index Functional Clock Select $1"
bitfld.long 0x00 0.--2. "SEL,CT32BIT bit timer 0 Functional Clock Source" "0: Main Clock,1: FRO_DIV1 Clock,2: Audio PLL Clock,3: Master Clock In,4: 32 KHZ Wake Clock,?,?,7: None output gated to reduce power"
repeat.end
group.long 0x7C0++0x03
line.long 0x00 "AUDIOMCLKSEL,Audio MCLK Clock Select"
bitfld.long 0x00 0.--2. "SEL,Audio MCLK Clock Source Select" "0: FRO_DIV8 Clock,1: AUDIO PLL Clock (Shared Domain),?,?,?,?,?,7: None output gated to reduce power"
group.long 0x7C4++0x03
line.long 0x00 "AUDIOMCLKDIV,Audio MCLK Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Audio MCLK Clock Divider Value"
group.long 0x7E0++0x03
line.long 0x00 "CLKOUTSEL0,CLKOUT Clock Select 0"
bitfld.long 0x00 0.--2. "SEL,Clock Output Select 1st Stage" "0: OSC_CLK Clock,1: Low Power Oscillator Clock (LPOSC),2: FRO_DIV2 Clock,3: Main Clock,4: DSP Main Clock,?,?,7: None output gated to reduce power"
group.long 0x7E4++0x03
line.long 0x00 "CLKOUTSEL1,CLKOUT Clock Select 1"
bitfld.long 0x00 0.--2. "SEL,Clock Out Source" "0: CLKOUTSEL0 Multiplexed Output,1: Main System PLL Clock,2: SYSPLL0 AUX0_PLL_Clock,3: DSP PLL Clock,4: SYSPLL0 AUX1_PLL_Clock,5: AUDIO PLL Clock,6: 32 KHz RTC Clock,7: None output gated to reduce power"
group.long 0x7E8++0x03
line.long 0x00 "CLKOUTFCLKDIV,CLKOUT Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock-Out Clock Divider Value"
group.long 0x800++0x03
line.long 0x00 "I3C01FCLKSEL,I3C0 I3C1 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,I3C0 I3C1 Clock Source" "0: Main Clock,1: FRO_DIV8 Clock,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x804++0x03
line.long 0x00 "I3C01FCLKSTCSEL,I3C0 I3C1 Functional Slow Time Control Clock Select"
bitfld.long 0x00 0.--2. "SEL,I3C0 I3C1 Clock Source" "0: I3C0 FCLK,1: Low Power Oscillator Clock (LPOSC),?,?,?,?,?,7: None output gated to reduce power"
group.long 0x808++0x03
line.long 0x00 "I3C01FCLKSTCDIV,I3C0 I3C1 Functional Slow Time Control Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,I3C0 I3C1 Clock Divider Value"
group.long 0x80C++0x03
line.long 0x00 "I3C01FCLKSDIV,I3C0 I3C1 Functional Slow Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halt the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,I3C0 I3C1 Clock Divider Value"
group.long 0x810++0x03
line.long 0x00 "I3C01FCLKDIV,I3C0 I3C1 Functional Clock Divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halts the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,I3C0 I3C1 Clock Divider Value"
group.long 0x814++0x03
line.long 0x00 "I3C01FCLKSTSTCLKSEL,I3C01 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,I3C0 I3C1 FCLK Test Clock Source" "0: Low Power Oscillator Clock (LPOSC),?,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x820++0x03
line.long 0x00 "WDT1FCLKSEL,Watchdog Timer 1 Functional Clock Select"
bitfld.long 0x00 0.--2. "SEL,WDT1 Functional Clock Source" "0: Low Power Oscillator Clock (LPOSC),1: MAIN_CLOCK,?,?,?,?,?,7: None output gated to reduce power"
group.long 0x830++0x03
line.long 0x00 "ACMP0FCLKSEL,Analog Comparator 0 Clock Select"
bitfld.long 0x00 0.--2. "SEL,ACMP0 Fast Functional Clock Source" "0: Main Clock,1: FRO_DIV4 Clock,2: SYSPLL0 AUX0_PLL_Clock,3: SYSPLL0 AUX1_PLL_Clock,?,?,?,7: None output gated to reduce power"
group.long 0x834++0x03
line.long 0x00 "ACMP0FCLKDIV,Analog comparator 0 FCLK divider"
bitfld.long 0x00 31. "REQFLAG,Divider Status Flag" "0: The Divider change has finished (clock being..,1: The Divider value has changed"
bitfld.long 0x00 30. "HALT,Halts the Divider Counter" "0: DIVIDER_COUNTER_NOT_HALT,1: Halt (stop) the Divider Counter"
newline
bitfld.long 0x00 29. "RESET,Reset the Divider Counter" "0: DIVIDER_COUNTER_NOT_RESET,1: Reset the Divider Counter"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock Out Clock Divider Value"
tree.end
tree.end
tree "CRC"
base ad:0x40120000
group.long 0x00++0x03
line.long 0x00 "MODE,MODE Register"
bitfld.long 0x00 5. "CMPL_SUM,1's Complement for CRC Sum" "0: Do not use 1's complement for CRC Sum,1: Use 1's complement for CRC Sum"
bitfld.long 0x00 4. "BIT_RVS_SUM,Bit-order Reverse for CRC Sum" "0: Do not use bit-order reverse for CRC Sum,1: Use bit-order reverse for CRC Sum"
newline
bitfld.long 0x00 3. "CMPL_WR,1's Complement for Write Data" "0: Do not use 1's complement for WR_DATA,1: Use 1's complement for WR_DATA"
bitfld.long 0x00 2. "BIT_RVS_WR,Bit-order Reverse for Write Data" "0: Do not use bit-order reverse for WR_DATA (per..,1: Use bit-order reverse for WR_DATA (per byte)"
newline
bitfld.long 0x00 0.--1. "CRC_POLY,CRC Polynomial" "0: Use CRC-CCITT polynomial,1: Use CRC-16 polynomial,2: Use CRC-32 polynomial,?..."
group.long 0x04++0x03
line.long 0x00 "SEED,CRC Seed Register"
hexmask.long 0x00 0.--31. 1. "CRC_SEED,CRC Seed"
rgroup.long 0x08++0x03
line.long 0x00 "SUM,CRC Sum"
hexmask.long 0x00 0.--31. 1. "CRC_SUM,CRC Sum"
group.long 0x08++0x03
line.long 0x00 "WR_DATA,CRC Write Data"
hexmask.long 0x00 0.--31. 1. "WR_DATA,CRC Write Data"
tree.end
tree "CTIMER (Counter/Timer)"
repeat 5. (list 0. 1. 2. 3. 4.) (list ad:0x40028000 ad:0x40029000 ad:0x4002A000 ad:0x4002B000 ad:0x4002C000)
tree "CTIMER$1"
base $2
group.long 0x00++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1"
bitfld.long 0x00 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1"
newline
bitfld.long 0x00 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1"
bitfld.long 0x00 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1"
newline
bitfld.long 0x00 3. "MR3INT,Interrupt flag for match channel 3" "0,1"
bitfld.long 0x00 2. "MR2INT,Interrupt flag for match channel 2" "0,1"
newline
bitfld.long 0x00 1. "MR1INT,Interrupt flag for match channel 1" "0,1"
bitfld.long 0x00 0. "MR0INT,Interrupt flag for match channel 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "TCR,Timer Control Register"
bitfld.long 0x00 1. "CRST,Counter reset" "0: Disabled,1: ENABLED"
bitfld.long 0x00 0. "CEN,Counter enable" "0: Disabled,1: Enabled"
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter"
hexmask.long 0x00 0.--31. 1. "TCVAL,Timer counter value"
group.long 0x0C++0x03
line.long 0x00 "PR,Prescale Register"
hexmask.long 0x00 0.--31. 1. "PRVAL,Prescale reload value"
group.long 0x10++0x03
line.long 0x00 "PC,Prescale Counter"
hexmask.long 0x00 0.--31. 1. "PCVAL,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 27. "MR3RL,Reload MR3" "0: Disabled,1: MR3RL_1"
bitfld.long 0x00 26. "MR2RL,Reload MR2" "0: Disabled,1: MR2RL_1"
newline
bitfld.long 0x00 25. "MR1RL,Reload MR1" "0: Disabled,1: MR1RL_1"
bitfld.long 0x00 24. "MR0RL,Reload MR0" "0: Disabled,1: MR0RL_1"
newline
bitfld.long 0x00 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x00 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled"
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x18)++0x03
line.long 0x00 "MR[$1],Match Register $1"
hexmask.long 0x00 0.--31. 1. "MATCH,Timer counter match value"
repeat.end
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0: Disabled,1: CAP3I_1"
bitfld.long 0x00 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC" "0: CAP3FE_0,1: CAP3FE_1"
newline
bitfld.long 0x00 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC" "0: CAP3RE_0,1: CAP3RE_1"
bitfld.long 0x00 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0: Disabled,1: CAP2I_1"
newline
bitfld.long 0x00 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC" "0: CAP2FE_0,1: CAP2FE_1"
bitfld.long 0x00 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC" "0: CAP2RE_0,1: CAP2RE_1"
newline
bitfld.long 0x00 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0: Disabled,1: CAP1I_1"
bitfld.long 0x00 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC" "0: CAP1FE_0,1: CAP1FE_1"
newline
bitfld.long 0x00 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC" "0: CAP1RE_0,1: CAP1RE_1"
bitfld.long 0x00 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0: Disabled,1: CAPOI_1"
newline
bitfld.long 0x00 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC" "0: CAP0FE_0,1: CAPOFE_1"
bitfld.long 0x00 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC" "0: CAP0RE_0,1: CAPORE_1"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x2C)++0x03
line.long 0x00 "CR[$1],Capture Register $1"
hexmask.long 0x00 0.--31. 1. "CAP,Timer counter capture value"
repeat.end
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. "EMC3,External Match Control 3" "0: Do Nothing,1: Clear,2: Set,3: Toggle"
bitfld.long 0x00 8.--9. "EMC2,External Match Control 2" "0: Do Nothing,1: Clear,2: Set,3: Toggle"
newline
bitfld.long 0x00 6.--7. "EMC1,External Match Control 1" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle"
bitfld.long 0x00 4.--5. "EMC0,External Match Control 0" "0: Do Nothing,1: Clear,2: Set,3: Toggle"
newline
bitfld.long 0x00 3. "EM3,External Match 3" "0,1"
bitfld.long 0x00 2. "EM2,External Match 2" "0,1"
newline
bitfld.long 0x00 1. "EM1,External Match 1" "0,1"
bitfld.long 0x00 0. "EM0,External Match 0" "0,1"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,?..."
bitfld.long 0x00 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1"
newline
bitfld.long 0x00 2.--3. "CINSEL,Count Input Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3"
bitfld.long 0x00 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting" "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
bitfld.long 0x00 3. "PWMEN3,PWM mode enable for channel3" "0: Match,1: PWM"
bitfld.long 0x00 2. "PWMEN2,PWM mode enable for channel2" "0: Match,1: PWM"
newline
bitfld.long 0x00 1. "PWMEN1,PWM mode enable for channel1" "0: Match,1: PWM"
bitfld.long 0x00 0. "PWMEN0,PWM mode enable for channel0" "0: Match,1: PWM"
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x78)++0x03
line.long 0x00 "MSR[$1],Match Shadow Register $1"
hexmask.long 0x00 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value"
repeat.end
tree.end
repeat.end
tree.end
tree "DEBUGGER_MAILBOX (Debug)"
base ad:0x4010F000
group.long 0x00++0x03
line.long 0x00 "CSW,Command and status word"
bitfld.long 0x00 5. "CHIP_RESET_REQ,Chip Reset Request" "0,1"
bitfld.long 0x00 4. "SOFT_RESET,Soft Reset" "0,1"
newline
bitfld.long 0x00 3. "AHB_OR_ERR,AHB Overrun Error" "0: No AHB Overrun Error,1: AHB Overrun Error"
bitfld.long 0x00 2. "DBG_OR_ERR,Debug Overrun Error" "0: No Debug Overrun error,1: Debug Overrun Error"
newline
bitfld.long 0x00 1. "REQ_PENDING,Request Pending" "0: NO_REQUEST_PENDING,1: Request for Re-synchronization Pending"
bitfld.long 0x00 0. "RESYNCH_REQ,Re-synchronization Request" "0: NO_REQUEST,1: Request for re-synchronization"
group.long 0x04++0x03
line.long 0x00 "REQUEST,Request Value"
hexmask.long 0x00 0.--31. 1. "REQUEST,Request Value"
group.long 0x08++0x03
line.long 0x00 "RETURN,Return Value"
hexmask.long 0x00 0.--31. 1. "RETURN,Return Value"
rgroup.long 0xFC++0x03
line.long 0x00 "ID,Identification"
hexmask.long 0x00 0.--31. 1. "ID,Identification Value"
tree.end
tree "DMA (DMA0 controller)"
repeat 2. (list 0. 1.) (list ad:0x40104000 ad:0x40105000)
tree "DMA$1"
base $2
sif cpuis("IMXRT595-CM33")
group.long 0x00++0x03
line.long 0x00 "CTRL,DMA control"
bitfld.long 0x00 0. "ENABLE,DMA controller master enable" "0: DMA controller is disabled,1: Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "INTSTAT,Interrupt status"
bitfld.long 0x00 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending" "0: No error interrupts are pending,1: At least one error interrupt is pending"
bitfld.long 0x00 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "0: No enabled interrupts are pending,1: At least one enabled interrupt is pending"
group.long 0x08++0x03
line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table"
hexmask.long.tbyte 0x00 9.--31. 1. "OFFSET,Offset"
group.long 0x20++0x03
line.long 0x00 "ENABLESET0,Channel Enable read and set for all DMA channels"
bitfld.long 0x00 31. "ENABLE31,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 30. "ENABLE30,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 29. "ENABLE29,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 28. "ENABLE28,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 27. "ENABLE27,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 26. "ENABLE26,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 25. "ENABLE25,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 24. "ENABLE24,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 23. "ENABLE23,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 22. "ENABLE22,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 21. "ENABLE21,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 20. "ENABLE20,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 19. "ENABLE19,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 18. "ENABLE18,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 17. "ENABLE17,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 16. "ENABLE16,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 15. "ENABLE15,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 14. "ENABLE14,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 13. "ENABLE13,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 12. "ENABLE12,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 11. "ENABLE11,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 10. "ENABLE10,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 9. "ENABLE9,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 8. "ENABLE8,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 7. "ENABLE7,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 6. "ENABLE6,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 5. "ENABLE5,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 4. "ENABLE4,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 3. "ENABLE3,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 2. "ENABLE2,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 1. "ENABLE1,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 0. "ENABLE0,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
group.long 0x24++0x03
line.long 0x00 "ENABLESET1,Channel Enable read and set for all DMA channels"
bitfld.long 0x00 4. "ENABLE36,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 3. "ENABLE35,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 2. "ENABLE34,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.long 0x00 1. "ENABLE33,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
newline
bitfld.long 0x00 0. "ENABLE32,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled"
group.long 0x28++0x03
line.long 0x00 "ENABLECLR0,Channel Enable Clear for all DMA channels"
eventfld.long 0x00 31. "CLR31,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 30. "CLR30,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 29. "CLR29,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 28. "CLR28,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 27. "CLR27,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 26. "CLR26,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 25. "CLR25,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 24. "CLR24,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 23. "CLR23,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 22. "CLR22,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 21. "CLR21,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 20. "CLR20,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 19. "CLR19,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 18. "CLR18,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 17. "CLR17,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 16. "CLR16,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 15. "CLR15,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 14. "CLR14,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 13. "CLR13,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 12. "CLR12,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 11. "CLR11,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 10. "CLR10,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 9. "CLR9,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 8. "CLR8,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 7. "CLR7,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 6. "CLR6,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 5. "CLR5,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 4. "CLR4,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 3. "CLR3,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 2. "CLR2,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 1. "CLR1,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 0. "CLR0,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared"
group.long 0x2C++0x03
line.long 0x00 "ENABLECLR1,Channel Enable Clear for all DMA channels"
eventfld.long 0x00 4. "CLR36,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 3. "CLR35,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 2. "CLR34,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared"
eventfld.long 0x00 1. "CLR33,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared"
newline
eventfld.long 0x00 0. "CLR32,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared"
rgroup.long 0x30++0x03
line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels"
bitfld.long 0x00 31. "ACTIVE31,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 30. "ACTIVE30,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 29. "ACTIVE29,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 28. "ACTIVE28,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 27. "ACTIVE27,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 26. "ACTIVE26,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 25. "ACTIVE25,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 24. "ACTIVE24,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 23. "ACTIVE23,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 22. "ACTIVE22,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 21. "ACTIVE21,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 20. "ACTIVE20,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 19. "ACTIVE19,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 18. "ACTIVE18,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 17. "ACTIVE17,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 16. "ACTIVE16,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 15. "ACTIVE15,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 14. "ACTIVE14,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 13. "ACTIVE13,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 12. "ACTIVE12,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 11. "ACTIVE11,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 10. "ACTIVE10,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 9. "ACTIVE9,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 8. "ACTIVE8,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 7. "ACTIVE7,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 6. "ACTIVE6,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 5. "ACTIVE5,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 4. "ACTIVE4,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 3. "ACTIVE3,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 2. "ACTIVE2,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 1. "ACTIVE1,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 0. "ACTIVE0,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
rgroup.long 0x34++0x03
line.long 0x00 "ACTIVE1,Channel Active status for all DMA channels"
bitfld.long 0x00 4. "ACTIVE36,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 3. "ACTIVE35,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 2. "ACTIVE34,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
bitfld.long 0x00 1. "ACTIVE33,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
newline
bitfld.long 0x00 0. "ACTIVE32,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active"
rgroup.long 0x38++0x03
line.long 0x00 "BUSY0,Channel Busy status for all DMA channels"
bitfld.long 0x00 31. "BUSY31,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 30. "BUSY30,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 29. "BUSY29,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 28. "BUSY28,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 27. "BUSY27,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 26. "BUSY26,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 25. "BUSY25,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 24. "BUSY24,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 23. "BUSY23,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 22. "BUSY22,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 21. "BUSY21,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 20. "BUSY20,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 19. "BUSY19,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 18. "BUSY18,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 17. "BUSY17,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 16. "BUSY16,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 15. "BUSY15,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 14. "BUSY14,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 13. "BUSY13,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 12. "BUSY12,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 11. "BUSY11,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 10. "BUSY10,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 9. "BUSY9,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 8. "BUSY8,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 7. "BUSY7,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 6. "BUSY6,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 5. "BUSY5,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 4. "BUSY4,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 3. "BUSY3,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 2. "BUSY2,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 1. "BUSY1,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 0. "BUSY0,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
rgroup.long 0x3C++0x03
line.long 0x00 "BUSY1,Channel Busy status for all DMA channels"
bitfld.long 0x00 4. "BUSY36,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 3. "BUSY35,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 2. "BUSY34,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
bitfld.long 0x00 1. "BUSY33,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
newline
bitfld.long 0x00 0. "BUSY32,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy"
group.long 0x40++0x03
line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels"
bitfld.long 0x00 31. "ERR31,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 30. "ERR30,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 29. "ERR29,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 28. "ERR28,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 27. "ERR27,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 26. "ERR26,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 25. "ERR25,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 24. "ERR24,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 23. "ERR23,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 22. "ERR22,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 21. "ERR21,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 20. "ERR20,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 19. "ERR19,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 18. "ERR18,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 17. "ERR17,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 16. "ERR16,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 15. "ERR15,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 14. "ERR14,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 13. "ERR13,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 12. "ERR12,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 11. "ERR11,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 10. "ERR10,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 9. "ERR9,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 8. "ERR8,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 7. "ERR7,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 6. "ERR6,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 5. "ERR5,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 4. "ERR4,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 3. "ERR3,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 2. "ERR2,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 1. "ERR1,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 0. "ERR0,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
group.long 0x44++0x03
line.long 0x00 "ERRINT1,Error Interrupt status for all DMA channels"
bitfld.long 0x00 4. "ERR36,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 3. "ERR35,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 2. "ERR34,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
bitfld.long 0x00 1. "ERR33,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
newline
bitfld.long 0x00 0. "ERR32,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel"
group.long 0x48++0x03
line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels"
bitfld.long 0x00 31. "INTEN31,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 30. "INTEN30,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 29. "INTEN29,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 28. "INTEN28,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 27. "INTEN27,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 26. "INTEN26,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 25. "INTEN25,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 24. "INTEN24,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 23. "INTEN23,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 22. "INTEN22,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 21. "INTEN21,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 20. "INTEN20,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 19. "INTEN19,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 18. "INTEN18,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 17. "INTEN17,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 16. "INTEN16,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 15. "INTEN15,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 14. "INTEN14,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 13. "INTEN13,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 12. "INTEN12,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 11. "INTEN11,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 10. "INTEN10,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 9. "INTEN9,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 8. "INTEN8,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 7. "INTEN7,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 6. "INTEN6,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 5. "INTEN5,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 4. "INTEN4,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 3. "INTEN3,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 2. "INTEN2,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 1. "INTEN1,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 0. "INTEN0,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
group.long 0x4C++0x03
line.long 0x00 "INTENSET1,Interrupt Enable read and Set for all DMA channels"
bitfld.long 0x00 4. "INTEN36,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 3. "INTEN35,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 2. "INTEN34,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
bitfld.long 0x00 1. "INTEN33,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
newline
bitfld.long 0x00 0. "INTEN32,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled"
wgroup.long 0x50++0x03
line.long 0x00 "INTENCLR0,Interrupt Enable Clear for all DMA channels"
bitfld.long 0x00 31. "CLR31,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 30. "CLR30,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 29. "CLR29,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 28. "CLR28,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 27. "CLR27,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 26. "CLR26,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 25. "CLR25,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 24. "CLR24,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 23. "CLR23,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 22. "CLR22,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 21. "CLR21,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 20. "CLR20,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 19. "CLR19,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 18. "CLR18,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 17. "CLR17,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 16. "CLR16,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 15. "CLR15,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 14. "CLR14,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 13. "CLR13,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 12. "CLR12,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 11. "CLR11,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 10. "CLR10,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 9. "CLR9,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 8. "CLR8,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 7. "CLR7,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 6. "CLR6,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 5. "CLR5,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 4. "CLR4,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 3. "CLR3,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 2. "CLR2,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
newline
bitfld.long 0x00 1. "CLR1,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
bitfld.long 0x00 0. "CLR0,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1"
wgroup.long 0x54++0x03
line.long 0x00 "INTENCLR1,Interrupt Enable Clear for all DMA channels"
bitfld.long 0x00 4. "CLR36,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1"
bitfld.long 0x00 3. "CLR35,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1"
newline
bitfld.long 0x00 2. "CLR34,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1"
bitfld.long 0x00 1. "CLR33,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1"
newline
bitfld.long 0x00 0. "CLR32,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1"
group.long 0x58++0x03
line.long 0x00 "INTA0,Interrupt A status for all DMA channels"
bitfld.long 0x00 31. "INTA31,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 30. "INTA30,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 29. "INTA29,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 28. "INTA28,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 27. "INTA27,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 26. "INTA26,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 25. "INTA25,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 24. "INTA24,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 23. "INTA23,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 22. "INTA22,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 21. "INTA21,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 20. "INTA20,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 19. "INTA19,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 18. "INTA18,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 17. "INTA17,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 16. "INTA16,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 15. "INTA15,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 14. "INTA14,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 13. "INTA13,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 12. "INTA12,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 11. "INTA11,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 10. "INTA10,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 9. "INTA9,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 8. "INTA8,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 7. "INTA7,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 6. "INTA6,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 5. "INTA5,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 4. "INTA4,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 3. "INTA3,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 2. "INTA2,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 1. "INTA1,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 0. "INTA0,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
group.long 0x5C++0x03
line.long 0x00 "INTA1,Interrupt A status for all DMA channels"
bitfld.long 0x00 4. "INTA36,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 3. "INTA35,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 2. "INTA34,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
bitfld.long 0x00 1. "INTA33,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
newline
bitfld.long 0x00 0. "INTA32,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active"
group.long 0x60++0x03
line.long 0x00 "INTB0,Interrupt B status for all DMA channels"
bitfld.long 0x00 31. "INTB31,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 30. "INTB30,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 29. "INTB29,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 28. "INTB28,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 27. "INTB27,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 26. "INTB26,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 25. "INTB25,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 24. "INTB24,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 23. "INTB23,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 22. "INTB22,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 21. "INTB21,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 20. "INTB20,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 19. "INTB19,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 18. "INTB18,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 17. "INTB17,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 16. "INTB16,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 15. "INTB15,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 14. "INTB14,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 13. "INTB13,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 12. "INTB12,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 11. "INTB11,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 10. "INTB10,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 9. "INTB9,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 8. "INTB8,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 7. "INTB7,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 6. "INTB6,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 5. "INTB5,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
group.long 0x64++0x03
line.long 0x00 "INTB1,Interrupt B status for all DMA channels"
bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
newline
bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active"
wgroup.long 0x68++0x03
line.long 0x00 "SETVALID0,Set ValidPending control bits for all DMA channels"
bitfld.long 0x00 31. "SETVALID31,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 30. "SETVALID30,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 29. "SETVALID29,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 28. "SETVALID28,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 27. "SETVALID27,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 26. "SETVALID26,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 25. "SETVALID25,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 24. "SETVALID24,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 23. "SETVALID23,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 22. "SETVALID22,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 21. "SETVALID21,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 20. "SETVALID20,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 19. "SETVALID19,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 18. "SETVALID18,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 17. "SETVALID17,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 16. "SETVALID16,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 15. "SETVALID15,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 14. "SETVALID14,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 13. "SETVALID13,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 12. "SETVALID12,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 11. "SETVALID11,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 10. "SETVALID10,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 9. "SETVALID9,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 8. "SETVALID8,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 7. "SETVALID7,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 6. "SETVALID6,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 5. "SETVALID5,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 4. "SETVALID4,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 3. "SETVALID3,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 2. "SETVALID2,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 1. "SETVALID1,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 0. "SETVALID0,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
wgroup.long 0x6C++0x03
line.long 0x00 "SETVALID1,Set ValidPending control bits for all DMA channels"
bitfld.long 0x00 4. "SETVALID36,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 3. "SETVALID35,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 2. "SETVALID34,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
bitfld.long 0x00 1. "SETVALID33,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
newline
bitfld.long 0x00 0. "SETVALID32,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.."
wgroup.long 0x70++0x03
line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels"
bitfld.long 0x00 31. "SETTRIG31,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 30. "SETTRIG30,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 29. "SETTRIG29,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 28. "SETTRIG28,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 27. "SETTRIG27,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 26. "SETTRIG26,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 25. "SETTRIG25,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 24. "SETTRIG24,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 23. "SETTRIG23,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 22. "SETTRIG22,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 21. "SETTRIG21,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 20. "SETTRIG20,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 19. "SETTRIG19,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 18. "SETTRIG18,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 17. "SETTRIG17,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 16. "SETTRIG16,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 15. "SETTRIG15,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 14. "SETTRIG14,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 13. "SETTRIG13,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 12. "SETTRIG12,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 11. "SETTRIG11,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 10. "SETTRIG10,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 9. "SETTRIG9,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 8. "SETTRIG8,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 7. "SETTRIG7,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 6. "SETTRIG6,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 5. "SETTRIG5,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 4. "SETTRIG4,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 3. "SETTRIG3,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 2. "SETTRIG2,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 1. "SETTRIG1,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 0. "SETTRIG0,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
wgroup.long 0x74++0x03
line.long 0x00 "SETTRIG1,Set Trigger control bits for all DMA channels"
bitfld.long 0x00 4. "SETTRIG36,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 3. "SETTRIG35,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 2. "SETTRIG34,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
bitfld.long 0x00 1. "SETTRIG33,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
newline
bitfld.long 0x00 0. "SETTRIG32,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel"
wgroup.long 0x78++0x03
line.long 0x00 "ABORT0,Channel Abort control for all DMA channels"
bitfld.long 0x00 31. "ABORT31,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 30. "ABORT30,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 29. "ABORT29,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 28. "ABORT28,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 27. "ABORT27,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 26. "ABORT26,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 25. "ABORT25,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 24. "ABORT24,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 23. "ABORT23,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 22. "ABORT22,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 21. "ABORT21,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 20. "ABORT20,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 19. "ABORT19,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 18. "ABORT18,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 17. "ABORT17,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 16. "ABORT16,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 15. "ABORT15,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 14. "ABORT14,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 13. "ABORT13,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 12. "ABORT12,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 11. "ABORT11,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 10. "ABORT10,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 9. "ABORT9,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 8. "ABORT8,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 7. "ABORT7,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 6. "ABORT6,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 5. "ABORT5,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 4. "ABORT4,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 3. "ABORT3,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 2. "ABORT2,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 1. "ABORT1,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 0. "ABORT0,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
wgroup.long 0x7C++0x03
line.long 0x00 "ABORT1,Channel Abort control for all DMA channels"
bitfld.long 0x00 4. "ABORT36,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 3. "ABORT35,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 2. "ABORT34,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
bitfld.long 0x00 1. "ABORT33,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
newline
bitfld.long 0x00 0. "ABORT32,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel"
endif
repeat 37. (increment 0 1)(increment 0 0x10)
tree "CHANNEL[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0x400)++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "DSTBURSTWRAP,Destination Burst Wrap" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 14. "SRCBURSTWRAP,Source Burst Wrap" "0: Disabled,1: Enabled"
bitfld.long 0x00 8.--11. "BURSTPOWER,Burst Power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "TRIGBURST,Trigger Burst" "0: Single transfer,1: Burst transfer"
bitfld.long 0x00 5. "TRIGTYPE,Trigger Type" "0: Edge,1: Level"
newline
bitfld.long 0x00 4. "TRIGPOL,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
bitfld.long 0x00 1. "HWTRIGEN,Hardware Triggering Enable for channel" "0: Hardware triggering not used for channel,1: Hardware triggering used for channel"
newline
bitfld.long 0x00 0. "PERIPHREQEN,Peripheral request Enable" "0: Peripheral DMA requests disabled,1: Peripheral DMA requests enabled"
rgroup.long ($2+0x404)++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. "TRIG,Trigger flag" "0: Not triggered,1: Triggered"
bitfld.long 0x00 0. "VALIDPENDING,Valid pending flag for this channel" "0: No effect on DMA operation,1: Valid pending"
group.long ($2+0x408)++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded"
bitfld.long 0x00 14.--15. "DSTINC,Destination address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width"
newline
bitfld.long 0x00 12.--13. "SRCINC,Source address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width"
bitfld.long 0x00 8.--9. "WIDTH,Transfer width used for this DMA channel" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
newline
bitfld.long 0x00 5. "SETINTB,Set Interrupt flag B for channel" "0: No effect,1: Set"
bitfld.long 0x00 4. "SETINTA,Set Interrupt flag A for channel" "0: No effect,1: Set"
newline
bitfld.long 0x00 3. "CLRTRIG,Clear Trigger" "0: Not cleared,1: Cleared"
bitfld.long 0x00 2. "SWTRIG,Software Trigger" "0: Not set,1: Set"
newline
bitfld.long 0x00 1. "RELOAD,Reload" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "CFGVALID,Configuration Valid flag" "0: Not valid,1: Valid"
endif
tree.end
repeat.end
tree.end
repeat.end
tree.end
tree "DMIC"
base ad:0x40121000
sif cpuis("IMXRT595-CM33")
group.long 0xF00++0x03
line.long 0x00 "CHANEN,Channel Enable"
bitfld.long 0x00 7. "EN_CH7,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled"
bitfld.long 0x00 6. "EN_CH6,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled"
newline
bitfld.long 0x00 5. "EN_CH5,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled"
bitfld.long 0x00 4. "EN_CH4,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled"
newline
bitfld.long 0x00 3. "EN_CH3,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled"
bitfld.long 0x00 2. "EN_CH2,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled"
newline
bitfld.long 0x00 1. "EN_CH1,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled"
bitfld.long 0x00 0. "EN_CH0,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled"
group.long 0xF10++0x03
line.long 0x00 "USE2FS,Use 2 FS register"
bitfld.long 0x00 0. "USE2FS,Use 2FS register" "0: Use 1 FS output for PCM data,1: Use 2 FS output for PCM data"
group.long 0xF14++0x03
line.long 0x00 "GLOBAL_SYNC_EN,Global Channel Synchronization Enable"
hexmask.long.byte 0x00 0.--7. 1. "CH_SYNC_EN,Channel synch enable"
group.long 0xF18++0x03
line.long 0x00 "GLOBAL_COUNT_VAL,Global channel synchronization counter value"
hexmask.long 0x00 0.--31. 1. "CCOUNTVAL,Channel Counter Value"
group.long 0xF1C++0x03
line.long 0x00 "DECRESET,DMIC decimator reset"
hexmask.long.byte 0x00 0.--7. 1. "DECRESET,Decimator reset"
group.long 0xF80++0x03
line.long 0x00 "HWVADGAIN,HWVAD Input Gain"
bitfld.long 0x00 0.--3. "INPUTGAIN,Input Gain" "0: minus10bits,1: minus8bits,2: minus6bits,3: minus4bits,4: minus2bits,5: 0 bits (default),6: plus2bits,7: plus4bits,8: plus6bits,9: plus8bits,10: plus10bits,11: plus12bits,12: plus14bits,?..."
group.long 0xF84++0x03
line.long 0x00 "HWVADHPFS,HWVAD Filter Control"
bitfld.long 0x00 0.--1. "HPFS,The HPFS field chooses the High Pass filter in first part of HWVAD" "0: BYPASS,1: High Pass 1750 Hz,2: High Pass 215 Hz,?..."
group.long 0xF88++0x03
line.long 0x00 "HWVADST10,HWVAD Control"
bitfld.long 0x00 0. "ST10,STAGE 1" "0: Normal operation waiting for HWVAD trigger..,1: Reset internal interrupt flag by writing a.."
group.long 0xF8C++0x03
line.long 0x00 "HWVADRSTT,HWVAD Filter Reset"
bitfld.long 0x00 0. "RSST,Reset HWVAD" "0,1"
group.long 0xF90++0x03
line.long 0x00 "HWVADTHGN,HWVAD Noise Estimator Gain"
bitfld.long 0x00 0.--3. "THGN,Gain Factor for Noise Estimator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF94++0x03
line.long 0x00 "HWVADTHGS,HWVAD Signal Estimator Gain"
bitfld.long 0x00 0.--3. "THGS,Signal Gain Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF98++0x03
line.long 0x00 "HWVADLOWZ,HWVAD Noise Envelope Estimator"
hexmask.long.word 0x00 0.--15. 1. "LOWZ,Average Noise-floor Value"
endif
repeat 8. (increment 0 1)(increment 0 0x100)
tree "CHANNEL[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0x00)++0x03
line.long 0x00 "OSR,Oversample Rate"
hexmask.long.byte 0x00 0.--7. 1. "OSR,Oversample Rate"
group.long ($2+0x04)++0x03
line.long 0x00 "DIVHFCLK,DMIC Clock"
bitfld.long 0x00 0.--3. "PDMDIV,PDM Clock Divider Value" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 6,5: Divide by 8,6: Divide by 12,7: Divide by 16,8: Divide by 24,9: Divide by 32,10: Divide by 48,11: Divide by 64,12: Divide by 96,13: Divide by 128,?..."
group.long ($2+0x08)++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation Filter for 2 FS"
bitfld.long 0x00 0.--1. "COMP,Compensation value" "0: Compensation = 0,1: Compensation = -0.16,2: Compensation = -0.15,3: Compensation = -0.13"
group.long ($2+0x0C)++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation Filter for 4 FS"
bitfld.long 0x00 0.--1. "COMP,Compensation value" "0: Compensation = 0,1: Compensation = -0.16,2: Compensation = -0.15,3: Compensation = -0.13"
group.long ($2+0x10)++0x03
line.long 0x00 "GAINSHIFT,Decimator Gain Shift"
bitfld.long 0x00 0.--4. "GAIN,Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long ($2+0x80)++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. "TRIGLVL,FIFO Trigger Level for Interrupt" "0: Trigger when the FIFO has received one entry..,1: Trigger when the FIFO has received two entries,?,?,?,?,?,?,?,?,?,?,?,?,14: Trigger when the FIFO has received 15 entries,15: Trigger when the FIFO has received 16..,?..."
bitfld.long 0x00 3. "DMAEN,DMA Enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
bitfld.long 0x00 1. "RESETN,FIFO Reset" "0: Reset the FIFO,1: Normal operation"
newline
bitfld.long 0x00 0. "ENABLE,FIFO Enable" "0: Disabled,1: FIFO is enabled"
group.long ($2+0x84)++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
eventfld.long 0x00 2. "UNDERRUN,Underrun Detected (write 1 to clear)" "0,1"
eventfld.long 0x00 1. "OVERRUN,Overrun Detected (write 1 to clear)" "0,1"
newline
eventfld.long 0x00 0. "INT,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long ($2+0x88)++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,PCM Data"
group.long ($2+0x8C)++0x03
line.long 0x00 "PHY_CTRL,Physical Control"
bitfld.long 0x00 1. "PHY_HALF,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
bitfld.long 0x00 0. "PHY_FALL,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long ($2+0x90)++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. "SIGNEXTEND,Sign Extend" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "SATURATEAT16BIT,Saturate at 16 Bit" "0: Do not Saturate,1: Saturate"
newline
bitfld.long 0x00 4.--7. "DCGAIN,DC Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "DCPOLE,DC Block Filter" "0: Flat Response no filter,1: HZ_155,2: HZ_78,3: HZ_39"
endif
tree.end
repeat.end
tree.end
tree "FLEXCOMM"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.) (list ad:0x40106000 ad:0x40107000 ad:0x40108000 ad:0x40109000 ad:0x40122000 ad:0x40123000 ad:0x40124000 ad:0x40125000 ad:0x40209000 ad:0x4020A000 ad:0x4020B000 ad:0x4020C000 ad:0x4020D000 ad:0x4020E000 ad:0x40126000 ad:0x40127000)
tree "FLEXCOMM$1"
base $2
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID"
hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID"
rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present"
newline
rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present"
rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function"
newline
rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.."
bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..."
rgroup.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral Identification"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
repeat.end
tree "FLEXCOMM16"
base ad:0x40128000
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID"
hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID"
rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present"
newline
rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present"
rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function"
newline
rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.."
bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..."
rgroup.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral Identification"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "FLEXIO"
base ad:0x40032000
rgroup.long 0x00++0x03
line.long 0x00 "VERID,Version ID Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
rgroup.long 0x04++0x03
line.long 0x00 "PARAM,Parameter Register"
hexmask.long.byte 0x00 24.--31. 1. "TRIGGER,Trigger Number"
hexmask.long.byte 0x00 16.--23. 1. "PIN,Pin Number"
newline
hexmask.long.byte 0x00 8.--15. 1. "TIMER,Timer Number"
hexmask.long.byte 0x00 0.--7. 1. "SHIFTER,Shifter Number"
group.long 0x08++0x03
line.long 0x00 "CTRL,FlexIO Control Register"
bitfld.long 0x00 31. "DOZEN,Doze Enable" "0: FlexIO enabled in Doze modes,1: FlexIO disabled in Doze modes"
bitfld.long 0x00 30. "DBGE,Debug Enable" "0: FlexIO is disabled in debug modes,1: FlexIO is enabled in debug modes"
newline
bitfld.long 0x00 2. "FASTACC,Fast Access" "0: Configures for normal register accesses to..,1: Configures for fast register accesses to FlexIO"
bitfld.long 0x00 1. "SWRST,Software Reset" "0: Software reset is disabled,1: Software reset is enabled all FlexIO.."
newline
bitfld.long 0x00 0. "FLEXEN,FlexIO Enable" "0: FlexIO module is disabled,1: FlexIO module is enabled"
rgroup.long 0x0C++0x03
line.long 0x00 "PIN,Pin State Register"
hexmask.long.word 0x00 0.--15. 1. "PDI,Pin Data Input"
group.long 0x10++0x03
line.long 0x00 "SHIFTSTAT,Shifter Status Register"
hexmask.long.byte 0x00 0.--7. 1. "SSF,Shifter Status Flag"
group.long 0x14++0x03
line.long 0x00 "SHIFTERR,Shifter Error Register"
hexmask.long.byte 0x00 0.--7. 1. "SEF,Shifter Error Flags"
group.long 0x18++0x03
line.long 0x00 "TIMSTAT,Timer Status Register"
hexmask.long.byte 0x00 0.--7. 1. "TSF,Timer Status Flags"
group.long 0x20++0x03
line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable"
hexmask.long.byte 0x00 0.--7. 1. "SSIE,Shifter Status Interrupt Enable"
group.long 0x24++0x03
line.long 0x00 "SHIFTEIEN,Shifter Error Interrupt Enable"
hexmask.long.byte 0x00 0.--7. 1. "SEIE,Shifter Error Interrupt Enable"
group.long 0x28++0x03
line.long 0x00 "TIMIEN,Timer Interrupt Enable Register"
hexmask.long.byte 0x00 0.--7. 1. "TEIE,Timer Status Interrupt Enable"
group.long 0x30++0x03
line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable"
hexmask.long.byte 0x00 0.--7. 1. "SSDE,Shifter Status DMA Enable"
group.long 0x38++0x03
line.long 0x00 "TIMERSDEN,Timer Status DMA Enable"
hexmask.long.byte 0x00 0.--7. 1. "TSDE,Timer Status DMA Enable"
group.long 0x40++0x03
line.long 0x00 "SHIFTSTATE,Shifter State Register"
bitfld.long 0x00 0.--2. "STATE,Current State Pointer" "0,1,2,3,4,5,6,7"
group.long 0x48++0x03
line.long 0x00 "TRGSTAT,Trigger Status Register"
hexmask.long.word 0x00 0.--15. 1. "ETSF,External Trigger Status Flags"
group.long 0x4C++0x03
line.long 0x00 "TRIGIEN,External Trigger Interrupt Enable Register"
hexmask.long.word 0x00 0.--15. 1. "TRIE,External Trigger Interrupt Enable"
group.long 0x50++0x03
line.long 0x00 "PINSTAT,Pin Status Register"
hexmask.long.word 0x00 0.--15. 1. "PSF,Pin Status Flags"
group.long 0x54++0x03
line.long 0x00 "PINIEN,Pin Interrupt Enable Register"
hexmask.long.word 0x00 0.--15. 1. "PSIE,Pin Status Interrupt Enable"
group.long 0x58++0x03
line.long 0x00 "PINREN,Pin Rising Edge Enable Register"
hexmask.long.word 0x00 0.--15. 1. "PRE,Pin Rising Edge"
group.long 0x5C++0x03
line.long 0x00 "PINFEN,Pin Falling Edge Enable Register"
hexmask.long.word 0x00 0.--15. 1. "PFE,Pin Falling Edge"
group.long 0x60++0x03
line.long 0x00 "PINOUTD,Pin Output Data Register"
hexmask.long.word 0x00 0.--15. 1. "OUTD,Output Data"
group.long 0x64++0x03
line.long 0x00 "PINOUTE,Pin Output Enable Register"
hexmask.long.word 0x00 0.--15. 1. "OUTE,Output Enable"
group.long 0x68++0x03
line.long 0x00 "PINOUTDIS,Pin Output Disable Register"
hexmask.long.word 0x00 0.--15. 1. "OUTDIS,Output Disable"
group.long 0x6C++0x03
line.long 0x00 "PINOUTCLR,Pin Output Clear Register"
hexmask.long.word 0x00 0.--15. 1. "OUTCLR,Output Clear"
group.long 0x70++0x03
line.long 0x00 "PINOUTSET,Pin Output Set Register"
hexmask.long.word 0x00 0.--15. 1. "OUTSET,Output Set"
group.long 0x74++0x03
line.long 0x00 "PINOUTTOG,Pin Output Toggle Register"
hexmask.long.word 0x00 0.--15. 1. "OUTTOG,Output Toggle"
repeat 8. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "SHIFTCTL[$1],Shifter Control N Register $1"
bitfld.long 0x00 24.--26. "TIMSEL,Timer Select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23. "TIMPOL,Timer Polarity" "0: Shift on posedge of Shift clock,1: Shift on negedge of Shift clock"
newline
bitfld.long 0x00 16.--17. "PINCFG,Shifter Pin Configuration" "0: Shifter pin output disabled,1: Shifter pin open drain or bidirectional..,2: Shifter pin bidirectional output data,3: Shifter pin output"
bitfld.long 0x00 8.--11. "PINSEL,Shifter Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "PINPOL,Shifter Pin Polarity" "0: Pin is active high,1: Pin is active low"
bitfld.long 0x00 0.--2. "SMOD,Shifter Mode" "0: Disabled,1: Receive mode,2: Transmit mode,?,4: Match Store mode,5: Match Continuous mode,6: State mode,7: Logic mode"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "SHIFTCFG[$1],Shifter Configuration N Register $1"
bitfld.long 0x00 16.--19. "PWIDTH,Parallel Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "SSIZE,Shifter Size" "0: Shift register is 32-bit,1: Shift register is 24-bit"
newline
bitfld.long 0x00 9. "LATST,Late Store" "0: Shift register stores the pre-shift register..,1: Shift register stores the post-shift register.."
bitfld.long 0x00 8. "INSRC,Input Source" "0: pin,1: Shifter N+1 Output"
newline
bitfld.long 0x00 4.--5. "SSTOP,Shifter Stop bit" "0: Stop bit disabled for..,?,2: Transmitter outputs stop bit value 0 on store..,3: Transmitter outputs stop bit value 1 on store.."
bitfld.long 0x00 0.--1. "SSTART,Shifter Start bit" "0: Start bit disabled for..,1: Start bit disabled for..,2: Transmitter outputs start bit value 0 before..,3: Transmitter outputs start bit value 1 before.."
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "SHIFTBUF[$1],Shifter Buffer N Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUF,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x280)++0x03
line.long 0x00 "SHIFTBUFBIS[$1],Shifter Buffer N Bit Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBIS,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x300)++0x03
line.long 0x00 "SHIFTBUFBYS[$1],Shifter Buffer N Byte Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBYS,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x380)++0x03
line.long 0x00 "SHIFTBUFBBS[$1],Shifter Buffer N Bit Byte Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBBS,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x400)++0x03
line.long 0x00 "TIMCTL[$1],Timer Control N Register $1"
bitfld.long 0x00 24.--28. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
newline
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
newline
bitfld.long 0x00 8.--11. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
newline
bitfld.long 0x00 6. "PININS,Timer Pin Input Select" "0: Timer pin input and output are selected by..,1: Timer pin input is selected by PINSEL+1 timer.."
bitfld.long 0x00 5. "ONETIM,Timer One Time Operation" "0: The timer enable event is generated as normal,1: The timer enable event is blocked unless.."
newline
bitfld.long 0x00 0.--2. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud mode,2: Dual 8-bit counters PWM high mode,3: Single 16-bit counter mode,4: Single 16-bit counter disable mode,5: Dual 8-bit counters word mode,6: Dual 8-bit counters PWM low mode,7: Single 16-bit input capture mode"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x480)++0x03
line.long 0x00 "TIMCFG[$1],Timer Configuration N Register $1"
bitfld.long 0x00 24.--25. "TIMOUT,Timer Output" "0: Timer output is logic one when enabled and is..,1: Timer output is logic zero when enabled and..,2: Timer output is logic one when enabled and on..,3: Timer output is logic zero when enabled and.."
bitfld.long 0x00 20.--22. "TIMDEC,Timer Decrement" "0: Decrement counter on FlexIO clock Shift clock..,1: Decrement counter on Trigger input (both..,2: Decrement counter on Pin input (both edges)..,3: Decrement counter on Trigger input (both..,4: Decrement counter on FlexIO clock divided by..,5: Decrement counter on FlexIO clock divided by..,6: Decrement counter on Pin input (rising edge)..,7: Decrement counter on Trigger input (rising.."
newline
bitfld.long 0x00 16.--18. "TIMRST,Timer Reset" "0: Timer never reset,1: Timer reset on Timer Output high,2: Timer reset on Timer Pin equal to Timer Output,3: Timer reset on Timer Trigger equal to Timer..,4: Timer reset on Timer Pin rising edge,?,6: Timer reset on Trigger rising edge,7: Timer reset on Trigger rising or falling edge"
bitfld.long 0x00 12.--14. "TIMDIS,Timer Disable" "0: Timer never disabled,1: Timer disabled on Timer N-1 disable,2: Timer disabled on Timer compare (upper 8-bits..,3: Timer disabled on Timer compare (upper 8-bits..,4: Timer disabled on Pin rising or falling edge,5: Timer disabled on Pin rising or falling edge..,6: Timer disabled on Trigger falling edge,?..."
newline
bitfld.long 0x00 8.--10. "TIMENA,Timer Enable" "0: Timer always enabled,1: Timer enabled on Timer N-1 enable,2: Timer enabled on Trigger high,3: Timer enabled on Trigger high and Pin high,4: Timer enabled on Pin rising edge,5: Timer enabled on Pin rising edge and Trigger..,6: Timer enabled on Trigger rising edge,7: Timer enabled on Trigger rising or falling edge"
bitfld.long 0x00 4.--5. "TSTOP,Timer Stop Bit" "0: Stop bit disabled,1: Stop bit is enabled on timer compare,2: Stop bit is enabled on timer disable,3: Stop bit is enabled on timer compare and.."
newline
bitfld.long 0x00 1. "TSTART,Timer Start Bit" "0: Start bit disabled,1: Start bit enabled"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x500)++0x03
line.long 0x00 "TIMCMP[$1],Timer Compare N Register $1"
hexmask.long.word 0x00 0.--15. 1. "CMP,Timer Compare Value"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x680)++0x03
line.long 0x00 "SHIFTBUFNBS[$1],Shifter Buffer N Nibble Byte Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFNBS,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x700)++0x03
line.long 0x00 "SHIFTBUFHWS[$1],Shifter Buffer N Half Word Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFHWS,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x780)++0x03
line.long 0x00 "SHIFTBUFNIS[$1],Shifter Buffer N Nibble Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFNIS,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x800)++0x03
line.long 0x00 "SHIFTBUFOES[$1],Shifter Buffer N Odd Even Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFOES,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x880)++0x03
line.long 0x00 "SHIFTBUFEOS[$1],Shifter Buffer N Even Odd Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFEOS,Shift Buffer"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x900)++0x03
line.long 0x00 "SHIFTBUFHBS[$1],Shifter Buffer N Halfword Byte Swapped Register $1"
hexmask.long 0x00 0.--31. 1. "SHIFTBUFHBS,Shift Buffer"
repeat.end
tree.end
tree "FLEXSPI"
tree "FLEXSPI0"
base ad:0x40134000
group.long 0x00++0x03
line.long 0x00 "MCR0,Module Control Register 0"
hexmask.long.byte 0x00 24.--31. 1. "AHBGRANTWAIT,Timeout wait cycle for AHB command grant"
hexmask.long.byte 0x00 16.--23. 1. "IPGRANTWAIT,Time out wait cycle for IP command grant"
newline
bitfld.long 0x00 15. "LEARNEN,This bit is used to enable/disable data learning feature" "0: LEARNEN_0,1: LEARNEN_1"
bitfld.long 0x00 14. "SCKFREERUNEN,This bit is used to force SCLK output free-running" "0: SCKFREERUNEN_0,1: SCKFREERUNEN_1"
newline
bitfld.long 0x00 13. "COMBINATIONEN,This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0])" "0: COMBINATIONEN_0,1: COMBINATIONEN_1"
bitfld.long 0x00 12. "DOZEEN,Doze mode enable bit" "0: Doze mode support disabled,1: Doze mode support enabled"
newline
bitfld.long 0x00 11. "HSEN,Half Speed Serial Flash access Enable" "0: Disable divide by 2 of serial flash clock for..,1: Enable divide by 2 of serial flash clock for.."
bitfld.long 0x00 8.--10. "SERCLKDIV,The serial root clock could be divided inside FlexSPI wrapper" "0: Divided by 1,1: Divided by 2,2: Divided by 3,3: Divided by 4,4: Divided by 5,5: Divided by 6,6: Divided by 7,7: Divided by 8"
newline
bitfld.long 0x00 4.--5. "RXCLKSRC,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI..,1: Dummy Read strobe generated by FlexSPI..,?,3: Flash provided Read strobe and input from DQS.."
bitfld.long 0x00 1. "MDIS,Module Disable" "0,1"
newline
bitfld.long 0x00 0. "SWRESET,Software Reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "MCR1,Module Control Register 1"
hexmask.long.word 0x00 16.--31. 1. "SEQWAIT,Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"
hexmask.long.word 0x00 0.--15. 1. "AHBBUSWAIT,AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles AHB Bus will get an error response"
group.long 0x08++0x03
line.long 0x00 "MCR2,Module Control Register 2"
hexmask.long.byte 0x00 24.--31. 1. "RESUMEWAIT,Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed"
bitfld.long 0x00 19. "SCKBDIFFOPT,B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK)" "0: B_SCLK pad is used as port B SCLK clock output,1: B_SCLK pad is used as port A SCLK inverted.."
newline
bitfld.long 0x00 15. "SAMEDEVICEEN,All external devices are same devices (both in types and size) for A1/A2/B1/B2" "0: In Individual mode..,1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register.."
bitfld.long 0x00 14. "CLRLEARNPHASE,The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1" "0,1"
newline
bitfld.long 0x00 11. "CLRAHBBUFOPT,This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK" "0: AHB RX/TX Buffer will not be cleaned..,1: AHB RX/TX Buffer will be cleaned.."
group.long 0x0C++0x03
line.long 0x00 "AHBCR,AHB Bus Control Register"
bitfld.long 0x00 10. "READSZALIGN,AHB Read Size Alignment" "0: AHB read size will be decided by other..,1: AHB read size to up size to 8 bytes aligned.."
bitfld.long 0x00 6. "READADDROPT,AHB Read Address option bit" "0: There is AHB read burst start address..,1: There is no AHB read burst start address.."
newline
bitfld.long 0x00 5. "PREFETCHEN,AHB Read Prefetch Enable" "0,1"
bitfld.long 0x00 4. "BUFFERABLEEN,Enable AHB bus bufferable write access support" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "CACHABLEEN,Enable AHB bus cachable read access support" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "APAREN,Parallel mode enabled for AHB triggered Command (both read and write)" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
group.long 0x10++0x03
line.long 0x00 "INTEN,Interrupt Enable Register"
bitfld.long 0x00 13. "KEYERROREN,OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details" "0,1"
bitfld.long 0x00 12. "KEYDONEEN,OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details" "0,1"
newline
bitfld.long 0x00 11. "SEQTIMEOUTEN,Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details" "0,1"
bitfld.long 0x00 10. "AHBBUSERROREN,AHB Bus error interrupt enable.Refer Interrupts chapter for more details" "0,1"
newline
bitfld.long 0x00 9. "SCKSTOPBYWREN,SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable" "0,1"
bitfld.long 0x00 8. "SCKSTOPBYRDEN,SCLK is stopped during command sequence because Async RX FIFO full interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "DATALEARNFAILEN,Data Learning failed interrupt enable" "0,1"
bitfld.long 0x00 6. "IPTXWEEN,IP TX FIFO WaterMark empty interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "IPRXWAEN,IP RX FIFO WaterMark available interrupt enable" "0,1"
bitfld.long 0x00 4. "AHBCMDERREN,AHB triggered Command Sequences Error Detected interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "IPCMDERREN,IP triggered Command Sequences Error Detected interrupt enable" "0,1"
bitfld.long 0x00 2. "AHBCMDGEEN,AHB triggered Command Sequences Grant Timeout interrupt enable" "0,1"
newline
bitfld.long 0x00 1. "IPCMDGEEN,IP triggered Command Sequences Grant Timeout interrupt enable" "0,1"
bitfld.long 0x00 0. "IPCMDDONEEN,IP triggered Command Sequences Execution finished interrupt enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "INTR,Interrupt Register"
rbitfld.long 0x00 13. "KEYERROR,OTFAD key blob processing error interrupt" "0,1"
eventfld.long 0x00 12. "KEYDONE,OTFAD key blob processing done interrupt" "0,1"
newline
eventfld.long 0x00 11. "SEQTIMEOUT,Sequence execution timeout interrupt" "0,1"
eventfld.long 0x00 10. "AHBBUSERROR,AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt" "0,1"
newline
eventfld.long 0x00 9. "SCKSTOPBYWR,SCLK is stopped during command sequence because Async TX FIFO empty interrupt" "0,1"
eventfld.long 0x00 8. "SCKSTOPBYRD,SCLK is stopped during command sequence because Async RX FIFO full interrupt" "0,1"
newline
eventfld.long 0x00 7. "DATALEARNFAIL,Data Learning failed interrupt" "0,1"
eventfld.long 0x00 6. "IPTXWE,IP TX FIFO watermark empty interrupt" "0,1"
newline
eventfld.long 0x00 5. "IPRXWA,IP RX FIFO watermark available interrupt" "0,1"
eventfld.long 0x00 4. "AHBCMDERR,AHB triggered Command Sequences Error Detected interrupt" "0,1"
newline
eventfld.long 0x00 3. "IPCMDERR,IP triggered Command Sequences Error Detected interrupt" "0,1"
eventfld.long 0x00 2. "AHBCMDGE,AHB triggered Command Sequences Grant Timeout interrupt" "0,1"
newline
eventfld.long 0x00 1. "IPCMDGE,IP triggered Command Sequences Grant Timeout interrupt" "0,1"
eventfld.long 0x00 0. "IPCMDDONE,IP triggered Command Sequences Execution finished interrupt" "0,1"
group.long 0x18++0x03
line.long 0x00 "LUTKEY,LUT Key Register"
hexmask.long 0x00 0.--31. 1. "KEY,The Key to lock or unlock LUT"
group.long 0x1C++0x03
line.long 0x00 "LUTCR,LUT Control Register"
bitfld.long 0x00 1. "UNLOCK,Unlock LUT" "0,1"
bitfld.long 0x00 0. "LOCK,Lock LUT" "0,1"
group.long 0x20++0x03
line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x24++0x03
line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x28++0x03
line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x2C++0x03
line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x30++0x03
line.long 0x00 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x34++0x03
line.long 0x00 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x38++0x03
line.long 0x00 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x3C++0x03
line.long 0x00 "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x60++0x03
line.long 0x00 "FLSHA1CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x64++0x03
line.long 0x00 "FLSHA2CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x68++0x03
line.long 0x00 "FLSHB1CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x6C++0x03
line.long 0x00 "FLSHB2CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x70)++0x03
line.long 0x00 "FLSHCR1A$1,Flash Control Register $1"
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
newline
bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
newline
bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x78)++0x03
line.long 0x00 "FLSHCR1B$1,Flash Control Register $1"
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
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bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
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bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x80)++0x03
line.long 0x00 "FLSHCR2A$1,Flash Control Register 2"
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
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hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x88)++0x03
line.long 0x00 "FLSHCR2B$1,Flash Control Register 2"
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
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hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.long 0x94++0x03
line.long 0x00 "FLSHCR4,Flash Control Register 4"
bitfld.long 0x00 3. "WMENB,Write mask enable bit for flash device on port B" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
bitfld.long 0x00 2. "WMENA,Write mask enable bit for flash device on port A" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
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bitfld.long 0x00 0. "WMOPT1,Write mask option bit 1" "0: DQS pin will be used as Write Mask when..,1: DQS pin will not be used as Write Mask when.."
group.long 0xA0++0x03
line.long 0x00 "IPCR0,IP Control Register 0"
hexmask.long 0x00 0.--31. 1. "SFAR,Serial Flash Address for IP command"
group.long 0xA4++0x03
line.long 0x00 "IPCR1,IP Control Register 1"
bitfld.long 0x00 31. "IPAREN,Parallel mode Enabled for IP command" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
bitfld.long 0x00 24.--26. "ISEQNUM,Sequence Number for IP command: ISEQNUM+1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "ISEQID,Sequence Index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "IDATSZ,Flash Read/Program Data Size (in Bytes) for IP command"
group.long 0xB0++0x03
line.long 0x00 "IPCMD,IP Command Register"
bitfld.long 0x00 0. "TRG,Setting this bit will trigger an IP Command" "0,1"
group.long 0xB4++0x03
line.long 0x00 "DLPR,Data Learn Pattern Register"
hexmask.long 0x00 0.--31. 1. "DLP,Data Learning Pattern"
group.long 0xB8++0x03
line.long 0x00 "IPRXFCR,IP RX FIFO Control Register"
hexmask.long.byte 0x00 2.--8. 1. "RXWMRK,Watermark level is (RXWMRK+1)*64 Bits"
bitfld.long 0x00 1. "RXDMAEN,IP RX FIFO reading by DMA enabled" "0: IP RX FIFO would be read by processor,1: IP RX FIFO would be read by DMA"
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bitfld.long 0x00 0. "CLRIPRXF,Clear all valid data entries in IP RX FIFO" "0,1"
group.long 0xBC++0x03
line.long 0x00 "IPTXFCR,IP TX FIFO Control Register"
hexmask.long.byte 0x00 2.--8. 1. "TXWMRK,Watermark level is (TXWMRK+1)*64 Bits"
bitfld.long 0x00 1. "TXDMAEN,IP TX FIFO filling by DMA enabled" "0: IP TX FIFO would be filled by processor,1: IP TX FIFO would be filled by DMA"
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bitfld.long 0x00 0. "CLRIPTXF,Clear all valid data entries in IP TX FIFO" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DLLCRA,DLL Control Register 0"
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
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bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
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bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
group.long 0xC4++0x03
line.long 0x00 "DLLCRB,DLL Control Register 0"
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
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bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
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bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
rgroup.long 0xE0++0x03
line.long 0x00 "STS0,Status Register 0"
bitfld.long 0x00 8.--11. "DATALEARNPHASEB,Indicate the sampling clock phase selection on Port B after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DATALEARNPHASEA,Indicate the sampling clock phase selection on Port A after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2.--3. "ARBCMDSRC,This status field indicates the trigger source of current command sequence granted by arbitrator" "0: Triggered by AHB read command (triggered by..,1: Triggered by AHB write command (triggered by..,2: Triggered by IP command (triggered by setting..,3: Triggered by suspended command (resumed)"
bitfld.long 0x00 1. "ARBIDLE,This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface" "0,1"
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bitfld.long 0x00 0. "SEQIDLE,This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface" "0,1"
rgroup.long 0xE4++0x03
line.long 0x00 "STS1,Status Register 1"
bitfld.long 0x00 24.--27. "IPCMDERRCODE,Indicates the Error Code when IP command Error detected" "0: IPCMDERRCODE_0,?,2: IP command with JMP_ON_CS instruction used in..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,6: Flash access start address exceed the whole..,?,?,?,?,?,?,?,14: Sequence execution timeout,15: Flash boundary crossed"
bitfld.long 0x00 16.--19. "IPCMDERRID,Indicates the sequence Index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "AHBCMDERRCODE,Indicates the Error Code when AHB command Error detected" "0: AHBCMDERRCODE_0,?,2: AHB Write command with JMP_ON_CS instruction..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,?,?,?,?,?,?,?,?,14: Sequence execution timeout,?..."
bitfld.long 0x00 0.--3. "AHBCMDERRID,Indicates the sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xE8++0x03
line.long 0x00 "STS2,Status Register 2"
bitfld.long 0x00 24.--29. "BREFSEL,Flash B sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. "BSLVSEL,Flash B sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "BREFLOCK,Flash B sample clock reference delay line locked" "0,1"
bitfld.long 0x00 16. "BSLVLOCK,Flash B sample clock slave delay line locked" "0,1"
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bitfld.long 0x00 8.--13. "AREFSEL,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 2.--7. "ASLVSEL,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "AREFLOCK,Flash A sample clock reference delay line locked" "0,1"
bitfld.long 0x00 0. "ASLVLOCK,Flash A sample clock slave delay line locked" "0,1"
rgroup.long 0xEC++0x03
line.long 0x00 "AHBSPNDSTS,AHB Suspend Status Register"
hexmask.long.word 0x00 16.--31. 1. "DATLFT,Left Data size for suspended command sequence (in byte)"
bitfld.long 0x00 1.--3. "BUFID,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "ACTIVE,Indicates if an AHB read prefetch command sequence has been suspended" "0,1"
rgroup.long 0xF0++0x03
line.long 0x00 "IPRXFSTS,IP RX FIFO Status Register"
hexmask.long.word 0x00 16.--31. 1. "RDCNTR,Total Read Data Counter: RDCNTR * 64 Bits"
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP RX FIFO"
rgroup.long 0xF4++0x03
line.long 0x00 "IPTXFSTS,IP TX FIFO Status Register"
hexmask.long.word 0x00 16.--31. 1. "WRCNTR,Total Write Data Counter: WRCNTR * 64 Bits"
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP TX FIFO"
repeat 32. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x100)++0x03
line.long 0x00 "RFDR[$1],IP RX FIFO Data Register x $1"
hexmask.long 0x00 0.--31. 1. "RXDATA,RX Data"
repeat.end
repeat 32. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x180)++0x03
line.long 0x00 "TFDR[$1],IP TX FIFO Data Register x $1"
hexmask.long 0x00 0.--31. 1. "TXDATA,TX Data"
repeat.end
repeat 64. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "LUT[$1],LUT x $1"
bitfld.long 0x00 26.--31. "OPCODE1,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "NUM_PADS1,NUM_PADS1" "0,1,2,3"
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hexmask.long.byte 0x00 16.--23. 1. "OPERAND1,OPERAND1"
bitfld.long 0x00 10.--15. "OPCODE0,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--9. "NUM_PADS0,NUM_PADS0" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "OPERAND0,OPERAND0"
repeat.end
tree.end
tree "FLEXSPI1"
base ad:0x4013C000
group.long 0x00++0x03
line.long 0x00 "MCR0,Module Control Register 0"
hexmask.long.byte 0x00 24.--31. 1. "AHBGRANTWAIT,Timeout wait cycle for AHB command grant"
hexmask.long.byte 0x00 16.--23. 1. "IPGRANTWAIT,Time out wait cycle for IP command grant"
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bitfld.long 0x00 15. "LEARNEN,This bit is used to enable/disable data learning feature" "0: LEARNEN_0,1: LEARNEN_1"
bitfld.long 0x00 14. "SCKFREERUNEN,This bit is used to force SCLK output free-running" "0: SCKFREERUNEN_0,1: SCKFREERUNEN_1"
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bitfld.long 0x00 13. "COMBINATIONEN,This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0])" "0: COMBINATIONEN_0,1: COMBINATIONEN_1"
bitfld.long 0x00 12. "DOZEEN,Doze mode enable bit" "0: Doze mode support disabled,1: Doze mode support enabled"
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bitfld.long 0x00 11. "HSEN,Half Speed Serial Flash access Enable" "0: Disable divide by 2 of serial flash clock for..,1: Enable divide by 2 of serial flash clock for.."
bitfld.long 0x00 8.--10. "SERCLKDIV,The serial root clock could be divided inside FlexSPI wrapper" "0: Divided by 1,1: Divided by 2,2: Divided by 3,3: Divided by 4,4: Divided by 5,5: Divided by 6,6: Divided by 7,7: Divided by 8"
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bitfld.long 0x00 4.--5. "RXCLKSRC,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI..,1: Dummy Read strobe generated by FlexSPI..,?,3: Flash provided Read strobe and input from DQS.."
bitfld.long 0x00 1. "MDIS,Module Disable" "0,1"
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bitfld.long 0x00 0. "SWRESET,Software Reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "MCR1,Module Control Register 1"
hexmask.long.word 0x00 16.--31. 1. "SEQWAIT,Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"
hexmask.long.word 0x00 0.--15. 1. "AHBBUSWAIT,AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles AHB Bus will get an error response"
group.long 0x08++0x03
line.long 0x00 "MCR2,Module Control Register 2"
hexmask.long.byte 0x00 24.--31. 1. "RESUMEWAIT,Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed"
bitfld.long 0x00 19. "SCKBDIFFOPT,B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK)" "0: B_SCLK pad is used as port B SCLK clock output,1: B_SCLK pad is used as port A SCLK inverted.."
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bitfld.long 0x00 15. "SAMEDEVICEEN,All external devices are same devices (both in types and size) for A1/A2/B1/B2" "0: In Individual mode..,1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register.."
bitfld.long 0x00 14. "CLRLEARNPHASE,The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1" "0,1"
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bitfld.long 0x00 11. "CLRAHBBUFOPT,This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK" "0: AHB RX/TX Buffer will not be cleaned..,1: AHB RX/TX Buffer will be cleaned.."
group.long 0x0C++0x03
line.long 0x00 "AHBCR,AHB Bus Control Register"
bitfld.long 0x00 6. "READADDROPT,AHB Read Address option bit" "0: There is AHB read burst start address..,1: There is no AHB read burst start address.."
bitfld.long 0x00 5. "PREFETCHEN,AHB Read Prefetch Enable" "0,1"
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bitfld.long 0x00 4. "BUFFERABLEEN,Enable AHB bus bufferable write access support" "0: Disabled,1: Enabled"
bitfld.long 0x00 3. "CACHABLEEN,Enable AHB bus cachable read access support" "0: Disabled,1: Enabled"
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bitfld.long 0x00 0. "APAREN,Parallel mode enabled for AHB triggered Command (both read and write)" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
group.long 0x10++0x03
line.long 0x00 "INTEN,Interrupt Enable Register"
bitfld.long 0x00 11. "SEQTIMEOUTEN,Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details" "0,1"
bitfld.long 0x00 10. "AHBBUSTIMEOUTEN,AHB Bus timeout interrupt.Refer Interrupts chapter for more details" "0,1"
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bitfld.long 0x00 9. "SCKSTOPBYWREN,SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable" "0,1"
bitfld.long 0x00 8. "SCKSTOPBYRDEN,SCLK is stopped during command sequence because Async RX FIFO full interrupt enable" "0,1"
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bitfld.long 0x00 7. "DATALEARNFAILEN,Data Learning failed interrupt enable" "0,1"
bitfld.long 0x00 6. "IPTXWEEN,IP TX FIFO WaterMark empty interrupt enable" "0,1"
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bitfld.long 0x00 5. "IPRXWAEN,IP RX FIFO WaterMark available interrupt enable" "0,1"
bitfld.long 0x00 4. "AHBCMDERREN,AHB triggered Command Sequences Error Detected interrupt enable" "0,1"
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bitfld.long 0x00 3. "IPCMDERREN,IP triggered Command Sequences Error Detected interrupt enable" "0,1"
bitfld.long 0x00 2. "AHBCMDGEEN,AHB triggered Command Sequences Grant Timeout interrupt enable" "0,1"
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bitfld.long 0x00 1. "IPCMDGEEN,IP triggered Command Sequences Grant Timeout interrupt enable" "0,1"
bitfld.long 0x00 0. "IPCMDDONEEN,IP triggered Command Sequences Execution finished interrupt enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "INTR,Interrupt Register"
eventfld.long 0x00 11. "SEQTIMEOUT,Sequence execution timeout interrupt" "0,1"
eventfld.long 0x00 10. "AHBBUSTIMEOUT,AHB Bus timeout interrupt.Refer Interrupts chapter for more details" "0,1"
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eventfld.long 0x00 9. "SCKSTOPBYWR,SCLK is stopped during command sequence because Async TX FIFO empty interrupt" "0,1"
eventfld.long 0x00 8. "SCKSTOPBYRD,SCLK is stopped during command sequence because Async RX FIFO full interrupt" "0,1"
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eventfld.long 0x00 7. "DATALEARNFAIL,Data Learning failed interrupt" "0,1"
eventfld.long 0x00 6. "IPTXWE,IP TX FIFO watermark empty interrupt" "0,1"
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eventfld.long 0x00 5. "IPRXWA,IP RX FIFO watermark available interrupt" "0,1"
eventfld.long 0x00 4. "AHBCMDERR,AHB triggered Command Sequences Error Detected interrupt" "0,1"
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eventfld.long 0x00 3. "IPCMDERR,IP triggered Command Sequences Error Detected interrupt" "0,1"
eventfld.long 0x00 2. "AHBCMDGE,AHB triggered Command Sequences Grant Timeout interrupt" "0,1"
newline
eventfld.long 0x00 1. "IPCMDGE,IP triggered Command Sequences Grant Timeout interrupt" "0,1"
eventfld.long 0x00 0. "IPCMDDONE,IP triggered Command Sequences Execution finished interrupt" "0,1"
group.long 0x18++0x03
line.long 0x00 "LUTKEY,LUT Key Register"
hexmask.long 0x00 0.--31. 1. "KEY,The Key to lock or unlock LUT"
group.long 0x1C++0x03
line.long 0x00 "LUTCR,LUT Control Register"
bitfld.long 0x00 1. "UNLOCK,Unlock LUT" "0,1"
bitfld.long 0x00 0. "LOCK,Lock LUT" "0,1"
group.long 0x20++0x03
line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x24++0x03
line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x28++0x03
line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x2C++0x03
line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x30++0x03
line.long 0x00 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x34++0x03
line.long 0x00 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x38++0x03
line.long 0x00 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x3C++0x03
line.long 0x00 "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x60++0x03
line.long 0x00 "FLSHA1CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x64++0x03
line.long 0x00 "FLSHA2CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x68++0x03
line.long 0x00 "FLSHB1CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x6C++0x03
line.long 0x00 "FLSHB2CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x70)++0x03
line.long 0x00 "FLSHCR1A$1,Flash Control Register $1"
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
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bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
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bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x78)++0x03
line.long 0x00 "FLSHCR1B$1,Flash Control Register $1"
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
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bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
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bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x80)++0x03
line.long 0x00 "FLSHCR2A$1,Flash Control Register 2"
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
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hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--3. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x88)++0x03
line.long 0x00 "FLSHCR2B$1,Flash Control Register 2"
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
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hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--3. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.long 0x94++0x03
line.long 0x00 "FLSHCR4,Flash Control Register 4"
bitfld.long 0x00 3. "WMENB,Write mask enable bit for flash device on port B" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
bitfld.long 0x00 2. "WMENA,Write mask enable bit for flash device on port A" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
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bitfld.long 0x00 0. "WMOPT1,Write mask option bit 1" "0: DQS pin will be used as Write Mask when..,1: DQS pin will not be used as Write Mask when.."
group.long 0xA0++0x03
line.long 0x00 "IPCR0,IP Control Register 0"
hexmask.long 0x00 0.--31. 1. "SFAR,Serial Flash Address for IP command"
group.long 0xA4++0x03
line.long 0x00 "IPCR1,IP Control Register 1"
bitfld.long 0x00 31. "IPAREN,Parallel mode Enabled for IP command" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
bitfld.long 0x00 24.--26. "ISEQNUM,Sequence Number for IP command: ISEQNUM+1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "ISEQID,Sequence Index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "IDATSZ,Flash Read/Program Data Size (in Bytes) for IP command"
group.long 0xB0++0x03
line.long 0x00 "IPCMD,IP Command Register"
bitfld.long 0x00 0. "TRG,Setting this bit will trigger an IP Command" "0,1"
group.long 0xB4++0x03
line.long 0x00 "DLPR,Data Learn Pattern Register"
hexmask.long 0x00 0.--31. 1. "DLP,Data Learning Pattern"
group.long 0xB8++0x03
line.long 0x00 "IPRXFCR,IP RX FIFO Control Register"
hexmask.long.byte 0x00 2.--8. 1. "RXWMRK,Watermark level is (RXWMRK+1)*64 Bits"
bitfld.long 0x00 1. "RXDMAEN,IP RX FIFO reading by DMA enabled" "0: IP RX FIFO would be read by processor,1: IP RX FIFO would be read by DMA"
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bitfld.long 0x00 0. "CLRIPRXF,Clear all valid data entries in IP RX FIFO" "0,1"
group.long 0xBC++0x03
line.long 0x00 "IPTXFCR,IP TX FIFO Control Register"
hexmask.long.byte 0x00 2.--8. 1. "TXWMRK,Watermark level is (TXWMRK+1)*64 Bits"
bitfld.long 0x00 1. "TXDMAEN,IP TX FIFO filling by DMA enabled" "0: IP TX FIFO would be filled by processor,1: IP TX FIFO would be filled by DMA"
newline
bitfld.long 0x00 0. "CLRIPTXF,Clear all valid data entries in IP TX FIFO" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DLLCRA,DLL Control Register 0"
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
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bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
newline
bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
group.long 0xC4++0x03
line.long 0x00 "DLLCRB,DLL Control Register 0"
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
newline
bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
newline
bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
rgroup.long 0xE0++0x03
line.long 0x00 "STS0,Status Register 0"
bitfld.long 0x00 8.--11. "DATALEARNPHASEB,Indicate the sampling clock phase selection on Port B after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DATALEARNPHASEA,Indicate the sampling clock phase selection on Port A after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2.--3. "ARBCMDSRC,This status field indicates the trigger source of current command sequence granted by arbitrator" "0: Triggered by AHB read command (triggered by..,1: Triggered by AHB write command (triggered by..,2: Triggered by IP command (triggered by setting..,3: Triggered by suspended command (resumed)"
bitfld.long 0x00 1. "ARBIDLE,This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface" "0,1"
newline
bitfld.long 0x00 0. "SEQIDLE,This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface" "0,1"
rgroup.long 0xE4++0x03
line.long 0x00 "STS1,Status Register 1"
bitfld.long 0x00 24.--27. "IPCMDERRCODE,Indicates the Error Code when IP command Error detected" "0: IPCMDERRCODE_0,?,2: IP command with JMP_ON_CS instruction used in..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,6: Flash access start address exceed the whole..,?,?,?,?,?,?,?,14: Sequence execution timeout,15: Flash boundary crossed"
bitfld.long 0x00 16.--19. "IPCMDERRID,Indicates the sequence Index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "AHBCMDERRCODE,Indicates the Error Code when AHB command Error detected" "0: AHBCMDERRCODE_0,?,2: AHB Write command with JMP_ON_CS instruction..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,?,?,?,?,?,?,?,?,14: Sequence execution timeout,?..."
bitfld.long 0x00 0.--3. "AHBCMDERRID,Indicates the sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xE8++0x03
line.long 0x00 "STS2,Status Register 2"
bitfld.long 0x00 24.--29. "BREFSEL,Flash B sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. "BSLVSEL,Flash B sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 17. "BREFLOCK,Flash B sample clock reference delay line locked" "0,1"
bitfld.long 0x00 16. "BSLVLOCK,Flash B sample clock slave delay line locked" "0,1"
newline
bitfld.long 0x00 8.--13. "AREFSEL,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 2.--7. "ASLVSEL,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "AREFLOCK,Flash A sample clock reference delay line locked" "0,1"
bitfld.long 0x00 0. "ASLVLOCK,Flash A sample clock slave delay line locked" "0,1"
rgroup.long 0xEC++0x03
line.long 0x00 "AHBSPNDSTS,AHB Suspend Status Register"
hexmask.long.word 0x00 16.--31. 1. "DATLFT,Left Data size for suspended command sequence (in byte)"
bitfld.long 0x00 1.--3. "BUFID,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "ACTIVE,Indicates if an AHB read prefetch command sequence has been suspended" "0,1"
rgroup.long 0xF0++0x03
line.long 0x00 "IPRXFSTS,IP RX FIFO Status Register"
hexmask.long.word 0x00 16.--31. 1. "RDCNTR,Total Read Data Counter: RDCNTR * 64 Bits"
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP RX FIFO"
rgroup.long 0xF4++0x03
line.long 0x00 "IPTXFSTS,IP TX FIFO Status Register"
hexmask.long.word 0x00 16.--31. 1. "WRCNTR,Total Write Data Counter: WRCNTR * 64 Bits"
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP TX FIFO"
repeat 32. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x100)++0x03
line.long 0x00 "RFDR[$1],IP RX FIFO Data Register x $1"
hexmask.long 0x00 0.--31. 1. "RXDATA,RX Data"
repeat.end
repeat 32. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x180)++0x03
line.long 0x00 "TFDR[$1],IP TX FIFO Data Register x $1"
hexmask.long 0x00 0.--31. 1. "TXDATA,TX Data"
repeat.end
repeat 64. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "LUT[$1],LUT x $1"
bitfld.long 0x00 26.--31. "OPCODE1,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "NUM_PADS1,NUM_PADS1" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "OPERAND1,OPERAND1"
bitfld.long 0x00 10.--15. "OPCODE0,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "NUM_PADS0,NUM_PADS0" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "OPERAND0,OPERAND0"
repeat.end
tree.end
tree.end
tree "FREQME (Frequency Measurement)"
base ad:0x4002F000
rgroup.long 0x00++0x03
line.long 0x00 "FREQMECTRL_R,Frequency Measurement (in Read mode)"
bitfld.long 0x00 31. "MEASURE_IN_PROGRESS,Measure in Progress" "0: Process complete,1: In Progress"
hexmask.long 0x00 0.--30. 1. "RESULT,Result"
wgroup.long 0x00++0x03
line.long 0x00 "FREQMECTRL_W,Frequency Measurement (in Write mode)"
bitfld.long 0x00 31. "MEASURE_IN_PROGRESS,Measure in Progress" "0: FORCE_TERMINATE,1: Initiates Measurement Cycle"
bitfld.long 0x00 9. "PULSE_POL,Pulse Polarity" "0: High Period,1: Low Period"
newline
bitfld.long 0x00 8. "PULSE_MODE,Pulse Width Measurement mode select" "0: Frequency Measurement Mode,1: Pulse Width Measurement mode"
bitfld.long 0x00 0.--4. "REF_SCALE,Reference Clock Scaling Factor" "0: Count cycle = 2 ^ 0 = 1,1: Count cycle = 2 ^ 1 = 2,2: Count cycle = 2 ^ 2 = 4,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Count cycle = 2 ^ 31 = 2 147 483 648"
tree.end
tree "GPIOHS (GPIO General Purpose I/O (GPIO))"
tree "GPIO"
base ad:0x40100000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "Port0_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "Port0_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x20)++0x00
line.byte 0x00 "Port1_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x30)++0x00
line.byte 0x00 "Port1_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x40)++0x00
line.byte 0x00 "Port2_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x50)++0x00
line.byte 0x00 "Port2_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x60)++0x00
line.byte 0x00 "Port3_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x70)++0x00
line.byte 0x00 "Port3_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x80)++0x00
line.byte 0x00 "Port4_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x90)++0x00
line.byte 0x00 "Port4_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0xA0)++0x00
line.byte 0x00 "Port5_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0xB0)++0x00
line.byte 0x00 "Port5_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0xC0)++0x00
line.byte 0x00 "Port6_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )
group.byte ($2+0xD0)++0x00
line.byte 0x00 "Port6_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1000)++0x03
line.long 0x00 "Port0_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1040)++0x03
line.long 0x00 "Port0_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1080)++0x03
line.long 0x00 "Port1_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x10C0)++0x03
line.long 0x00 "Port1_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1100)++0x03
line.long 0x00 "Port2_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1140)++0x03
line.long 0x00 "Port2_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1180)++0x03
line.long 0x00 "Port3_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x11C0)++0x03
line.long 0x00 "Port3_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1200)++0x03
line.long 0x00 "Port4_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1240)++0x03
line.long 0x00 "Port4_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1280)++0x03
line.long 0x00 "Port5_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x12C0)++0x03
line.long 0x00 "Port5_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1300)++0x03
line.long 0x00 "Port6_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x1340)++0x03
line.long 0x00 "Port6_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2000)++0x03
line.long 0x00 "DIR[$1],Port direction $1"
bitfld.long 0x00 31. "DIRP31,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 30. "DIRP30,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 29. "DIRP29,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 28. "DIRP28,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 27. "DIRP27,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 26. "DIRP26,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 25. "DIRP25,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 24. "DIRP24,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 23. "DIRP23,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 22. "DIRP22,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 21. "DIRP21,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 20. "DIRP20,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 19. "DIRP19,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 18. "DIRP18,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 17. "DIRP17,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 16. "DIRP16,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 15. "DIRP15,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 14. "DIRP14,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 13. "DIRP13,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 12. "DIRP12,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 11. "DIRP11,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 10. "DIRP10,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 9. "DIRP9,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 8. "DIRP8,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 7. "DIRP7,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 6. "DIRP6,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 5. "DIRP5,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 4. "DIRP4,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 3. "DIRP3,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 2. "DIRP2,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 1. "DIRP1,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 0. "DIRP0,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2080)++0x03
line.long 0x00 "MASK[$1],Port mask $1"
bitfld.long 0x00 31. "MASKP31,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 30. "MASKP30,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 29. "MASKP29,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 28. "MASKP28,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 27. "MASKP27,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 26. "MASKP26,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 25. "MASKP25,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 24. "MASKP24,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 23. "MASKP23,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 22. "MASKP22,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 21. "MASKP21,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 20. "MASKP20,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 19. "MASKP19,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 18. "MASKP18,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 17. "MASKP17,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 16. "MASKP16,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 15. "MASKP15,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 14. "MASKP14,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 13. "MASKP13,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 12. "MASKP12,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 11. "MASKP11,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 10. "MASKP10,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 9. "MASKP9,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 8. "MASKP8,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 7. "MASKP7,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 6. "MASKP6,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 5. "MASKP5,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 4. "MASKP4,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 3. "MASKP3,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 2. "MASKP2,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 1. "MASKP1,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 0. "MASKP0,Port Mask" "0: Read MPIN,1: Read MPIN"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2100)++0x03
line.long 0x00 "PIN[$1],Port pin $1"
bitfld.long 0x00 31. "PORT31,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 30. "PORT30,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 29. "PORT29,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 28. "PORT28,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 27. "PORT27,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 26. "PORT26,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 25. "PORT25,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 24. "PORT24,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 23. "PORT23,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 22. "PORT22,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 21. "PORT21,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 20. "PORT20,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 19. "PORT19,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 18. "PORT18,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 17. "PORT17,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 16. "PORT16,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 15. "PORT15,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 14. "PORT14,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 13. "PORT13,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 12. "PORT12,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 11. "PORT11,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 10. "PORT10,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 9. "PORT9,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 8. "PORT8,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 7. "PORT7,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 6. "PORT6,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 5. "PORT5,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 4. "PORT4,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 3. "PORT3,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 2. "PORT2,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 1. "PORT1,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 0. "PORT0,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2180)++0x03
line.long 0x00 "MPIN[$1],Masked Port Pin $1"
bitfld.long 0x00 31. "MPORTP31,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 30. "MPORTP30,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 29. "MPORTP29,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 28. "MPORTP28,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 27. "MPORTP27,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 26. "MPORTP26,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 25. "MPORTP25,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 24. "MPORTP24,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 23. "MPORTP23,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 22. "MPORTP22,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 21. "MPORTP21,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 20. "MPORTP20,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 19. "MPORTP19,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 18. "MPORTP18,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 17. "MPORTP17,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 16. "MPORTP16,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 15. "MPORTP15,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 14. "MPORTP14,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 13. "MPORTP13,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 12. "MPORTP12,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 11. "MPORTP11,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 10. "MPORTP10,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 9. "MPORTP9,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 8. "MPORTP8,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 7. "MPORTP7,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 6. "MPORTP6,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 5. "MPORTP5,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 4. "MPORTP4,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 3. "MPORTP3,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 2. "MPORTP2,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 1. "MPORTP1,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 0. "MPORTP0,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2200)++0x03
line.long 0x00 "SET[$1],Port set $1"
hexmask.long 0x00 0.--31. 1. "SETP,Read or set output bits"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2280)++0x03
line.long 0x00 "CLR[$1],Port clear $1"
eventfld.long 0x00 31. "CLRP31,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 30. "CLRP30,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 29. "CLRP29,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 28. "CLRP28,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 27. "CLRP27,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 26. "CLRP26,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 25. "CLRP25,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 24. "CLRP24,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 23. "CLRP23,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 22. "CLRP22,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 21. "CLRP21,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 20. "CLRP20,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 19. "CLRP19,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 18. "CLRP18,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 17. "CLRP17,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 16. "CLRP16,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 15. "CLRP15,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 14. "CLRP14,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 13. "CLRP13,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 12. "CLRP12,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 11. "CLRP11,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 10. "CLRP10,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 9. "CLRP9,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 8. "CLRP8,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 7. "CLRP7,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 6. "CLRP6,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 5. "CLRP5,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 4. "CLRP4,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 3. "CLRP3,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 2. "CLRP2,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 1. "CLRP1,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 0. "CLRP0,Clear output bits" "0: No operation,1: Clears output bit"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2300)++0x03
line.long 0x00 "NOT[$1],Port toggle $1"
bitfld.long 0x00 31. "NOTP31,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 30. "NOTP30,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 29. "NOTP29,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 28. "NOTP28,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 27. "NOTP27,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 26. "NOTP26,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 25. "NOTP25,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 24. "NOTP24,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 23. "NOTP23,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 22. "NOTP22,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 21. "NOTP21,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 20. "NOTP20,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 19. "NOTP19,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 18. "NOTP18,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 17. "NOTP17,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 16. "NOTP16,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 15. "NOTP15,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 14. "NOTP14,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 13. "NOTP13,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 12. "NOTP12,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 11. "NOTP11,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 10. "NOTP10,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 9. "NOTP9,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 8. "NOTP8,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 7. "NOTP7,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 6. "NOTP6,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 5. "NOTP5,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 4. "NOTP4,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 3. "NOTP3,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 2. "NOTP2,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 1. "NOTP1,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 0. "NOTP0,Toggle output bits" "0: No operation,1: Toggle output bit"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2380)++0x03
line.long 0x00 "DIRSET[$1],Port direction set $1"
bitfld.long 0x00 31. "DIRSETP31,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 30. "DIRSETP30,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 29. "DIRSETP29,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 28. "DIRSETP28,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 27. "DIRSETP27,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 26. "DIRSETP26,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 25. "DIRSETP25,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 24. "DIRSETP24,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 23. "DIRSETP23,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 22. "DIRSETP22,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 21. "DIRSETP21,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 20. "DIRSETP20,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 19. "DIRSETP19,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 18. "DIRSETP18,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 17. "DIRSETP17,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 16. "DIRSETP16,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 15. "DIRSETP15,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 14. "DIRSETP14,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 13. "DIRSETP13,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 12. "DIRSETP12,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 11. "DIRSETP11,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 10. "DIRSETP10,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 9. "DIRSETP9,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 8. "DIRSETP8,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 7. "DIRSETP7,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 6. "DIRSETP6,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 5. "DIRSETP5,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 4. "DIRSETP4,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 3. "DIRSETP3,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 2. "DIRSETP2,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 1. "DIRSETP1,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 0. "DIRSETP0,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2400)++0x03
line.long 0x00 "DIRCLR[$1],Port direction clear $1"
eventfld.long 0x00 31. "DIRCLRP31,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 30. "DIRCLRP30,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 29. "DIRCLRP29,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 28. "DIRCLRP28,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 27. "DIRCLRP27,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 26. "DIRCLRP26,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 25. "DIRCLRP25,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 24. "DIRCLRP24,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 23. "DIRCLRP23,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 22. "DIRCLRP22,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 21. "DIRCLRP21,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 20. "DIRCLRP20,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 19. "DIRCLRP19,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 18. "DIRCLRP18,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 17. "DIRCLRP17,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 16. "DIRCLRP16,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 15. "DIRCLRP15,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 14. "DIRCLRP14,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 13. "DIRCLRP13,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 12. "DIRCLRP12,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 11. "DIRCLRP11,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 10. "DIRCLRP10,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 9. "DIRCLRP9,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 8. "DIRCLRP8,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 7. "DIRCLRP7,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 6. "DIRCLRP6,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 5. "DIRCLRP5,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 4. "DIRCLRP4,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 3. "DIRCLRP3,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 2. "DIRCLRP2,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 1. "DIRCLRP1,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 0. "DIRCLRP0,Clear direction bits" "0: No operation,1: Clears direction bits"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2480)++0x03
line.long 0x00 "DIRNOT[$1],Port direction toggle $1"
hexmask.long 0x00 0.--28. 1. "DIRNOTP,Toggle direction bits"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2500)++0x03
line.long 0x00 "INTENA[$1],Interrupt A enable control $1"
bitfld.long 0x00 31. "INT_EN31,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 30. "INT_EN30,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 29. "INT_EN29,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 28. "INT_EN28,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 27. "INT_EN27,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 26. "INT_EN26,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 25. "INT_EN25,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 24. "INT_EN24,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 23. "INT_EN23,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 22. "INT_EN22,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 21. "INT_EN21,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 20. "INT_EN20,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 19. "INT_EN19,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 18. "INT_EN18,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 17. "INT_EN17,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 16. "INT_EN16,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 15. "INT_EN15,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 14. "INT_EN14,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 13. "INT_EN13,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 12. "INT_EN12,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 11. "INT_EN11,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 10. "INT_EN10,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 9. "INT_EN9,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 8. "INT_EN8,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 7. "INT_EN7,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 6. "INT_EN6,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 5. "INT_EN5,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 4. "INT_EN4,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 3. "INT_EN3,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 2. "INT_EN2,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 1. "INT_EN1,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 0. "INT_EN0,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2580)++0x03
line.long 0x00 "INTENB[$1],Interrupt B enable control $1"
bitfld.long 0x00 31. "INT_EN31,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 30. "INT_EN30,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 29. "INT_EN29,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 28. "INT_EN28,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 27. "INT_EN27,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 26. "INT_EN26,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 25. "INT_EN25,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 24. "INT_EN24,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 23. "INT_EN23,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 22. "INT_EN22,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 21. "INT_EN21,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 20. "INT_EN20,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 19. "INT_EN19,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 18. "INT_EN18,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 17. "INT_EN17,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 16. "INT_EN16,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 15. "INT_EN15,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 14. "INT_EN14,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 13. "INT_EN13,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 12. "INT_EN12,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 11. "INT_EN11,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 10. "INT_EN10,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 9. "INT_EN9,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 8. "INT_EN8,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 7. "INT_EN7,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 6. "INT_EN6,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 5. "INT_EN5,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 4. "INT_EN4,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 3. "INT_EN3,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 2. "INT_EN2,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 1. "INT_EN1,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 0. "INT_EN0,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2600)++0x03
line.long 0x00 "INTPOL[$1],Interupt polarity control $1"
bitfld.long 0x00 31. "POL_CTL31,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 30. "POL_CTL30,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 29. "POL_CTL29,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 28. "POL_CTL28,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 27. "POL_CTL27,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 26. "POL_CTL26,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 25. "POL_CTL25,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 24. "POL_CTL24,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 23. "POL_CTL23,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 22. "POL_CTL22,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 21. "POL_CTL21,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 20. "POL_CTL20,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 19. "POL_CTL19,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 18. "POL_CTL18,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 17. "POL_CTL17,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 16. "POL_CTL16,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 15. "POL_CTL15,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 14. "POL_CTL14,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 13. "POL_CTL13,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 12. "POL_CTL12,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 11. "POL_CTL11,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 10. "POL_CTL10,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 9. "POL_CTL9,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 8. "POL_CTL8,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 7. "POL_CTL7,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 6. "POL_CTL6,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 5. "POL_CTL5,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 4. "POL_CTL4,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 3. "POL_CTL3,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 2. "POL_CTL2,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 1. "POL_CTL1,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 0. "POL_CTL0,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2680)++0x03
line.long 0x00 "INTEDG[$1],Interrupt edge select $1"
bitfld.long 0x00 31. "EDGE31,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 30. "EDGE30,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 29. "EDGE29,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 28. "EDGE28,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 27. "EDGE27,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 26. "EDGE26,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 25. "EDGE25,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 24. "EDGE24,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 23. "EDGE23,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 22. "EDGE22,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 21. "EDGE21,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 20. "EDGE20,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 19. "EDGE19,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 18. "EDGE18,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 17. "EDGE17,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 16. "EDGE16,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 15. "EDGE15,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 14. "EDGE14,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 13. "EDGE13,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 12. "EDGE12,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 11. "EDGE11,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 10. "EDGE10,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 9. "EDGE9,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 8. "EDGE8,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 7. "EDGE7,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 6. "EDGE6,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 5. "EDGE5,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 4. "EDGE4,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 3. "EDGE3,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 2. "EDGE2,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 1. "EDGE1,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 0. "EDGE0,Edge or level mode select bits" "0: Level mode,1: Edge mode"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2700)++0x03
line.long 0x00 "INTSTATA[$1],Interrupt status for interrupt A $1"
hexmask.long 0x00 0.--31. 1. "STATUS,Interrupt status"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2780)++0x03
line.long 0x00 "INTSTATB[$1],Interrupt status for interrupt B $1"
hexmask.long 0x00 0.--31. 1. "STATUS,Interrupt status"
repeat.end
tree.end
tree "SECGPIO"
base ad:0x40204000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "Port0_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "Port0_B$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1000)++0x03
line.long 0x00 "Port0_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1040)++0x03
line.long 0x00 "Port0_W$1,Word pin registers for all port GPIO pins"
hexmask.long 0x00 0.--31. 1. "PWORD,PWORD"
repeat.end
wgroup.long 0x2000++0x03
line.long 0x00 "DIR0,Port direction"
bitfld.long 0x00 31. "DIRP31,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 30. "DIRP30,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 29. "DIRP29,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 28. "DIRP28,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 27. "DIRP27,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 26. "DIRP26,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 25. "DIRP25,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 24. "DIRP24,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 23. "DIRP23,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 22. "DIRP22,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 21. "DIRP21,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 20. "DIRP20,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 19. "DIRP19,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 18. "DIRP18,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 17. "DIRP17,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 16. "DIRP16,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 15. "DIRP15,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 14. "DIRP14,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 13. "DIRP13,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 12. "DIRP12,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 11. "DIRP11,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 10. "DIRP10,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 9. "DIRP9,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 8. "DIRP8,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 7. "DIRP7,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 6. "DIRP6,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 5. "DIRP5,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 4. "DIRP4,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 3. "DIRP3,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 2. "DIRP2,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
newline
bitfld.long 0x00 1. "DIRP1,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
bitfld.long 0x00 0. "DIRP0,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output"
group.long 0x2080++0x03
line.long 0x00 "MASK0,Port mask"
bitfld.long 0x00 31. "MASKP31,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 30. "MASKP30,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 29. "MASKP29,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 28. "MASKP28,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 27. "MASKP27,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 26. "MASKP26,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 25. "MASKP25,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 24. "MASKP24,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 23. "MASKP23,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 22. "MASKP22,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 21. "MASKP21,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 20. "MASKP20,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 19. "MASKP19,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 18. "MASKP18,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 17. "MASKP17,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 16. "MASKP16,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 15. "MASKP15,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 14. "MASKP14,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 13. "MASKP13,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 12. "MASKP12,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 11. "MASKP11,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 10. "MASKP10,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 9. "MASKP9,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 8. "MASKP8,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 7. "MASKP7,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 6. "MASKP6,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 5. "MASKP5,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 4. "MASKP4,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 3. "MASKP3,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 2. "MASKP2,Port Mask" "0: Read MPIN,1: Read MPIN"
newline
bitfld.long 0x00 1. "MASKP1,Port Mask" "0: Read MPIN,1: Read MPIN"
bitfld.long 0x00 0. "MASKP0,Port Mask" "0: Read MPIN,1: Read MPIN"
group.long 0x2100++0x03
line.long 0x00 "PIN0,Port pin"
bitfld.long 0x00 31. "PORT31,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 30. "PORT30,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 29. "PORT29,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 28. "PORT28,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 27. "PORT27,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 26. "PORT26,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 25. "PORT25,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 24. "PORT24,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 23. "PORT23,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 22. "PORT22,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 21. "PORT21,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 20. "PORT20,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 19. "PORT19,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 18. "PORT18,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 17. "PORT17,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 16. "PORT16,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 15. "PORT15,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 14. "PORT14,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 13. "PORT13,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 12. "PORT12,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 11. "PORT11,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 10. "PORT10,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 9. "PORT9,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 8. "PORT8,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 7. "PORT7,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 6. "PORT6,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 5. "PORT5,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 4. "PORT4,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 3. "PORT3,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 2. "PORT2,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
newline
bitfld.long 0x00 1. "PORT1,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
bitfld.long 0x00 0. "PORT0,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit"
group.long 0x2180++0x03
line.long 0x00 "MPIN0,Masked Port Pin"
bitfld.long 0x00 31. "MPORTP31,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 30. "MPORTP30,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 29. "MPORTP29,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 28. "MPORTP28,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 27. "MPORTP27,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 26. "MPORTP26,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 25. "MPORTP25,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 24. "MPORTP24,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 23. "MPORTP23,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 22. "MPORTP22,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 21. "MPORTP21,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 20. "MPORTP20,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 19. "MPORTP19,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 18. "MPORTP18,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 17. "MPORTP17,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 16. "MPORTP16,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 15. "MPORTP15,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 14. "MPORTP14,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 13. "MPORTP13,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 12. "MPORTP12,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 11. "MPORTP11,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 10. "MPORTP10,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 9. "MPORTP9,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 8. "MPORTP8,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 7. "MPORTP7,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 6. "MPORTP6,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 5. "MPORTP5,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 4. "MPORTP4,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 3. "MPORTP3,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 2. "MPORTP2,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
newline
bitfld.long 0x00 1. "MPORTP1,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
bitfld.long 0x00 0. "MPORTP0,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.."
group.long 0x2200++0x03
line.long 0x00 "SET0,Port set"
hexmask.long 0x00 0.--31. 1. "SETP,Read or set output bits"
group.long 0x2280++0x03
line.long 0x00 "CLR0,Port clear"
eventfld.long 0x00 31. "CLRP31,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 30. "CLRP30,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 29. "CLRP29,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 28. "CLRP28,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 27. "CLRP27,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 26. "CLRP26,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 25. "CLRP25,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 24. "CLRP24,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 23. "CLRP23,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 22. "CLRP22,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 21. "CLRP21,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 20. "CLRP20,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 19. "CLRP19,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 18. "CLRP18,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 17. "CLRP17,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 16. "CLRP16,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 15. "CLRP15,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 14. "CLRP14,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 13. "CLRP13,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 12. "CLRP12,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 11. "CLRP11,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 10. "CLRP10,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 9. "CLRP9,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 8. "CLRP8,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 7. "CLRP7,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 6. "CLRP6,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 5. "CLRP5,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 4. "CLRP4,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 3. "CLRP3,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 2. "CLRP2,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x00 1. "CLRP1,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x00 0. "CLRP0,Clear output bits" "0: No operation,1: Clears output bit"
wgroup.long 0x2300++0x03
line.long 0x00 "NOT0,Port toggle"
bitfld.long 0x00 31. "NOTP31,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 30. "NOTP30,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 29. "NOTP29,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 28. "NOTP28,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 27. "NOTP27,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 26. "NOTP26,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 25. "NOTP25,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 24. "NOTP24,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 23. "NOTP23,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 22. "NOTP22,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 21. "NOTP21,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 20. "NOTP20,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 19. "NOTP19,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 18. "NOTP18,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 17. "NOTP17,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 16. "NOTP16,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 15. "NOTP15,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 14. "NOTP14,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 13. "NOTP13,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 12. "NOTP12,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 11. "NOTP11,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 10. "NOTP10,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 9. "NOTP9,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 8. "NOTP8,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 7. "NOTP7,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 6. "NOTP6,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 5. "NOTP5,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 4. "NOTP4,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 3. "NOTP3,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 2. "NOTP2,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x00 1. "NOTP1,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x00 0. "NOTP0,Toggle output bits" "0: No operation,1: Toggle output bit"
wgroup.long 0x2380++0x03
line.long 0x00 "DIRSET0,Port direction set"
bitfld.long 0x00 31. "DIRSETP31,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 30. "DIRSETP30,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 29. "DIRSETP29,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 28. "DIRSETP28,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 27. "DIRSETP27,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 26. "DIRSETP26,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 25. "DIRSETP25,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 24. "DIRSETP24,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 23. "DIRSETP23,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 22. "DIRSETP22,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 21. "DIRSETP21,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 20. "DIRSETP20,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 19. "DIRSETP19,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 18. "DIRSETP18,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 17. "DIRSETP17,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 16. "DIRSETP16,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 15. "DIRSETP15,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 14. "DIRSETP14,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 13. "DIRSETP13,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 12. "DIRSETP12,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 11. "DIRSETP11,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 10. "DIRSETP10,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 9. "DIRSETP9,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 8. "DIRSETP8,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 7. "DIRSETP7,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 6. "DIRSETP6,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 5. "DIRSETP5,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 4. "DIRSETP4,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 3. "DIRSETP3,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 2. "DIRSETP2,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x00 1. "DIRSETP1,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x00 0. "DIRSETP0,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
group.long 0x2400++0x03
line.long 0x00 "DIRCLR0,Port direction clear"
eventfld.long 0x00 31. "DIRCLRP31,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 30. "DIRCLRP30,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 29. "DIRCLRP29,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 28. "DIRCLRP28,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 27. "DIRCLRP27,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 26. "DIRCLRP26,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 25. "DIRCLRP25,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 24. "DIRCLRP24,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 23. "DIRCLRP23,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 22. "DIRCLRP22,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 21. "DIRCLRP21,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 20. "DIRCLRP20,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 19. "DIRCLRP19,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 18. "DIRCLRP18,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 17. "DIRCLRP17,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 16. "DIRCLRP16,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 15. "DIRCLRP15,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 14. "DIRCLRP14,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 13. "DIRCLRP13,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 12. "DIRCLRP12,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 11. "DIRCLRP11,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 10. "DIRCLRP10,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 9. "DIRCLRP9,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 8. "DIRCLRP8,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 7. "DIRCLRP7,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 6. "DIRCLRP6,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 5. "DIRCLRP5,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 4. "DIRCLRP4,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 3. "DIRCLRP3,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 2. "DIRCLRP2,Clear direction bits" "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x00 1. "DIRCLRP1,Clear direction bits" "0: No operation,1: Clears direction bits"
eventfld.long 0x00 0. "DIRCLRP0,Clear direction bits" "0: No operation,1: Clears direction bits"
wgroup.long 0x2480++0x03
line.long 0x00 "DIRNOT0,Port direction toggle"
hexmask.long 0x00 0.--28. 1. "DIRNOTP,Toggle direction bits"
group.long 0x2500++0x03
line.long 0x00 "INTENA0,Interrupt A enable control"
bitfld.long 0x00 31. "INT_EN31,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 30. "INT_EN30,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 29. "INT_EN29,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 28. "INT_EN28,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 27. "INT_EN27,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 26. "INT_EN26,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 25. "INT_EN25,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 24. "INT_EN24,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 23. "INT_EN23,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 22. "INT_EN22,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 21. "INT_EN21,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 20. "INT_EN20,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 19. "INT_EN19,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 18. "INT_EN18,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 17. "INT_EN17,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 16. "INT_EN16,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 15. "INT_EN15,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 14. "INT_EN14,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 13. "INT_EN13,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 12. "INT_EN12,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 11. "INT_EN11,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 10. "INT_EN10,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 9. "INT_EN9,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 8. "INT_EN8,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 7. "INT_EN7,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 6. "INT_EN6,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 5. "INT_EN5,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 4. "INT_EN4,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 3. "INT_EN3,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 2. "INT_EN2,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x00 1. "INT_EN1,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x00 0. "INT_EN0,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
group.long 0x2580++0x03
line.long 0x00 "INTENB0,Interrupt B enable control"
bitfld.long 0x00 31. "INT_EN31,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 30. "INT_EN30,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 29. "INT_EN29,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 28. "INT_EN28,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 27. "INT_EN27,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 26. "INT_EN26,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 25. "INT_EN25,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 24. "INT_EN24,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 23. "INT_EN23,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 22. "INT_EN22,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 21. "INT_EN21,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 20. "INT_EN20,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 19. "INT_EN19,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 18. "INT_EN18,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 17. "INT_EN17,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 16. "INT_EN16,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 15. "INT_EN15,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 14. "INT_EN14,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 13. "INT_EN13,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 12. "INT_EN12,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 11. "INT_EN11,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 10. "INT_EN10,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 9. "INT_EN9,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 8. "INT_EN8,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 7. "INT_EN7,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 6. "INT_EN6,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 5. "INT_EN5,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 4. "INT_EN4,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 3. "INT_EN3,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 2. "INT_EN2,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x00 1. "INT_EN1,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x00 0. "INT_EN0,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
group.long 0x2600++0x03
line.long 0x00 "INTPOL0,Interupt polarity control"
bitfld.long 0x00 31. "POL_CTL31,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 30. "POL_CTL30,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 29. "POL_CTL29,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 28. "POL_CTL28,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 27. "POL_CTL27,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 26. "POL_CTL26,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 25. "POL_CTL25,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 24. "POL_CTL24,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 23. "POL_CTL23,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 22. "POL_CTL22,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 21. "POL_CTL21,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 20. "POL_CTL20,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 19. "POL_CTL19,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 18. "POL_CTL18,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 17. "POL_CTL17,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 16. "POL_CTL16,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 15. "POL_CTL15,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 14. "POL_CTL14,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 13. "POL_CTL13,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 12. "POL_CTL12,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 11. "POL_CTL11,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 10. "POL_CTL10,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 9. "POL_CTL9,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 8. "POL_CTL8,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 7. "POL_CTL7,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 6. "POL_CTL6,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 5. "POL_CTL5,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 4. "POL_CTL4,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 3. "POL_CTL3,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 2. "POL_CTL2,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x00 1. "POL_CTL1,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x00 0. "POL_CTL0,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
group.long 0x2680++0x03
line.long 0x00 "INTEDG0,Interrupt edge select"
bitfld.long 0x00 31. "EDGE31,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 30. "EDGE30,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 29. "EDGE29,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 28. "EDGE28,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 27. "EDGE27,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 26. "EDGE26,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 25. "EDGE25,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 24. "EDGE24,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 23. "EDGE23,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 22. "EDGE22,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 21. "EDGE21,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 20. "EDGE20,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 19. "EDGE19,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 18. "EDGE18,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 17. "EDGE17,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 16. "EDGE16,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 15. "EDGE15,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 14. "EDGE14,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 13. "EDGE13,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 12. "EDGE12,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 11. "EDGE11,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 10. "EDGE10,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 9. "EDGE9,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 8. "EDGE8,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 7. "EDGE7,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 6. "EDGE6,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 5. "EDGE5,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 4. "EDGE4,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 3. "EDGE3,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 2. "EDGE2,Edge or level mode select bits" "0: Level mode,1: Edge mode"
newline
bitfld.long 0x00 1. "EDGE1,Edge or level mode select bits" "0: Level mode,1: Edge mode"
bitfld.long 0x00 0. "EDGE0,Edge or level mode select bits" "0: Level mode,1: Edge mode"
group.long 0x2700++0x03
line.long 0x00 "INTSTATA0,Interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. "STATUS,Interrupt status"
group.long 0x2780++0x03
line.long 0x00 "INTSTATB0,Interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. "STATUS,Interrupt status"
tree.end
tree.end
tree "HASHCRYPT"
base ad:0x40208000
group.long 0x00++0x03
line.long 0x00 "CTRL,Control"
bitfld.long 0x00 12. "HASHSWPB,Hash Swap Bytes" "0,1"
bitfld.long 0x00 9. "DMA_O,DMA to Drain the Digest/Output" "0: DMA is not used,1: DMA will drain the data"
newline
bitfld.long 0x00 8. "DMA_I,DMA to Fill INDATA" "0: DMA is not used,1: DMA will push in the data"
bitfld.long 0x00 5. "RELOAD,Reload" "0: DISABLED,1: Allows the SHA RELOAD registers to be used"
newline
bitfld.long 0x00 4. "NEW_HASH,New Hash Operation" "?,1: Starts a new Hash/Crypto and initializes the.."
bitfld.long 0x00 0.--2. "MODE,Operational Mode" "0: DISABLED,1: SHA1 is enabled,2: SHA2-256 is enabled,?,4: AES is enabled (see also CRYPTCFG register..,5: ICB-AES is enabled (see also CRYPTCFG..,?..."
group.long 0x04++0x03
line.long 0x00 "STATUS,Status"
rbitfld.long 0x00 16.--21. "ICBIDX,ICB Index Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 5. "NEEDIV,Need IV/Nonce" "0: No IV/Nonce is needed either because written..,1: IV/Nonce is needed and INDATA/ALIAS will be.."
newline
rbitfld.long 0x00 4. "NEEDKEY,Need Key to be Written" "0: No Key is needed and writes will not be..,1: Key is needed and INDATA/ALIAS will be.."
eventfld.long 0x00 2. "ERROR,Error" "0: No error,1: An error occurred since last cleared (written.."
newline
rbitfld.long 0x00 1. "DIGEST,Digest/Outdata" "0: Digest is not ready,1: Digest is ready"
rbitfld.long 0x00 0. "WAITING,Waiting for Data" "0: Not waiting for data - may be disabled or may..,1: Waiting for data to be written (16 words)"
group.long 0x08++0x03
line.long 0x00 "INTENSET,Interrupt Enable"
bitfld.long 0x00 2. "ERROR,Interrupt on Error" "0: Interrupt not enabled on Error,1: Interrupt is enabled on Error (until cleared)"
bitfld.long 0x00 1. "DIGEST,Digest/Outdata" "0: Interrupt not enabled when Digest is ready,1: Interrupt is enabled when Digest is ready"
newline
bitfld.long 0x00 0. "WAITING,Interrupt When Waiting for Data Input" "0: Interrupt not enabled when waiting,1: Interrupt is enabled when waiting"
group.long 0x0C++0x03
line.long 0x00 "INTENCLR,Interrupt Clear"
eventfld.long 0x00 2. "ERROR,Error" "0,1"
eventfld.long 0x00 1. "DIGEST,Digest" "0,1"
newline
eventfld.long 0x00 0. "WAITING,Waiting" "0,1"
group.long 0x10++0x03
line.long 0x00 "MEMCTRL,Memory Control"
hexmask.long.word 0x00 16.--26. 1. "COUNT,Count"
bitfld.long 0x00 0. "MASTER,Master" "0: Mastering is not used and the normal DMA or..,1: Mastering is enabled and DMA and INDATA.."
group.long 0x14++0x03
line.long 0x00 "MEMADDR,Memory Address"
hexmask.long 0x00 0.--31. 1. "BASE,Base"
wgroup.long 0x20++0x03
line.long 0x00 "INDATA,Input Data"
hexmask.long 0x00 0.--31. 1. "DATA,Data"
repeat 7. (increment 0 1) (increment 0 0x4)
wgroup.long ($2+0x24)++0x03
line.long 0x00 "ALIAS[$1],Alias $1"
hexmask.long 0x00 0.--31. 1. "DATA,Data"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x40)++0x03
line.long 0x00 "DIGEST[$1],Digest0 n/Output Data0 n $1"
hexmask.long 0x00 0.--31. 1. "DIGEST,Digest"
repeat.end
group.long 0x80++0x03
line.long 0x00 "CRYPTCFG,Cryptographic Configuration"
bitfld.long 0x00 22.--23. "ICBSTRM,ICB Stream Size" "0: BLOCKS_8,1: BLOCKS_16,2: BLOCKS_32,3: BLOCKS_64"
bitfld.long 0x00 20.--21. "ICBSZ,ICB Size" "0: 32 bits of the IV/ctr are used (from 127:96),1: 64 bits of the IV/ctr are used (from 127:64),2: 96 bits of the IV/ctr are used (from 127:32),3: All 128 bits of the IV/ctr are used"
newline
bitfld.long 0x00 16. "STREAMLAST,Stream Last" "0,1"
bitfld.long 0x00 10.--12. "AESCTRPOS,AES CTR Position" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--9. "AESKEYSZ,AES Key Size" "0: 128 bit key,1: 192 bit key,2: 256 bit key,?..."
bitfld.long 0x00 7. "AESSECRET,AES Secret" "0: User key provided in normal way,1: Secret key provided in hidden way by HW"
newline
bitfld.long 0x00 6. "AESDECRYPT,AES Decrypt" "0: Encrypt,1: DECRYPT"
bitfld.long 0x00 4.--5. "AESMODE,AES Cipher Mode" "0: ECB - used as is,1: CBC mode (see details on IV/nonce),2: CTR mode (see details on IV/nonce),?..."
newline
bitfld.long 0x00 3. "MSW1ST,Most Significant Word 1st Load" "0,1"
bitfld.long 0x00 2. "SWAPDAT,Swap Data/IV Inputs" "0,1"
newline
bitfld.long 0x00 1. "SWAPKEY,Swap Key" "0,1"
bitfld.long 0x00 0. "MSW1ST_OUT,Most Significant Word 1st Out" "0,1"
rgroup.long 0x84++0x03
line.long 0x00 "CONFIG,Configuration"
bitfld.long 0x00 11. "ICB,ICB" "0,1"
bitfld.long 0x00 8. "SECRET,Reads 1 if AES Secret key is available" "0,1"
newline
bitfld.long 0x00 7. "AESKEY,Reads 1 if AES 192 and 256 also included" "0,1"
bitfld.long 0x00 6. "AES,Reads 1 if AES 128 is included" "0,1"
newline
bitfld.long 0x00 3. "AHB,Reads 1 if AHB Master is enabled" "0,1"
bitfld.long 0x00 1. "DMA,Reads 1 if DMA is connected" "0,1"
newline
bitfld.long 0x00 0. "DUAL,Reads 1 if 2 x 512 bit buffers 0 if only 1 x 512 bit" "0,1"
group.long 0x8C++0x03
line.long 0x00 "LOCK,Lock"
hexmask.long.word 0x00 4.--15. 1. "PATTERN,Must write 0xA75 to change lock state"
bitfld.long 0x00 0.--1. "SECLOCK,Secure Lock" "0: Unlocks so block is open to all,1: Locks to the current security level,?..."
repeat 4. (increment 0 1) (increment 0 0x4)
wgroup.long ($2+0x90)++0x03
line.long 0x00 "MASK[$1],Mask $1"
hexmask.long 0x00 0.--31. 1. "MASK,A random word"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x4)
group.long ($2+0xA0)++0x03
line.long 0x00 "RELOAD[$1],DIGEST/OUTDATA Reload $1"
hexmask.long 0x00 0.--31. 1. "DIGEST,SHA Digest word to reload"
repeat.end
wgroup.long 0xD0++0x03
line.long 0x00 "PRNG_SEED,PRNG Seed"
hexmask.long 0x00 0.--31. 1. "PRNG_SEED,SHA Digest word to reload"
wgroup.long 0xD8++0x03
line.long 0x00 "PRNG_OUT,PRNG Output"
hexmask.long 0x00 0.--31. 1. "PRNG_OUT_R,SHA Digest word to reload"
tree.end
tree "I2C (Inter-Integrated Circuit)"
repeat 15. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 15.) (list ad:0x40106000 ad:0x40107000 ad:0x40108000 ad:0x40109000 ad:0x40122000 ad:0x40123000 ad:0x40124000 ad:0x40125000 ad:0x40209000 ad:0x4020A000 ad:0x4020B000 ad:0x4020C000 ad:0x4020D000 ad:0x4020E000 ad:0x40127000)
tree "I2C$1"
base $2
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration Register"
bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable"
bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled"
group.long 0x804++0x03
line.long 0x00 "STAT,Status Register"
bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
newline
bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle"
rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active"
newline
bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun"
rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting"
newline
bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected"
rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected"
newline
rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching"
newline
rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..."
rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending"
newline
bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.."
bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss"
newline
rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..."
rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set Register"
bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out Register"
hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value"
bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock Divider Register"
hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value"
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status Register"
bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE"
bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE"
newline
bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE"
bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE"
newline
bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE"
bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE"
newline
bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE"
bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE"
newline
bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE"
bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE"
newline
bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master Control Register"
bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable"
bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop"
newline
bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start"
bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master Timing Register"
bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks"
bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Master Data Register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave Control Register"
bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.."
bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK"
newline
bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Slave Data Register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register"
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x848)++0x03
line.long 0x00 "SLVADR$1,Slave Address Register"
bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode"
hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address"
newline
bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored"
repeat.end
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register"
hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0"
bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor Receiver Data Register"
bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged"
bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
newline
bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected"
hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral Identification Register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture"
tree.end
repeat.end
tree.end
tree "I2S (Inter-Integrated Sound Bus Controller)"
repeat 14. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.) (list ad:0x40106000 ad:0x40107000 ad:0x40108000 ad:0x40109000 ad:0x40122000 ad:0x40123000 ad:0x40124000 ad:0x40125000 ad:0x40209000 ad:0x4020A000 ad:0x4020B000 ad:0x4020C000 ad:0x4020D000 ad:0x4020E000)
tree "I2S$1"
base $2
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair"
bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length"
bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: Inverted"
newline
bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE"
bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM"
newline
bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL"
bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED"
newline
bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW"
bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA"
newline
bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode"
bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs"
newline
bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE"
bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair"
hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position"
hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length"
group.long 0xC08++0x03
line.long 0x00 "STAT,Status Register for the Primary Channel Pair"
rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED"
rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
newline
eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR"
rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock Divider"
hexmask.long.word 0x00 0.--11. 1. "DIV,Divider"
group.long 0xC20++0x03
line.long 0x00 "PCFG11,Configuration Register 1 for Channel Pair 1"
bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL"
bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED"
group.long 0xC24++0x03
line.long 0x00 "PCFG21,Configuration Register 2 for Channel Pair 1"
hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC28++0x03
line.long 0x00 "PSTAT1,Status Register for Channel Pair 1"
bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused"
bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
newline
bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR"
bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy"
group.long 0xC40++0x03
line.long 0x00 "PCFG12,Configuration Register 1 for Channel Pair 2"
bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL"
bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED"
group.long 0xC44++0x03
line.long 0x00 "PCFG22,Configuration Register 2 for Channel Pair 2"
hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC48++0x03
line.long 0x00 "PSTAT2,Status Register for Channel Pair 2"
bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused"
bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
newline
bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR"
bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy"
group.long 0xC60++0x03
line.long 0x00 "PCFG13,Configuration Register 1 for Channel Pair 3"
bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL"
bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED"
group.long 0xC64++0x03
line.long 0x00 "PCFG23,Configuration Register 2 for Channel Pair 3"
hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC68++0x03
line.long 0x00 "PSTAT3,Status Register for Channel Pair 3"
bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused"
bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
newline
bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR"
bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO Configuration and Enable"
bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop"
bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1"
newline
bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1"
bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.."
newline
bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED"
rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits"
newline
bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16"
bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO"
newline
bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO Status"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..."
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..."
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.."
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.."
newline
rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt"
eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured"
newline
eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO Trigger Settings"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.."
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read"
bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read"
bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared"
bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared"
newline
bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared"
bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING"
bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING"
bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO Write Data"
hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits"
hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO Read Data"
hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits"
hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop"
hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO Size Register"
bitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module Identification"
hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture"
tree.end
repeat.end
tree.end
tree "I3C"
repeat 2. (list 0. 1.) (list ad:0x40036000 ad:0x40037000)
tree "I3C$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MCONFIG,Master Configuration Register"
bitfld.long 0x00 28.--31. "I2CBAUD,I2C baud rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 25.--27. "SKEW,Skew" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24. "ODHPP,Open drain high push-pull" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "ODBAUD,Open drain baud rate"
newline
bitfld.long 0x00 12.--15. "PPLOW,Push-Pull low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PPBAUD,Push-pull baud rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "ODSTOP,Open drain stop" "0,1"
bitfld.long 0x00 4.--5. "HKEEP,High-Keeper" "0: NONE,1: WIRED_IN,2: PASSIVE_SDA,3: PASSIVE_ON_SDA_SCL"
newline
bitfld.long 0x00 3. "DISTO,Disable Timeout" "0,1"
bitfld.long 0x00 0.--1. "MSTENA,Master enable" "0: MASTER_OFF,1: MASTER_ON,2: MASTER_CAPABLE,?..."
group.long 0x04++0x03
line.long 0x00 "SCONFIG,Slave Configuration Register"
hexmask.long.byte 0x00 25.--31. 1. "SADDR,Static address"
hexmask.long.byte 0x00 16.--23. 1. "BAMATCH,Bus available match"
newline
bitfld.long 0x00 9. "OFFLINE,Offline" "0,1"
bitfld.long 0x00 8. "IDRAND,ID random" "0,1"
newline
bitfld.long 0x00 4. "DDROK,Double Data Rate OK" "0,1"
bitfld.long 0x00 3. "S0IGNORE,S0/S1 errors ignore" "0,1"
newline
bitfld.long 0x00 2. "MATCHSS,Match START or STOP" "0,1"
bitfld.long 0x00 1. "NACK,Not acknowledge" "0,1"
newline
bitfld.long 0x00 0. "SLVENA,Slave enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "SSTATUS,Slave Status Register"
rbitfld.long 0x00 30.--31. "TIMECTRL,Time control" "0: NO_TIME_CONTROL,?,2: ASYNC_MODE,?..."
rbitfld.long 0x00 28.--29. "ACTSTATE,Activity state from Common Command Codes (CCC)" "0: NO_LATENCY,1: LATENCY_1MS,2: LATENCY_100MS,3: LATENCY_10S"
newline
rbitfld.long 0x00 27. "HJDIS,Hot-Join is disabled" "0,1"
rbitfld.long 0x00 25. "MRDIS,Master requests are disabled" "0,1"
newline
rbitfld.long 0x00 24. "IBIDIS,In-Band Interrupts are disabled" "0,1"
rbitfld.long 0x00 20.--21. "EVDET,Event details" "0: NONE,1: NO_REQUEST,2: NACKED,3: ACKED"
newline
bitfld.long 0x00 18. "EVENT,Event" "0,1"
bitfld.long 0x00 17. "CHANDLED,Common-Command-Code handled" "0,1"
newline
bitfld.long 0x00 16. "HDRMATCH,High Data Rate command match" "0,1"
rbitfld.long 0x00 15. "ERRWARN,Error warning" "0,1"
newline
bitfld.long 0x00 14. "CCC,Common Command Code" "0,1"
bitfld.long 0x00 13. "DACHG,DACHG" "0,1"
newline
rbitfld.long 0x00 12. "TXNOTFULL,Transmit buffer is not full" "0,1"
rbitfld.long 0x00 11. "RX_PEND,Received message pending" "0,1"
newline
bitfld.long 0x00 10. "STOP,Stop" "0,1"
bitfld.long 0x00 9. "MATCHED,Matched" "0,1"
newline
bitfld.long 0x00 8. "START,Start" "0,1"
rbitfld.long 0x00 6. "STHDR,Status High Data Rate" "0,1"
newline
rbitfld.long 0x00 5. "STDAA,Status Dynamic Address Assignment" "0,1"
rbitfld.long 0x00 4. "STREQWR,Status request" "0,1"
newline
rbitfld.long 0x00 3. "STREQRD,Status required" "0,1"
rbitfld.long 0x00 2. "STCCCH,Status Common Command Code Handler" "0,1"
newline
rbitfld.long 0x00 1. "STMSG,Status message" "0,1"
rbitfld.long 0x00 0. "STNOTSTOP,Status not stop" "0,1"
group.long 0x0C++0x03
line.long 0x00 "SCTRL,Slave Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VENDINFO,Vendor information"
bitfld.long 0x00 20.--21. "ACTSTATE,Activity state (of slave)" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "PENDINT,Pending interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "IBIDATA,In-Band Interrupt data"
newline
bitfld.long 0x00 0.--1. "EVENT,EVENT" "0: NORMAL_MODE,1: IBI,2: MASTER_REQUEST,3: HOT_JOIN_REQUEST"
group.long 0x10++0x03
line.long 0x00 "SINTSET,Slave Interrupt Set Register"
bitfld.long 0x00 18. "EVENT,Event interrupt enable" "0,1"
bitfld.long 0x00 17. "CHANDLED,Common Command Code (CCC) (that was handled by I3C module) interrupt enable" "0,1"
newline
bitfld.long 0x00 16. "DDRMATCHED,Double Data Rate (DDR) interrupt enable" "0,1"
bitfld.long 0x00 15. "ERRWARN,Error/warning interrupt enable" "0,1"
newline
bitfld.long 0x00 14. "CCC,Common Command Code (CCC) (that was not handled by I3C module) interrupt enable" "0,1"
bitfld.long 0x00 13. "DACHG,Dynamic address change interrupt enable" "0,1"
newline
bitfld.long 0x00 12. "TXSEND,Transmit interrupt enable" "0,1"
bitfld.long 0x00 11. "RXPEND,Receive interrupt enable" "0,1"
newline
bitfld.long 0x00 10. "STOP,Stop interrupt enable" "0,1"
bitfld.long 0x00 9. "MATCHED,Match interrupt enable" "0,1"
newline
bitfld.long 0x00 8. "START,Start interrupt enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "SINTCLR,Slave Interrupt Clear Register"
eventfld.long 0x00 18. "EVENT,EVENT interrupt enable clear" "0,1"
eventfld.long 0x00 17. "CHANDLED,CHANDLED interrupt enable clear" "0,1"
newline
eventfld.long 0x00 16. "DDRMATCHED,DDRMATCHED interrupt enable clear" "0,1"
eventfld.long 0x00 15. "ERRWARN,ERRWARN interrupt enable clear" "0,1"
newline
eventfld.long 0x00 14. "CCC,CCC interrupt enable clear" "0,1"
eventfld.long 0x00 13. "DACHG,DACHG interrupt enable clear" "0,1"
newline
eventfld.long 0x00 12. "TXSEND,TXSEND interrupt enable clear" "0,1"
eventfld.long 0x00 11. "RXPEND,RXPEND interrupt enable clear" "0,1"
newline
eventfld.long 0x00 10. "STOP,STOP interrupt enable clear" "0,1"
eventfld.long 0x00 9. "MATCHED,MATCHED interrupt enable clear" "0,1"
newline
eventfld.long 0x00 8. "START,START interrupt enable clear" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "SINTMASKED,Slave Interrupt Mask Register"
bitfld.long 0x00 18. "EVENT,EVENT interrupt mask" "0,1"
bitfld.long 0x00 17. "CHANDLED,CHANDLED interrupt mask" "0,1"
newline
bitfld.long 0x00 16. "DDRMATCHED,DDRMATCHED interrupt mask" "0,1"
bitfld.long 0x00 15. "ERRWARN,ERRWARN interrupt mask" "0,1"
newline
bitfld.long 0x00 14. "CCC,CCC interrupt mask" "0,1"
bitfld.long 0x00 13. "DACHG,DACHG interrupt mask" "0,1"
newline
bitfld.long 0x00 12. "TXSEND,TXSEND interrupt mask" "0,1"
bitfld.long 0x00 11. "RXPEND,RXPEND interrupt mask" "0,1"
newline
bitfld.long 0x00 10. "STOP,STOP interrupt mask" "0,1"
bitfld.long 0x00 9. "MATCHED,MATCHED interrupt mask" "0,1"
newline
bitfld.long 0x00 8. "START,START interrupt mask" "0,1"
group.long 0x1C++0x03
line.long 0x00 "SERRWARN,Slave Errors and Warnings Register"
bitfld.long 0x00 17. "OWRITE,Over-write error" "0,1"
bitfld.long 0x00 16. "OREAD,Over-read error" "0,1"
newline
bitfld.long 0x00 11. "S0S1,S0 or S1 error" "0,1"
bitfld.long 0x00 10. "HCRC,HDR-DDR CRC error" "0,1"
newline
bitfld.long 0x00 9. "HPAR,HDR parity error" "0,1"
bitfld.long 0x00 8. "SPAR,SDR parity error" "0,1"
newline
bitfld.long 0x00 4. "INVSTART,Invalid start error" "0,1"
bitfld.long 0x00 3. "TERM,Terminated error" "0,1"
newline
bitfld.long 0x00 2. "URUNNACK,Underrun and Not Acknowledged (NACKed) error" "0,1"
bitfld.long 0x00 1. "URUN,Underrun error" "0,1"
newline
bitfld.long 0x00 0. "ORUN,Overrun error" "0,1"
group.long 0x20++0x03
line.long 0x00 "SDMACTRL,Slave DMA Control Register"
bitfld.long 0x00 4.--5. "DMAWIDTH,Width of DMA operations" "0: BYTE,1: BYTE_AGAIN,2: HALF_WORD,?..."
bitfld.long 0x00 2.--3. "DMATB,DMA Write (To-bus) trigger" "0: NOT_USED,1: ENABLE_ONE_FRAME,2: ENABLE,?..."
newline
bitfld.long 0x00 0.--1. "DMAFB,DMA Read (From-bus) trigger" "0: DMA not used,1: DMA is enabled for 1 frame,2: DMA enable,?..."
group.long 0x2C++0x03
line.long 0x00 "SDATACTRL,Slave Data Control Register"
rbitfld.long 0x00 31. "RXEMPTY,RX is empty" "0: RX is not empty,1: RX is empty"
rbitfld.long 0x00 30. "TXFULL,TX is full" "0: TX is not full,1: TX is full"
newline
rbitfld.long 0x00 24.--28. "RXCOUNT,Count of bytes in RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 16.--20. "TXCOUNT,Count of bytes in TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--7. "RXTRIG,Trigger level for RX FIFO fullness" "0: Trigger on not empty,1: Trigger on or more full,2: Trigger on .5 or more full,3: Trigger on 3/4 or more full"
bitfld.long 0x00 4.--5. "TXTRIG,Trigger level for TX FIFO emptiness" "0: Trigger on empty,1: Trigger on full or less,2: Trigger on .5 full or less,3: Trigger on 1 less than full or less (Default)"
newline
bitfld.long 0x00 3. "UNLOCK,Unlock" "0,1"
bitfld.long 0x00 1. "FLUSHFB,Flushes the from-bus buffer/FIFO" "0,1"
newline
bitfld.long 0x00 0. "FLUSHTB,Flush the to-bus buffer/FIFO" "0,1"
wgroup.long 0x30++0x03
line.long 0x00 "SWDATAB,Slave Write Data Byte Register"
bitfld.long 0x00 16. "END_ALSO,End also" "0,1"
bitfld.long 0x00 8. "END,End" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DATA,The data byte to send to the master"
wgroup.long 0x34++0x03
line.long 0x00 "SWDATABE,Slave Write Data Byte End"
hexmask.long.byte 0x00 0.--7. 1. "DATA,The data byte to send to the master"
wgroup.long 0x38++0x03
line.long 0x00 "SWDATAH,Slave Write Data Half-word Register"
bitfld.long 0x00 16. "END,End of message" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "DATA1,The 2nd byte to send to the master"
newline
hexmask.long.byte 0x00 0.--7. 1. "DATA0,The 1st byte to send to the master"
wgroup.long 0x3C++0x03
line.long 0x00 "SWDATAHE,Slave Write Data Half-word End Register"
hexmask.long.byte 0x00 8.--15. 1. "DATA1,The 2nd byte to send to the master"
hexmask.long.byte 0x00 0.--7. 1. "DATA0,The 1st byte to send to the master"
rgroup.long 0x40++0x03
line.long 0x00 "SRDATAB,Slave Read Data Byte Register"
hexmask.long.byte 0x00 0.--7. 1. "DATA0,Byte read from the master"
rgroup.long 0x48++0x03
line.long 0x00 "SRDATAH,Slave Read Data Half-word Register"
hexmask.long.byte 0x00 8.--15. 1. "MSB,The 2nd byte read from the slave"
hexmask.long.byte 0x00 0.--7. 1. "LSB,The 1st byte read from the slave"
rgroup.long 0x60++0x03
line.long 0x00 "SCAPABILITIES,Slave Capabilities Register"
bitfld.long 0x00 31. "DMA,DMA" "0: DMA is not supported,1: DMA is supported"
bitfld.long 0x00 30. "INT,INT" "0: Interrupts are not supported,1: Interrupts are supported"
newline
bitfld.long 0x00 28.--29. "FIFORX,FIFO receive" "0: FIFO_2BYTE,1: FIFO_4BYTE,2: FIFO_8BYTE,3: FIFO_16BYTE"
bitfld.long 0x00 26.--27. "FIFOTX,FIFO transmit" "0: FIFO_2BYTE,1: FIFO_4BYTE,2: FIFO_8BYTE,3: FIFO_16BYTE"
newline
bitfld.long 0x00 23.--25. "EXTFIFO,External FIFO" "?,1: STD_EXT_FIFO,?..."
bitfld.long 0x00 21. "TIMECTRL,Time control" "0: NO_TIME_CONTROL_TYPE,1: ATLEAST1_TIME_CONTROL"
newline
bitfld.long 0x00 16.--20. "IBI_MR_HJ,In-Band Interrupts Master Requests Hot Join events" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 12.--15. "CCCHANDLE,Common Command Codes (CCC) handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. "SADDR,Static address" "0: NO_STATIC,1: STATIC,2: HW_CONTROL,3: CONFIG"
bitfld.long 0x00 9. "MASTER,Master" "0: MASTERNOTSUPPORTED,1: MASTERSUPPORTED"
newline
bitfld.long 0x00 6.--8. "HDRSUPP,HDR support" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2.--5. "IDREG,ID register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--1. "IDENA,ID 48b handler" "0: APPLICATION,1: HW,2: HW_BUT,3: PARTNO"
group.long 0x64++0x03
line.long 0x00 "SDYNADDR,Slave Dynamic Address Register"
hexmask.long.word 0x00 16.--31. 1. "KEY,Key"
bitfld.long 0x00 12. "MAPSA,Map a Static Address" "0,1"
newline
bitfld.long 0x00 8.--11. "MAPIDX,Mapped Dynamic Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 1.--7. 1. "DADDR,Dynamic address"
newline
bitfld.long 0x00 0. "DAVALID,DAVALID" "0: DANOTASSIGNED,1: DAASSIGNED"
group.long 0x68++0x03
line.long 0x00 "SMAXLIMITS,Slave Maximum Limits Register"
hexmask.long.word 0x00 16.--27. 1. "MAXWR,Maximum write length"
hexmask.long.word 0x00 0.--11. 1. "MAXRD,Maximum read length"
group.long 0x6C++0x03
line.long 0x00 "SIDPARTNO,Slave ID Part Number Register"
hexmask.long 0x00 0.--31. 1. "PARTNO,Part number"
group.long 0x70++0x03
line.long 0x00 "SIDEXT,Slave ID Extension Register"
hexmask.long.byte 0x00 16.--23. 1. "BCR,Bus Characteristics Register"
hexmask.long.byte 0x00 8.--15. 1. "DCR,Device Characteristic Register"
group.long 0x74++0x03
line.long 0x00 "SVENDORID,Slave Vendor ID Register"
hexmask.long.word 0x00 0.--14. 1. "VID,Vendor ID"
group.long 0x78++0x03
line.long 0x00 "STCCLOCK,Slave Time Control Clock Register"
hexmask.long.byte 0x00 8.--15. 1. "FREQ,Clock frequency"
hexmask.long.byte 0x00 0.--7. 1. "ACCURACY,Clock accuracy"
rgroup.long 0x7C++0x03
line.long 0x00 "SMSGMAPADDR,Slave Message-Mapped Address Register"
bitfld.long 0x00 16.--19. "MAPLASTM2,Previous match index 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "MAPLASTM1,Previous match index 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "MAPLAST,Matched address index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x84++0x03
line.long 0x00 "MCTRL,Master Main Control Register"
hexmask.long.byte 0x00 16.--23. 1. "RDTERM,Read terminate"
hexmask.long.byte 0x00 9.--15. 1. "ADDR,ADDR"
newline
bitfld.long 0x00 8. "DIR,DIR" "0: DIR,1: DIRREAD"
bitfld.long 0x00 6.--7. "IBIRESP,In-Band Interrupt (IBI) response" "0: ACK,1: NACK,2: ACK_WITH_MANDATORY,3: MANUAL"
newline
bitfld.long 0x00 4.--5. "TYPE,Bus type with START" "0: I3C,1: I2C,2: DDR,3: For ForcedExit this is forced IBHR"
bitfld.long 0x00 0.--2. "REQUEST,Request" "0: NONE,1: EMITSTARTADDR,2: EMITSTOP,3: IBIACKNACK,4: PROCESSDAA,?,6: FORCEEXIT and IBHR,7: AUTOIBI"
group.long 0x88++0x03
line.long 0x00 "MSTATUS,Master Status Register"
hexmask.long.byte 0x00 24.--30. 1. "IBIADDR,IBI address"
bitfld.long 0x00 19. "NOWMASTER,Now master (now this module is a master)" "0,1"
newline
rbitfld.long 0x00 15. "ERRWARN,Error or warning" "0,1"
bitfld.long 0x00 13. "IBIWON,In-Band Interrupt (IBI) won" "0,1"
newline
rbitfld.long 0x00 12. "TXNOTFULL,TX buffer/FIFO not yet full" "0,1"
rbitfld.long 0x00 11. "RXPEND,RXPEND" "0,1"
newline
bitfld.long 0x00 10. "COMPLETE,COMPLETE" "0,1"
bitfld.long 0x00 9. "MCTRLDONE,Master control done" "0,1"
newline
bitfld.long 0x00 8. "SLVSTART,Slave start" "0,1"
rbitfld.long 0x00 6.--7. "IBITYPE,In-Band Interrupt (IBI) type" "0: NONE,1: IBI,2: MR,3: HJ"
newline
rbitfld.long 0x00 5. "NACKED,Not acknowledged" "0,1"
rbitfld.long 0x00 4. "BETWEEN,Between messages or Dynamic Address Assignments (DAA)" "0,1"
newline
rbitfld.long 0x00 0.--2. "STATE,State of the master" "0: IDLE,1: SLVREQ,2: MSGSDR,3: NORMACT,4: MSGDDR,5: DAA,6: IBIACK,7: IBIRCV"
group.long 0x8C++0x03
line.long 0x00 "MIBIRULES,Master In-band Interrupt Registry and Rules Register"
bitfld.long 0x00 31. "NOBYTE,No IBI byte" "0,1"
bitfld.long 0x00 30. "MSB0,Set Most Significant address Bit to 0" "0,1"
newline
bitfld.long 0x00 24.--29. "ADDR4,ADDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. "ADDR3,ADDR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "ADDR2,ADDR2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--11. "ADDR1,ADDR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "ADDR0,ADDR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x90++0x03
line.long 0x00 "MINTSET,Master Interrupt Set Register"
bitfld.long 0x00 19. "NOWMASTER,Now master (now this I3C module is a master) interrupt enable" "0,1"
bitfld.long 0x00 15. "ERRWARN,Error or warning (ERRWARN) interrupt enable" "0,1"
newline
bitfld.long 0x00 13. "IBIWON,In-Band Interrupt (IBI) won interrupt enable" "0,1"
bitfld.long 0x00 12. "TXNOTFULL,TX buffer/FIFO is not full interrupt enable" "0,1"
newline
bitfld.long 0x00 11. "RXPEND,RX pending interrupt enable" "0,1"
bitfld.long 0x00 10. "COMPLETE,Completed message interrupt enable" "0,1"
newline
bitfld.long 0x00 9. "MCTRLDONE,Master control done interrupt enable" "0,1"
bitfld.long 0x00 8. "SLVSTART,Slave start interrupt enable" "0,1"
wgroup.long 0x94++0x03
line.long 0x00 "MINTCLR,Master Interrupt Clear Register"
bitfld.long 0x00 19. "NOWMASTER,NOWMASTER interrupt enable clear" "0,1"
bitfld.long 0x00 15. "ERRWARN,ERRWARN interrupt enable clear" "0,1"
newline
bitfld.long 0x00 13. "IBIWON,IBIWON interrupt enable clear" "0,1"
bitfld.long 0x00 12. "TXNOTFULL,TXNOTFULL interrupt enable clear" "0,1"
newline
bitfld.long 0x00 11. "RXPEND,RXPEND interrupt enable clear" "0,1"
bitfld.long 0x00 10. "COMPLETE,COMPLETE interrupt enable clear" "0,1"
newline
bitfld.long 0x00 9. "MCTRLDONE,MCTRLDONE interrupt enable clear" "0,1"
bitfld.long 0x00 8. "SLVSTART,SLVSTART interrupt enable clear" "0,1"
rgroup.long 0x98++0x03
line.long 0x00 "MINTMASKED,Master Interrupt Mask Register"
bitfld.long 0x00 19. "NOWMASTER,NOWMASTER interrupt mask" "0,1"
bitfld.long 0x00 15. "ERRWARN,ERRWARN interrupt mask" "0,1"
newline
bitfld.long 0x00 13. "IBIWON,IBIWON interrupt mask" "0,1"
bitfld.long 0x00 12. "TXNOTFULL,TXNOTFULL interrupt mask" "0,1"
newline
bitfld.long 0x00 11. "RXPEND,RXPEND interrupt mask" "0,1"
bitfld.long 0x00 10. "COMPLETE,COMPLETE interrupt mask" "0,1"
newline
bitfld.long 0x00 9. "MCTRLDONE,MCTRLDONE interrupt mask" "0,1"
bitfld.long 0x00 8. "SLVSTART,SLVSTART interrupt mask" "0,1"
group.long 0x9C++0x03
line.long 0x00 "MERRWARN,Master Errors and Warnings Register"
bitfld.long 0x00 20. "TIMEOUT,TIMEOUT error" "0,1"
bitfld.long 0x00 19. "INVREQ,Invalid request error" "0,1"
newline
bitfld.long 0x00 18. "MSGERR,Message error" "0,1"
bitfld.long 0x00 17. "OWRITE,Over-write error" "0,1"
newline
bitfld.long 0x00 16. "OREAD,Over-read error" "0,1"
bitfld.long 0x00 10. "HCRC,High data rate CRC error" "0,1"
newline
bitfld.long 0x00 9. "HPAR,High data rate parity" "0,1"
bitfld.long 0x00 4. "TERM,Terminate error" "0,1"
newline
bitfld.long 0x00 3. "WRABT,WRABT (Write abort) error" "0,1"
bitfld.long 0x00 2. "NACK,Not acknowledge (NACK) error" "0,1"
group.long 0xA0++0x03
line.long 0x00 "MDMACTRL,Master DMA Control Register"
bitfld.long 0x00 4.--5. "DMAWIDTH,DMA width" "0: BYTE,1: BYTE_AGAIN,2: HALF_WORD,?..."
bitfld.long 0x00 2.--3. "DMATB,DMA to bus" "0: NOT_USED,1: ENABLE_ONE_FRAME,2: ENABLE,?..."
newline
bitfld.long 0x00 0.--1. "DMAFB,DMA from bus" "0: NOT_USED,1: ENABLE_ONE_FRAME,2: ENABLE,?..."
group.long 0xAC++0x03
line.long 0x00 "MDATACTRL,Master Data Control Register"
rbitfld.long 0x00 31. "RXEMPTY,RX is empty" "0,1"
rbitfld.long 0x00 30. "TXFULL,TX is full" "0,1"
newline
rbitfld.long 0x00 24.--28. "RXCOUNT,RX byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 16.--20. "TXCOUNT,TX byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--7. "RXTRIG,RX trigger level" "0,1,2,3"
bitfld.long 0x00 4.--5. "TXTRIG,TX trigger level" "0,1,2,3"
newline
bitfld.long 0x00 2. "UNLOCK,Unlock" "0,1"
bitfld.long 0x00 1. "FLUSHFB,Flush from-bus buffer/FIFO" "0,1"
newline
bitfld.long 0x00 0. "FLUSHTB,Flush to-bus buffer/FIFO" "0,1"
wgroup.long 0xB0++0x03
line.long 0x00 "MWDATAB,Master Write Data Byte Register"
bitfld.long 0x00 16. "END_ALSO,End of message also" "0,1"
bitfld.long 0x00 8. "END,End of message" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "VALUE,Data byte"
wgroup.long 0xB4++0x03
line.long 0x00 "MWDATABE,Master Write Data Byte End Register"
hexmask.long.byte 0x00 0.--7. 1. "VALUE,Data"
wgroup.long 0xB8++0x03
line.long 0x00 "MWDATAH,Master Write Data Half-word Register"
bitfld.long 0x00 16. "END,End of message" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "DATA1,Data byte 1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DATA0,Data byte 0"
wgroup.long 0xBC++0x03
line.long 0x00 "MWDATAHE,Master Write Data Byte End Register"
hexmask.long.byte 0x00 8.--15. 1. "DATA1,DATA 1"
hexmask.long.byte 0x00 0.--7. 1. "DATA0,DATA 0"
rgroup.long 0xC0++0x03
line.long 0x00 "MRDATAB,Master Read Data Byte Register"
hexmask.long.byte 0x00 0.--7. 1. "VALUE,VALUE"
rgroup.long 0xC8++0x03
line.long 0x00 "MRDATAH,Master Read Data Half-word Register"
hexmask.long.byte 0x00 8.--15. 1. "MSB,MSB"
hexmask.long.byte 0x00 0.--7. 1. "LSB,LSB"
wgroup.long 0xD0++0x03
line.long 0x00 "MWMSG_SDR_CONTROL,Master Write Message in SDR mode"
bitfld.long 0x00 11.--15. "LEN,Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "I2C,I2C" "0: I3C message,1: I2C message"
newline
bitfld.long 0x00 8. "END,End of SDR message" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "ADDR,Address to be written to"
newline
bitfld.long 0x00 0. "DIR,Direction" "0: ,1: "
wgroup.long 0xD0++0x03
line.long 0x00 "MWMSG_SDR_DATA,Master Write Message Data in SDR mode"
bitfld.long 0x00 16. "END,End of message" "0,1"
hexmask.long.word 0x00 0.--15. 1. "DATA16B,Data"
rgroup.long 0xD4++0x03
line.long 0x00 "MRMSG_SDR,Master Read Message in SDR mode"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data"
wgroup.long 0xD8++0x03
line.long 0x00 "MWMSG_DDR_CONTROL,Master Write Message in DDR mode"
bitfld.long 0x00 14. "END,End of message" "0,1"
hexmask.long.word 0x00 0.--9. 1. "LEN,Length of message"
wgroup.long 0xD8++0x03
line.long 0x00 "MWMSG_DDR_DATA,Master Write Message Data in DDR mode"
bitfld.long 0x00 16. "END,End of message" "0,1"
hexmask.long.word 0x00 0.--15. 1. "DATA16B,Data"
group.long 0xDC++0x03
line.long 0x00 "MRMSG_DDR,Master Read Message in DDR mode"
hexmask.long.word 0x00 16.--25. 1. "CLEN,Current length"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data"
group.long 0xE4++0x03
line.long 0x00 "MDYNADDR,Master Dynamic Address Register"
hexmask.long.byte 0x00 1.--7. 1. "DADDR,Dynamic address"
bitfld.long 0x00 0. "DAVALID,Dynamic address valid" "0,1"
rgroup.long 0xFFC++0x03
line.long 0x00 "SID,Slave Module ID Register"
hexmask.long 0x00 0.--31. 1. "ID,ID"
tree.end
repeat.end
tree.end
tree "INPUTMUX"
base ad:0x40026000
sif cpuis("IMXRT595-CM33")
repeat 7. (increment 0 1) (increment 0 0x4)
group.long ($2+0x00)++0x03
line.long 0x00 "SCT0_IN_SEL[$1],SCT Peripheral Input multiplexer index $1"
bitfld.long 0x00 0.--4. "SCT_IN_SEL,SCT0 Input Selection" "0: SCT0_PIN_INP0,1: SCT0_PIN_INP1,2: SCT0_PIN_INP2,3: SCT0_PIN_INP3,4: SCT0_PIN_INP4,5: SCT0_PIN_INP5,6: SCT0_PIN_INP6,7: SCT0_PIN_INP7,8: CT32BIT0_MAT0,9: CT32BIT1_MAT0,10: SCT_IN_SEL_10,11: SCT_IN_SEL_11,12: SCT_IN_SEL_12,13: SCT_IN_SEL_13,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: SCT_IN_SEL_16,17: SHARED I2S0_SCLK,18: SHARED I2S1_SCLK,19: SHARED I2S0_WS,20: SHARED I2S1_WS,21: SCT_IN_SEL_21,22: SCT_IN_SEL_22,23: SCT_IN_SEL_23,?..."
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "PINT_SEL[$1],GPIO Pin Input Multiplexer index $1"
hexmask.long.byte 0x00 0.--7. 1. "PINT_SEL,Interrupt select"
repeat.end
repeat 27. (increment 0 1) (increment 0 0x04)
group.long ($2+0x140)++0x03
line.long 0x00 "DSP_INT_SEL[$1],Fusion DSP Interrupt Input Multiplexer $1"
bitfld.long 0x00 0.--5. "DSP_INT_SEL,Fusion DSP Input(n) Selection" "0: FLEXCOMM0_IRQ,1: FLEXCOMM1_IRQ,2: FLEXCOMM2_IRQ,3: FLEXCOMM3_IRQ,4: FLEXCOMM4_IRQ,5: FLEXCOMM5_IRQ,6: FLEXCOMM6_IRQ,7: FLEXCOMM7_IRQ,8: FLEXCOMM14_IRQ,9: FLEXCOMM16_IRQ,10: GPIO_INT0_IRQ0,11: GPIO_INT0_IRQ1,12: GPIO_INT0_IRQ2,13: GPIO_INT0_IRQ3,14: GPIO_INT0_IRQ4,15: GPIO_INT0_IRQ5,16: GPIO_INT0_IRQ6,17: GPIO_INT0_IRQ7,18: NSHSGPIO_INT0_IRQ0,19: NSHSGPIO_INT1_IRQ1,20: WDT1,21: DMAC0_IRQ,22: DMAC1_IRQ,23: MU_B_IRQ,24: UTICK0_IRQ,25: MRT0_IRQ,26: OS_EVENT_TIMER or OS_EVENT_WAKEUP,27: CTIMER0,28: CTIMER1,29: CTIMER2,30: CTIMER3,31: CTIMER4,32: RTC_LITE0_ALARM or RTC_LITE0_WAKEUP,33: I3C0,34: I3C1,35: DMIC0,36: HWVAD,37: LCDIF_IRQ,38: GPU_IRQ,39: SMARTDMA_IRQ,40: FLEXIO_IRQ,?..."
repeat.end
repeat 37. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[$1],DMAC0 Input Trigger Select $1"
bitfld.long 0x00 0.--4. "DMAC0_ITRIG_SEL,DMA Input Trigger Selection" "0: GPIO_INT0,1: GPIO_INT1,2: GPIO_INT2,3: GPIO_INT3,4: T0_DMAREQ_M0,5: T0_DMAREQ_M1,6: T1_DMAREQ_M0,7: T1_DMAREQ_M1,8: T2_DMAREQ_M0,9: T2_DMAREQ_M1,10: T3_DMAREQ_M0,11: T3_DMAREQ_M1,12: T4_DMAREQ_M0,13: T4_DMAREQ_M1,14: DMA0_TRIGOUT_A,15: DMA0_TRIGOUT_B,16: DMA0_TRIGOUT_C,17: DMA0_TRIGOUT_D,18: SCT_DMAC0_REQ0,19: SCT_DMAC1_REQ1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,22: FlexSPI0_RX_DMA,23: FlexSPI0_TX_DMA,24: ADC_DMA,25: FlexSPI1_RX_DMA,26: FlexSPI1_TX_DMA,?..."
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x300)++0x03
line.long 0x00 "DMAC0_OTRIG_SEL[$1],DMAC0 Output Trigger Select $1"
bitfld.long 0x00 0.--5. "DMAC0_OTRIG_SEL,DMAC0 Output Triggers Select for A B C D IE" "0: DMAC0_OTRIG_CH0,1: DMAC0_OTRIG_CH1,2: DMAC0_OTRIG_CH2,3: DMAC0_OTRIG_CH3,4: DMAC0_OTRIG_CH4,5: DMAC0_OTRIG_CH5,6: DMAC0_OTRIG_CH6,7: DMAC0_OTRIG_CH7,8: DMAC0_OTRIG_CH8,9: DMAC0_OTRIG_CH9,10: DMAC0_OTRIG_CH10,11: DMAC0_OTRIG_CH11,12: DMAC0_OTRIG_CH12,13: DMAC0_OTRIG_CH13,14: DMAC0_OTRIG_CH14,15: DMAC0_OTRIG_CH15,16: DMAC0_OTRIG_CH16,17: DMAC0_OTRIG_CH17,18: DMAC0_OTRIG_CH18,19: DMAC0_OTRIG_CH19,20: DMAC0_OTRIG_CH20,21: DMAC0_OTRIG_CH21,22: DMAC0_OTRIG_CH22,23: DMAC0_OTRIG_CH23,24: DMAC0_OTRIG_CH24,25: DMAC0_OTRIG_CH25,26: DMAC0_OTRIG_CH26,27: DMAC0_OTRIG_CH27,28: DMAC0_OTRIG_CH28,29: DMAC0_OTRIG_CH29,30: DMAC0_OTRIG_CH30,31: DMAC0_OTRIG_CH31,32: DMAC0_OTRIG_CH32,33: DMAC0_OTRIG_CH33,34: DMAC0_OTRIG_CH34,35: DMAC0_OTRIG_CH35,36: DMAC0_OTRIG_CH36,?..."
repeat.end
group.long 0x320++0x03
line.long 0x00 "DMAC0_CHMUX_SEL0,DMAC0 Channel mux select 0"
bitfld.long 0x00 0. "DMAC0_CHMUX_SEL,DMAC0 Channel mux select 0" "0: DMAC0_CHMUX_SEL_0,1: DMAC0_CHMUX_SEL_1"
group.long 0x324++0x03
line.long 0x00 "DMAC0_CHMUX_SEL1,DMAC0 Channel mux select 1"
bitfld.long 0x00 0. "DMAC0_CHMUX_SEL,DMAC0 Channel mux select 1" "0: DMAC0_CHMUX_SEL_0,1: DMAC0_CHMUX_SEL_1"
repeat 13. (strings "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 )
group.long ($2+0x328)++0x03
line.long 0x00 "DMAC0_CHMUX_SEL$1,DMAC0 Channel mux select $1"
bitfld.long 0x00 0. "DMAC0_CHMUX_SEL,DMAC0 Channel mux select" "0: DMAC0_CHMUX_SEL_0,1: DMAC0_CHMUX_SEL_1"
repeat.end
group.long 0x35C++0x03
line.long 0x00 "DMAC0_CHMUX_SEL15,DMAC0 Channel mux select 15"
bitfld.long 0x00 0. "DMAC0_CHMUX_SEL,DMA Channel mux select" "0: DMAC0_CHMUX_SEL_0,1: DMAC0_CHMUX_SEL_0_1"
repeat 37. (increment 0 1) (increment 0 0x04)
group.long ($2+0x400)++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[$1],DMAC1 Input Trigger Select $1"
bitfld.long 0x00 0.--4. "DMAC1_ITRIG_SEL,DMA Input Trigger Selection" "0: GPIO_INT0,1: GPIO_INT1,2: GPIO_INT2,3: GPIO_INT3,4: T0_DMAREQ_M0,5: T0_DMAREQ_M1,6: T1_DMAREQ_M0,7: T1_DMAREQ_M1,8: T2_DMAREQ_M0,9: T2_DMAREQ_M1,10: T3_DMAREQ_M0,11: T3_DMAREQ_M1,12: T4_DMAREQ_M0,13: T4_DMAREQ_M1,14: DMA0_TRIGOUT_A,15: DMA0_TRIGOUT_B,16: DMA0_TRIGOUT_C,17: DMA0_TRIGOUT_D,18: SCT_DMAC0_REQ0,19: SCT_DMAC1_REQ1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,22: FlexSPI0_RX_DMA,23: FlexSPI0_TX_DMA,24: ADC_DMA,25: FlexSPI1_RX_DMA,26: FlexSPI1_TX_DMA,?..."
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x500)++0x03
line.long 0x00 "DMAC1_OTRIG_SEL[$1],DMAC1 Output Trigger Select $1"
bitfld.long 0x00 0.--5. "DMAC1_OTRIG_SEL,DMA Output Trigger Selection" "0: DMAC1_OTRIG_CH0,1: DMAC1_OTRIG_CH1,2: DMAC1_OTRIG_CH2,3: DMAC1_OTRIG_CH3,4: DMAC1_OTRIG_CH4,5: DMAC1_OTRIG_CH5,6: DMAC1_OTRIG_CH6,7: DMAC1_OTRIG_CH7,8: DMAC1_OTRIG_CH8,9: DMAC1_OTRIG_CH9,10: DMAC1_OTRIG_CH10,11: DMAC1_OTRIG_CH11,12: DMAC1_OTRIG_CH12,13: DMAC1_OTRIG_CH13,14: DMAC1_OTRIG_CH14,15: DMAC1_OTRIG_CH15,16: DMAC1_OTRIG_CH16,17: DMAC1_OTRIG_CH17,18: DMAC1_OTRIG_CH18,19: DMAC1_OTRIG_CH19,20: DMAC1_OTRIG_CH20,21: DMAC1_OTRIG_CH21,22: DMAC1_OTRIG_CH22,23: DMAC1_OTRIG_CH23,24: DMAC1_OTRIG_CH24,25: DMAC1_OTRIG_CH25,26: DMAC1_OTRIG_CH26,27: DMAC1_OTRIG_CH27,28: DMAC1_OTRIG_CH28,29: DMAC1_OTRIG_CH29,30: DMAC1_OTRIG_CH30,31: DMAC1_OTRIG_CH31,32: DMAC1_OTRIG_CH32,33: DMAC1_OTRIG_CH33,34: DMAC1_OTRIG_CH34,35: DMAC1_OTRIG_CH35,36: DMAC1_OTRIG_CH36,?..."
repeat.end
repeat 14. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
group.long ($2+0x520)++0x03
line.long 0x00 "DMAC1_CHMUX_SEL$1,DMAC1 Channel mux select $1"
bitfld.long 0x00 0. "DMAC1_CHMUX_SEL,DMAC1 Channel mux select" "0: DMAC1_CHMUX_SEL_0,1: DMAC1_CHMUX_SEL_1"
repeat.end
group.long 0x558++0x03
line.long 0x00 "DMAC1_CHMUX_SEL14,DMAC1 Channel mux select 14"
bitfld.long 0x00 0. "DMAC1_CHMUX_SEL,DMA channel mux select" "0: DMAC1_CHMUX_SEL_0,1: DMAC1_CHMUX_SEL_1"
group.long 0x55C++0x03
line.long 0x00 "DMAC1_CHMUX_SEL15,DMAC1 Channel mux select 15"
bitfld.long 0x00 0. "DMAC1_CHMUX_SEL,DMAC1 Channel mux select" "0: DMAC1_CHMUX_SEL_0,1: DMAC1_CHMUX_SEL_1"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x700)++0x03
line.long 0x00 "FMEASURE_CH_SEL[$1],Frequency Measurement Input Channel Multiplexers $1"
bitfld.long 0x00 0.--4. "FMEASURE_SEL,Frequency Measure Channel Selection" "0: FMEASURE_SEL0,1: FMEASURE_SEL1,2: FMEASURE_SEL2,3: Low Power Oscillator Clock (LPOSC),4: RTC 32 kHz OSC,5: FMEASURE_SEL5,6: FREQME_GPIO_CLK,?,?,?,?,11: FMEASURE_SEL11,?..."
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x720)++0x03
line.long 0x00 "SMART_DMA_TRIG_CH_SEL[$1],SMART_DMA trigger channel select $1"
hexmask.long.byte 0x00 0.--6. 1. "SMART_DMA_IN_SEL,SMART_DMA Input(n) Selection"
repeat.end
group.long 0x740++0x03
line.long 0x00 "DMAC0_REQ_ENA0,DMAC0 request enable 0"
bitfld.long 0x00 31. "I3C1_TX_FLEXIO_SHFT7,I3C1_TX / FLEXIO_SHFT7 enable" "0: I3C1_TX_FLEXIO_SHFT7_0,1: I3C1_TX_FLEXIO_SHFT7_1"
bitfld.long 0x00 30. "I3C1_RX_FLEXIO_SHFT6,I3C1_RX / FLEXIO_SHFT6 enable" "0: I3C1_RX_FLEXIO_SHFT6_0,1: I3C1_RX_FLEXIO_SHFT6_1"
newline
bitfld.long 0x00 29. "FLEXCOMM16_TX_FLEXIO_SHFT5,FLEXCOMM16 RX / FLEXIO_SHFT5 enable" "0: FLEXCOMM16_TX_FLEXIO_SHFT5_0,1: FLEXCOMM16_TX_FLEXIO_SHFT5_1"
bitfld.long 0x00 28. "FLEXCOMM16_RX_FLEXIO_SHFT4,FLEXCOMM16 RX / FLEXIO SHFT4 enable" "0: FLEXCOMM16_RX_0,1: FLEXCOMM16_RX_1"
newline
bitfld.long 0x00 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable" "0: FLEXCOMM14_TX_0,1: FLEXCOMM14_TX_1"
bitfld.long 0x00 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable" "0: FLEXCOMM14_RX_0,1: FLEXCOMM14_RX_1"
newline
bitfld.long 0x00 25. "I3C0_TX,I3C TX enable" "0: I3C0_TX_0,1: I3C0_TX_1"
bitfld.long 0x00 24. "I3C0_RX,I3C RX enable" "0: I3C0_RX_0,1: I3C0_RX_1"
newline
bitfld.long 0x00 23. "DMIC0_CH7_FLEXCOMM13_TX_DMA,DMIC0 channel 7 / FLEXCOMM13 TX DMA enable" "0: DMIC0_CH7_FLEXCOMM13_TX_DMA_0,1: DMIC0_CH7_FLEXCOMM13_TX_DMA_1"
bitfld.long 0x00 22. "DMIC0_CH6_FLEXCOMM13_RX_DMA,DMIC0 channel 6 / FLEXCOMM13 RX DMA enable" "0: DMIC0_CH6_FLEXCOMM13_RX_DMA_0,1: DMIC0_CH6_FLEXCOMM13_RX_DMA_1"
newline
bitfld.long 0x00 21. "DMIC0_CH5_FLEXCOMM10_TX_DMA,DMIC0 channel 5 / FLEXCOMM10 TX DMA enable" "0: DMIC0_CH5_FLEXCOMM10_TX_DMA_0,1: DMIC0_CH5_FLEXCOMM10_TX_DMA_1"
bitfld.long 0x00 20. "DMIC0_CH4_FLEXCOMM10_RX_DMA,DMIC0 channel 4 / FLEXCOMM10 RX DMA enable" "0: DMIC0_CH4_FLEXCOMM10_RX_DMA_0,1: DMIC0_CH4_FLEXCOMM10_RX_DMA_1"
newline
bitfld.long 0x00 19. "DMIC0_CH3_FLEXCOMM9_TX_DMA,DMIC0 channel 3 / FLEXCOMM9 TX DMA enable" "0: DMIC0_CH3_FLEXCOMM9_TX_DMA_0,1: DMIC0_CH3_FLEXCOMM9_TX_DMA_1"
bitfld.long 0x00 18. "DMIC0_CH2_FLEXCOMM9_RX_DMA,DMIC0 channel 2 / FLEXCOMM9 RX DMA enable" "0: DMIC0_CH2_FLEXCOMM9_RX_DMA_0,1: DMIC0_CH2_FLEXCOMM9_RX_DMA_1"
newline
bitfld.long 0x00 17. "DMIC0_CH1_FLEXCOMM8_TX_DMA,DMIC0 channel 1 / FLEXCOMM8 TX DMA enable" "0: DMIC0_CH1_FLEXCOMM8_TX_DMA_0,1: DMIC0_CH1_FLEXCOMM8_TX_DMA_1"
bitfld.long 0x00 16. "DMIC0_CH0_FLEXCOMM8_RX_DMA,DMIC0 channel 0 / FLEXCOMM8 RX DMA enable" "0: DMIC0_CH0_FLEXCOMM8_RX_DMA_0,1: DMIC0_CH0_FLEXCOMM8_RX_DMA_1"
newline
bitfld.long 0x00 15. "FLEXCOMM7_TX,FLEXCOMM7 TX enable" "0: FLEXCOMM7_TX_0,1: FLEXCOMM7_TX_1"
bitfld.long 0x00 14. "FLEXCOMM7_RX,FLEXCOMM7 RX enable" "0: FLEXCOMM5_RX_0,1: FLEXCOMM5_RX_1"
newline
bitfld.long 0x00 13. "FLEXCOMM6_TX,FLEXCOMM6 TX enable" "0: FLEXCOMM6_TX_0,1: FLEXCOMM6_TX_1"
bitfld.long 0x00 12. "FLEXCOMM6_RX,FLEXCOMM6 RX enable" "0: FLEXCOMM6_RX_0,1: FLEXCOMM6_RX_1"
newline
bitfld.long 0x00 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable" "0: FLEXCOMM5_TX_0,1: FLEXCOMM5_TX_1"
bitfld.long 0x00 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable" "0: FLEXCOMM5_RX_0,1: FLEXCOMM5_RX_1"
newline
bitfld.long 0x00 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable" "0: FLEXCOMM4_TX_0,1: FLEXCOMM4_TX_1"
bitfld.long 0x00 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable" "0: FLEXCOMM4_RX_0,1: FLEXCOMM4_RX_1"
newline
bitfld.long 0x00 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable" "0: FLEXCOMM3_TX_1,1: FLEXCOMM3_TX_0"
bitfld.long 0x00 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable" "0: FLEXCOMM3_RX_0,1: FLEXCOMM3_RX_1"
newline
bitfld.long 0x00 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable" "0: FLEXCOMM2_TX_0,1: FLEXCOMM2_TX_1"
bitfld.long 0x00 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable" "0: FLEXCOMM2_RX_0,1: FLEXCOMM2_RX_1"
newline
bitfld.long 0x00 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable" "0: FLEXCOMM1_TX_0,1: FLEXCOMM1_TX_1"
bitfld.long 0x00 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable" "0: FLEXCOMM1_RX_0,1: FLEXCOMM1_RX_1"
newline
bitfld.long 0x00 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable" "0: FLEXCOMM0_TX_0,1: FLEXCOMM0_TX_1"
bitfld.long 0x00 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable" "0: FLEXCOMM0_RX_0,1: FLEXCOMM0_RX_1"
group.long 0x744++0x03
line.long 0x00 "DMAC0_REQ_ENA1,DMAC0 request enable 1"
bitfld.long 0x00 4. "HASHCRYPT_IN,HASHCRYPT_IN" "0: HASHCRYPT_IN_0,1: HASHCRYPT_IN_1"
bitfld.long 0x00 3. "FLEXIO_SHFT3_FLEXCOMM12_TX,FLEXIO_SHFT3_FLEXCOMM12_TX" "0: FLEXIO_SHFT3_FLEXCOMM12_TX_0,1: FLEXIO_SHFT3_FLEXCOMM12_TX_1"
newline
bitfld.long 0x00 2. "FLEXIO_SHFT2_FLEXCOMM12_RX,FLEXIO_SHFT2_FLEXCOMM12_RX" "0: FLEXIO_SHFT2_FLEXCOMM12_RX_0,1: FLEXIO_SHFT2_FLEXCOMM12_RX_1"
bitfld.long 0x00 1. "FLEXIO_SHFT1_FLEXCOMM11_TX,FLEXIO_SHFT1_FLEXCOMM11_TX" "0: FLEXIO_SHFT1_FLEXCOMM11_TX_0,1: FLEXIO_SHFT1_FLEXCOMM11_TX_1"
newline
bitfld.long 0x00 0. "FLEXIO_SHFT0_FLEXCOMM11_RX,FLEXIO_SHFT0_FLEXCOMM11_RX" "0: FLEXIO_SHFT0_FLEXCOMM11_RX_0,1: FLEXIO_SHFT0_FLEXCOMM11_RX_1"
group.long 0x748++0x03
line.long 0x00 "DMAC0_REQ_ENA0_SET,DMAC0 request enable set 0"
bitfld.long 0x00 31. "I3C1_TX_FLEXIO_SHFT7,I3C1_TX / FLEXIO_SHFT7 enable" "0: I3C1_TX_FLEXIO_SHFT7_0,1: I3C1_TX_FLEXIO_SHFT7_1"
bitfld.long 0x00 30. "I3C1_RX_FLEXIO_SHFT6,I3C1_RX / FLEXIO SHFT6 enable" "0: I3C1_RX_FLEXIO_SHFT6_0,1: I3C1_RX_FLEXIO_SHFT6_1"
newline
bitfld.long 0x00 29. "FLEXCOMM16_TX_FLEXIO_SHFT5,FLEXCOMM16 RX / FLEXIO SHFT5 enable" "0: FLEXCOMM16_TX_FLEXIO_SHFT5_0,1: FLEXCOMM16_TX_FLEXIO_SHFT5_1"
bitfld.long 0x00 28. "FLEXCOMM16_RX_FLEXIO_SHFT4,FLEXCOMM16 RX / FLEXIO SHFT4 enable" "0: FLEXCOMM16_RX_0,1: Sets the ENA0 bit"
newline
bitfld.long 0x00 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable set" "0: FLEXCOMM14_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable set" "0: FLEXCOMM14_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 25. "I3C0_TX,I3C TX enable set" "0: I3C0_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 24. "I3C0_RX,I3C RX enable set" "0: I3C0_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 23. "DMIC0_CH7_FLEXCOMM13_TX_DMA,DMIC0 channel 7 / FLEXCOMM13 TX DMA enable" "0: DMIC0_CH7_FLEXCOMM13_TX_DMA_0,1: DMIC0_CH7_FLEXCOMM13_TX_DMA_1"
bitfld.long 0x00 22. "DMIC0_CH6_FLEXCOMM13_RX_DMA,DMIC0 channel 6 / FLEXCOMM10 RX DMA enable" "0: DMIC0_CH6_FLEXCOMM13_RX_DMA_0,1: DMIC0_CH6_FLEXCOMM13_RX_DMA_1"
newline
bitfld.long 0x00 21. "DMIC0_CH5_FLEXCOMM10_TX_DMA,DMIC0 channel 5 / FLEXCOMM10 TX DMA enable" "0: DMIC0_CH5_FLEXCOMM10_TX_DMA_0,1: DMIC0_CH5_FLEXCOMM10_TX_DMA_1"
bitfld.long 0x00 20. "DMIC0_CH4_FLEXCOMM10_RX_DMA,DMIC0 channel 4 / FLEXCOMM10 RX DMA enable" "0: DMIC0_CH4_FLEXCOMM10_RX_DMA_0,1: DMIC0_CH4_FLEXCOMM10_RX_DMA_1"
newline
bitfld.long 0x00 19. "DMIC0_CH3_FLEXCOMM9_TX_DMA,DMIC0 channel 3 / FLEXCOMM9 TX DMA enable" "0: DMIC0_CH3_FLEXCOMM9_TX_DMA_0,1: DMIC0_CH3_FLEXCOMM9_TX_DMA_1"
bitfld.long 0x00 18. "DMIC0_CH2_FLEXCOMM9_RX_DMA,DMIC0 channel 2 / FLEXCOMM9 RX DMA enable" "0: DMIC0_CH2_FLEXCOMM9_RX_DMA_0,1: DMIC0_CH2_FLEXCOMM9_RX_DMA_1"
newline
bitfld.long 0x00 17. "DMIC0_CH1_FLEXCOMM8_TX_DMA,DMIC0 channel 1 / FLEXCOMM8 TX DMA enable" "0: DMIC0_CH1_FLEXCOMM8_TX_DMA_0,1: DMIC0_CH1_FLEXCOMM8_TX_DMA_1"
bitfld.long 0x00 16. "DMIC0_CH0_FLEXCOMM8_RX_DMA,DMIC0 channel 0 / FLEXCOMM8 RX DMA enable" "0: DMIC0_CH0_FLEXCOMM8_RX_DMA_0,1: DMIC0_CH0_FLEXCOMM8_RX_DMA_1"
newline
bitfld.long 0x00 15. "FLEXCOMM7_TX,FLEXCOMM7 TX enable" "0: FLEXCOMM7_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 14. "FLEXCOMM7_RX,FLEXCOMM7 RX enable" "0: FLEXCOMM5_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 13. "FLEXCOMM6_TX,FLEXCOMM6 TX enable" "0: FLEXCOMM6_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 12. "FLEXCOMM6_RX,FLEXCOMM6 RX enable" "0: FLEXCOMM6_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable set" "0: FLEXCOMM5_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable set" "0: FLEXCOMM5_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable set" "0: FLEXCOMM4_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable set" "0: FLEXCOMM4_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable set" "0: FLEXCOMM3_TX_1,1: Sets the ENA0 Bit"
bitfld.long 0x00 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable set" "0: FLEXCOMM3_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable set" "0: FLEXCOMM2_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable set" "0: FLEXCOMM2_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable set" "0: FLEXCOMM1_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable set" "0: FLEXCOMM1_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable set" "0: FLEXCOMM0_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable set" "0: FLEXCOMM0_RX_0,1: Sets the ENA0 Bit"
group.long 0x74C++0x03
line.long 0x00 "DMAC0_REQ_ENA1_SET,DMAC0 request enable set 1"
bitfld.long 0x00 4. "HASHCRYPT_IN,HASHCRYPT_IN" "0: HASHCRYPT_IN_0,1: Sets the ENA1 Bit"
bitfld.long 0x00 3. "FLEXIO_SHFT3_FLEXCOMM12_TX,FLEXIO_SHFT3_FLEXCOMM12_TX" "0: FLEXIO_SHFT3_FLEXCOMM12_TX_0,1: FLEXIO_SHFT3_FLEXCOMM12_TX_1"
newline
bitfld.long 0x00 2. "FLEXIO_SHFT2_FLEXCOMM12_RX,FLEXIO_SHFT2_FLEXCOMM12_RX" "0: FLEXIO_SHFT2_FLEXCOMM12_RX_0,1: FLEXIO_SHFT2_FLEXCOMM12_RX_1"
bitfld.long 0x00 1. "FLEXIO_SHFT1_FLEXCOMM11_TX,FLEXIO_SHFT1_FLEXCOMM11_TX" "0: FLEXIO_SHFT1_FLEXCOMM11_TX_0,1: FLEXIO_SHFT1_FLEXCOMM11_TX_1"
newline
bitfld.long 0x00 0. "FLEXIO_SHFT0_FLEXCOMM11_RX,FLEXIO_SHFT0_FLEXCOMM11_RX" "0: FLEXIO_SHFT0_FLEXCOMM11_RX_0,1: FLEXIO_SHFT0_FLEXCOMM11_RX_1"
group.long 0x750++0x03
line.long 0x00 "DMAC0_REQ_ENA0_CLR,DMAC0 request enable clear 0"
bitfld.long 0x00 31. "I3C1_TX_FLEXIO_SHFT7,I3C1_TX / FLEXIO SHFT7 enable" "0: I3C1_TX_FLEXIO_SHFT7_0,1: I3C1_TX_FLEXIO_SHFT7_1"
bitfld.long 0x00 30. "I3C1_RX_FLEXIO_SHFT6,I3C1_RX / FLEXIO SHFT6 enable" "0: I3C1_RX_FLEXIO_SHFT6_0,1: I3C1_RX_FLEXIO_SHFT6_1"
newline
bitfld.long 0x00 29. "FLEXCOMM16_TX_FLEXIO_SHFT5,FLEXCOMM16 RX / FLEXIO SHFT5 enable" "0: FLEXCOMM16_TX_FLEXIO_SHFT5_0,1: FLEXCOMM16_TX_FLEXIO_SHFT5_1"
bitfld.long 0x00 28. "FLEXCOMM16_RX_FLEXIO_SHFT4,FLEXCOMM16 RX / FLEXIO SHFT4 enable" "0: FLEXCOMM16_RX_0,1: Clears the ENA0 bit"
newline
bitfld.long 0x00 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable clear" "0: FLEXCOMM14_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable clear" "0: FLEXCOMM14_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 25. "I3C0_TX,I3C TX enable clear" "0: I3C0_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 24. "I3C0_RX,I3C RX enable clear" "0: I3C0_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 23. "DMIC0_CH7_FLEXCOMM13_TX_DMA,DMIC0 channel 7 / FLEXCOMM13 TX DMA enable" "0: DMIC0_CH7_FLEXCOMM13_TX_DMA_0,1: DMIC0_CH7_FLEXCOMM13_TX_DMA_1"
bitfld.long 0x00 22. "DMIC0_CH6_FLEXCOMM13_RX_DMA,DMIC0 channel 6 / FLEXCOMM13 RX DMA enable" "0: DMIC0_CH6_FLEXCOMM13_RX_DMA_0,1: DMIC0_CH6_FLEXCOMM13_RX_DMA_1"
newline
bitfld.long 0x00 21. "DMIC0_CH5_FLEXCOMM10_TX_DMA,DMIC0 channel 5 / FLEXCOMM10 TX DMA enable" "0: DMIC0_CH5_FLEXCOMM10_TX_DMA_0,1: DMIC0_CH5_FLEXCOMM10_TX_DMA_1"
bitfld.long 0x00 20. "DMIC0_CH4_FLEXCOMM10_RX_DMA,DMIC0 channel 4 / FLEXCOMM10 RX DMA enable" "0: DMIC0_CH4_FLEXCOMM10_RX_DMA_0,1: DMIC0_CH4_FLEXCOMM10_RX_DMA_1"
newline
bitfld.long 0x00 19. "DMIC0_CH3_FLEXCOMM9_TX_DMA,DMIC0 channel 3 / FLEXCOMM9 TX DMA enable" "0: DMIC0_CH3_FLEXCOMM9_TX_DMA_0,1: DMIC0_CH3_FLEXCOMM9_TX_DMA_1"
bitfld.long 0x00 18. "DMIC0_CH2_FLEXCOMM9_RX_DMA,DMIC0 channel 2 / FLEXCOMM9 RX DMA enable" "0: DMIC0_CH2_FLEXCOMM9_RX_DMA_0,1: DMIC0_CH2_FLEXCOMM9_RX_DMA_1"
newline
bitfld.long 0x00 17. "DMIC0_CH1_FLEXCOMM8_TX_DMA,DMIC0 channel 1 / FLEXCOMM8 TX DMA enable" "0: DMIC0_CH1_FLEXCOMM8_TX_DMA_0,1: DMIC0_CH1_FLEXCOMM8_TX_DMA_1"
bitfld.long 0x00 16. "DMIC0_CH0_FLEXCOMM8_RX_DMA,DMIC0 channel 0 / FLEXCOMM8 RX DMA enable" "0: DMIC0_CH0_FLEXCOMM8_RX_DMA_0,1: DMIC0_CH0_FLEXCOMM8_RX_DMA_1"
newline
bitfld.long 0x00 15. "FLEXCOMM7_TX,FLEXCOMM7 TX enable" "0: FLEXCOMM7_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 14. "FLEXCOMM7_RX,FLEXCOMM7 RX enable" "0: FLEXCOMM5_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 13. "FLEXCOMM6_TX,FLEXCOMM6 TX enable" "0: FLEXCOMM6_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 12. "FLEXCOMM6_RX,FLEXCOMM6 RX enable" "0: FLEXCOMM6_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable clear" "0: FLEXCOMM5_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable clear" "0: FLEXCOMM5_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable clear" "0: FLEXCOMM4_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable clear" "0: FLEXCOMM4_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable clear" "0: FLEXCOMM3_TX_1,1: Clears the ENA0 Bit"
bitfld.long 0x00 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable clear" "0: FLEXCOMM3_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable clear" "0: FLEXCOMM2_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable clear" "0: FLEXCOMM2_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable clear" "0: FLEXCOMM1_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable clear" "0: FLEXCOMM1_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable clear" "0: FLEXCOMM0_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable clear" "0: FLEXCOMM0_RX_0,1: Clears the ENA0 Bit"
group.long 0x754++0x03
line.long 0x00 "DMAC0_REQ_ENA1_CLR,DMAC0 request enable 1 clear"
bitfld.long 0x00 4. "HASHCRYPT_IN,HASHCRYPT_IN" "0: HASHCRYPT_IN_0,1: Clears the ENA1 Bit"
bitfld.long 0x00 3. "FLEXIO_SHFT3_FLEXCOMM12_TX,FLEXIO_SHFT3_FLEXCOMM12_TX" "0: FLEXIO_SHFT3_FLEXCOMM12_TX_0,1: FLEXIO_SHFT3_FLEXCOMM12_TX_1"
newline
bitfld.long 0x00 2. "FLEXIO_SHFT2_FLEXCOMM12_RX,FLEXIO_SHFT2_FLEXCOMM12_RX" "0: FLEXIO_SHFT2_FLEXCOMM12_RX_0,1: FLEXIO_SHFT2_FLEXCOMM12_RX_1"
bitfld.long 0x00 1. "FLEXIO_SHFT1_FLEXCOMM11_TX,FLEXIO_SHFT1_FLEXCOMM11_TX" "0: FLEXIO_SHFT1_FLEXCOMM11_TX_0,1: FLEXIO_SHFT1_FLEXCOMM11_TX_1"
newline
bitfld.long 0x00 0. "FLEXIO_SHFT0_FLEXCOMM11_RX,FLEXIO_SHFT0_FLEXCOMM11_RX" "0: FLEXIO_SHFT0_FLEXCOMM11_RX_0,1: FLEXIO_SHFT0_FLEXCOMM11_RX_1"
group.long 0x760++0x03
line.long 0x00 "DMAC1_REQ_ENA0,DMAC1 request enable 0"
bitfld.long 0x00 31. "I3C1_TX_FLEXIO_SHFT7,I3C1_TX / FLEXIO_SHFT7 enable" "0: I3C1_TX_FLEXIO_SHFT7_0,1: I3C1_TX_FLEXIO_SHFT7_1"
bitfld.long 0x00 30. "I3C1_RX_FLEXIO_SHFT6,I3C1_RX / FLEXIO_SHFT6 enable" "0: I3C1_RX_FLEXIO_SHFT6_0,1: I3C1_RX_FLEXIO_SHFT6_1"
newline
bitfld.long 0x00 29. "FLEXCOMM16_TX_FLEXIO_SHFT5,FLEXCOMM16 RX / FLEXIO_SHFT5 enable" "0: FLEXCOMM16_TX_FLEXIO_SHFT5_0,1: FLEXCOMM16_TX_FLEXIO_SHFT5_1"
bitfld.long 0x00 28. "FLEXCOMM16_RX_FLEXIO_SHFT4,FLEXCOMM16 RX / FLEXIO_SHFT4 enable" "0: FLEXCOMM16_RX_0,1: FLEXCOMM16_RX_1"
newline
bitfld.long 0x00 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable" "0: FLEXCOMM14_TX_0,1: FLEXCOMM14_TX_1"
bitfld.long 0x00 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable" "0: FLEXCOMM14_RX_0,1: FLEXCOMM14_RX_1"
newline
bitfld.long 0x00 25. "I3C0_TX,I3C TX enable" "0: I3C0_TX_0,1: I3C0_TX_1"
bitfld.long 0x00 24. "I3C0_RX,I3C RX enable" "0: I3C0_RX_0,1: I3C0_RX_1"
newline
bitfld.long 0x00 23. "DMIC0_CH7_FLEXCOMM13_TX_DMA,DMIC0 channel 7 / FLEXCOMM13 TX DMA enable" "0: DMIC0_CH7_FLEXCOMM13_TX_DMA_0,1: DMIC0_CH7_FLEXCOMM13_TX_DMA_1"
bitfld.long 0x00 22. "DMIC0_CH6_FLEXCOMM13_RX_DMA,DMIC0 channel 6 / FLEXCOMM13 RX DMA enable" "0: DMIC0_CH6_FLEXCOMM13_RX_DMA_0,1: DMIC0_CH6_FLEXCOMM13_RX_DMA_1"
newline
bitfld.long 0x00 21. "DMIC0_CH5_FLEXCOMM10_TX_DMA,DMIC0 channel 5 / FLEXCOMM10 TX DMA enable" "0: DMIC0_CH2_FLEXCOMM10_TX_DMA_0,1: DMIC0_CH2_FLEXCOMM10_TX_DMA_1"
bitfld.long 0x00 20. "DMIC0_CH4_FLEXCOMM10_RX_DMA,DMIC0 channel 4 / FLEXCOMM10 RX DMA enable" "0: DMIC0_CH4_FLEXCOMM10_RX_DMA_0,1: DMIC0_CH4_FLEXCOMM10_RX_DMA_1"
newline
bitfld.long 0x00 19. "DMIC0_CH3_FLEXCOMM9_TX_DMA,DMIC0 channel 3 / FLEXCOMM9 TX DMA enable" "0: DMIC0_CH3_FLEXCOMM9_TX_DMA_0,1: DMIC0_CH3_FLEXCOMM9_TX_DMA_1"
bitfld.long 0x00 18. "DMIC0_CH2_FLEXCOMM9_RX_DMA,DMIC0 channel 2/ FLEXCOMM9 RX DMA enable" "0: DMIC0_CH2_FLEXCOMM9_RX_DMA_0,1: DMIC0_CH2_FLEXCOMM9_RX_DMA_1"
newline
bitfld.long 0x00 17. "DMIC0_CH1_FLEXCOMM8_TX_DMA,DMIC0 channel 1 / FLEXCOMM8 TX DMA enable" "0: DMIC0_CH1_FLEXCOMM8_TX_DMA_0,1: DMIC0_CH1_FLEXCOMM8_TX_DMA_1"
bitfld.long 0x00 16. "DMIC0_CH0_FLEXCOMM8_RX_DMA,DMIC0 channel 0 / FLEXCOMM8 RX DMA enable" "0: DMIC0_CH0_FLEXCOMM8_RX_DMA_0,1: DMIC0_CH0_FLEXCOMM8_RX_DMA_1"
newline
bitfld.long 0x00 15. "FLEXCOMM7_TX,FLEXCOMM7_TX" "0: FLEXCOMM7_TX_0,1: FLEXCOMM7_TX_1"
bitfld.long 0x00 14. "FLEXCOMM7_RX,FLEXCOMM7_RX" "0: FLEXCOMM5_RX_0,1: FLEXCOMM5_RX_1"
newline
bitfld.long 0x00 13. "FLEXCOMM6_TX,FLEXCOMM6_TX" "0: FLEXCOMM6_TX_0,1: FLEXCOMM6_TX_1"
bitfld.long 0x00 12. "FLEXCOMM6_RX,FLEXCOMM6_RX" "0: FLEXCOMM6_RX_0,1: FLEXCOMM6_RX_1"
newline
bitfld.long 0x00 11. "FLEXCOMM5_TX,FLEXCOMM5_TX" "0: FLEXCOMM5_TX_0,1: FLEXCOMM5_TX_1"
bitfld.long 0x00 10. "FLEXCOMM5_RX,FLEXCOMM5_RX" "0: FLEXCOMM5_RX_0,1: FLEXCOMM5_RX_1"
newline
bitfld.long 0x00 9. "FLEXCOMM4_TX,FLEXCOMM4_TX" "0: FLEXCOMM4_TX_0,1: FLEXCOMM4_TX_1"
bitfld.long 0x00 8. "FLEXCOMM4_RX,FLEXCOMM4_RX" "0: FLEXCOMM4_RX_0,1: FLEXCOMM4_RX_1"
newline
bitfld.long 0x00 7. "FLEXCOMM3_TX,FLEXCOMM3_TX" "0: FLEXCOMM3_TX_1,1: FLEXCOMM3_TX_0"
bitfld.long 0x00 6. "FLEXCOMM3_RX,FLEXCOMM3_RX" "0: FLEXCOMM3_RX_0,1: FLEXCOMM3_RX_1"
newline
bitfld.long 0x00 5. "FLEXCOMM2_TX,FLEXCOMM2_TX" "0: FLEXCOMM2_TX_0,1: FLEXCOMM2_TX_1"
bitfld.long 0x00 4. "FLEXCOMM2_RX,FLEXCOMM2_RX" "0: FLEXCOMM2_RX_0,1: FLEXCOMM2_RX_1"
newline
bitfld.long 0x00 3. "FLEXCOMM1_TX,FLEXCOMM1_TX" "0: FLEXCOMM1_TX_0,1: FLEXCOMM1_TX_1"
bitfld.long 0x00 2. "FLEXCOMM1_RX,FLEXCOMM1_RX" "0: FLEXCOMM1_RX_0,1: FLEXCOMM1_RX_1"
newline
bitfld.long 0x00 1. "FLEXCOMM0_TX,FLEXCOMM0_TX" "0: FLEXCOMM0_TX_0,1: FLEXCOMM0_TX_1"
bitfld.long 0x00 0. "FLEXCOMM0_RX,FLEXCOMM0_RX" "0: FLEXCOMM0_RX_0,1: FLEXCOMM0_RX_1"
group.long 0x764++0x03
line.long 0x00 "DMAC1_REQ_ENA1,DMAC1 request enable 1"
bitfld.long 0x00 4. "HASHCRYPT_IN,HASHCRYPT_IN" "0: HASHCRYPT_IN_0,1: HASHCRYPT_IN_1"
bitfld.long 0x00 3. "FLEXIO_SHFT3_FLEXCOMM12_TX,FLEXIO_SHFT3_FLEXCOMM12_TX" "0: FLEXIO_SHFT3_FLEXCOMM12_TX_0,1: FLEXIO_SHFT3_FLEXCOMM12_TX_1"
newline
bitfld.long 0x00 2. "FLEXIO_SHFT2_FLEXCOMM12_RX,FLEXIO_SHFT2_FLEXCOMM12_RX" "0: FLEXIO_SHFT2_FLEXCOMM12_RX_0,1: FLEXIO_SHFT2_FLEXCOMM12_RX_1"
bitfld.long 0x00 1. "FLEXIO_SHFT1_FLEXCOMM11_TX,FLEXIO_SHFT1_FLEXCOMM11_TX" "0: FLEXIO_SHFT1_FLEXCOMM11_TX_0,1: FLEXIO_SHFT1_FLEXCOMM11_TX_1"
newline
bitfld.long 0x00 0. "FLEXIO_SHFT0_FLEXCOMM11_RX,FLEXIO_SHFT0_FLEXCOMM11_RX" "0: FLEXIO_SHFT0_FLEXCOMM11_RX_0,1: FLEXIO_SHFT0_FLEXCOMM11_RX_1"
group.long 0x768++0x03
line.long 0x00 "DMAC1_REQ_ENA0_SET,DMAC1 request enable set 0"
bitfld.long 0x00 31. "I3C1_TX_FLEXIO_SHFT7,I3C1_TX / FLEXIO_SHFT7 enable" "0: I3C1_TX_FLEXIO_SHFT7_0,1: I3C1_TX_FLEXIO_SHFT7_1"
bitfld.long 0x00 30. "I3C1_RX_FLEXIO_SHFT6,I3C1_RX / FLEXIO_SHFT6 enable" "0: I3C1_RX_FLEXIO_SHFT6_0,1: I3C1_RX_FLEXIO_SHFT6_1"
newline
bitfld.long 0x00 29. "FLEXCOMM16_TX_FLEXIO_SHFT5,FLEXCOMM16 TX / FLEXIO_SHFT5 enable" "0: FLEXCOMM16_TX_FLEXIO_SHFT5_0,1: FLEXCOMM16_TX_FLEXIO_SHFT5_1"
bitfld.long 0x00 28. "FLEXCOMM16_RX_FLEXIO_SHFT4,FLEXCOMM16 RX / FLEXIO_SHFT4 enable" "0: FLEXCOMM16_RX_0,1: Sets the ENA0 bit"
newline
bitfld.long 0x00 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable set" "0: FLEXCOMM14_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable set" "0: FLEXCOMM14_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 25. "I3C0_TX,I3C TX enable set" "0: I3C0_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 24. "I3C0_RX,I3C RX enable set" "0: I3C0_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 23. "DMIC0_CH7_FLEXCOMM13_TX_DMA,DMIC0 channel 7 / FLEXCOMM13 TX DMA enable" "0: DMIC0_CH7_FLEXCOMM13_TX_DMA_0,1: DMIC0_CH7_FLEXCOMM13_TX_DMA_1"
bitfld.long 0x00 22. "DMIC0_CH6_FLEXCOMM13_RX_DMA,DMIC0 channel 6 / FLEXCOMM13 RX DMA enable" "0: DMIC0_CH6_FLEXCOMM13_RX_DMA_0,1: DMIC0_CH6_FLEXCOMM13_RX_DMA_1"
newline
bitfld.long 0x00 21. "DMIC0_CH5_FLEXCOMM10_TX_DMA,DMIC0 channel 5 / FLEXCOMM10 TX DMA enable" "0: DMIC0_CH5_FLEXCOMM10_TX_DMA_0,1: DMIC0_CH5_FLEXCOMM10_TX_DMA_1"
bitfld.long 0x00 20. "DMIC0_CH4_FLEXCOMM10_RX_DMA,DMIC0 channel 4 / FLEXCOMM10 RX DMA enable" "0: DMIC0_CH4_FLEXCOMM10_RX_DMA_0,1: DMIC0_CH4_FLEXCOMM10_RX_DMA_1"
newline
bitfld.long 0x00 19. "DMIC0_CH3_FLEXCOMM9_TX_DMA,DMIC0 channel 3 / FLEXCOMM9 TX DMA enable" "0: DMIC0_CH3_FLEXCOMM9_TX_DMA_0,1: DMIC0_CH3_FLEXCOMM9_TX_DMA_1"
bitfld.long 0x00 18. "DMIC0_CH2_FLEXCOMM9_RX_DMA,DMIC0 channel 2 / FLEXCOMM9 RX DMA enable" "0: DMIC0_CH2_FLEXCOMM9_RX_DMA_0,1: DMIC0_CH2_FLEXCOMM9_RX_DMA_1"
newline
bitfld.long 0x00 17. "DMIC0_CH1_FLEXCOMM8_TX_DMA,DMIC0 channel 1 / FLEXCOMM8 TX DMA enable" "0: DMIC0_CH1_FLEXCOMM8_TX_DMA_0,1: DMIC0_CH1_FLEXCOMM8_TX_DMA_1"
bitfld.long 0x00 16. "DMIC0_CH0_FLEXCOMM8_RX_DMA,DMIC0 channel 0 / FLEXCOMM8 RX DMA enable" "0: DMIC0_CH0_FLEXCOMM8_RX_DMA_0,1: DMIC0_CH0_FLEXCOMM8_RX_DMA_1"
newline
bitfld.long 0x00 15. "FLEXCOMM7_TX,FLEXCOMM7 TX enable" "0: FLEXCOMM7_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 14. "FLEXCOMM7_RX,FLEXCOMM7 RX enable" "0: FLEXCOMM5_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 13. "FLEXCOMM6_TX,FLEXCOMM6 TX enable" "0: FLEXCOMM6_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 12. "FLEXCOMM6_RX,FLEXCOMM6 RX enable" "0: FLEXCOMM6_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable set" "0: FLEXCOMM5_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable set" "0: FLEXCOMM5_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable set" "0: FLEXCOMM4_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable set" "0: FLEXCOMM4_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable set" "0: FLEXCOMM3_TX_1,1: Sets the ENA0 Bit"
bitfld.long 0x00 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable set" "0: FLEXCOMM3_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable set" "0: FLEXCOMM2_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable set" "0: FLEXCOMM2_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable set" "0: FLEXCOMM1_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable set" "0: FLEXCOMM1_RX_0,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable set" "0: FLEXCOMM0_TX_0,1: Sets the ENA0 Bit"
bitfld.long 0x00 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable set" "0: FLEXCOMM0_RX_0,1: Sets the ENA0 Bit"
group.long 0x76C++0x03
line.long 0x00 "DMAC1_REQ_ENA1_SET,DMAC1 request enable set 1"
bitfld.long 0x00 4. "HASHCRYPT_IN,HASHCRYPT_IN" "0: HASHCRYPT_IN_0,1: Sets the ENA1 Bit"
bitfld.long 0x00 3. "FLEXIO_SHFT3_FLEXCOMM12_TX,FLEXIO_SHFT3_FLEXCOMM12_TX" "0: FLEXIO_SHFT3_FLEXCOMM12_TX_0,1: FLEXIO_SHFT3_FLEXCOMM12_TX_1"
newline
bitfld.long 0x00 2. "FLEXIO_SHFT2_FLEXCOMM12_RX,FLEXIO_SHFT2_FLEXCOMM12_RX" "0: FLEXIO_SHFT2_FLEXCOMM12_RX_0,1: FLEXIO_SHFT2_FLEXCOMM12_RX_1"
bitfld.long 0x00 1. "FLEXIO_SHFT1_FLEXCOMM11_TX,FLEXIO_SHFT_FLEXCOMM_TX" "0: FLEXIO_SHFT1_FLEXCOMM11_TX_0,1: FLEXIO_SHFT1_FLEXCOMM11_TX_1"
newline
bitfld.long 0x00 0. "FLEXIO_SHFT0_FLEXCOMM11_RX,FLEXIO_SHFT_FLEXCOMM_RX" "0: FLEXIO_SHFT0_FLEXCOMM11_RX_0,1: FLEXIO_SHFT0_FLEXCOMM11_RX_1"
group.long 0x770++0x03
line.long 0x00 "DMAC1_REQ_ENA0_CLR,DMAC1 request enable clear 0"
bitfld.long 0x00 31. "I3C1_TX_FLEXIO_SHFT7,I3C1_TX / FLEXIO_SHFT7 enable" "0: I3C1_TX_FLEXIO_SHFT7_0,1: I3C1_TX_FLEXIO_SHFT7_1"
bitfld.long 0x00 30. "I3C1_RX_FLEXIO_SHFT6,I3C1_RX / FLEXIO_SHFT6 enable" "0: I3C1_RX_FLEXIO_SHFT6_0,1: I3C1_RX_FLEXIO_SHFT6_1"
newline
bitfld.long 0x00 29. "FLEXCOMM16_TX_FLEXIO_SHFT5,FLEXCOMM16 TX / FLEXIO_SHFT5 enable" "0: FLEXCOMM16_TX_FLEXIO_SHFT5_0,1: FLEXCOMM16_TX_FLEXIO_SHFT5_1"
bitfld.long 0x00 28. "FLEXCOMM16_RX_FLEXIO_SHFT4,FLEXCOMM16 RX / FLEXIO_SHFT4 enable" "0: FLEXCOMM16_RX_0,1: Clears the ENA0 bit"
newline
bitfld.long 0x00 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable clear" "0: FLEXCOMM14_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable clear" "0: FLEXCOMM14_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 25. "I3C0_TX,I3C TX enable clear" "0: I3C0_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 24. "I3C0_RX,I3C RX enable clear" "0: I3C0_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 23. "DMIC0_CH7_FLEXCOMM13_TX_DMA,DMIC0 channel 7 / FLEXCOMM13 TX DMA enable" "0: DMIC0_CH7_FLEXCOMM13_TX_DMA_0,1: DMIC0_CH7_FLEXCOMM13_TX_DMA_1"
bitfld.long 0x00 22. "DMIC0_CH6_FLEXCOMM13_RX_DMA,DMIC0 channel 6 / FLEXCOMM13 RX DMA enable" "0: DMIC0_CH6_FLEXCOMM13_RX_DMA_0,1: DMIC0_CH6_FLEXCOMM13_RX_DMA_1"
newline
bitfld.long 0x00 21. "DMIC0_CH5_FLEXCOMM10_TX_DMA,DMIC0 channel 5 / FLEXCOMM10 TX DMA enable" "0: DMIC0_CH5_FLEXCOMM10_TX_DMA_0,1: DMIC0_CH5_FLEXCOMM10_TX_DMA_1"
bitfld.long 0x00 20. "DMIC0_CH4_FLEXCOMM10_RX_DMA,DMIC0 channel 4 / FLEXCOMM10 RX DMA enable" "0: DMIC0_CH4_FLEXCOMM10_RX_DMA_0,1: DMIC0_CH4_FLEXCOMM10_RX_DMA_1"
newline
bitfld.long 0x00 19. "DMIC0_CH3_FLEXCOMM9_TX_DMA,DMIC0 channel 3 / FLEXCOMM9 TX DMA enable" "0: DMIC0_CH3_FLEXCOMM9_TX_DMA_0,1: DMIC0_CH3_FLEXCOMM9_TX_DMA_1"
bitfld.long 0x00 18. "DMIC0_CH2_FLEXCOMM9_RX_DMA,DMIC0 channel 2 / FLEXCOMM9 RX DMA enable" "0: DMIC0_CH2_FLEXCOMM9_RX_DMA_0,1: DMIC0_CH2_FLEXCOMM9_RX_DMA_1"
newline
bitfld.long 0x00 17. "DMIC0_CH1_FLEXCOMM8_TX_DMA,DMIC0 channel 1 / FLEXCOMM8 TX DMA enable" "0: DMIC0_CH1_FLEXCOMM8_TX_DMA_0,1: DMIC0_CH1_FLEXCOMM8_TX_DMA_1"
bitfld.long 0x00 16. "DMIC0_CH0_FLEXCOMM8_RX_DMA,DMIC0 channel 0 / FLEXCOMM8_RX_DMA enable" "0: DMIC0_CH0_FLEXCOMM8_RX_DMA_0,1: DMIC0_CH0_FLEXCOMM8_RX_DMA_1"
newline
bitfld.long 0x00 15. "FLEXCOMM7_TX,FLEXCOMM7 TX enable" "0: FLEXCOMM7_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 14. "FLEXCOMM7_RX,FLEXCOMM7 RX enable" "0: FLEXCOMM5_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 13. "FLEXCOMM6_TX,FLEXCOMM6 TX enable" "0: FLEXCOMM6_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 12. "FLEXCOMM6_RX,FLEXCOMM6 RX enable" "0: FLEXCOMM6_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable clear" "0: FLEXCOMM5_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable clear" "0: FLEXCOMM5_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable clear" "0: FLEXCOMM4_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable clear" "0: FLEXCOMM4_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable clear" "0: FLEXCOMM3_TX_1,1: Clears the ENA0 Bit"
bitfld.long 0x00 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable clear" "0: FLEXCOMM3_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable clear" "0: FLEXCOMM2_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable clear" "0: FLEXCOMM2_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable clear" "0: FLEXCOMM1_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable clear" "0: FLEXCOMM1_RX_0,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable clear" "0: FLEXCOMM0_TX_0,1: Clears the ENA0 Bit"
bitfld.long 0x00 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable clear" "0: FLEXCOMM0_RX_0,1: Clears the ENA0 Bit"
group.long 0x774++0x03
line.long 0x00 "DMAC1_REQ_ENA1_CLR,DMAC1 request enable 1 clear"
bitfld.long 0x00 4. "HASHCRYPT_IN,HASHCRYPT_IN" "0: HASHCRYPT_IN_0,1: Clears the ENA1 Bit"
bitfld.long 0x00 3. "FLEXIO_SHFT3_FLEXCOMM12_TX,FLEXIO_SHFT3_FLEXCOMM12_TX" "0: FLEXIO_SHFT3_FLEXCOMM12_TX_0,1: FLEXIO_SHFT3_FLEXCOMM12_TX_1"
newline
bitfld.long 0x00 2. "FLEXIO_SHFT2_FLEXCOMM12_RX,FLEXIO_SHFT2_FLEXCOMM12_RX" "0: FLEXIO_SHFT2_FLEXCOMM12_RX_0,1: FLEXIO_SHFT2_FLEXCOMM12_RX_1"
bitfld.long 0x00 1. "FLEXIO_SHFT1_FLEXCOMM11_TX,FLEXIO_SHFT1_FLEXCOMM11_TX" "0: FLEXIO_SHFT1_FLEXCOMM11_TX_0,1: FLEXIO_SHFT1_FLEXCOMM11_TX_1"
newline
bitfld.long 0x00 0. "FLEXIO_SHFT0_FLEXCOMM11_RX,FLEXIO_SHFT0_FLEXCOMM11_RX" "0: FLEXIO_SHFT0_FLEXCOMM11_RX_0,1: FLEXIO_SHFT0_FLEXCOMM11_RX_1"
group.long 0x780++0x03
line.long 0x00 "DMAC0_ITRIG_ENA0,DMAC0 Input Trigger Enable 0"
bitfld.long 0x00 26. "FLEXSPI1_TX,FlexSPI1_TX" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 25. "FLEXSPI1_RX,FlexSPI1_RX" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 24. "ADC,ADC" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 23. "FLEXSPI0_TX,FlexSPI0_TX" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 22. "FLEXSPI0_RX,FlexSPI0_RX" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 21. "ACMP,ACMP" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 20. "HASHCRYPT_OUT,HASHCRYPT_OUT" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 19. "SCT_DMA_REQ1,SCT_DMA_REQ1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 18. "SCT_DMA_REQ0,SCT_DMA_REQ0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 17. "DMA_TRIGOUT_D,DMA_TRIGOUT_D" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 16. "DMA_TRIGOUT_C,DMA_TRIGOUT_C" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 15. "DMA_TRIGOUT_B,DMA_TRIGOUT_B" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 14. "DMA_TRIGOUT_A,DMA_TRIGOUT_A" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 13. "T4_DMAREQ_M1,T4_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 12. "T4_DMAREQ_M0,T4_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 11. "T3_DMAREQ_M1,T3_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 10. "T3_DMAREQ_M0,T3_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 9. "T2_DMAREQ_M1,T2_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 8. "T2_DMAREQ_M0,T2_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 7. "T1_DMAREQ_M1,T1_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 6. "T1_DMAREQ_M0,T1_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 5. "T0_DMAREQ_M1,T0_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 4. "T0_DMAREQ_M0,T0_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 3. "GPIO_INT3,GPIO_INT3" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 2. "GPIO_INT2,GPIO_INT2" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 1. "GPIO_INT1,GPIO_INT1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 0. "GPIO_INT0,GPIO_INT0" "0: DISABLE,1: ENABLE"
wgroup.long 0x788++0x03
line.long 0x00 "DMAC0_ITRIG_ENA0_SET,DMAC0 Input Trigger Enable 0 Set"
bitfld.long 0x00 26. "FLEXSPI1_TX,FlexSPI1_TX set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 25. "FLEXSPI1_RX,FlexSPI1_RX set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 24. "ADC,ADC set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 23. "FLEXSPI0_TX,FlexSPI0_TX set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 22. "FLEXSPI0_RX,FlexSPI0_RX set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 21. "ACMP,ACMP set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 20. "HASHCRYPT_OUT,HASHCRYPT_OUT set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 19. "SCT_DMA_REQ1,SCT_DMA_REQ1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 18. "SCT_DMA_REQ0,SCT_DMA_REQ0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 17. "SDMA0_TRIGOUT_D,SDMA0_TRIGOUT_D set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 16. "SDMA0_TRIGOUT_C,SDMA0_TRIGOUT_C set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 15. "SDMA0_TRIGOUT_B,SDMA0_TRIGOUT_B set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 14. "SDMA0_TRIGOUT_A,SDMA0_TRIGOUT_Aset" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 13. "T4_DMAREQ_M1,T4_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 12. "T4_DMAREQ_M0,T4_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 11. "T3_DMAREQ_M1,T3_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 10. "T3_DMAREQ_M0,T3_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 9. "T2_DMAREQ_M1,T2_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 8. "T2_DMAREQ_M0,T2_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 7. "T1_DMAREQ_M1,T1_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 6. "T1_DMAREQ_M0,T1_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 5. "T0_DMAREQ_M1,T0_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 4. "T0_DMAREQ_M0,T0_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 3. "GPIO_INT3,GPIO_INT3 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 2. "GPIO_INT2,GPIO_INT2 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 1. "GPIO_INT1,GPIO_INT1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 0. "GPIO_INT0,GPIO_INT0 set" "0: No Effect,1: Sets the ENA0 Bit"
wgroup.long 0x790++0x03
line.long 0x00 "DMAC0_ITRIG_ENA0_CLR,DMAC0 Input Trigger Enable 0 Clear"
bitfld.long 0x00 26. "FLEXSPI1_TX,FlexSPI1_TX clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 25. "FLEXSPI1_RX,FlexSPI1_RX clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 24. "ADC,ADC clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 23. "FLEXSPI0_TX,FlexSPI0_TX clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 22. "FLEXSPI0_RX,FlexSPI0_RX clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 21. "ACMP,ACMP clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 20. "HASHCRYPT_OUT,HASHCRYPT_OUT clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 19. "SCT_DMA_REQ1,SCT_DMA_REQ1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 18. "SCT_DMA_REQ0,SCT_DMA_REQ0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 17. "SDMA0_TRIGOUT_D,SDMA0_TRIGOUT_D clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 16. "SDMA0_TRIGOUT_C,SDMA0_TRIGOUT_C clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 15. "SDMA0_TRIGOUT_B,SDMA0_TRIGOUT_B clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 14. "SDMA0_TRIGOUT_A,SDMA0_TRIGOUT_A clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 13. "T4_DMAREQ_M1,T4_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 12. "T4_DMAREQ_M0,T4_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 11. "T3_DMAREQ_M1,T3_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 10. "T3_DMAREQ_M0,T3_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 9. "T2_DMAREQ_M1,T2_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 8. "T2_DMAREQ_M0,T2_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 7. "T1_DMAREQ_M1,T1_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 6. "T1_DMAREQ_M0,T1_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 5. "T0_DMAREQ_M1,T0_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 4. "T0_DMAREQ_M0,T0_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 3. "GPIO_INT3,GPIO_INT3 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 2. "GPIO_INT2,GPIO_INT2 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 1. "GPIO_INT1,GPIO_INT1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 0. "GPIO_INT0,GPIO_INT0 clear" "0: No Effect,1: Clears the ENA0 Bit"
group.long 0x7A0++0x03
line.long 0x00 "DMAC1_ITRIG_ENA0,DMAC1 Input Trigger Enable 0"
bitfld.long 0x00 26. "FLEXSPI1_TX,FlexSPI1_TX" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 25. "FLEXSPI1_RX,FlexSPI1_RX" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 24. "ADC,ADC" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 23. "FLEXSPI0_TX,FlexSPI0_TX" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 22. "FLEXSPI0_RX,FlexSPI0_RX" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 21. "ACMP,ACMP" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 20. "HASHCRYPT_OUT,HASHCRYPT_OUT" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 19. "SCT_DMA_REQ1,SCT_DMA_REQ1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 18. "SCT_DMA_REQ0,SCT_DMA_REQ0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 17. "DMA_TRIGOUT_D,DMA_TRIGOUT_D" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 16. "DMA_TRIGOUT_C,DMA_TRIGOUT_C" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 15. "DMA_TRIGOUT_B,DMA_TRIGOUT_B" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 14. "DMA_TRIGOUT_A,DMA_TRIGOUT_A" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 13. "T4_DMAREQ_M1,T4_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 12. "T4_DMAREQ_M0,T4_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 11. "T3_DMAREQ_M1,T3_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 10. "T3_DMAREQ_M0,T3_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 9. "T2_DMAREQ_M1,T2_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 8. "T2_DMAREQ_M0,T2_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 7. "T1_DMAREQ_M1,T1_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 6. "T1_DMAREQ_M0,T1_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 5. "T0_DMAREQ_M1,T0_DMAREQ_M1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 4. "T0_DMAREQ_M0,T0_DMAREQ_M0" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 3. "GPIO_INT3,GPIO_INT3" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 2. "GPIO_INT2,GPIO_INT2" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 1. "GPIO_INT1,GPIO_INT1" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 0. "GPIO_INT0,GPIO_INT0" "0: DISABLE,1: ENABLE"
wgroup.long 0x7A8++0x03
line.long 0x00 "DMAC1_ITRIG_ENA0_SET,DMAC1 Input Trigger Enable 0 set"
bitfld.long 0x00 26. "FLEXSPI1_TX,FlexSPI1_TX set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 25. "FLEXSPI1_RX,FlexSPI1_RX set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 24. "ADC,ADC set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 23. "FLEXSPI0_TX,FlexSPI0_TX set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 22. "FLEXSPI0_RX,FlexSPI0_RX set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 21. "ACMP,ACMP set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 20. "HASHCRYPT_OUT,HASHCRYPT_OUT set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 19. "SCT_DMA_REQ1,SCT_DMA_REQ1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 18. "SCT_DMA_REQ0,SCT_DMA_REQ0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 17. "SDMA0_TRIGOUT_D,SDMA0_TRIGOUT_D set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 16. "SDMA0_TRIGOUT_C,SDMA0_TRIGOUT_C set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 15. "SDMA0_TRIGOUT_B,SDMA0_TRIGOUT_B set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 14. "SDMA0_TRIGOUT_A,SDMA0_TRIGOUT_A set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 13. "T4_DMAREQ_M1,T4_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 12. "T4_DMAREQ_M0,T4_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 11. "T3_DMAREQ_M1,T3_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 10. "T3_DMAREQ_M0,T3_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 9. "T2_DMAREQ_M1,T2_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 8. "T2_DMAREQ_M0,T2_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 7. "T1_DMAREQ_M1,T1_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 6. "T1_DMAREQ_M0,T1_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 5. "T0_DMAREQ_M1,T0_DMAREQ_M1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 4. "T0_DMAREQ_M0,T0_DMAREQ_M0 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 3. "GPIO_INT3,GPIO_INT3 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 2. "GPIO_INT2,GPIO_INT2 set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x00 1. "GPIO_INT1,GPIO_INT1 set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x00 0. "GPIO_INT0,GPIO_INT0 set" "0: No Effect,1: Sets the ENA0 Bit"
wgroup.long 0x7B0++0x03
line.long 0x00 "DMAC1_ITRIG_ENA0_CLR,DMAC1 Input Trigger Enable 0 clear"
bitfld.long 0x00 26. "FLEXSPI1_TX,FlexSPI1_TX clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 25. "FLEXSPI1_RX,FlexSPI1_RX clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 24. "ADC,ADC clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 23. "FLEXSPI0_TX,FlexSPI0_TX clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 22. "FLEXSPI0_RX,FlexSPI0_RXclear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 21. "ACMP,ACMP clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 20. "HASHCRYPT_OUT,HASHCRYPT_OUTclear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 19. "SCT_DMA_REQ1,SCT_DMA_REQ1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 18. "SCT_DMA_REQ0,SCT_DMA_REQ0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 17. "SDMA0_TRIGOUT_D,SDMA0_TRIGOUT_D clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 16. "SDMA0_TRIGOUT_C,SDMA0_TRIGOUT_C clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 15. "SDMA0_TRIGOUT_B,SDMA0_TRIGOUT_B clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 14. "SDMA0_TRIGOUT_A,SDMA0_TRIGOUT_A clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 13. "T4_DMAREQ_M1,T4_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 12. "T4_DMAREQ_M0,T4_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 11. "T3_DMAREQ_M1,T3_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 10. "T3_DMAREQ_M0,T3_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 9. "T2_DMAREQ_M1,T2_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 8. "T2_DMAREQ_M0,T2_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 7. "T1_DMAREQ_M1,T1_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 6. "T1_DMAREQ_M0,T1_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 5. "T0_DMAREQ_M1,T0_DMAREQ_M1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 4. "T0_DMAREQ_M0,T0_DMAREQ_M0 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 3. "GPIO_INT3,GPIO_INT3 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 2. "GPIO_INT2,GPIO_INT2 clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x00 1. "GPIO_INT1,GPIO_INT1 clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x00 0. "GPIO_INT0,GPIO_INT0 clear" "0: No Effect,1: Clears the ENA0 Bit"
endif
repeat 5. (increment 0 1)(increment 0 0x10)
tree "CT32BIT_CAP_SEL[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0x600)++0x03
line.long 0x00 "CT32BIT_CAP_SEL[0],CT32BIT Timer Capture Multiplexers"
bitfld.long 0x00 0.--4. "CAPn_SEL,Counter Timer n Capture Input m" "0: CT_INP0 (function must be selected in IOPCTL),1: CT_INP1 (function must be selected in IOPCTL),2: CT_INP2 (function must be selected in IOPCTL),3: CT_INP3 (function must be selected in IOPCTL),4: CT_INP4 (function must be selected in IOPCTL),5: CT_INP5 (function must be selected in IOPCTL),6: CT_INP6 (function must be selected in IOPCTL),7: CT_INP7 (function must be selected in IOPCTL),8: CT_INP8 (function must be selected in IOPCTL),9: CT_INP9 (function must be selected in IOPCTL),10: CT_INP10 (function must be selected in IOPCTL),11: CT_INP11 (function must be selected in IOPCTL),12: CT_INP12 (function must be selected in IOPCTL),13: CT_INP13 (function must be selected in IOPCTL),14: CT_INP14 (function must be selected in IOPCTL),15: CT_INP15 (function must be selected in IOPCTL),16: SHARED I2S0_WS,17: SHARED I2S1_WS,18: USB1_FRAME_TOGGLE (see USB Controller Chapter),?..."
group.long ($2+0x604)++0x03
line.long 0x00 "CT32BIT_CAP_SEL[1],CT32BIT Timer Capture Multiplexers"
bitfld.long 0x00 0.--4. "CAPn_SEL,Counter Timer n Capture Input m" "0: CT_INP0 (function must be selected in IOPCTL),1: CT_INP1 (function must be selected in IOPCTL),2: CT_INP2 (function must be selected in IOPCTL),3: CT_INP3 (function must be selected in IOPCTL),4: CT_INP4 (function must be selected in IOPCTL),5: CT_INP5 (function must be selected in IOPCTL),6: CT_INP6 (function must be selected in IOPCTL),7: CT_INP7 (function must be selected in IOPCTL),8: CT_INP8 (function must be selected in IOPCTL),9: CT_INP9 (function must be selected in IOPCTL),10: CT_INP10 (function must be selected in IOPCTL),11: CT_INP11 (function must be selected in IOPCTL),12: CT_INP12 (function must be selected in IOPCTL),13: CT_INP13 (function must be selected in IOPCTL),14: CT_INP14 (function must be selected in IOPCTL),15: CT_INP15 (function must be selected in IOPCTL),16: SHARED I2S0_WS,17: SHARED I2S1_WS,18: USB1_FRAME_TOGGLE (see USB Controller Chapter),?..."
group.long ($2+0x608)++0x03
line.long 0x00 "CT32BIT_CAP_SEL[2],CT32BIT Timer Capture Multiplexers"
bitfld.long 0x00 0.--4. "CAPn_SEL,Counter Timer n Capture Input m" "0: CT_INP0 (function must be selected in IOPCTL),1: CT_INP1 (function must be selected in IOPCTL),2: CT_INP2 (function must be selected in IOPCTL),3: CT_INP3 (function must be selected in IOPCTL),4: CT_INP4 (function must be selected in IOPCTL),5: CT_INP5 (function must be selected in IOPCTL),6: CT_INP6 (function must be selected in IOPCTL),7: CT_INP7 (function must be selected in IOPCTL),8: CT_INP8 (function must be selected in IOPCTL),9: CT_INP9 (function must be selected in IOPCTL),10: CT_INP10 (function must be selected in IOPCTL),11: CT_INP11 (function must be selected in IOPCTL),12: CT_INP12 (function must be selected in IOPCTL),13: CT_INP13 (function must be selected in IOPCTL),14: CT_INP14 (function must be selected in IOPCTL),15: CT_INP15 (function must be selected in IOPCTL),16: SHARED I2S0_WS,17: SHARED I2S1_WS,18: USB1_FRAME_TOGGLE (see USB Controller Chapter),?..."
group.long ($2+0x60C)++0x03
line.long 0x00 "CT32BIT_CAP_SEL[3],CT32BIT Timer Capture Multiplexers"
bitfld.long 0x00 0.--4. "CAPn_SEL,Counter Timer n Capture Input m" "0: CT_INP0 (function must be selected in IOPCTL),1: CT_INP1 (function must be selected in IOPCTL),2: CT_INP2 (function must be selected in IOPCTL),3: CT_INP3 (function must be selected in IOPCTL),4: CT_INP4 (function must be selected in IOPCTL),5: CT_INP5 (function must be selected in IOPCTL),6: CT_INP6 (function must be selected in IOPCTL),7: CT_INP7 (function must be selected in IOPCTL),8: CT_INP8 (function must be selected in IOPCTL),9: CT_INP9 (function must be selected in IOPCTL),10: CT_INP10 (function must be selected in IOPCTL),11: CT_INP11 (function must be selected in IOPCTL),12: CT_INP12 (function must be selected in IOPCTL),13: CT_INP13 (function must be selected in IOPCTL),14: CT_INP14 (function must be selected in IOPCTL),15: CT_INP15 (function must be selected in IOPCTL),16: SHARED I2S0_WS,17: SHARED I2S1_WS,18: USB1_FRAME_TOGGLE (see USB Controller Chapter),?..."
endif
tree.end
repeat.end
tree.end
tree "IOPCTL"
base ad:0x40004000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x00)++0x03
line.long 0x00 "PIO0_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x40)++0x03
line.long 0x00 "PIO0_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x80)++0x03
line.long 0x00 "PIO1_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC0)++0x03
line.long 0x00 "PIO1_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "PIO2_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x140)++0x03
line.long 0x00 "PIO2_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "PIO3_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C0)++0x03
line.long 0x00 "PIO3_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "PIO4_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "PIO4_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "PIO5_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2C0)++0x03
line.long 0x00 "PIO5_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x300)++0x03
line.long 0x00 "PIO6_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x340)++0x03
line.long 0x00 "PIO6_$1,IOPCTL configuration"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
repeat.end
group.long 0x400++0x03
line.long 0x00 "FC15_I2C_SCL,Flexcomm 15 SCL"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
group.long 0x404++0x03
line.long 0x00 "FC15_I2C_SDA,Flexcomm 15 SDA"
bitfld.long 0x00 11. "IIENA,Input Invert Enable" "0: Disabled Input function is not inverted,1: Enabled Input is function inverted"
bitfld.long 0x00 10. "ODENA,Open-drain mode enable" "0: Normal push-pull output,1: Simulated open-drain output (high drive.."
newline
bitfld.long 0x00 9. "AMENA,Analog Mux Enable" "0: Analog multiplexor disabled required for..,1: Analog multiplexor enabled required for.."
bitfld.long 0x00 8. "FULLDRIVE,Drive Selector" "0: Normal output drive,1: Full output drive twice the drive of normal.."
newline
bitfld.long 0x00 7. "SLEWRATE,Slew Rate Control" "0: Standard mode output slew rate is not..,1: Slow mode output slew rate control is enabled.."
bitfld.long 0x00 6. "IBENA,Input Buffer Enable" "0: Input buffer disabled,1: Input buffer enabled"
newline
bitfld.long 0x00 5. "PUPDSEL,Pullup or Pulldown Selector" "0: PUPDSEL_0,1: PUPDSEL_1"
bitfld.long 0x00 4. "PUPDENA,Pullup / Pulldown Enable" "0: PUPDENA_0,1: PUPDENA_1"
newline
bitfld.long 0x00 0.--3. "FSEL,Function Selector (Digital Function)" "0: Function 0,1: Function 1,2: Function 2,3: Function 3,4: Function 4,5: Function 5,6: Function 6,7: Function 7,8: Function 8,9: Function 9,10: Function 10,11: Function 11,12: Function 12,13: Function 13,14: Function 14,15: Function 15"
tree.end
sif cpuis("IMXRT595-CM33")||cpuis("IMXRT555")
tree "LCDIF (LCD Interface)"
base ad:0x40210000
group.long 0x1240++0x03
line.long 0x00 "FrameBufferConfig0,Frame Buffer and Timing control"
bitfld.long 0x00 29. "BACK_PRESSURE_DISABLE," "0,1"
rbitfld.long 0x00 28. "FLIP_IN_PROGRESS,When the frame buffer address gets written to this bit gets set to one" "0,1"
newline
rbitfld.long 0x00 24. "UNDERFLOW,When the display FIFO underflows this bit gets set to one" "0,1"
bitfld.long 0x00 20. "RESET,Writing a one in this register will force a reset of the display controller" "0: For DBI this field should be = 0,1: Enable DPI Timing start a DPI transfer"
newline
bitfld.long 0x00 16. "VALID,The valid field defines whether we can copy a new set of registers at the next VBLANK or not" "0,1"
bitfld.long 0x00 12. "GAMMA,When Gamma is enabled the R G and B channels will be routed through the Gamma LUT to perform gamma correction" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 9. "SWITCHPANEL,When SwitchPanel of panel 0 is enabled output channel 0 will show the image of panel 1 not panel 0's" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 8. "OUTPUT,When Output is enabled pixels will be displayed" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 4. "MODE,Mode of the frame buffer" "0: DISABLE,1: TILE4x4 INPUT"
bitfld.long 0x00 0.--2. "FORMAT,The format of the frame buffer" "0,1,2,3,4,5,6,7"
group.long 0x1260++0x03
line.long 0x00 "FrameBufferAddress0,Starting address of the frame buffer"
bitfld.long 0x00 31. "TYPE," "0,1"
hexmask.long 0x00 0.--30. 1. "ADDRESS,ADDRESS"
group.long 0x1280++0x03
line.long 0x00 "FrameBufferStride0,Stride of the frame buffer in bytes"
hexmask.long.tbyte 0x00 0.--16. 1. "STRIDE,Number of bytes from start of one line to next line"
group.long 0x1360++0x03
line.long 0x00 "DisplayDitherConfig0,Configuration register for dithering"
bitfld.long 0x00 31. "ENABLE,Enabling dithering allows R8G8B8 modes to show better on panels with less bits-per-pixel" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 16.--19. "RED_SIZE,Number of important bits for the red channel for the panel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "GREEN_SIZE,Number of important bits for the green channel for the panel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "BLUE_SIZE,Number of important bits for the blue channel for the panel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1380++0x03
line.long 0x00 "DisplayDitherTableLow0,Dither table low"
bitfld.long 0x00 28.--31. "Y1_X3,Dither threshold value for x y=3 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "Y1_X2,Dither threshold value for x y=2 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "Y1_X1,Dither threshold value for x y=1 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "Y1_X0,Dither threshold value for x y=0 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "Y0_X3,Dither threshold value for x y=3 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "Y0_X2,Dither threshold value for x y=2 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "Y0_X1,Dither threshold value for x y=1 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "Y0_X0,Dither threshold value for x y=0 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x13A0++0x03
line.long 0x00 "DisplayDitherTableHigh0,Dither table high"
bitfld.long 0x00 28.--31. "Y3_X3,Dither threshold value for x y=3 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "Y3_X2,Dither threshold value for x y=2 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "Y3_X1,Dither threshold value for x y=1 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "Y3_X0,Dither threshold value for x y=0 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "Y2_X3,Dither threshold value for x y=3 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "Y2_X2,Dither threshold value for x y=2 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "Y2_X1,Dither threshold value for x y=1 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "Y2_X0,Dither threshold value for x y=0 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x13C0++0x03
line.long 0x00 "PanelConfig0,Panel configuration"
bitfld.long 0x00 31. "SEQUENCING,Enable software or hardware panel sequencing" "0: hardware,1: software"
bitfld.long 0x00 9. "CLOCK_POLARITY,Clock polarity" "0: POSITIVE,1: NEGATIVE"
newline
bitfld.long 0x00 8. "CLOCK,Clock enable/disable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 5. "DATA_POLARITY,Data polarity" "0: POSITIVE,1: NEGATIVE"
newline
bitfld.long 0x00 1. "DE_POLARITY,Data Enable polarity" "0: POSITIVE,1: NEGATIVE"
bitfld.long 0x00 0. "DE,Data Enable enabled/disabled" "0: DISABLED,1: ENABLED"
group.long 0x13E0++0x03
line.long 0x00 "PanelTiming0,Timing for hardware panel sequencing"
bitfld.long 0x00 28.--31. "POWER_DISABLE,Number of VSYNCs to wait after power has been disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "BACKLIGHT_DISABLE,Number of VSYNCs to wait after backlight has been disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "CLOCK_DISABLE,Number of VSYNCs to wait after clock has been disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "DATA_DISABLE,Number of VSYNCs to wait after data has been disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "DATA_ENABLE,Number of VSYNCs to wait after data has been enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CLOCK_ENABLE,Number of VSYNCs to wait after clock has been enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "BACKLIGHT_ENABLE,Number of VSYNCs to wait after backlight has been enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "POWER_ENABLE,Number of VSYNCsto wait after power has been enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1400++0x03
line.long 0x00 "HDisplay0,Horizontal Total and Display End counters"
hexmask.long.word 0x00 16.--28. 1. "TOTAL,Total number of horizontal pixels"
hexmask.long.word 0x00 0.--12. 1. "DISPLAY_END,Number of visible horizontal pixels"
group.long 0x1420++0x03
line.long 0x00 "HSync0,Horizontal Sync counters"
bitfld.long 0x00 31. "POLARITY,Polarity of the horizontal sync pulse" "0: POSITIVE,1: NEGATIVE"
bitfld.long 0x00 30. "PULSE,Horizontal sync pulse control" "0: DISABLED,1: ENABLED"
newline
hexmask.long.word 0x00 16.--28. 1. "END,End of horizontal sync pulse"
hexmask.long.word 0x00 0.--12. 1. "START,Start of horizontal sync pulse"
group.long 0x1480++0x03
line.long 0x00 "VDisplay0,Vertical Total and Display End counters"
hexmask.long.word 0x00 16.--27. 1. "TOTAL,Total number of vertical lines"
hexmask.long.word 0x00 0.--11. 1. "DISPLAY_END,Number of visible vertical lines"
group.long 0x14A0++0x03
line.long 0x00 "VSync0,Vertical Sync counters"
bitfld.long 0x00 31. "POLARITY,Polarity of the vertical sync pulse" "0: POSITIVE,1: ACTIVE-LOW"
bitfld.long 0x00 30. "PULSE,Vertical sync pulse control" "0: DISABLED,1: ENABLED"
newline
hexmask.long.word 0x00 16.--27. 1. "END,End of the vertical sync pulse"
hexmask.long.word 0x00 0.--11. 1. "START,Start of the vertical sync pulse"
rgroup.long 0x14C0++0x03
line.long 0x00 "DisplayCurrentLocation0,Current x y location of display controller"
hexmask.long.word 0x00 16.--31. 1. "Y,Current Y location"
hexmask.long.word 0x00 0.--15. 1. "X,Current X location"
group.long 0x14E0++0x03
line.long 0x00 "GammaIndex0,Index into gamma table"
hexmask.long.byte 0x00 0.--7. 1. "INDEX,Index into gamma table"
group.long 0x1500++0x03
line.long 0x00 "GammaData0,Translation values for the gamma table"
hexmask.long.byte 0x00 16.--23. 1. "RED,Red translation value"
hexmask.long.byte 0x00 8.--15. 1. "GREEN,Green translation value"
newline
hexmask.long.byte 0x00 0.--7. 1. "BLUE,Blue translation value"
group.long 0x1520++0x03
line.long 0x00 "CursorConfig,Configuration register for the cursor"
rbitfld.long 0x00 31. "FLIP_IN_PROGRESS,When the cursor address gets written to this bit gets set to one" "0,1"
bitfld.long 0x00 16.--20. "HOT_SPOT_X,Horizontal offset to cursor hotspot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "HOT_SPOT_Y,Vertical offset to cursor hotspot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. "DISPLAY,Display Controller owning the cursor" "0: DISPLAY0,1: DISPLAY1"
newline
bitfld.long 0x00 0.--1. "FORMAT,Format of the cursor" "0,1,2,3"
group.long 0x1530++0x03
line.long 0x00 "CursorAddress,Address of the cursor shape"
bitfld.long 0x00 31. "TYPE," "0,1"
hexmask.long 0x00 0.--30. 1. "ADDRESS,ADDRESS"
group.long 0x1540++0x03
line.long 0x00 "CursorLocation,Location of the cursor on the owning display"
hexmask.long.word 0x00 16.--27. 1. "Y,Y location of cursor's hotspot"
hexmask.long.word 0x00 0.--12. 1. "X,X location of cursor's hotspot"
group.long 0x1550++0x03
line.long 0x00 "CursorBackground,The background color for Masked cursors"
hexmask.long.byte 0x00 16.--23. 1. "RED,Red value"
hexmask.long.byte 0x00 8.--15. 1. "GREEN,Green value"
newline
hexmask.long.byte 0x00 0.--7. 1. "BLUE,Blue value"
group.long 0x1560++0x03
line.long 0x00 "CursorForeground,The foreground color for Masked cursors"
hexmask.long.byte 0x00 16.--23. 1. "RED,Red value"
hexmask.long.byte 0x00 8.--15. 1. "GREEN,Green value"
newline
hexmask.long.byte 0x00 0.--7. 1. "BLUE,Blue value"
group.long 0x1600++0x03
line.long 0x00 "DisplayIntr,Display interrupt register"
bitfld.long 0x00 0. "DISP0,Display0 interrupt" "0,1"
group.long 0x1610++0x03
line.long 0x00 "DisplayIntrEnable,The interrupt enable register for display_0 (and display_1 if present)"
bitfld.long 0x00 0. "DISP0,Display0 interrupt enable" "0,1"
group.long 0x1620++0x03
line.long 0x00 "DbiConfig0,Configuration register for DBI output"
bitfld.long 0x00 8.--11. "DBI_AC_TIME_UNIT,Time unit for AC characteristics" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "DBIX_POLARITY,D/CX Pin polarity" "0: DEFAULT,1: REVERSE"
newline
bitfld.long 0x00 6. "BUS_OUTPUT_SEL,Output bus select" "0: DPI,1: DBI"
bitfld.long 0x00 2.--5. "DBI_DATA_FORMAT,DBI interface data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.long 0x1640++0x03
line.long 0x00 "DbiIfReset0,Reset DBI interface to idle state"
bitfld.long 0x00 0. "DBI_IF_LEVEL_RESET,Reset DBI interface to idle state" "0,1"
group.long 0x1660++0x03
line.long 0x00 "DbiWrChar10,DBI write AC characteristics definition register 1"
bitfld.long 0x00 12.--15. "DBI_WR_CS_ASSERT,Cycle number=Setting*(DbiAcTimeUnit+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DBI_WR_EOR_WR_ASSERT,Cycle number=Setting*(DbiAcTimeUnit+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 0.--7. 1. "DBI_WR_PERIOD,Single write period duration"
group.long 0x1680++0x03
line.long 0x00 "DbiWrChar20,DBI write AC characteristics definition register 2"
hexmask.long.byte 0x00 8.--15. 1. "DBI_WR_CS_DE_ASRT,Cycle number=Setting*(DbiAcTimeUnit+1)"
hexmask.long.byte 0x00 0.--7. 1. "DBI_WR_EOR_WR_DE_ASRT,Cycle number=Setting*(DbiAcTimeUnit+1)"
wgroup.long 0x16A0++0x03
line.long 0x00 "DbiCmd0,DBI Command in/out port"
bitfld.long 0x00 30.--31. "DBI_COMMANDFLAG,DBI command flag" "0,1,2,3"
hexmask.long.word 0x00 0.--15. 1. "DBI_COMMAND_WORD,The type of data contained in this word is specified using DBI_COMMANDFLAG[bits 31:30]"
group.long 0x16C0++0x03
line.long 0x00 "DpiConfig0,The configuration register for DPI output"
bitfld.long 0x00 0.--2. "DPI_DATA_FORMAT,DPI interface data format" "0,1,2,3,4,5,6,7"
rgroup.long 0x16F0++0x03
line.long 0x00 "DcChipRev,Revision for the chip in BCD"
hexmask.long 0x00 0.--31. 1. "REV,Revision"
rgroup.long 0x1700++0x03
line.long 0x00 "DcChipDate,Shows the release date for the IP in YYYYMMDD (year month)"
hexmask.long 0x00 0.--31. 1. "DATE,Date"
rgroup.long 0x1720++0x03
line.long 0x00 "DcChipPatchRev,Patch revision"
hexmask.long 0x00 0.--31. 1. "PATCH_REV,Patch revision"
group.long 0x1740++0x03
line.long 0x00 "DcTileInCfg0,Tile input configuration"
bitfld.long 0x00 5. "CFG_MODE_EN,Configuration mode enable" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 4. "YUV2_RGB_EN,YUV2RGB module enable" "0,1"
newline
bitfld.long 0x00 2.--3. "YUV_STANDARD,YUV standard select" "0,1,2,3"
bitfld.long 0x00 0.--1. "TILE_FORMAT,Tile input data format 0 means non-tile input" "0,1,2,3"
group.long 0x1760++0x03
line.long 0x00 "DcTileUvFrameBufferAdr0,UV frame buffer address when tile input"
hexmask.long 0x00 0.--31. 1. "ADDRESS,UV frame buffer address when tile input"
group.long 0x1780++0x03
line.long 0x00 "DcTileUvFrameBufferStr0,UV frame buffer stride when tile input"
hexmask.long.word 0x00 0.--15. 1. "STRIDE,UV frame buffer stride when tile input"
rgroup.long 0x17B0++0x03
line.long 0x00 "DcProductId,Product ID"
hexmask.long 0x00 0.--31. 1. "PRODUCT_ID,Product ID"
group.long 0x1820++0x03
line.long 0x00 "DebugCounterSelect0,no description available"
hexmask.long.byte 0x00 0.--7. 1. "SELECT,Write a value to this field to pick up from 0~255 counters"
group.long 0x1840++0x03
line.long 0x00 "DebugCounterValue0,Debug Counter Value as specified in DebugCounterSelect"
hexmask.long 0x00 0.--31. 1. "VALUE,Selected debug counter value"
tree.end
tree "MIPI_DSI_HOST (MIPI DSI Host)"
base ad:0x40031000
group.long 0x00++0x03
line.long 0x00 "DSI_HOST_CFG_NUM_LANES,no description available"
hexmask.long 0x00 2.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--1. "dsi_host_cfg_num_lanes,Sets the number of active lanes that are to be used for transmitting data" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "DSI_HOST_CFG_NONCONTINUOUS_CLK,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dsi_host_cfg_noncontinuous_clk,Sets the Host Controller into non-continuous MIPI clock mode" "0,1"
group.long 0x08++0x03
line.long 0x00 "DSI_HOST_CFG_T_PRE,no description available"
hexmask.long 0x00 7.--31. 1. "reserved,reserved"
newline
hexmask.long.byte 0x00 0.--6. 1. "dsi_host_cfg_t_pre,Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation"
group.long 0x0C++0x03
line.long 0x00 "DSI_HOST_CFG_T_POST,no description available"
hexmask.long 0x00 7.--31. 1. "reserved,reserved"
newline
hexmask.long.byte 0x00 0.--6. 1. "dsi_host_cfg_t_post,Sets the number of byte clock periods ('clk_byte' input) to wait before putting the clock lane into LP mode after the data lanes have been detected to be in Stop State"
group.long 0x10++0x03
line.long 0x00 "DSI_HOST_CFG_TX_GAP,no description available"
hexmask.long 0x00 7.--31. 1. "reserved,reserved"
newline
hexmask.long.byte 0x00 0.--6. 1. "dsi_host_cfg_tx_gap,Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode again"
group.long 0x14++0x03
line.long 0x00 "DSI_HOST_CFG_AUTOINSERT_EOTP,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dsi_host_cfg_autoinsert_eotp,Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode" "0,1"
group.long 0x18++0x03
line.long 0x00 "DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP,no description available"
hexmask.long.tbyte 0x00 8.--31. 1. "reserved,reserved"
newline
hexmask.long.byte 0x00 0.--7. 1. "dsi_host_cfg_extra_cmds_after_eotp,Configures the DSI Host Controller to send extra End Of Transmission Packets after the end of a packet"
group.long 0x1C++0x03
line.long 0x00 "DSI_HOST_CFG_HTX_TO_COUNT,no description available"
hexmask.long.byte 0x00 24.--31. 1. "reserved,reserved"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "dsi_host_cfg_htx_to_count,Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification"
group.long 0x20++0x03
line.long 0x00 "DSI_HOST_CFG_LRX_H_TO_COUNT,no description available"
hexmask.long.byte 0x00 24.--31. 1. "reserved,reserved"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "dsi_host_cfg_lrx_h_to_count,Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification"
group.long 0x24++0x03
line.long 0x00 "DSI_HOST_CFG_BTA_H_TO_COUNT,no description available"
hexmask.long.byte 0x00 24.--31. 1. "reserved,reserved"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "dsi_host_cfg_bta_h_to_count,Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods that once reached will initiate a timeout error"
group.long 0x28++0x03
line.long 0x00 "DSI_HOST_CFG_TWAKEUP,no description available"
hexmask.long.word 0x00 19.--31. 1. "reserved,reserved"
newline
hexmask.long.tbyte 0x00 0.--18. 1. "dsi_host_cfg_twakeup,DPHY Twakeup timing parameter"
rgroup.long 0x2C++0x03
line.long 0x00 "DSI_HOST_CFG_STATUS_OUT,no description available"
hexmask.long 0x00 0.--31. 1. "dsi_host_cfg_status_out,Status Register"
rgroup.long 0x30++0x03
line.long 0x00 "DSI_HOST_RX_ERROR_STATUS,no description available"
hexmask.long.tbyte 0x00 11.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--10. 1. "dsi_host_rx_error_status,Status Register for Host receive error detection ECC errors CRC errors and for timeout indicators [0] ECC single bit error detected [1] ECC multi bit error detected [6:2] Errored bit position for single bit ECC error [7] CRC.."
group.long 0x100++0x03
line.long 0x00 "DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_cfg_dbi_pixel_payload_size,Maximum number of pixels that should be sent as one DSI packet"
group.long 0x104++0x03
line.long 0x00 "DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_cfg_dbi_pixel_fifo_send_level,In order to optimize DSI utility the DBI bridge buffers a cerntain number of DBI pixels before initiating a DSI packet"
group.long 0x200++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_cfg_dpi_pixel_payload_size,Maximum number of pixels that should be sent as one DSI packet"
group.long 0x204++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_cfg_dpi_pixel_fifo_send_level,In order to optimize DSI utility the DPI bridge buffers a cerntain number of DPI pixels before initiating a DSI packet"
group.long 0x208++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING,no description available"
hexmask.long 0x00 3.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--2. "dsi_host_cfg_dpi_interface_color_coding,Sets the distribution of RGB bits within the 24-bit d bus as specified by the DPI specification" "0,1,2,3,4,5,6,7"
group.long 0x20C++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_PIXEL_FORMAT,no description available"
hexmask.long 0x00 2.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--1. "dsi_host_cfg_dpi_pixel_format,Sets the DSI packet type of the pixels" "0,1,2,3"
group.long 0x210++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_VSYNC_POLARITY,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dsi_host_cfg_dpi_vsync_polarity,Sets polarity of dpi_vsync_input" "0: active low,1: active high"
group.long 0x214++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_HSYNC_POLARITY,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dsi_host_cfg_dpi_hsync_polarity,Sets polarity of dpi_hsync_input" "0: active low,1: active high"
group.long 0x218++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_VIDEO_MODE,no description available"
hexmask.long 0x00 2.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--1. "dsi_host_cfg_dpi_video_mode,Select DSI video mode that the host DPI module should generate packets for" "0,1,2,3"
group.long 0x21C++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_HFP,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_cfg_dpi_hfp,Sets the DSI packet payload size in bytes of the horizontal front porch blanking packet"
group.long 0x220++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_HBP,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_cfg_dpi_hbp,Sets the DSI packet payload size in bytes of the horizontal back porch blanking packet"
group.long 0x224++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_HSA,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_cfg_dpi_hsa,Sets the DSI packet payload size in bytes of the horizontal sync width filler blanking packet"
group.long 0x228++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dsi_host_cfg_dpi_enable_mult_pkts,Enable Multiple packets per video line" "0,1"
group.long 0x22C++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_VBP,no description available"
hexmask.long.tbyte 0x00 8.--31. 1. "reserved,reserved"
newline
hexmask.long.byte 0x00 0.--7. 1. "dsi_host_cfg_dpi_vbp,Sets the number of lines in the vertical back porch"
group.long 0x230++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_VFP,no description available"
hexmask.long.tbyte 0x00 8.--31. 1. "reserved,reserved"
newline
hexmask.long.byte 0x00 0.--7. 1. "dsi_host_cfg_dpi_vfp,Sets the number of lines in the vertical front porch"
group.long 0x234++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_BLLP_MODE,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dsi_host_cfg_dpi_bllp_mode,Optimize bllp periods to Low Power mode when possible" "0: blanking packets are sent during BLLP periods,1: LP mode is used for BLLP periods"
group.long 0x238++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dsi_host_cfg_dpi_use_null_pkt_bllp,Selects type of blanking packet to be sent during bllp region" "0: Blanking packet used in bllp region,1: Null packet used in bllp region"
group.long 0x23C++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_VACTIVE,no description available"
hexmask.long.tbyte 0x00 14.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--13. 1. "dsi_host_cfg_dpi_vactive,Sets the number of lines in the vertical active aread"
group.long 0x240++0x03
line.long 0x00 "DSI_HOST_CFG_DPI_VC,no description available"
hexmask.long 0x00 2.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--1. "dsi_host_cfg_dpi_vc,Sets the Virtual Channel (VC) of packets that will be sent to the receive packet interface" "0,1,2,3"
group.long 0x280++0x03
line.long 0x00 "DSI_HOST_TX_PAYLOAD,no description available"
hexmask.long 0x00 0.--31. 1. "dsi_host_tx_payload,Tx Payload data write register"
group.long 0x284++0x03
line.long 0x00 "DSI_HOST_PKT_CONTROL,no description available"
rbitfld.long 0x00 27.--31. "reserved,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long 0x00 0.--26. 1. "dsi_host_pkt_control,Tx packet control register"
group.long 0x288++0x03
line.long 0x00 "DSI_HOST_SEND_PACKET,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dsi_host_send_packet,Tx send packet writing to this register causes the packet described in dsi_host_pkt_control to be sent" "0,1"
rgroup.long 0x28C++0x03
line.long 0x00 "DSI_HOST_PKT_STATUS,no description available"
hexmask.long.tbyte 0x00 9.--31. 1. "reserved,reserved"
newline
abitfld.long 0x00 0.--8. "dsi_host_pkt_status,Status of APB to packet interface [0] - state machine not idle [1] - Tx packet done [2] - dphy direction" "0x000=0: tx had control,0x001=1: rx has control [3] - tx fifo overflow"
rgroup.long 0x290++0x03
line.long 0x00 "DSI_HOST_PKT_FIFO_WR_LEVEL,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_pkt_fifo_wr_level,Write level of APB to pkt interface fifo"
rgroup.long 0x294++0x03
line.long 0x00 "DSI_HOST_PKT_FIFO_RD_LEVEL,no description available"
hexmask.long.word 0x00 16.--31. 1. "reserved,reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "dsi_host_pkt_fifo_rd_level,Read level of APB to pkt interface fifo"
rgroup.long 0x298++0x03
line.long 0x00 "DSI_HOST_PKT_RX_PAYLOAD,no description available"
hexmask.long 0x00 0.--31. 1. "dsi_host_pkt_rx_payload,APB to pkt interface rx payload"
rgroup.long 0x29C++0x03
line.long 0x00 "DSI_HOST_PKT_RX_PKT_HEADER,no description available"
hexmask.long.byte 0x00 24.--31. 1. "reserved,reserved"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "dsi_host_pkt_rx_pkt_header,APB to pkt interface rx packet header [15:0] word count [21:16] data type [23:22] Virtual Channel"
rgroup.long 0x2A0++0x03
line.long 0x00 "DSI_HOST_IRQ_STATUS,no description available"
abitfld.long 0x00 0.--31. "dsi_host_irq_status,Status of APB to packet interface [0] - state machine not idle [1] - Tx packet done [2] - dphy direction" "0x00000000=0: tx had control,0x00000001=1: rx has control [3] - tx fifo.."
rgroup.long 0x2A4++0x03
line.long 0x00 "DSI_HOST_IRQ_STATUS2,no description available"
hexmask.long 0x00 3.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--2. "dsi_host_irq_status2,Status of APB to packet interface part 2 read part 2 first then dsi_host_irq_status" "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x03
line.long 0x00 "DSI_HOST_IRQ_MASK,no description available"
abitfld.long 0x00 0.--31. "dsi_host_irq_mask,irq mask [0] - state machine not idle [1] - Tx packet done [2] - dphy direction" "0x00000000=0: tx had control,0x00000001=1: rx has control [3] - tx fifo.."
group.long 0x2AC++0x03
line.long 0x00 "DSI_HOST_IRQ_MASK2,no description available"
hexmask.long 0x00 3.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--2. "dsi_host_irq_mask2,irq mask 2 [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error" "0,1,2,3,4,5,6,7"
group.long 0x300++0x03
line.long 0x00 "DPHY_PD_DPHY,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dphy_pd_dphy,DPHY PD_DPHY input control see DPHY datasheet" "0,1"
group.long 0x304++0x03
line.long 0x00 "DPHY_M_PRG_HS_PREPARE,no description available"
hexmask.long 0x00 2.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--1. "dphy_m_prg_hs_prepare,DPHY m_PRG_HS_PREPARE input see DPHY datasheet" "0,1,2,3"
group.long 0x308++0x03
line.long 0x00 "DPHY_MC_PRG_HS_PREPARE,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dphy_mc_prg_hs_prepare,DPHY mc_PRG_HS_PREPARE input see DPHY datasheet" "0,1"
group.long 0x30C++0x03
line.long 0x00 "DPHY_M_PRG_HS_ZERO,no description available"
hexmask.long 0x00 5.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--4. "dphy_m_prg_hs_zero,DPHY m_PRG_HS_ZERO input see DPHY datasheet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x310++0x03
line.long 0x00 "DPHY_MC_PRG_HS_ZERO,no description available"
hexmask.long 0x00 6.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--5. "dphy_mc_prg_hs_zero,DPHY mc_PRG_HS_ZERO input see DPHY datasheet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x314++0x03
line.long 0x00 "DPHY_M_PRG_HS_TRAIL,no description available"
hexmask.long 0x00 4.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--3. "dphy_m_prg_hs_trail,DPHY m_PRG_HS_TRAIL input see DPHY datasheet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x318++0x03
line.long 0x00 "DPHY_MC_PRG_HS_TRAIL,no description available"
hexmask.long 0x00 4.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--3. "dphy_mc_prg_hs_trail,DPHY mc_PRG_HS_TRAIL input see DPHY datasheet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x31C++0x03
line.long 0x00 "DPHY_TST,no description available"
hexmask.long 0x00 6.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--5. "dphy_tst,DPHY TST input see DPHY datasheet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x320++0x03
line.long 0x00 "DPHY_RTERM_SEL,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dphy_rterm_sel,DPHY RTERM_SEL input see DPHY datasheet" "0,1"
group.long 0x324++0x03
line.long 0x00 "DPHY_AUTO_PD_EN,no description available"
hexmask.long 0x00 1.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0. "dphy_auto_pd_en,DPHY AUTO_PD_EN input see DPHY datasheet" "0,1"
group.long 0x328++0x03
line.long 0x00 "DPHY_RXLPRP,no description available"
hexmask.long 0x00 2.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--1. "dphy_rxlprp,DPHY RXLPRP input see DPHY datasheet" "0,1,2,3"
group.long 0x32C++0x03
line.long 0x00 "DPHY_RXCDRP,no description available"
hexmask.long 0x00 2.--31. 1. "reserved,reserved"
newline
bitfld.long 0x00 0.--1. "dphy_rxcdrp,DPHY RXCDRP input see DPHY datasheet" "0,1,2,3"
tree.end
endif
tree "MRT (Multi-Rate Timer (MRT))"
base ad:0x4002D000
sif cpuis("IMXRT595-CM33")
group.long 0xF0++0x03
line.long 0x00 "MODCFG,Module Configuration"
bitfld.long 0x00 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register" "0: Hardware status mode,1: MULTI_TASK_MODE"
bitfld.long 0x00 4.--8. "NOB,Number Of Bits: identifies the number of timer bits in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--3. "NOC,Number Of Channels: identifies the number of channels in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF4++0x03
line.long 0x00 "IDLE_CH,Idle Channel"
bitfld.long 0x00 4.--7. "CHAN,Idle channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF8++0x03
line.long 0x00 "IRQ_FLAG,Global Interrupt Flag"
bitfld.long 0x00 3. "GFLAG3,Monitors the interrupt flag of TIMER3 and acts similarly to channel 0" "0,1"
bitfld.long 0x00 2. "GFLAG2,Monitors the interrupt flag of TIMER2 and acts similarly to channel 0" "0,1"
newline
bitfld.long 0x00 1. "GFLAG1,Monitors the interrupt flag of TIMER1 and acts similarly to channel 0" "0,1"
bitfld.long 0x00 0. "GFLAG0,Monitors the interrupt flag of TIMER0" "0: No pending interrupt,1: PENDING_INTERRUPT"
rgroup.long 0xFC++0x03
line.long 0x00 "ID_CODE,Multi-Rate Timer ID code"
hexmask.long 0x00 0.--31. 1. "ID_CODE,Multi-Rate Timer ID code"
endif
repeat 4. (increment 0 1)(increment 0 0x10)
tree "CHANNEL[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0x00)++0x03
line.long 0x00 "INTVAL,Time Interval Value"
bitfld.long 0x00 31. "LOAD,Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register" "0: No force load,1: Force load"
hexmask.long.tbyte 0x00 0.--23. 1. "IVALUE,Time interval load value"
rgroup.long ($2+0x04)++0x03
line.long 0x00 "TIMER,Timer"
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Holds the current timer value of the down-counter"
group.long ($2+0x08)++0x03
line.long 0x00 "CTRL,Control"
bitfld.long 0x00 1.--2. "MODE,Selects the timer mode" "0: REPEAT_INTERRUPT_MODE,1: ONE_SHOT_INTERRUPT_MODE,2: ONE_SHOT_STALL_MODE,?..."
bitfld.long 0x00 0. "INTEN,Enable the TIMER n interrupt" "0: Disabled,1: Enabled"
group.long ($2+0x0C)++0x03
line.long 0x00 "STAT,Status"
eventfld.long 0x00 2. "INUSE,Channel-In-Use flag" "0: This timer channel is not in use,1: This timer channel is in use"
rbitfld.long 0x00 1. "RUN,Indicates the state of TIMER n" "0: Idle state,1: Running"
newline
bitfld.long 0x00 0. "INTFLAG,Monitors the interrupt flag" "0: No pending interrupt,1: Pending interrupt"
endif
tree.end
repeat.end
tree.end
tree "MU (MUA)"
base ad:0x40110000
rgroup.long 0x00++0x03
line.long 0x00 "VER,Version ID Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
rgroup.long 0x04++0x03
line.long 0x00 "PAR,Parameter Register"
hexmask.long 0x00 0.--31. 1. "PARAMETER,This bitfield contains the parameter settings of MUA"
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x20)++0x03
line.long 0x00 "TR[$1],Transmit Register $1"
hexmask.long 0x00 0.--31. 1. "DATA,DATA"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x40)++0x03
line.long 0x00 "RR[$1],Receive Register $1"
hexmask.long 0x00 0.--31. 1. "DATA,DATA"
repeat.end
group.long 0x60++0x03
line.long 0x00 "SR,Status Register"
eventfld.long 0x00 28.--31. "GIPn,GIPn" "0: MUA general purpose interrupt n is not pending,1: MUA general purpose interrupt n is pending,?..."
rbitfld.long 0x00 24.--27. "RFn,RFn" "0: MUA RRn register is not full (default),1: MUA RRn register has received data from MUB..,?..."
newline
rbitfld.long 0x00 20.--23. "TEn,TEn" "0: MUA TRn register is not empty,1: MUA TRn register is empty (default),?..."
eventfld.long 0x00 10. "RAIP,RAIP" "0: Processor B-side did not enter reset,1: Processor B-side entered reset"
newline
eventfld.long 0x00 9. "RDIP,RDIP" "0: Processor B-side did not exit reset,1: Processor B-side exited from reset"
rbitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the MUA in..,1: MUA initiated flags update processing"
newline
rbitfld.long 0x00 7. "RS,RS" "0: The MUB side of the MU is not in reset,1: The MUB side of the MU is in reset"
rbitfld.long 0x00 5.--6. "PM,PM" "0: The MUB processor is in Run Mode,1: The MUB processor is in WAIT Mode,2: The MUB processor is in STOP/VLPS Mode,3: The MUB processor is in LLS/VLLS Mode"
newline
rbitfld.long 0x00 4. "EP,EP" "0: The MUA side event is not pending (default),1: The MUA side event is pending"
rbitfld.long 0x00 0.--2. "Fn,Fn" "0: Fn bit in the MUB CR register is written 0..,1: Fn bit in the MUB CR register is written 1,?..."
group.long 0x64++0x03
line.long 0x00 "CR,Control Register"
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables MUA General Interrupt n,1: Enables MUA General Interrupt n,?..."
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables MUA Receive Interrupt n,1: Enables MUA Receive Interrupt n,?..."
newline
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables MUA Transmit Interrupt n,1: Enables MUA Transmit Interrupt n,?..."
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: MUA General Interrupt n is not requested to..,1: MUA General Interrupt n is requested to the MUB,?..."
newline
bitfld.long 0x00 12. "RAIE,RAIE" "0: Disables Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
bitfld.long 0x00 6. "RDIE,RDIE" "0: Disables Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
newline
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the MU reset"
bitfld.long 0x00 0.--2. "Fn,Fn" "0: Clears the Fn bit in the SR register,1: Sets the Fn bit in the SR register,?..."
tree.end
tree "NVIC"
base ad:0xE000E100
repeat 16. (increment 0 1) (increment 0 0x4)
group.long ($2+0x00)++0x03
line.long 0x00 "ISER[$1],Interrupt Set Enable Register $1"
bitfld.long 0x00 31. "SETENA31,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 30. "SETENA30,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 29. "SETENA29,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 28. "SETENA28,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 27. "SETENA27,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 26. "SETENA26,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 25. "SETENA25,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 24. "SETENA24,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 23. "SETENA23,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 22. "SETENA22,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 21. "SETENA21,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 20. "SETENA20,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 19. "SETENA19,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 18. "SETENA18,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 17. "SETENA17,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 16. "SETENA16,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 15. "SETENA15,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 14. "SETENA14,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 13. "SETENA13,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 12. "SETENA12,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 11. "SETENA11,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 10. "SETENA10,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 9. "SETENA9,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 8. "SETENA8,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 7. "SETENA7,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 6. "SETENA6,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 5. "SETENA5,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 4. "SETENA4,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 3. "SETENA3,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 2. "SETENA2,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 1. "SETENA1,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 0. "SETENA0,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
repeat.end
repeat 16. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "ICER[$1],Interrupt Clear Enable Register $1"
bitfld.long 0x00 31. "CLRENA31,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 30. "CLRENA30,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 29. "CLRENA29,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 28. "CLRENA28,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 27. "CLRENA27,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 26. "CLRENA26,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 25. "CLRENA25,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 24. "CLRENA24,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 23. "CLRENA23,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 22. "CLRENA22,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 21. "CLRENA21,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 20. "CLRENA20,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 19. "CLRENA19,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 18. "CLRENA18,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 17. "CLRENA17,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 16. "CLRENA16,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 15. "CLRENA15,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 14. "CLRENA14,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 13. "CLRENA13,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 12. "CLRENA12,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 11. "CLRENA11,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 10. "CLRENA10,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 9. "CLRENA9,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 8. "CLRENA8,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 7. "CLRENA7,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 6. "CLRENA6,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 5. "CLRENA5,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 4. "CLRENA4,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 3. "CLRENA3,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 2. "CLRENA2,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 1. "CLRENA1,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 0. "CLRENA0,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "ISPR[$1],Interrupt Set Pending Register $1"
bitfld.long 0x00 31. "SETPEND31,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 30. "SETPEND30,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 29. "SETPEND29,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 28. "SETPEND28,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 27. "SETPEND27,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 26. "SETPEND26,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 25. "SETPEND25,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 24. "SETPEND24,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 23. "SETPEND23,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 22. "SETPEND22,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 21. "SETPEND21,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 20. "SETPEND20,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 19. "SETPEND19,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 18. "SETPEND18,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 17. "SETPEND17,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 16. "SETPEND16,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 15. "SETPEND15,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 14. "SETPEND14,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 13. "SETPEND13,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 12. "SETPEND12,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 11. "SETPEND11,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 10. "SETPEND10,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 9. "SETPEND9,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 8. "SETPEND8,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 7. "SETPEND7,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 6. "SETPEND6,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 5. "SETPEND5,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 4. "SETPEND4,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 3. "SETPEND3,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 2. "SETPEND2,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 1. "SETPEND1,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 0. "SETPEND0,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x180)++0x03
line.long 0x00 "ICPR[$1],Interrupt Clear Pending Register $1"
bitfld.long 0x00 31. "CLRPEND31,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 30. "CLRPEND30,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 29. "CLRPEND29,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 28. "CLRPEND28,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 27. "CLRPEND27,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 26. "CLRPEND26,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 25. "CLRPEND25,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 24. "CLRPEND24,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 23. "CLRPEND23,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 22. "CLRPEND22,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 21. "CLRPEND21,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 20. "CLRPEND20,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 19. "CLRPEND19,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 18. "CLRPEND18,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 17. "CLRPEND17,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 16. "CLRPEND16,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 15. "CLRPEND15,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 14. "CLRPEND14,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 13. "CLRPEND13,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 12. "CLRPEND12,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 11. "CLRPEND11,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 10. "CLRPEND10,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 9. "CLRPEND9,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 8. "CLRPEND8,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 7. "CLRPEND7,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 6. "CLRPEND6,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 5. "CLRPEND5,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 4. "CLRPEND4,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 3. "CLRPEND3,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 2. "CLRPEND2,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 1. "CLRPEND1,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 0. "CLRPEND0,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "IABR[$1],Interrupt Active Bit Register $1"
bitfld.long 0x00 31. "ACTIVE31,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 30. "ACTIVE30,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 29. "ACTIVE29,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 28. "ACTIVE28,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 27. "ACTIVE27,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 26. "ACTIVE26,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 25. "ACTIVE25,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 24. "ACTIVE24,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 23. "ACTIVE23,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 22. "ACTIVE22,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 21. "ACTIVE21,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 20. "ACTIVE20,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 19. "ACTIVE19,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 18. "ACTIVE18,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 17. "ACTIVE17,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 16. "ACTIVE16,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 15. "ACTIVE15,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 14. "ACTIVE14,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 13. "ACTIVE13,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 12. "ACTIVE12,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 11. "ACTIVE11,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 10. "ACTIVE10,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 9. "ACTIVE9,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 8. "ACTIVE8,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 7. "ACTIVE7,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 6. "ACTIVE6,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 5. "ACTIVE5,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 4. "ACTIVE4,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 3. "ACTIVE3,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 2. "ACTIVE2,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 1. "ACTIVE1,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 0. "ACTIVE0,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x280)++0x03
line.long 0x00 "ITNS[$1],Interrupt Target Non-secure Register $1"
bitfld.long 0x00 31. "INTS31,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 30. "INTS30,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 29. "INTS29,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 28. "INTS28,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 27. "INTS27,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 26. "INTS26,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 25. "INTS25,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 24. "INTS24,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 23. "INTS23,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 22. "INTS22,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 21. "INTS21,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 20. "INTS20,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 19. "INTS19,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 18. "INTS18,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 17. "INTS17,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 16. "INTS16,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 15. "INTS15,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 14. "INTS14,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 13. "INTS13,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 12. "INTS12,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 11. "INTS11,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 10. "INTS10,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 9. "INTS9,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 8. "INTS8,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 7. "INTS7,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 6. "INTS6,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 5. "INTS5,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 4. "INTS4,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 3. "INTS3,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 2. "INTS2,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 1. "INTS1,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 0. "INTS0,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
repeat.end
repeat 120. (increment 0 1) (increment 0 0x04)
group.long ($2+0x300)++0x03
line.long 0x00 "IPR[$1],Interrupt Priority Register $1"
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,no description available"
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,no description available"
newline
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,no description available"
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,no description available"
repeat.end
wgroup.long 0xE00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID of the interrupt to trigger in the range 0-479"
tree.end
tree "OCOTP (OCOTP Controller)"
base ad:0x40130000
repeat 496. (increment 0 1) (increment 0 0x4)
group.long ($2+0x00)++0x03
line.long 0x00 "OTP_SHADOW[$1],OTP shadow register N $1"
hexmask.long 0x00 0.--31. 1. "shadow,OTP shadow register"
repeat.end
group.long 0x800++0x03
line.long 0x00 "OTP_CTRL,Control/address register"
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
bitfld.long 0x00 15. "WORDLOCK,Set to write-lock the fuse word when it's being programming" "0,1"
newline
bitfld.long 0x00 12. "CRC_TEST,Set to start CRC calculation" "0,1"
bitfld.long 0x00 11. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "ADDR,OTP word address for read/programming"
group.long 0x804++0x03
line.long 0x00 "OTP_PDN,Power-down register"
bitfld.long 0x00 0. "PDN,This bit indicates the PDN value of OTP memory" "0,1"
group.long 0x808++0x03
line.long 0x00 "OTP_WRITE_DATA,OTP programming data register"
hexmask.long 0x00 0.--31. 1. "WRITE_DATA,Fuse word programming data"
group.long 0x80C++0x03
line.long 0x00 "OTP_READ_CTRL,OTP read start register"
bitfld.long 0x00 0. "READ,Write 1 to start read operation" "0,1"
rgroup.long 0x810++0x03
line.long 0x00 "OTP_READ_DATA,OTP read data register"
hexmask.long 0x00 0.--31. 1. "READ_DATA,Fuse word read data from read operation"
group.long 0x814++0x03
line.long 0x00 "OTP_CLK_DIV,OTP clock divider register"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0,1"
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0,1"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0,1"
bitfld.long 0x00 0.--3. "DIV,Clock divider value by -1 encoding" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16"
group.long 0x81C++0x03
line.long 0x00 "OTP_CRC_ADDR,CRC address range register"
bitfld.long 0x00 24.--26. "CRC_REF_ADDR,Specify which of the 8 CRC reference value to use for CRC calculation" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 12.--20. 1. "CRC_END_ADDR,CRC ending fuse word address"
newline
hexmask.long.word 0x00 0.--8. 1. "CRC_START_ADDR,CRC starting fuse word address"
rgroup.long 0x820++0x03
line.long 0x00 "OTP_CRC_VALUE,CRC result register"
hexmask.long 0x00 0.--31. 1. "CRC_VALUE,The CRC result value"
group.long 0x824++0x03
line.long 0x00 "OTP_STATUS,Status register"
rbitfld.long 0x00 25. "FUSE_LATCHED,Indicate all shadows registers have been loaded with their corresponding fuse words when set by the controller after reset" "0,1"
bitfld.long 0x00 24. "CRC_FAIL,CRC failed when set by hardware for CRC operation" "0,1"
newline
bitfld.long 0x00 23. "ERROR,Set by the controller when a read/write access to a locked region (OTP or shadow register) is requested" "0,1"
rbitfld.long 0x00 22. "BUSY,OTP controller status bit" "0,1"
newline
bitfld.long 0x00 21. "DED_RELOAD,OTP Double Error Detect status of ECC during reload process" "0,1"
bitfld.long 0x00 20. "SEC_RELOAD,OTP Single Error Corrected status of ECC during reload process" "0,1"
newline
rbitfld.long 0x00 14. "PWOK,OTP Power OK status" "0,1"
rbitfld.long 0x00 13. "ACK,OTP ACK value" "0,1"
newline
bitfld.long 0x00 12. "PROGFAIL,OTP PROGFAIL status" "0,1"
bitfld.long 0x00 11. "LOCKED,OTP LOCKED status during read/write operation" "0,1"
newline
bitfld.long 0x00 10. "DED,OTP Double Error Detection status of ECC during read operation" "0,1"
bitfld.long 0x00 9. "SEC,OTP Single Error Corrected status of ECC during read operation" "0,1"
rgroup.long 0x82C++0x03
line.long 0x00 "OTP_VERSION,VERSION ID register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR_VER,OTP controller major version"
hexmask.long.byte 0x00 16.--23. 1. "MINOR_VER,OTP controller minor version"
newline
hexmask.long.word 0x00 0.--15. 1. "STEP_VER,OTP controller step version"
tree.end
tree "OSTIMER"
base ad:0x40113000
rgroup.long 0x00++0x03
line.long 0x00 "EVTIMERL,EVTIMER Low Register"
hexmask.long 0x00 0.--31. 1. "EVTIMER_COUNT_VALUE,EVTimer Count value"
rgroup.long 0x04++0x03
line.long 0x00 "EVTIMERH,EVTIMER High Register"
hexmask.long 0x00 0.--31. 1. "EVTIMER_COUNT_VALUE,EVTimer Count value"
rgroup.long 0x08++0x03
line.long 0x00 "CAPTURE_L,Local Capture Low Register for CPU"
hexmask.long 0x00 0.--31. 1. "CAPTURE_VALUE,EVTimer Capture value"
rgroup.long 0x0C++0x03
line.long 0x00 "CAPTURE_H,Local Capture High Register for CPU"
hexmask.long 0x00 0.--31. 1. "CAPTURE_VALUE,EVTimer Capture value"
group.long 0x10++0x03
line.long 0x00 "MATCH_L,Local Match Low Register for CPU"
hexmask.long 0x00 0.--31. 1. "MATCH_VALUE,EVTimer Match value"
group.long 0x14++0x03
line.long 0x00 "MATCH_H,Local Match High Register for CPU"
hexmask.long 0x00 0.--31. 1. "MATCH_VALUE,EVTimer Match value"
group.long 0x1C++0x03
line.long 0x00 "OSEVENT_CTRL,OS Event Timer Control Register for CPU"
bitfld.long 0x00 2. "MATCH_WR_RDY,EVTimer Match Write Ready" "0,1"
bitfld.long 0x00 1. "OSTIMER_INTENA,Interrupt/Wake-up Request" "0: Interrupt/wake-up requests due to the..,1: An interrupt/wake-up request to the domain.."
newline
bitfld.long 0x00 0. "OSTIMER_INTRFLAG,Interrupt Flag" "0,1"
tree.end
tree "OTFAD"
base ad:0x40134000
sif cpuis("IMXRT595-CM33")
group.long 0xC00++0x03
line.long 0x00 "CR,Control Register"
bitfld.long 0x00 31. "GE,Global OTFAD Enable" "0: OTFAD has decryption disabled,1: OTFAD has decryption enabled and processes.."
bitfld.long 0x00 7. "RRAE,Restricted Register Access Enable" "0: Register access is fully enabled,1: Register access is restricted and only the CR.."
newline
bitfld.long 0x00 3. "FLDM,Force Logically Disabled Mode" "0: No effect on the operating mode,1: Force entry into LDM after a write with this.."
rgroup.long 0xC04++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 29. "GEM,Global Enable Mode" "0: OTFAD is disabled,1: OTFAD is enabled and processes data fetched.."
bitfld.long 0x00 28. "RRAM,Restricted Register Access Mode" "0: Register access is fully enabled,1: Register access is restricted and only the CR.."
newline
bitfld.long 0x00 24.--27. "HRL,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "NCTX,Number of Contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "MODE,Operating Mode" "0: Operating in Normal mode (NRM),1: Unused (reserved),2: Unused (reserved),3: Operating in Logically Disabled Mode (LDM)"
bitfld.long 0x00 1. "MDPCP,MDPC Present" "0,1"
endif
repeat 4. (increment 0 1)(increment 0 0x40)
tree "CTX[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0xD00)++0x03
line.long 0x00 "CTX_KEY0,AES Key Word"
hexmask.long 0x00 0.--31. 1. "KEY,AES Key"
group.long ($2+0xD04)++0x03
line.long 0x00 "CTX_KEY1,AES Key Word"
hexmask.long 0x00 0.--31. 1. "KEY,AES Key"
group.long ($2+0xD08)++0x03
line.long 0x00 "CTX_KEY2,AES Key Word"
hexmask.long 0x00 0.--31. 1. "KEY,AES Key"
group.long ($2+0xD0C)++0x03
line.long 0x00 "CTX_KEY3,AES Key Word"
hexmask.long 0x00 0.--31. 1. "KEY,AES Key"
group.long ($2+0xD10)++0x03
line.long 0x00 "CTX_CTR0,AES Counter Word"
hexmask.long 0x00 0.--31. 1. "CTR,AES Counter"
group.long ($2+0xD14)++0x03
line.long 0x00 "CTX_CTR1,AES Counter Word"
hexmask.long 0x00 0.--31. 1. "CTR,AES Counter"
group.long ($2+0xD18)++0x03
line.long 0x00 "CTX_RGD_W0,AES Region Descriptor Word0"
hexmask.long.tbyte 0x00 10.--31. 1. "SRTADDR,Start Address"
group.long ($2+0xD1C)++0x03
line.long 0x00 "CTX_RGD_W1,AES Region Descriptor Word1"
hexmask.long.tbyte 0x00 10.--31. 1. "ENDADDR,End Address"
bitfld.long 0x00 2. "RO,Read-Only" "0: The context registers can be accessed..,1: The context registers are read-only and.."
newline
bitfld.long 0x00 1. "ADE,AES Decryption Enable" "0: Bypass the fetched data,1: Perform the CTR-AES128 mode decryption on the.."
bitfld.long 0x00 0. "VLD,Valid" "0: Context is invalid,1: Context is valid"
endif
tree.end
repeat.end
tree.end
tree "PINT (Pin Interrupts and Pattern Match)"
base ad:0x40025000
group.long 0x00++0x03
line.long 0x00 "ISEL,Pin Interrupt Mode"
hexmask.long.byte 0x00 0.--7. 1. "PMODE,Interrupt mode"
group.long 0x04++0x03
line.long 0x00 "IENR,Pin Interrupt Level or Rising Edge Interrupt Enable"
hexmask.long.byte 0x00 0.--7. 1. "ENRL,Enable Interrupt"
wgroup.long 0x08++0x03
line.long 0x00 "SIENR,Pin Interrupt Level or Rising Edge Interrupt Set"
hexmask.long.byte 0x00 0.--7. 1. "SETENRL,Set bits in the IENR"
group.long 0x0C++0x03
line.long 0x00 "CIENR,Pin Interrupt Level (Rising Edge Interrupt) Clear"
hexmask.long.byte 0x00 0.--7. 1. "CENRL,Clear bits in the IENR"
group.long 0x10++0x03
line.long 0x00 "IENF,Pin Interrupt Active Level or Falling Edge Interrupt Enable"
hexmask.long.byte 0x00 0.--7. 1. "ENAF,Enable Interrupt"
wgroup.long 0x14++0x03
line.long 0x00 "SIENF,Pin Interrupt Active Level or Falling Edge Interrupt Set"
hexmask.long.byte 0x00 0.--7. 1. "SETENAF,Set bits in the IENF"
wgroup.long 0x18++0x03
line.long 0x00 "CIENF,Pin Interrupt Active Level or Falling Edge Interrupt Clear"
hexmask.long.byte 0x00 0.--7. 1. "CENAF,Clear bits in the IENF"
group.long 0x1C++0x03
line.long 0x00 "RISE,Pin Interrupt Rising Edge"
hexmask.long.byte 0x00 0.--7. 1. "RDET,Rising edge detect"
group.long 0x20++0x03
line.long 0x00 "FALL,Pin Interrupt Falling Edge"
hexmask.long.byte 0x00 0.--7. 1. "FDET,Falling edge detect"
group.long 0x24++0x03
line.long 0x00 "IST,Pin Interrupt Status"
hexmask.long.byte 0x00 0.--7. 1. "PSTAT,Pin interrupt status"
group.long 0x28++0x03
line.long 0x00 "PMCTRL,Pattern Match Interrupt Control"
hexmask.long.byte 0x00 24.--31. 1. "PMAT,Pattern Matches"
bitfld.long 0x00 1. "ENA_RXEV,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true" "0: Disabled- RXEV output to the CPU is disabled,1: Enabled- RXEV output to the CPU is enabled"
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bitfld.long 0x00 0. "SEL_PMATCH,Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function" "0: Pin interrupt- interrupts are driven in..,1: Pattern match- interrupts are driven in.."
group.long 0x2C++0x03
line.long 0x00 "PMSRC,Pattern Match Interrupt Bit-Slice Source"
bitfld.long 0x00 29.--31. "SRC7,Selects the input source for bit slice 7" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 26.--28. "SRC6,Selects the input source for bit slice 6" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
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bitfld.long 0x00 23.--25. "SRC5,Selects the input source for bit slice 5" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 20.--22. "SRC4,Selects the input source for bit slice 4" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
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bitfld.long 0x00 17.--19. "SRC3,Selects the input source for bit slice 3" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 14.--16. "SRC2,Selects the input source for bit slice 2" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
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bitfld.long 0x00 11.--13. "SRC1,Selects the input source for bit slice 1" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 8.--10. "SRC0,Selects the input source for bit slice 0" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
group.long 0x30++0x03
line.long 0x00 "PMCFG,Pattern Match Interrupt Bit Slice Configuration"
bitfld.long 0x00 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
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bitfld.long 0x00 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
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bitfld.long 0x00 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
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bitfld.long 0x00 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
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bitfld.long 0x00 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint" "0: No effect,1: Endpoint"
bitfld.long 0x00 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint" "0: No effect,1: Endpoint"
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bitfld.long 0x00 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint" "0: No effect,1: Endpoint"
bitfld.long 0x00 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint" "0: No effect,1: Endpoint"
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bitfld.long 0x00 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint" "0: No effect,1: Endpoint"
bitfld.long 0x00 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint" "0: No effect,1: Endpoint"
newline
bitfld.long 0x00 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint" "0: No effect,1: Endpoint"
tree.end
tree "PMC (Power Management)"
base ad:0x40135000
rgroup.long 0x04++0x03
line.long 0x00 "STATUS,Status"
bitfld.long 0x00 0. "ACTIVEFSM,General sequencer and finite state machine status" "0: All PMC finite state machines are idle,1: One or more PMC finite state machines are.."
group.long 0x08++0x03
line.long 0x00 "FLAGS,Wakeup Interrupt Reset Flags"
eventfld.long 0x00 31. "DEEPPDF,Deep powerdown wakeup flag" "0: No deep powerdown wakeup since last time flag..,1: Deep powerdown was entered since the last.."
eventfld.long 0x00 30. "RESETNPADF,Reset pad flag" "0: No reset detected since last time this flag..,1: Reset pad wakeup caused a wakeup or reset.."
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eventfld.long 0x00 29. "INTNPADF,Interrupt pin flag" "0: No interrupt detected since flag last cleared,1: Pad interrupt caused a wakeup or interrupt.."
eventfld.long 0x00 28. "AUTOWKF,PMC Auto Wakeup Interrupt flag" "0: No PMC Auto Wakeup Interrupt detected since..,1: PMC Auto wakeup caused a deep sleep wakeup.."
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eventfld.long 0x00 27. "RTCF,RTC Wakeup from deep powerdown mode flag" "0: No RTC wakeup detected since last time flag..,1: RTC wakeup caused a deep powerdown wakeup"
eventfld.long 0x00 24. "HVD1V8F,vdd1v8 High-Voltage Detector Flag" "0: vdd1v8 HVD has not tripped since last clear,1: vdd1v8 HVD tripped since last time this bit.."
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eventfld.long 0x00 22. "HVDCOREF,vddcore High-Voltage Detector Flag" "0: vddcore HVD has not tripped since last clear,1: vddcore HVD tripped since last time this bit.."
eventfld.long 0x00 20. "LVDCOREF,vddcore Low-Voltage Detector Flag" "0: vddcore LVD has not tripped since last clear,1: vddcore LVD tripped since last time this bit.."
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eventfld.long 0x00 18. "PORAO18F,vdd_ao18 power on reset flag" "0: No vdd_ao18 power on event detected since..,1: vdd_ao18 power on detect caused a reset"
eventfld.long 0x00 17. "POR1V8F,vdd1v8 power on reset flag" "0: No vdd1v8 power on event detected since last..,1: vdd1v8 power on detect caused a reset or deep.."
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eventfld.long 0x00 16. "PORCOREF,vddcore POR Flag" "0: vddcore POR was not tripped since the last..,1: POR triggered by the vddcore POR monitor"
group.long 0x0C++0x03
line.long 0x00 "CTRL,PMC control register"
bitfld.long 0x00 29. "INTRPADEN,PMIC_IRQ_N enable" "0: Interrupt pad low has no effect,1: Interrupt pad low triggers an interrupt and.."
bitfld.long 0x00 28. "AUTOWKEN,PMC automatic wakeup enable and interrupt enable" "0: Auto wakeup interrupt and counter disabled,1: Auto wakeup interrupt generated when PMC.."
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bitfld.long 0x00 25. "HVD1V8RE,vdd1v8 High-Voltage Detector Reset Enable" "0: vdd1v8 HVD reset disabled,1: vdd1v8 HVD causes reset"
bitfld.long 0x00 24. "HVD1V8IE,vdd1v8 High-Voltage Detector Interrupt Enable" "0: vdd1v8 HVD interrupt disabled,1: vdd1v8 HVD causes interrupt and wakeup from.."
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bitfld.long 0x00 23. "HVDCORERE,vddcore High-Voltage Detector Reset Enable" "0: vddcore HVD reset disabled,1: vddcore HVD causes reset"
bitfld.long 0x00 22. "HVDCOREIE,vddcore High-Voltage Detector Interrupt Enable" "0: vddcore HVD interrupt disabled,1: vddcore HVD causes interrupt and wakeup from.."
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bitfld.long 0x00 21. "LVDCORERE,vddcore Low-Voltage Detector Reset Enable" "0: vddcore LVD reset disabled,1: vddcore LVD causes reset"
bitfld.long 0x00 20. "LVDCOREIE,vddcore Low-Voltage Detector Interrupt Enable" "0: vddcore LVD interrupt disabled,1: vddcore LVD causes interrupt and wakeup from.."
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bitfld.long 0x00 18. "OTPSWREN,OTP Switch RBB enable" "0,1"
bitfld.long 0x00 4. "BUFEN,Enable analog buffer for references or ATX2" "0: Disabled,1: Enabled"
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bitfld.long 0x00 1. "CLKDIVEN,Internal clock divider enable" "0: 16MHz clock selected,1: 4MHz clock selected"
bitfld.long 0x00 0. "APPLYCFG,Apply updated PMC PDRUNCFG bits" "0: Always reads 0,1: Write 1 = initiate update sequencing of PMC.."
group.long 0x10++0x03
line.long 0x00 "RUNCTRL,PMC controls used during run mode"
bitfld.long 0x00 0.--5. "CORELVL,Vddcore voltage value when SYSCTL is in run mode" "?,1: VALUE_01,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: VALUE_10,?,?,19: VALUE_13,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,38: VALUE_26,?,?,?,?,?,?,?,?,?,?,?,50: VALUE_32,?..."
group.long 0x14++0x03
line.long 0x00 "SLEEPCTRL,PMC controls used during deep sleep mode"
bitfld.long 0x00 0.--5. "CORELVL,Vddcore voltage value when SYSCTL is in sleep mode" "0: VALUE_0x00,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,38: 1.007498V = 0.595833 + 0x26 10.8333mV,?,?,?,?,?,?,?,?,?,?,?,50: VALUE_0x32,?..."
group.long 0x18++0x03
line.long 0x00 "LVDCORECTRL,PMC Active vddcore LVD monitor trip adjust"
bitfld.long 0x00 0.--3. "LVDCORELVL,Vddcore LVD falling trip voltage" "0: VALUE_0b0000,?,?,?,?,?,?,7: 0.825V = 0.720V + 7 15mV,?,?,?,?,?,?,?,15: VALUE_0b1111"
group.long 0x24++0x03
line.long 0x00 "AUTOWKUP,PMC Automatic wakeup from deepsleep mode"
hexmask.long.word 0x00 0.--15. 1. "AUTOWKTIME,Auto wake up delay timer"
group.long 0x28++0x03
line.long 0x00 "PMICCFG,PMIC Power Mode Select Control Configuration"
bitfld.long 0x00 7. "VDD1V8M3,vdd1v8 state in PMIC mode 3" "0: DISABLE,1: Powered"
bitfld.long 0x00 6. "VDD1V8M2,vdd1v8 state in PMIC mode 2" "0: DISABLE,1: Powered"
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bitfld.long 0x00 5. "VDD1V8M1,vdd1v8 state in PMIC mode 1" "0: DISABLE,1: Powered"
bitfld.long 0x00 4. "VDD1V8M0,vdd1v8 state in PMIC mode 0" "0: DISABLE,1: Powered"
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bitfld.long 0x00 3. "VDDCOREM3,vddcore state in PMIC mode 3" "0: DISABLE,1: Powered"
bitfld.long 0x00 2. "VDDCOREM2,vddcore state in PMIC mode 2" "0: DISABLE,1: Powered"
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bitfld.long 0x00 1. "VDDCOREM1,vddcore state in PMIC mode 1" "0: DISABLE,1: Powered"
bitfld.long 0x00 0. "VDDCOREM0,vddcore state in PMIC mode 0" "0: DISABLE,1: Powered"
group.long 0x2C++0x03
line.long 0x00 "PADVRANGE,PMC GPIO VDDIO Range Selection Control"
bitfld.long 0x00 8.--9. "VDDIO_4RANGE,VDDIO4RANGE" "0: 1.71 - 1.98V,1: 1.71 - 1.98V vdde detector off,2: Not allowed,3: Not allowed (hardware translates to 00 =.."
bitfld.long 0x00 6.--7. "VDDIO_3RANGE,VDDIO3RANGE" "0: 1.71 - 3.6V,1: 1.71 - 1.98V vdde detector off,2: 3.00 - 3.6V vdde detector off,3: Not allowed (hardware translates to 00 =.."
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bitfld.long 0x00 4.--5. "VDDIO_2RANGE,VDDIO2RANGE" "0: 1.71 - 1.98V,1: 1.71 - 1.98V vdde detector off,2: Not allowed,3: Not allowed (hardware translates to 00 =.."
bitfld.long 0x00 2.--3. "VDDIO_1RANGE,VDDIO1RANGE It is recommended that the user change this value to 01 to reduce power consumption" "0: 1.71 - 1.98V,1: 1.71 - 1.98V vdde detector off,2: Not allowed,3: Not allowed (hardware translates to 00 =.."
newline
bitfld.long 0x00 0.--1. "VDDIO_0RANGE,VDDIO0RANGE" "0: 1.71 - 1.98V,1: 1.71 - 1.98V vdde detector off,2: Not allowed,3: Not allowed (hardware translates to 10)"
group.long 0x30++0x03
line.long 0x00 "MEMSEQCTRL,PMC Memory sequencer Control"
bitfld.long 0x00 0.--5. "MEMSEQNUM,Number of memories to turn on/off at a time" "0: In SPLLRAMs case 1st array power then..,1: Turn on 1st memory partition at a time..,?,?,?,5: Turn on 5th memory partitions in parallel..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: All memories are switched on/off at the same.."
group.long 0x60++0x03
line.long 0x00 "TSENSOR,PMC Temperature Sensor Control"
bitfld.long 0x00 0.--3. "TSENSM,Temperature sensor mode select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "POWERQUAD (PowerQuad)"
base ad:0x40200000
group.long 0x00++0x03
line.long 0x00 "OUTBASE,Output Base"
hexmask.long 0x00 0.--31. 1. "OUTBASE,Base address register for the output region"
group.long 0x04++0x03
line.long 0x00 "OUTFORMAT,Output Format"
hexmask.long.byte 0x00 8.--15. 1. "OUT_SCALER,Output Scaler Value"
bitfld.long 0x00 4.--5. "OUT_FORMATEXT,Output External Format" "0,1,2,3"
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bitfld.long 0x00 0.--1. "OUT_FORMATINT,Output Internal Format" "0,1,2,3"
group.long 0x08++0x03
line.long 0x00 "TMPBASE,Temporary Base"
hexmask.long 0x00 0.--31. 1. "TMPBASE,Base address register for the temporary region"
group.long 0x0C++0x03
line.long 0x00 "TMPFORMAT,Temporary Format"
hexmask.long.byte 0x00 8.--15. 1. "TMP_SCALER,Temporary Scaler Value"
bitfld.long 0x00 4.--5. "TMP_FORMATEXT,Temporary External Format" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "TMP_FORMATINT,Temporary Internal Format" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "INABASE,Input A Base"
hexmask.long 0x00 0.--31. 1. "INABASE,Input A Base"
group.long 0x14++0x03
line.long 0x00 "INAFORMAT,Input A Format"
hexmask.long.byte 0x00 8.--15. 1. "INA_SCALER,Input A Scaler Value"
bitfld.long 0x00 4.--5. "INA_FORMATEXT,Input A External Format" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "INA_FORMATINT,Input A Internal Format" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "INBBASE,Input B Base"
hexmask.long 0x00 0.--31. 1. "INBBASE,Input B Base"
group.long 0x1C++0x03
line.long 0x00 "INBFORMAT,Input B Format"
hexmask.long.byte 0x00 8.--15. 1. "INB_SCALER,Input B Scaler Value"
bitfld.long 0x00 4.--5. "INB_FORMATEXT,Input B External Format" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "INB_FORMATINT,Input B Internal Format" "0,1,2,3"
group.long 0x100++0x03
line.long 0x00 "CONTROL,Control"
rbitfld.long 0x00 31. "INST_BUSY,Instruction Busy" "0,1"
bitfld.long 0x00 4.--7. "DECODE_MACHINE,Decode Machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DECODE_OPCODE,Decode Opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x104++0x03
line.long 0x00 "LENGTH,Length"
hexmask.long 0x00 0.--31. 1. "INST_LENGTH,Instruction Length"
group.long 0x108++0x03
line.long 0x00 "CPPRE,Coprocessor Pre-scale"
bitfld.long 0x00 17. "CPPRE_SAT8,Saturation 8" "0: SAT_8_BITS,1: SAT_16_BITS"
bitfld.long 0x00 16. "CPPRE_SAT,Saturation" "0: No saturation,1: Forces sub-32 bit saturation"
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hexmask.long.byte 0x00 8.--15. 1. "CPPRE_OUT,Output"
hexmask.long.byte 0x00 0.--7. 1. "CPPRE_IN,Input"
group.long 0x10C++0x03
line.long 0x00 "MISC,Miscellaneous"
hexmask.long 0x00 0.--31. 1. "INST_MISC,For Matrix : Used for scaling factor"
group.long 0x110++0x03
line.long 0x00 "CURSORY,Cursory"
bitfld.long 0x00 0. "CURSORY,Cursory Mode" "0: Disable Cursory mode,1: Enable Cursory Mode"
group.long 0x180++0x03
line.long 0x00 "CORDIC_X,Cordic input X"
hexmask.long 0x00 0.--31. 1. "CORDIC_X,Cordic Input x"
group.long 0x184++0x03
line.long 0x00 "CORDIC_Y,Cordic Input Y"
hexmask.long 0x00 0.--31. 1. "CORDIC_Y,Cordic Input y"
group.long 0x188++0x03
line.long 0x00 "CORDIC_Z,Cordic Input Z"
hexmask.long 0x00 0.--31. 1. "CORDIC_Z,Cordic Input z"
group.long 0x18C++0x03
line.long 0x00 "ERRSTAT,Error Status"
bitfld.long 0x00 4. "BUSERROR,Bus Error" "0: NO_ERROR,1: Error on Bus"
bitfld.long 0x00 3. "UNDERFLOW,Underflow" "0: NO_ERROR,1: Error on Underflow"
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bitfld.long 0x00 2. "FIXEDOVERFLOW,Fixed Point Overflow" "0: NO_ERROR,1: Error on Fixed Point Overflow"
bitfld.long 0x00 1. "NAN,Floating Point NaN" "0: NO_ERROR,1: Error on Floating Point NaN"
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bitfld.long 0x00 0. "OVERFLOW,Floating Point Overflow" "0: NO_ERROR,1: Error on Floating Point Overflow"
group.long 0x190++0x03
line.long 0x00 "INTREN,Interrupt Enable"
bitfld.long 0x00 7. "INTR_COMP,Interrupt on Instruction Completion" "0: DISABLE,1: Enable interrupt on instruction completion"
bitfld.long 0x00 4. "INTR_BERR,Interrupt on AHBM Bus Error" "0: DISABLE,1: Enable interrupt on AHBM Bus Error"
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bitfld.long 0x00 3. "INTR_UFLOW,Interrupt on Subnormal Truncation" "0: DISABLE,1: Enable interrupt on subnormal truncation"
bitfld.long 0x00 2. "INTR_FIXED,Interrupt on Fixed Point Overflow" "0: DISABLE,1: Enable interrupt on fixed point overflow"
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bitfld.long 0x00 1. "INTR_NAN,Interrupt Floating Point NaN" "0: DISABLE,1: Enable interrupt on floating point NaN"
bitfld.long 0x00 0. "INTR_OFLOW,Interrupt Floating Point Overflow" "0: DISABLE,1: Enable interrupt on floating point overflow"
group.long 0x194++0x03
line.long 0x00 "EVENTEN,Event Enable"
bitfld.long 0x00 7. "EVENT_COMP,Event Trigger on Instruction Completion" "0: DISABLE,1: Enable event trigger on instruction completion"
bitfld.long 0x00 4. "EVENT_BERR,Event Trigger on AHBM Bus Error" "0: DISABLE,1: Enable event trigger on AHBM bus error"
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bitfld.long 0x00 3. "EVENT_UFLOW,Event Trigger on Subnormal Truncation" "0: DISABLE,1: Enable event trigger on subnormal truncation"
bitfld.long 0x00 2. "EVENT_FIXED,Event Trigger on Fixed Point Overflow" "0: DISABLE,1: Enable event trigger on fixed point overflow"
newline
bitfld.long 0x00 1. "EVENT_NAN,Event Trigger on Floating Point NaN" "0: DISABLE,1: Enable event trigger on floating point NaN"
bitfld.long 0x00 0. "EVENT_OFLOW,Event Trigger on Floating Point Overflow" "0: DISABLE,1: Enable event trigger on Floating point overflow"
group.long 0x198++0x03
line.long 0x00 "INTRSTAT,Interrupt Status"
bitfld.long 0x00 0. "INTR_STAT,Interrupt Status" "0: No new interrupt,1: Interrupt captured"
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "GPREG[$1],General Purpose Register Bank n $1"
hexmask.long 0x00 0.--31. 1. "GPREG,General Purpose Register Bank"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x240)++0x03
line.long 0x00 "COMPREG[$1],Compute Register Bank n $1"
hexmask.long 0x00 0.--31. 1. "COMPREG,Compute Register Bank"
repeat.end
tree.end
tree "PUF (PUF Controller)"
base ad:0x40006000
group.long 0x00++0x03
line.long 0x00 "CTRL,PUF Control"
bitfld.long 0x00 6. "GETKEY,Get Key" "0,1"
bitfld.long 0x00 4. "SETKEY,Set Key" "0,1"
newline
bitfld.long 0x00 3. "GENERATEKEY,Set Intrinsic Key" "0,1"
bitfld.long 0x00 2. "START,Start" "0,1"
newline
bitfld.long 0x00 1. "ENROLL,Enroll" "0,1"
bitfld.long 0x00 0. "ZEROIZE,Zeroize" "0,1"
group.long 0x04++0x03
line.long 0x00 "KEYINDEX,PUF Key Index"
bitfld.long 0x00 0.--3. "KEYIDX,Key index for Set Key operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "KEYSIZE,PUF Key Size"
bitfld.long 0x00 0.--5. "KEYSIZE,Key Size for Set Key operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x20++0x03
line.long 0x00 "STAT,PUF Status"
bitfld.long 0x00 7. "CODEOUTAVAIL,Code Out Available" "0,1"
bitfld.long 0x00 6. "CODEINREQ,Code In Request" "0,1"
newline
bitfld.long 0x00 5. "KEYOUTAVAIL,Key Out Available" "0,1"
bitfld.long 0x00 4. "KEYINREQ,Key In Request" "0,1"
newline
bitfld.long 0x00 2. "ERROR,Error" "0,1"
bitfld.long 0x00 1. "SUCCESS,Success" "0,1"
newline
bitfld.long 0x00 0. "BUSY,Busy" "0,1"
rgroup.long 0x28++0x03
line.long 0x00 "ALLOW,PUF Allow"
bitfld.long 0x00 3. "ALLOWGETKEY,Allow Get Key" "0,1"
bitfld.long 0x00 2. "ALLOWSETKEY,Allow Set Key" "0,1"
newline
bitfld.long 0x00 1. "ALLOWSTART,Allow Start" "0,1"
bitfld.long 0x00 0. "ALLOWENROLL,Allow Enroll" "0,1"
wgroup.long 0x40++0x03
line.long 0x00 "KEYINPUT,PUF Key Input"
hexmask.long 0x00 0.--31. 1. "KEYIN,Key Input Data"
wgroup.long 0x44++0x03
line.long 0x00 "CODEINPUT,PUF Code Input"
hexmask.long 0x00 0.--31. 1. "CODEIN,AC/KC Input Data"
rgroup.long 0x48++0x03
line.long 0x00 "CODEOUTPUT,PUF Code Output"
hexmask.long 0x00 0.--31. 1. "CODEOUT,AC/KC Output Data"
rgroup.long 0x60++0x03
line.long 0x00 "KEYOUTINDEX,PUF Key Output Index"
bitfld.long 0x00 0.--3. "KEYOUTIDX,Key Output Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x64++0x03
line.long 0x00 "KEYOUTPUT,PUF Key Output"
hexmask.long 0x00 0.--31. 1. "KEYOUT,Key Output Data"
group.long 0xDC++0x03
line.long 0x00 "IFSTAT,PUF Interface Status and Clear"
eventfld.long 0x00 0. "ERROR,Error" "0,1"
group.long 0x100++0x03
line.long 0x00 "INTEN,PUF Interrupt Enable"
bitfld.long 0x00 7. "CODEOUTAVAILEN,Enable corresponding interrupt in STAT which is next part of AC/KC is available" "0,1"
bitfld.long 0x00 6. "CODEINREQEN,Enable corresponding interrupt in STAT which is request for next part of AC/KC" "0,1"
newline
bitfld.long 0x00 5. "KEYOUTAVAILEN,Enable corresponding interrupt in STAT which is next part of key is available" "0,1"
bitfld.long 0x00 4. "KEYINREQEN,Enable corresponding interrupt in STAT which is request for next part of key" "0,1"
newline
bitfld.long 0x00 2. "ERROREN,Enable corresponding interrupt in STAT which indicates that PUF is in the error state and no operations can be performed" "0,1"
bitfld.long 0x00 1. "SUCCESEN,Enable corresponding interrupt in STAT which indicates last operation was successful" "0,1"
newline
bitfld.long 0x00 0. "READYEN,Enable corresponding interrupt in STAT which indicates that the initialization or a operation is completed" "0,1"
group.long 0x104++0x03
line.long 0x00 "INTSTAT,PUF Interrupt Status"
bitfld.long 0x00 7. "CODEOUTAVAIL,Code Out Available" "0,1"
bitfld.long 0x00 6. "CODEINREQ,Code In Request" "0,1"
newline
bitfld.long 0x00 5. "KEYOUTAVAIL,Key Out Available" "0,1"
bitfld.long 0x00 4. "KEYINREQ,Key In Request" "0,1"
newline
bitfld.long 0x00 2. "ERROR,Error" "0,1"
bitfld.long 0x00 1. "SUCCESS,Success" "0,1"
newline
eventfld.long 0x00 0. "READY,Ready" "0,1"
group.long 0x108++0x03
line.long 0x00 "PWRCTRL,PUF Power Control"
bitfld.long 0x00 2. "CK_DIS,PUF RAM Clock Disable" "0: PUF RAM clock is disabled,1: PUF RAM clock is enabled"
bitfld.long 0x00 0. "RAM_ON,RAM Power On" "0: POWER_OFF,1: POWER_ON"
group.long 0x10C++0x03
line.long 0x00 "CFG,PUF Configuration"
bitfld.long 0x00 1. "BLOCKKEYOUTPUT,Block Key Output Data" "0: Disabled,1: ENABLED"
bitfld.long 0x00 0. "BLOCKENROLL_SETKEY,Block Enroll and Set Key Operation" "0: DISABLED,1: ENABLED"
group.long 0x200++0x03
line.long 0x00 "KEYLOCK,Key Lock"
bitfld.long 0x00 6.--7. "KEY3,Key 3" "0: Write access to KEY3MASK KEYENABLE[KEY3] and..,1: Write access to KEY3MASK KEYENABLE[KEY3] and..,2: Write access to KEY3MASK KEYENABLE[KEY3] and..,3: Write access to KEY3MASK KEYENABLE[KEY3] and.."
bitfld.long 0x00 4.--5. "KEY2,Key 2" "0: Write access to KEY2MASK KEYENABLE[KEY2] and..,1: Write access to KEY2MASK KEYENABLE[KEY2] and..,2: Write access to KEY2MASK KEYENABLE[KEY2] and..,3: Write access to KEY2MASK KEYENABLE[KEY2] and.."
newline
bitfld.long 0x00 2.--3. "KEY1,Key 1" "0: Write access to KEY1MASK KEYENABLE[KEY1] and..,1: Write access to KEY1MASK KEYENABLE[KEY1] and..,2: Write access to KEY1MASK KEYENABLE[KEY1] and..,3: Write access to KEY1MASK KEYENABLE[KEY1] and.."
bitfld.long 0x00 0.--1. "KEY0,Key 0" "0: Write access to KEY0MASK KEYENABLE[KEY0] and..,1: Write access to KEY0MASK KEYENABLE[KEY0] and..,2: Write access to KEY0MASK KEYENABLE[KEY0] and..,3: Write access to KEY0MASK KEYENABLE[KEY0] and.."
group.long 0x204++0x03
line.long 0x00 "KEYENABLE,Key Enable"
bitfld.long 0x00 6.--7. "KEY3,Key 3" "0: Data coming from the PUF Index 0 interface..,1: Data coming from the PUF Index 0 interface..,2: Data coming from the PUF Index 0 interface..,3: Data coming from the PUF Index 0 interface.."
bitfld.long 0x00 4.--5. "KEY2,Key 2" "0: Data coming from the PUF Index 0 interface..,1: Data coming from the PUF Index 0 interface..,2: Data coming from the PUF Index 0 interface..,3: Data coming from the PUF Index 0 interface.."
newline
bitfld.long 0x00 2.--3. "KEY1,Key 1" "0: Data coming from the PUF Index 0 interface..,1: Data coming from the PUF Index 0 interface..,2: Data coming from the PUF Index 0 interface..,3: Data coming from the PUF Index 0 interface.."
bitfld.long 0x00 0.--1. "KEY0,Key 0" "0: DISABLED,1: DISABLED,2: ENABLED,3: DISABLED"
wgroup.long 0x208++0x03
line.long 0x00 "KEYRESET,Key Reset"
bitfld.long 0x00 6.--7. "KEY3,Key 3" "?,?,2: Reset KEY3 Hold register and SHIFT_STATUS[KEY3],?..."
bitfld.long 0x00 4.--5. "KEY2,Key 2" "?,?,2: Reset KEY2 Hold register and SHIFT_STATUS[KEY2],?..."
newline
bitfld.long 0x00 2.--3. "KEY1,Key 1" "?,?,2: Reset KEY1 Hold register and SHIFT_STATUS[KEY1],?..."
bitfld.long 0x00 0.--1. "KEY0,Key 0" "?,?,2: Reset KEY0 Hold register and SHIFT_STATUS[KEY0],?..."
group.long 0x20C++0x03
line.long 0x00 "IDXBLK_L,Index Block Low"
bitfld.long 0x00 30.--31. "LOCK_IDX,Lock Index" "0,1,2,3"
bitfld.long 0x00 14.--15. "IDX7,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 12.--13. "IDX6,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 10.--11. "IDX5,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 8.--9. "IDX4,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 6.--7. "IDX3,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 4.--5. "IDX2,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 2.--3. "IDX1,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
group.long 0x210++0x03
line.long 0x00 "IDXBLK_H_DP,Index Block High Duplicate"
bitfld.long 0x00 14.--15. "IDX15,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 12.--13. "IDX14,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 10.--11. "IDX13,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 8.--9. "IDX12,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 6.--7. "IDX11,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 4.--5. "IDX10,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 2.--3. "IDX9,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 0.--1. "IDX8,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
repeat 4. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x214)++0x03
line.long 0x00 "KEYMASK[$1],Key Mask x $1"
hexmask.long 0x00 0.--31. 1. "KEYMASK,Key a Mask"
repeat.end
group.long 0x254++0x03
line.long 0x00 "IDXBLK_H,Index Block High"
bitfld.long 0x00 30.--31. "LOCK_IDX,Lock Index" "0,1,2,3"
bitfld.long 0x00 14.--15. "IDX15,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 12.--13. "IDX14,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 10.--11. "IDX13,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 8.--9. "IDX12,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 6.--7. "IDX11,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 4.--5. "IDX10,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 2.--3. "IDX9,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 0.--1. "IDX8,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
group.long 0x258++0x03
line.long 0x00 "IDXBLK_L_DP,Index Block Low Duplicate"
bitfld.long 0x00 14.--15. "IDX7,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 12.--13. "IDX6,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 10.--11. "IDX5,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 8.--9. "IDX4,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 6.--7. "IDX3,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 4.--5. "IDX2,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
newline
bitfld.long 0x00 2.--3. "IDX1,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
bitfld.long 0x00 0.--1. "IDX0,Index n" "?,1: PUF index is blocked,2: PUF index is accessible,?..."
tree.end
tree "RSTCTL (Reset Controller 0)"
tree "RSTCTL0"
base ad:0x40000000
group.long 0x00++0x03
line.long 0x00 "SYSRSTSTAT,System Reset Status Register"
bitfld.long 0x00 7. "WDT1_RESET,WatchDog Timer 1 reset was detected" "0: No WDT1 reset event detected,1: WDT1 reset event detected"
bitfld.long 0x00 6. "WDT0_RESET,WatchDog Timer 0 reset was detected" "0: No WDT0 reset event detected,1: WDT0 reset event detected"
newline
bitfld.long 0x00 5. "ARM_RESET,ARM reset was detected" "0: No ARM reset event is detected,1: ARM reset was detected"
bitfld.long 0x00 4. "PAD_RESET,PAD reset was detected" "0: PAD_RESET_IS_NOT_DETECTED,1: PAD event was detected"
newline
bitfld.long 0x00 0. "VDD_POR,VDD Power-On Reset (POR) was detected" "0: VDD_POR_EVENT_IS_NOT_DETECTED,1: VDD_POR_EVENT_WAS_DETECTED"
group.long 0x10++0x03
line.long 0x00 "PRSTCTL0,Peripheral Reset Control Register 0"
bitfld.long 0x00 30. "SMARTDMA,SMARTDMA Event/Algorithm handler reset control" "0: SMARTDMA_CLR,1: SMARTDMA_SET"
bitfld.long 0x00 29. "MIPI_DSI_PHY,MIPI DSI PHY reset control" "0: MIPI_DSI_PHY_CLR,1: MIPI_DSI_PHY_SET"
newline
bitfld.long 0x00 28. "MIPI_DSI_CONTROLLER,MIPI Digital serial Interface controller reset control" "0: MIPI_DSI_CONTROLLER_CLR,1: MIPI_DSI_CONTROLLER_SET"
bitfld.long 0x00 27. "DISPLAY_CONTROLLER,Display Controller reset control" "0: DISPLAY_CONTROLLER_CLR,1: DISPLAY_CONTROLLER_SET"
newline
bitfld.long 0x00 26. "GPU,GPU reset control" "0: Clear Reset,1: Set Reset"
bitfld.long 0x00 24. "SCT,SC Timer reset control" "0: Clear Reset,1: Set Reset"
newline
bitfld.long 0x00 23. "USBHS_SRAM,USB RAM reset control" "0: USBHS_SRAM_CLR,1: USBHS_SRAM_SET"
bitfld.long 0x00 22. "USBHS_HOST,USB HOST reset control" "0: USBHS_HOST_CLR,1: USBHS_HOST_SET"
newline
bitfld.long 0x00 21. "USBHS_DEVICE,USB HS Device reset control" "0: USBHS_DEVICE_CLR,1: USBHS_DEVICE_SET"
bitfld.long 0x00 20. "USBHS_PHY,USB PHY reset control" "0: USBHS_PHY_CLR,1: USBHS_PHY_SET"
newline
bitfld.long 0x00 18. "FLEXSPI1,FLEXSPI1 reset control" "0: FLEXSPI1_CLR,1: FLEXSPI1_SET"
bitfld.long 0x00 16. "FLEXSPI0_OTFAD,FLEXSPI0 and OTFAD reset control" "0: FLEXSPI0_OTFAD_CLR,1: FLEXSPI0_OTFAD_SET"
newline
bitfld.long 0x00 12. "RNG,RNG reset control" "0: Clear Reset,1: Set Reset"
bitfld.long 0x00 11. "PUF,PUF reset control" "0: Clear Reset,1: Set Reset"
newline
bitfld.long 0x00 10. "HASHCRYPT,Hash-Crypt reset control" "0: HASHCRYPT_CLR,1: HASHCRYPT_SET"
bitfld.long 0x00 9. "CASPER,CASPER reset control" "0: Clear Reset,1: CASPER_SET"
newline
bitfld.long 0x00 8. "POWERQUAD,POWERQUAD reset control" "0: POWERQUAD_CLR,1: POWERQUAD_SET"
bitfld.long 0x00 3. "AXI_SWITCH,AXI Switch reset control" "0: AXI_SWITCH_CLR,1: AXI_SWITCH_SET"
newline
bitfld.long 0x00 1. "DSP,Fusion F1 DSP reset control" "0: Clear Reset,1: Set Reset"
group.long 0x14++0x03
line.long 0x00 "PRSTCTL1,Peripheral Reset Control Register 1"
bitfld.long 0x00 24. "SHSGPIO0,Secure GPIO 0 reset control" "0: SHSGPIO0_CLR,1: SHSGPIO0_SET"
bitfld.long 0x00 16. "ADC0,Analog-to-Digital converter reset control" "0: Clear Reset,1: Set Reset"
newline
bitfld.long 0x00 15. "ACMP0,Analog comparator reset control" "0: Clear Reset,1: ACMP0_SET"
bitfld.long 0x00 3. "SDIO1,SDIO1 reset control" "0: Clear Reset,1: SDIO1_SET"
newline
bitfld.long 0x00 2. "SDIO0,SDIO0 reset control" "0: Clear Reset,1: SDIO0_SET"
group.long 0x18++0x03
line.long 0x00 "PRSTCTL2,Peripheral Reset Control Register 2"
bitfld.long 0x00 1. "WWDT0,Watchdog timer reset control" "0: Clear Reset,1: WWDT0_SET"
bitfld.long 0x00 0. "UTICK0,Micro-tick timer reset control" "0: Clear Reset,1: UTICK0_SET"
wgroup.long 0x40++0x03
line.long 0x00 "PRSTCTL0_SET,Peripheral Reset Control Register 0 SET"
bitfld.long 0x00 30. "SMARTDMA,SMARTDMA Event/Algorithm handler reset set" "0: SMARTDMA_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 29. "MIPI_DSI_PHY,MIPI DSI PHY reset set" "0: MIPI_DSI_PHY_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 28. "MIPI_DSI_CONTROLLER,MIPI DSI controller reset set" "0: MIPI_DSI_CONTROLLER_CLR,1: MIPI_DSI_CONTROLLER_SET"
bitfld.long 0x00 27. "DISPLAY_CONTROLLER,DISPLAY CONTROLLER reset set" "0: DISPLAY_CONTROLLER_CLR,1: DISPLAY_CONTROLLER_SET"
newline
bitfld.long 0x00 26. "GPU,GPU reset set" "0: No Effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 24. "SCT,SC Timer reset set" "0: No Effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 23. "USBHS_SRAM,USBHS SRAM reset set" "0: USBHS_SRAM_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 22. "USBHS_HOST,USB HOST reset set" "0: USBHS_HOST_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 21. "USBHS_DEVICE,USB Device reset set" "0: USBHS_DEVICE_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 20. "USBHS_PHY,USB PHY reset set" "0: USBHS_PHY_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 18. "FLEXSPI1,FLEXSPI1 reset set" "0: FLEXSPI1_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 16. "FLEXSPI0_OTFAD,FLEXSPI0 and OTFAD reset set" "0: FLEXSPI0_OTFAD_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 12. "RNG,RNG reset set" "0: No Effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 11. "PUF,PUF reset set" "0: No Effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 10. "HASHCRYPT,HASHCRYPT reset set" "0: HASHCRYPT_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 9. "CASPER,CASPER reset set" "0: CASPER_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 8. "POWERQUAD,POWERQUAD reset set" "0: POWERQUAD_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 3. "AXI_SWITCH,AXI SWITCH reset set" "0: AXI_SWITCH_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 1. "DSP,Fusion_ DSP reset set" "0: No Effect,1: Sets the PRSTCTL0 Bit"
wgroup.long 0x44++0x03
line.long 0x00 "PRSTCTL1_SET,Peripheral Reset Control Register 1 SET"
bitfld.long 0x00 24. "SHSGPIO0,SHSGPIO0 reset set" "0: SHSGPIO0_CLR,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 16. "ADC0,ADC0 reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x00 15. "ACMP0,ACMP0 reset set" "0: ACMP0_CLR,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 3. "SDIO1,SDIO1 reset set" "0: SDIO1_CLR,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x00 2. "SDIO0,SDIO0 reset set" "0: SDIO0_CLR,1: Sets the PRSTCTL1 Bit"
wgroup.long 0x48++0x03
line.long 0x00 "PRSTCTL2_SET,Peripheral Reset Control Register 2 SET"
bitfld.long 0x00 1. "WWDT0,WWDT0 reset set" "0: WWDT0_CLR,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x00 0. "UTICK0,Micro-tick timer 0 reset set" "0: UTICK0_CLR,1: Sets the PRSTCTL2 Bit"
wgroup.long 0x70++0x03
line.long 0x00 "PRSTCTL0_CLR,Peripheral Reset Control Register 0 CLR"
bitfld.long 0x00 30. "SMARTDMA,SMARTDMA Event/Algorithm handler reset clear" "0: SMARTDMA_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 29. "MIPI_DSI_PHY,MIPI DSI PHY reset clear" "0: MIPI_DSI_PHY_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 28. "MIPI_DSI_CONTROLLER,MIPI DSI controller reset clear" "0: MIPI_DSI_CONTROLLER_CLR,1: MIPI_DSI_CONTROLLER_SET"
bitfld.long 0x00 27. "DISPLAY_CONTROLLER,DISPLAY CONTROLLER reset clear" "0: DISPLAY_CONTROLLER_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 26. "GPU,GPU reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 24. "SCT,SCT reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 23. "USBHS_SRAM,USBHS SRAM reset clear" "0: USBHS_SRAM_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 22. "USBHS_HOST,USB HOST reset clear" "0: USBHS_HOST_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 21. "USBHS_DEVICE,USB DEVICE reset clear" "0: USBHS_DEVICE_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 20. "USBHS_PHY,USB PHY reset clear" "0: USBHS_PHY_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 18. "FLEXSPI1,FLEXSPI1 reset clear" "0: FLEXSPI1_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 16. "FLEXSPI0_OTFAD,FLEXSPI0 and OTFAD reset clear" "0: FLEXSPI0_OTFAD_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 12. "RNG,RNG reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 11. "PUF,PUF reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 10. "HASHCRYPT,HASHCRYPT reset clear" "0: HASHCRYPT_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 9. "CASPER,CASPER reset clear" "0: CASPER_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 8. "POWERQUAD,POWERQUAD reset clear" "0: POWERQUAD_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 3. "AXI_SWITCH,AXI SWITCH reset clear" "0: AXI_SWITCH_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 1. "DSP,Fusion_ F1 DSP reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
wgroup.long 0x74++0x03
line.long 0x00 "PRSTCTL1_CLR,Peripheral Reset Control Register 1 CLR"
bitfld.long 0x00 24. "SHSGPIO0,Secure HSGPIO0 reset clear" "0: SHSGPIO0_CLR,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 16. "ADC0,ADC0 reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x00 15. "ACMP0,ACMP0 reset clear" "0: ACMP0_CLR,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 3. "SDIO1,SDIO1 reset clear" "0: SDIO1_CLR,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x00 2. "SDIO0,SDIO0 reset clear" "0: SDIO0_CLR,1: Clears the PRSTCTL1 Bit"
wgroup.long 0x78++0x03
line.long 0x00 "PRSTCTL2_CLR,Peripheral Reset Control Register 2 CLR"
bitfld.long 0x00 1. "WWDT0,WWDT0 reset clear" "0: WWDT0_CLR,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x00 0. "UTICK0,Micro-tick timer 0 reset clear" "0: UTICK0_CLR,1: Clears the PRSTCTL2 Bit"
tree.end
tree "RSTCTL1"
base ad:0x40020000
rgroup.long 0x00++0x03
line.long 0x00 "SYSRSTSTAT,System Reset Status Register"
bitfld.long 0x00 7. "WDT1_RESET,WDT1 reset was detected" "0: No WDT1 reset event is detected,1: WDT1_RESET_WAS_DETECTED"
bitfld.long 0x00 6. "WDT0_RESET,WDT0 reset was detected" "0: No WDT0 reset event is detected,1: WDT0_RESET_WAS_DETECTED"
newline
bitfld.long 0x00 5. "ARM_RESET,ARM reset was detected" "0: No ARM reset event is detected,1: ARM_RESET_WAS_DETECTED"
bitfld.long 0x00 4. "PAD_RESET,PAD reset was detected" "0: PAD_RESET_IS_NOT_DETECTED,1: PAD reset event was detected"
newline
bitfld.long 0x00 0. "VDD_POR,VDD Power-On Reset (POR) was detected" "0: VDD_POR_EVENT_IS_NOT_DETECTED,1: VDD_POR_EVENT_WAS_DETECTED"
group.long 0x10++0x03
line.long 0x00 "PRSTCTL0,Peripheral Reset Control Register 0"
bitfld.long 0x00 29. "FLEXIO,FLEXIO reset control" "0: Clear Reset,1: FLEXIO_SET"
bitfld.long 0x00 27. "OSEVENT_TIMER,OSEVENT Timer reset control" "0: OSEVENT_TIMER_CLR,1: OSEVENT_TIMER_SET"
newline
bitfld.long 0x00 25. "FLEXCOMM16,Flexcomm SPI reset control" "0: FLEXCOMM16_SPI1_CLR,1: FLEXCOMM16_SPI1_SET"
bitfld.long 0x00 24. "DMIC0,DMIC0 reset control" "0: Clear Reset,1: DMIC0_SET"
newline
bitfld.long 0x00 23. "FLEXCOMM15_I2C,Flexcomm15 I2C reset control" "0: FLEXCOMM15_I2C_CLR,1: FLEXCOMM15_I2C_SET"
bitfld.long 0x00 22. "FLEXCOMM14,Flexcomm14 SPI0 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
newline
bitfld.long 0x00 21. "FLEXCOMM13,Flexcomm13 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
bitfld.long 0x00 20. "FLEXCOMM12,Flexcomm12 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
newline
bitfld.long 0x00 19. "FLEXCOMM11,Flexcomm11 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
bitfld.long 0x00 18. "FLEXCOMM10,Flexcomm10 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
newline
bitfld.long 0x00 17. "FLEXCOMM9,Flexcomm9 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
bitfld.long 0x00 16. "FLEXCOMM8,Flexcomm8 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
newline
bitfld.long 0x00 15. "FLEXCOMM7,Flexcomm7 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
bitfld.long 0x00 14. "FLEXCOMM6,Flexcomm6 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
newline
bitfld.long 0x00 13. "FLEXCOMM5,Flexcomm5 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
bitfld.long 0x00 12. "FLEXCOMM4,Flexcomm4 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
newline
bitfld.long 0x00 11. "FLEXCOMM3,Flexcomm3 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
bitfld.long 0x00 10. "FLEXCOMM2,Flexcomm2 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
newline
bitfld.long 0x00 9. "FLEXCOMM1,Flexcomm1 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
bitfld.long 0x00 8. "FLEXCOMM0,Flexcomm0 reset control" "0: FLEXCOMM_CLR,1: FLEXCOMM_SET"
group.long 0x14++0x03
line.long 0x00 "PRSTCTL1,Peripheral Reset Control Register 1"
bitfld.long 0x00 31. "FREQME,FREQME reset control" "0: Clear Reset,1: FREQME_SET"
bitfld.long 0x00 29. "SEMA,SEMA reset control" "0: Clear Reset,1: Set Reset"
newline
bitfld.long 0x00 28. "MU,MU reset control" "0: Clear Reset,1: Set Reset"
bitfld.long 0x00 24. "DMAC1,DMAC reset control" "0: Clear Reset,1: Set Reset"
newline
bitfld.long 0x00 23. "DMAC0,DMAC reset control" "0: Clear Reset,1: Set Reset"
bitfld.long 0x00 16. "CRC,CRC reset control" "0: Clear Reset,1: Set Reset"
newline
bitfld.long 0x00 7. "HSGPIO7,HSGPIO[7:0] reset control" "0: Clear Reset,1: HSGPIO_SET"
bitfld.long 0x00 6. "HSGPIO6,HSGPIO[7:0] reset control" "0: Clear Reset,1: HSGPIO_SET"
newline
bitfld.long 0x00 5. "HSGPIO5,HSGPIO[7:0] reset control" "0: Clear Reset,1: HSGPIO_SET"
bitfld.long 0x00 4. "HSGPIO4,HSGPIO[7:0] reset control" "0: Clear Reset,1: HSGPIO_SET"
newline
bitfld.long 0x00 3. "HSGPIO3,HSGPIO[7:0] reset control" "0: Clear Reset,1: HSGPIO_SET"
bitfld.long 0x00 2. "HSGPIO2,HSGPIO[7:0] reset control" "0: Clear Reset,1: HSGPIO_SET"
newline
bitfld.long 0x00 1. "HSGPIO1,HSGPIO[7:0] reset control" "0: Clear Reset,1: HSGPIO_SET"
bitfld.long 0x00 0. "HSGPIO0,HSGPIO[7:0] reset control" "0: Clear Reset,1: HSGPIO_SET"
group.long 0x18++0x03
line.long 0x00 "PRSTCTL2,Peripheral Reset Control Register 2"
bitfld.long 0x00 31. "PIMCTL,INPUTMUX reset control" "0: Clear Reset,1: PIMCTL_SET"
bitfld.long 0x00 30. "GPIOINTCTL,GPIOINTCTL reset control" "0: GPIOINTCTL_CLR,1: GPIOINTCTL_SET"
newline
bitfld.long 0x00 17. "I3C1,I3C1 reset control" "0: Clear Reset,1: Set Reset"
bitfld.long 0x00 16. "I3C0,I3C0 reset control" "0: Clear Reset,1: Set Reset"
newline
bitfld.long 0x00 10. "WWDT1,WWDT1 reset control" "0: Clear Reset,1: WWDT1_SET"
bitfld.long 0x00 8. "MRT0,MRT0 reset control" "0: Clear Reset,1: Set Reset"
newline
bitfld.long 0x00 4. "CT32BIT4,CT32BIT[4:0] reset" "0: CT32BIT_CLR,1: CT32BIT_SET"
bitfld.long 0x00 3. "CT32BIT3,CT32BIT[4:0] reset" "0: CT32BIT_CLR,1: CT32BIT_SET"
newline
bitfld.long 0x00 2. "CT32BIT2,CT32BIT[4:0] reset" "0: CT32BIT_CLR,1: CT32BIT_SET"
bitfld.long 0x00 1. "CT32BIT1,CT32BIT[4:0] reset" "0: CT32BIT_CLR,1: CT32BIT_SET"
newline
bitfld.long 0x00 0. "CT32BIT0,CT32BIT[4:0] reset" "0: CT32BIT_CLR,1: CT32BIT_SET"
wgroup.long 0x40++0x03
line.long 0x00 "PRSTCTL0_SET,Peripheral Reset Control Register 0 SET"
bitfld.long 0x00 29. "FLEXIO,FEXIO reset set" "0: FLEXIO_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 27. "OSEVENT_TIMER,OSEVENT Timer reset set" "0: OSEVENT_TIMER_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 25. "FLEXCOMM16,Flexcomm16 SPI1 reset set" "0: FLEXCOMM16_SPI1_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 24. "DMIC0,DMIC0 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 23. "FLEXCOMM15_I2C,Flexcomm15 I2C reset set" "0: FLEXCOMM15_I2C_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 22. "FLEXCOMM14,Flexcomm14 SPI0 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 21. "FLEXCOMM13,Flexcomm13 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 20. "FLEXCOMM12,Flexcomm12 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 19. "FLEXCOMM11,Flexcomm11 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 18. "FLEXCOMM10,Flexcomm10 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 17. "FLEXCOMM9,Flexcomm9 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 16. "FLEXCOMM8,Flexcomm8 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 15. "FLEXCOMM7,Flexcomm7 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 14. "FLEXCOMM6,Flexcomm6 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 13. "FLEXCOMM5,Flexcomm5 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 12. "FLEXCOMM4,Flexcomm4 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 11. "FLEXCOMM3,Flexcomm3 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 10. "FLEXCOMM2,Flexcomm2 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x00 9. "FLEXCOMM1,Flexcomm1 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x00 8. "FLEXCOMM0,Flexcomm0 reset set" "0: FLEXCOMM_CLR,1: Sets the PRSTCTL0 Bit"
wgroup.long 0x44++0x03
line.long 0x00 "PRSTCTL1_SET,Peripheral Reset Control Register 1 SET"
bitfld.long 0x00 31. "FREQME,FREQME reset set" "0: FREQME_CLR,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 29. "SEMA,SEMA reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x00 28. "MU,MU reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 24. "DMAC1,DMAC1 reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x00 23. "DMAC0,DMAC0 reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 16. "CRC,CRC reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x00 7. "HSGPIO7,HSGPIO7 reset set" "0: HSGPIO_CLR,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 6. "HSGPIO6,HSGPIO6 reset set" "0: HSGPIO_CLR,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x00 5. "HSGPIO5,HSGPIO5 reset set" "0: HSGPIO_CLR,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 4. "HSGPIO4,HSGPIO4 reset set" "0: HSGPIO_CLR,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x00 3. "HSGPIO3,HSGPIO3 reset set" "0: HSGPIO_CLR,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 2. "HSGPIO2,HSGPIO2 reset set" "0: HSGPIO_CLR,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x00 1. "HSGPIO1,HSGPIO1 reset set" "0: HSGPIO_CLR,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x00 0. "HSGPIO0,HSGPIO0 reset set" "0: HSGPIO_CLR,1: Sets the PRSTCTL1 Bit"
wgroup.long 0x48++0x03
line.long 0x00 "PRSTCTL2_SET,Peripheral Reset Control Register 2 SET"
bitfld.long 0x00 31. "PIMCTL,PIMCTL reset set" "0: PIMCTL_CLR,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x00 30. "GPIOINTCTL,GPIOINTCTL reset set" "0: GPIOINTCTL_CLR,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x00 17. "I3C1,I3C1 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x00 16. "I3C0,I3C0 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x00 10. "WWDT1,WWDT1 reset set" "0: WWDT1_CLR,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x00 8. "MRT0,MRT0 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x00 4. "CT32BIT4,CT32BIT4 reset set" "0: CT32BIT_CLR,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x00 3. "CT32BIT3,CT32BIT3 reset set" "0: CT32BIT_CLR,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x00 2. "CT32BIT2,CT32BIT2 reset set" "0: CT32BIT_CLR,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x00 1. "CT32BIT1,CT32BIT1 reset set" "0: CT32BIT_CLR,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x00 0. "CT32BIT0,CT32BIT0 reset set" "0: CT32BIT_CLR,1: Sets the PRSTCTL2 Bit"
wgroup.long 0x70++0x03
line.long 0x00 "PRSTCTL0_CLR,Peripheral Reset Control Register 0 CLR"
bitfld.long 0x00 29. "FLEXIO,FLEXIO reset clear" "0: FLEXIO_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 27. "OSEVENT_TIMER,OSEVENT Timer reset clear" "0: OSEVENT_TIMER_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 25. "FLEXCOMM16,Flexcomm SPI1 reset clear" "0: FLEXCOMM16_SPI1_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 24. "DMIC0,DMIC0 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 23. "FLEXCOMM15_I2C,Flexcomm I2C reset clear" "0: FLEXCOMM15_I2C_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 22. "FLEXCOMM14,FLexcomm SPI0 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 21. "FLEXCOMM13,Flexcomm13 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 20. "FLEXCOMM12,Flexcomm12 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 19. "FLEXCOMM11,Flexcomm11 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 18. "FLEXCOMM10,Flexcomm10 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 17. "FLEXCOMM9,Flexcomm9 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 16. "FLEXCOMM8,Flexcomm8 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 15. "FLEXCOMM7,Flexcomm7 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 14. "FLEXCOMM6,Flexcomm6 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 13. "FLEXCOMM5,Flexcomm5 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 12. "FLEXCOMM4,Flexcomm4 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 11. "FLEXCOMM3,Flexcomm3 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 10. "FLEXCOMM2,Flexcomm2 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x00 9. "FLEXCOMM1,Flexcomm1 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x00 8. "FLEXCOMM0,Flexcomm0 reset clear" "0: FLEXCOMM_CLR,1: Clears the PRSTCTL0 Bit"
wgroup.long 0x74++0x03
line.long 0x00 "PRSTCTL1_CLR,Peripheral Reset Control Register 1 CLR"
bitfld.long 0x00 31. "FREQME,FREQME reset clear" "0: FREQME_CLR,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 29. "SEMA,SMEA reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x00 28. "MU,MU reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 24. "DMAC1,DMAC1 reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x00 23. "DMAC0,DMAC0 reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 16. "CRC,CRC reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x00 7. "HSGPIO7,HSGPIO7 reset clear" "0: HSGPIO_CLR,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 6. "HSGPIO6,HSGPIO6 reset clear" "0: HSGPIO_CLR,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x00 5. "HSGPIO5,HSGPIO5 reset clear" "0: HSGPIO_CLR,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 4. "HSGPIO4,HSGPIO4 reset clear" "0: HSGPIO_CLR,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x00 3. "HSGPIO3,HSGPIO3 reset clear" "0: HSGPIO_CLR,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 2. "HSGPIO2,HSGPIO2 reset clear" "0: HSGPIO_CLR,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x00 1. "HSGPIO1,HSGPIO1 reset clear" "0: HSGPIO_CLR,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x00 0. "HSGPIO0,HSGPIO0 reset clear" "0: HSGPIO_CLR,1: Clears the PRSTCTL1 Bit"
wgroup.long 0x78++0x03
line.long 0x00 "PRSTCTL2_CLR,Peripheral Reset Control Register 2 CLR"
bitfld.long 0x00 31. "PIMCTL,PIMCTL reset clear" "0: PIMCTL_CLR,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x00 30. "GPIOINTCTL,GPIOINTCTL reset clear" "0: GPIOINTCTL_CLR,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x00 17. "I3C1,I3C[1:0] reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x00 16. "I3C0,I3C[1:0] reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x00 10. "WWDT1,WWDT1 reset clear" "0: WWDT1_CLR,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x00 8. "MRT0,MRT0 reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x00 4. "CT32BIT4,CT32BIT4 reset clear" "0: CT32BIT_CLR,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x00 3. "CT32BIT3,CT32BIT3 reset clear" "0: CT32BIT_CLR,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x00 2. "CT32BIT2,CT32BIT2 reset clear" "0: CT32BIT_CLR,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x00 1. "CT32BIT1,CT32BIT1 reset clear" "0: CT32BIT_CLR,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x00 0. "CT32BIT0,CT32BIT0 reset clear" "0: CT32BIT_CLR,1: Clears the PRSTCTL2 Bit"
tree.end
tree.end
tree "RTC (Real-time Counter)"
base ad:0x40030000
group.long 0x00++0x03
line.long 0x00 "CTRL,RTC Control"
bitfld.long 0x00 28.--31. "RTC_OSC_loadcap,Capacitive Load Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "RTC_SUBSEC_ENA,32-KHz Sub-second Counter Enable" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 8. "RTC_OSC_PD,The RTC Oscillator Enable" "0: Enable,1: Shut Off"
bitfld.long 0x00 7. "RTC_EN,RTC enable" "0: Disable,1: Enable"
newline
bitfld.long 0x00 6. "RTC1KHZ_EN,RTC 1 kHz Clock Enable" "0: Disable,1: Enable"
bitfld.long 0x00 5. "WAKEDPD_EN,RTC 1 kHz Timer Wake-up Enable for Deep Power-down" "0: Disable,1: Enable"
newline
bitfld.long 0x00 4. "ALARMDPD_EN,RTC 1 Hz Timer Alarm Enable for Deep Power-down" "0: Disable,1: Enable"
bitfld.long 0x00 3. "WAKE1KHZ,RTC 1 kHz Timer Wake-up Flag Status" "0: Run,1: Time-out"
newline
bitfld.long 0x00 2. "ALARM1HZ,RTC 1 Hz Timer Alarm Flag Status" "0: No match,1: MATCH"
bitfld.long 0x00 0. "SWRESET,Software Reset Control" "0: Not in reset,1: IN_RESET"
group.long 0x04++0x03
line.long 0x00 "MATCH,RTC Match"
hexmask.long 0x00 0.--31. 1. "MATVAL,Match Value"
group.long 0x08++0x03
line.long 0x00 "COUNT,RTC Counter"
hexmask.long 0x00 0.--31. 1. "VAL,Value"
group.long 0x0C++0x03
line.long 0x00 "WAKE,High-resolution/Wake-up Timer Control"
hexmask.long.word 0x00 0.--15. 1. "VAL,Value"
rgroup.long 0x10++0x03
line.long 0x00 "SUBSEC,RTC Sub-second Counter"
hexmask.long.word 0x00 0.--14. 1. "RTC_SUBSEC,RTC Sub-second Counter"
repeat 8. (increment 0 1) (increment 0 0x4)
group.long ($2+0x40)++0x03
line.long 0x00 "GPREG[$1],General Purpose $1"
hexmask.long 0x00 0.--31. 1. "GPDATA,General Purpose Data"
repeat.end
tree.end
tree "SAU"
base ad:0xE000EDD0
group.long 0xD0++0x03
line.long 0x00 "CTRL,Security Attribution Unit Control Register"
bitfld.long 0x00 1. "ALLNS,All Non-secure" "0: Memory is marked as Secure and is not..,1: Memory is marked as Non-secure"
bitfld.long 0x00 0. "ENABLE,Enable" "0: The SAU is disabled,1: The SAU is enabled"
group.long 0xD4++0x03
line.long 0x00 "TYPE,Security Attribution Unit Type Register"
hexmask.long.byte 0x00 0.--7. 1. "SREGION,SAU regions"
group.long 0xD8++0x03
line.long 0x00 "RNR,Security Attribution Unit Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. "REGION,Region number"
group.long 0xDC++0x03
line.long 0x00 "RBAR,Security Attribution Unit Region Base Address Register"
hexmask.long 0x00 5.--31. 1. "BADDR,Base address"
group.long 0xE0++0x03
line.long 0x00 "RLAR,Security Attribution Unit Region Limit Address Register"
hexmask.long 0x00 5.--31. 1. "LADDR,Limit address"
bitfld.long 0x00 1. "NSC,Non-secure callable" "0: Region is not Non-secure callable,1: Region is Non-secure callable"
newline
bitfld.long 0x00 0. "ENABLE,Enable" "0: SAU region is enabled,1: SAU region is disabled"
group.long 0xE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. "LSERR,Lazy state error flag" "0: Error has not occurred,1: Error has occurred"
bitfld.long 0x00 6. "SFARVALID,Secure fault address valid" "0: SFAR content not valid,1: SFAR content valid"
newline
bitfld.long 0x00 5. "LSPERR,Lazy state preservation error flag" "0: Error has not occurred,1: Error has occurred"
bitfld.long 0x00 4. "INVTRAN,Invalid transition flag" "0: Error has not occurred,1: Error has occurred"
newline
bitfld.long 0x00 3. "AUVIOL,Attribution unit violation flag" "0: Error has not occurred,1: Error has occurred"
bitfld.long 0x00 2. "INVER,Invalid exception return flag" "0: Error has not occurred,1: Error has occurred"
newline
bitfld.long 0x00 1. "INVIS,Invalid integrity signature flag" "0: Error has not occurred,1: Error has occurred"
bitfld.long 0x00 0. "INVEP,Invalid entry point" "0: Error has not occurred,1: Error has occurred"
group.long 0xE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,When the SFARVALID bit of the SFSR is set to 1 this field holds the address of an access that caused an SAU violation"
tree.end
tree "SCB"
base ad:0xE000ED00
group.long 0x0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register key: Reads as 0xFA05"
rbitfld.long 0x00 15. "ENDIANNESS,Data endianness bit" "0: Little-endian,1: BIG_ENDIAN"
newline
bitfld.long 0x00 14. "PRIS,Prioritize Secure exceptions" "0: Priority ranges of Secure and Non-secure..,1: Non-secure exceptions are de-prioritized"
bitfld.long 0x00 13. "BFHFNMINS,BusFault HardFault and NMI Non-secure enable" "0: BusFault HardFault and NMI are Secure,1: BusFault and NMI are Non-secure and.."
newline
bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt priority grouping field" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "SYSRESETREQS,System reset request Secure state only" "0: SYSRESETREQ functionality is available to..,1: SYSRESETREQ functionality is only available.."
newline
bitfld.long 0x00 2. "SYSRESETREQ,System reset request" "0: Do not request a system reset,1: Request a system reset"
bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for Debug use" "0,1"
group.long 0x10++0x03
line.long 0x00 "SCR,The SCR controls features of entry to and exit from low-power state"
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending bit" "0: Only enabled interrupts or events can wakeup..,1: Enabled events and all interrupts including.."
bitfld.long 0x00 3. "SLEEPDEEPS,Controls whether the SLEEPDEEP bit is only accessible from the Secure state" "0: The SLEEPDEEP bit is accessible from both..,1: The SLEEPDEEP bit behaves as RAZ/WI when.."
newline
bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low-power mode" "0: Sleep,1: Deep sleep"
bitfld.long 0x00 1. "SLEEPONEXIT,Indicates sleep-on-exit when returning from Handler mode to Thread mode" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR"
group.long 0x24++0x03
line.long 0x00 "SHCSR,System Handler Control and State Register"
bitfld.long 0x00 21. "HARDFAULTPENDED,HardFault exception pended state" "0: HardFault exception modification is disabled,1: HardFault exception modification is enabled"
bitfld.long 0x00 20. "SECUREFAULTPENDED,SecureFault exception pended state bit" "0: SecureFault exception modification is disabled,1: SecureFault exception modification is enabled"
newline
bitfld.long 0x00 19. "SECUREFAULTENA,SecureFault exception enable" "0: SecureFault exception is disabled,1: SecureFault exception is enabled"
bitfld.long 0x00 18. "USGFAULTENA,UsageFault enable" "0: UsageFault is disabled,1: UsageFault is enabled"
newline
bitfld.long 0x00 17. "BUSFAULTENA,BusFault enable" "0: BusFault is disabled,1: BusFault is enabled"
bitfld.long 0x00 16. "MEMFAULTENA,MemManage enable" "0: MemManage exception is disabled,1: MemManage exception is enabled"
newline
bitfld.long 0x00 15. "SVCALLPENDED,SVCall pending" "0: SVCall exception is not pending,1: SVCall exception is pending"
bitfld.long 0x00 14. "BUSFAULTPENDED,BusFault exception pending" "0: BusFault exception is pending,1: BusFault exception is not pending"
newline
bitfld.long 0x00 13. "MEMFAULTPENDED,MemManage exception pending" "0: MemManage exception is not pending,1: MemManage exception is pending"
bitfld.long 0x00 12. "USGFAULTPENDED,UsageFault exception pending" "0: UsageFault exception is not pending,1: UsageFault exception is pending"
newline
bitfld.long 0x00 11. "SYSTICKACT,SysTick exception active" "0: SysTick exception is not active,1: SysTick exception is active"
bitfld.long 0x00 10. "PENDSVACT,PendSV exception active" "0: PendSV exception is not active,1: PendSV exception is active"
newline
bitfld.long 0x00 8. "MONITORACT,Debug monitor active" "0: Debug monitor exception is not active,1: Debug monitor exception is active"
bitfld.long 0x00 7. "SVCALLACT,SVCall active" "0: SVCall exception is not active,1: SVCall exception is active"
newline
bitfld.long 0x00 5. "NMIACT,NMI exception active" "0: NMI exception is not active,1: NMI exception is active"
bitfld.long 0x00 4. "SECUREFAULTACT,SecureFault exception active" "0: SecureFault exception is not active,1: SecureFault exception is active"
newline
bitfld.long 0x00 3. "USGFAULTACT,UsageFault exception active" "0: UsageFault exception is not active,1: UsageFault exception is active"
bitfld.long 0x00 2. "HARDFAULTACT,HardFault exception active" "0: HardFault exception is not active,1: HardFault exception is active"
newline
bitfld.long 0x00 1. "BUSFAULTACT,BusFault exception active" "0: BusFault exception is not active,1: BusFault exception is active"
bitfld.long 0x00 0. "MEMFAULTACT,MemManage exception active" "0: MemManage exception is not active,1: MemManage exception is active"
group.long 0x8C++0x03
line.long 0x00 "NSACR,Non-secure Access Control Register"
bitfld.long 0x00 11. "CP11,CP11 access" "0,1"
bitfld.long 0x00 10. "CP10,CP10 access" "0: Non-secure accesses to the Floating-point..,1: Non-secure access to the Floatingpoint.."
newline
bitfld.long 0x00 7. "CP7,CP7 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
bitfld.long 0x00 6. "CP6,CP6 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
newline
bitfld.long 0x00 5. "CP5,CP5 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
bitfld.long 0x00 4. "CP4,CP4 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
newline
bitfld.long 0x00 3. "CP3,CP3 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
bitfld.long 0x00 2. "CP2,CP2 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
newline
bitfld.long 0x00 1. "CP1,CP1 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
bitfld.long 0x00 0. "CP0,CP0 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
tree.end
tree "SCNSCB"
base ad:0xE000E000
group.long 0x0C++0x03
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 23. "SUS11,State UNKNOWN Secure only 11" "0,1"
bitfld.long 0x00 22. "SU11,State UNKNOWN 11" "0,1"
newline
bitfld.long 0x00 21. "SUS10,State UNKNOWN Secure only 10" "0: The SU10 field is accessible from both..,1: The SU10 field is only accessible from the.."
bitfld.long 0x00 20. "SU10,State UNKNOWN 10" "0: The floating-point state is not permitted to..,1: The floating-point state is permitted to.."
newline
bitfld.long 0x00 15. "SUS7,State UNKNOWN Secure only 7" "0: The SU7 field is accessible from both..,1: The SU7 field is only accessible from the.."
bitfld.long 0x00 14. "SU7,State UNKNOWN 7" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
newline
bitfld.long 0x00 13. "SUS6,State UNKNOWN Secure only 6" "0: The SU6 field is accessible from both..,1: The SU6 field is only accessible from the.."
bitfld.long 0x00 12. "SU6,State UNKNOWN 6" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
newline
bitfld.long 0x00 11. "SUS5,State UNKNOWN Secure only 5" "0: The SU5 field is accessible from both..,1: The SU5 field is only accessible from the.."
bitfld.long 0x00 10. "SU5,State UNKNOWN 5" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
newline
bitfld.long 0x00 9. "SUS4,State UNKNOWN Secure only 4" "0: The SU4 field is accessible from both..,1: The SU4 field is only accessible from the.."
bitfld.long 0x00 8. "SU4,State UNKNOWN 4" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
newline
bitfld.long 0x00 7. "SUS3,State UNKNOWN Secure only 3" "0: The SU3 field is accessible from both..,1: The SU3 field is only accessible from the.."
bitfld.long 0x00 6. "SU3,State UNKNOWN 3" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
newline
bitfld.long 0x00 5. "SUS2,State UNKNOWN Secure only 2" "0: The SU2 field is accessible from both..,1: The SU2 field is only accessible from the.."
bitfld.long 0x00 4. "SU2,State UNKNOWN 2" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
newline
bitfld.long 0x00 3. "SUS1,State UNKNOWN Secure only 1" "0: The SU7 field is accessible from both..,1: The SU7 field is only accessible from the.."
bitfld.long 0x00 2. "SU1,State UNKNOWN 1" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
newline
bitfld.long 0x00 1. "SUS0,State UNKNOWN Secure only 0" "0: The SU0 field is accessible from both..,1: The SU0 field is only accessible from the.."
bitfld.long 0x00 0. "SU0,State UNKNOWN 0" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
tree.end
tree "SCT (SCTimer)"
base ad:0x40146000
sif cpuis("IMXRT595-CM33")
group.long 0x00++0x03
line.long 0x00 "CONFIG,SCTimer Configuration"
bitfld.long 0x00 18. "AUTOLIMIT_H,Auto Limit Higher" "0: Disable,1: Enable"
bitfld.long 0x00 17. "AUTOLIMIT_L,Auto Limit Lower" "0: Disable,1: Enable"
newline
hexmask.long.byte 0x00 9.--16. 1. "INSYNC,Input Synchronization"
bitfld.long 0x00 8. "NORELOAD_H,No Reload Higher Match" "0: Reload,1: No Reload"
newline
bitfld.long 0x00 7. "NORELOAD_L,No Reload Lower Match" "0: Reload,1: No Reload"
bitfld.long 0x00 3.--6. "CKSEL,SCT Clock Select" "0: Rising edges on input 0,1: Falling edges on input 0,2: Rising edges on input 1,3: Falling edges on input 1,4: Rising edges on input 2,5: Falling edges on input 2,6: Rising edges on input 3,7: Falling edges on input 3,8: Rising edges on input 4,9: Falling edges on input 4,10: Rising edges on input 5,11: Falling edges on input 5,12: Rising edges on input 6,13: Falling edges on input 6,14: Rising edges on input 7,15: Falling edges on input 7"
newline
bitfld.long 0x00 1.--2. "CLKMODE,SCT Clock Mode" "0: System Clock Mode,1: Sampled System Clock Mode,2: SCT Input Clock Mode,3: Asynchronous Mode"
bitfld.long 0x00 0. "UNIFY,SCT Operation" "0: Dual counter,1: Unified counter"
group.long 0x04++0x03
line.long 0x00 "CTRL,SCT Control"
hexmask.long.byte 0x00 21.--28. 1. "PRE_H,Prescaler for High Counter"
bitfld.long 0x00 20. "BIDIR_H,Bidirectional Select High" "0: Up,1: Up-down"
newline
bitfld.long 0x00 19. "CLRCTR_H,Clear Counter High" "0,1"
bitfld.long 0x00 18. "HALT_H,Halt Counter High" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 17. "STOP_H,Stop Counter High" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 16. "DOWN_H,Down Counter High" "0: Up,1: Down"
newline
hexmask.long.byte 0x00 5.--12. 1. "PRE_L,Prescaler for Low Counter"
bitfld.long 0x00 4. "BIDIR_L,Bidirectional Select Low" "0: Up,1: Up-down"
newline
bitfld.long 0x00 3. "CLRCTR_L,Clear Counter Low" "0,1"
bitfld.long 0x00 2. "HALT_L,Halt Counter Low" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "STOP_L,Stop Counter Low" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "DOWN_L,Down Counter Low" "0: Up,1: Down"
group.long 0x08++0x03
line.long 0x00 "LIMIT,SCT Limit Event Select"
hexmask.long.word 0x00 16.--31. 1. "LIMMSK_H,Limit Event Counter High"
hexmask.long.word 0x00 0.--15. 1. "LIMMSK_L,Limit Event Counter Low"
group.long 0x0C++0x03
line.long 0x00 "HALT,Halt Event Select"
hexmask.long.word 0x00 16.--31. 1. "HALTMSK_H,Halt Event High"
hexmask.long.word 0x00 0.--15. 1. "HALTMSK_L,Halt Event Low"
group.long 0x10++0x03
line.long 0x00 "STOP,Stop Event Select"
hexmask.long.word 0x00 16.--31. 1. "STOPMSK_H,Stop Event High"
hexmask.long.word 0x00 0.--15. 1. "STOPMSK_L,Stop Event Low"
group.long 0x14++0x03
line.long 0x00 "START,Start Event Select"
abitfld.long 0x00 16.--31. "STARTMSK_H,If bit n is one event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "STARTMSK_L,If bit n is one event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x40++0x03
line.long 0x00 "COUNT,Counter"
hexmask.long.word 0x00 16.--31. 1. "CTR_H,Counter High"
hexmask.long.word 0x00 0.--15. 1. "CTR_L,Counter Low"
group.long 0x44++0x03
line.long 0x00 "STATE,State"
bitfld.long 0x00 16.--20. "STATE_H,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "STATE_L,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x48++0x03
line.long 0x00 "INPUT,Input"
bitfld.long 0x00 31. "SIN15,Input 15 state" "0,1"
bitfld.long 0x00 30. "SIN14,Input 14 state" "0,1"
newline
bitfld.long 0x00 29. "SIN13,Input 13 state" "0,1"
bitfld.long 0x00 28. "SIN12,Input 12 state" "0,1"
newline
bitfld.long 0x00 27. "SIN11,Input 11 state" "0,1"
bitfld.long 0x00 26. "SIN10,Input 10 state" "0,1"
newline
bitfld.long 0x00 25. "SIN9,Input 9 state" "0,1"
bitfld.long 0x00 24. "SIN8,Input 8 state" "0,1"
newline
bitfld.long 0x00 23. "SIN7,Input 7 state" "0,1"
bitfld.long 0x00 22. "SIN6,Input 6 state" "0,1"
newline
bitfld.long 0x00 21. "SIN5,Input 5 state" "0,1"
bitfld.long 0x00 20. "SIN4,Input 4 state" "0,1"
newline
bitfld.long 0x00 19. "SIN3,Input 3 state" "0,1"
bitfld.long 0x00 18. "SIN2,Input 2 state" "0,1"
newline
bitfld.long 0x00 17. "SIN1,Input 1 state" "0,1"
bitfld.long 0x00 16. "SIN0,Input 0 state" "0,1"
newline
bitfld.long 0x00 15. "AIN15,Input 15 state" "0,1"
bitfld.long 0x00 14. "AIN14,Input 14 state" "0,1"
newline
bitfld.long 0x00 13. "AIN13,Input 13 state" "0,1"
bitfld.long 0x00 12. "AIN12,Input 12 state" "0,1"
newline
bitfld.long 0x00 11. "AIN11,Input 11 state" "0,1"
bitfld.long 0x00 10. "AIN10,Input 10 state" "0,1"
newline
bitfld.long 0x00 9. "AIN9,Input 9 state" "0,1"
bitfld.long 0x00 8. "AIN8,Input 8 state" "0,1"
newline
bitfld.long 0x00 7. "AIN7,Input 7 state" "0,1"
bitfld.long 0x00 6. "AIN6,Input 6 state" "0,1"
newline
bitfld.long 0x00 5. "AIN5,Input 5 state" "0,1"
bitfld.long 0x00 4. "AIN4,Input 4 state" "0,1"
newline
bitfld.long 0x00 3. "AIN3,Input 3 state" "0,1"
bitfld.long 0x00 2. "AIN2,Input 2 state" "0,1"
newline
bitfld.long 0x00 1. "AIN1,Input 1 state" "0,1"
bitfld.long 0x00 0. "AIN0,Input 0 state" "0,1"
group.long 0x4C++0x03
line.long 0x00 "REGMODE,Match/Capture Mode"
bitfld.long 0x00 31. "REGMOD_H15,Register Mode High n" "0: Match,1: Capture"
bitfld.long 0x00 30. "REGMOD_H14,Register Mode High n" "0: Match,1: Capture"
newline
bitfld.long 0x00 29. "REGMOD_H13,Register Mode High n" "0: Match,1: Capture"
bitfld.long 0x00 28. "REGMOD_H12,Register Mode High n" "0: Match,1: Capture"
newline
bitfld.long 0x00 27. "REGMOD_H11,Register Mode High n" "0: Match,1: Capture"
bitfld.long 0x00 26. "REGMOD_H10,Register Mode High n" "0: Match,1: Capture"
newline
bitfld.long 0x00 25. "REGMOD_H9,Register Mode High n" "0: Match,1: Capture"
bitfld.long 0x00 24. "REGMOD_H8,Register Mode High n" "0: Match,1: Capture"
newline
bitfld.long 0x00 23. "REGMOD_H7,Register Mode High n" "0: Match,1: Capture"
bitfld.long 0x00 22. "REGMOD_H6,Register Mode High n" "0: Match,1: Capture"
newline
bitfld.long 0x00 21. "REGMOD_H5,Register Mode High n" "0: Match,1: Capture"
bitfld.long 0x00 20. "REGMOD_H4,Register Mode High n" "0: Match,1: Capture"
newline
bitfld.long 0x00 19. "REGMOD_H3,Register Mode High n" "0: Match,1: Capture"
bitfld.long 0x00 18. "REGMOD_H2,Register Mode High n" "0: Match,1: Capture"
newline
bitfld.long 0x00 17. "REGMOD_H1,Register Mode High n" "0: Match,1: Capture"
bitfld.long 0x00 16. "REGMOD_H0,Register Mode High n" "0: Match,1: Capture"
newline
bitfld.long 0x00 15. "REGMOD_L15,Register Mode Low n" "0: Match,1: Capture"
bitfld.long 0x00 14. "REGMOD_L14,Register Mode Low n" "0: Match,1: Capture"
newline
bitfld.long 0x00 13. "REGMOD_L13,Register Mode Low n" "0: Match,1: Capture"
bitfld.long 0x00 12. "REGMOD_L12,Register Mode Low n" "0: Match,1: Capture"
newline
bitfld.long 0x00 11. "REGMOD_L11,Register Mode Low n" "0: Match,1: Capture"
bitfld.long 0x00 10. "REGMOD_L10,Register Mode Low n" "0: Match,1: Capture"
newline
bitfld.long 0x00 9. "REGMOD_L9,Register Mode Low n" "0: Match,1: Capture"
bitfld.long 0x00 8. "REGMOD_L8,Register Mode Low n" "0: Match,1: Capture"
newline
bitfld.long 0x00 7. "REGMOD_L7,Register Mode Low n" "0: Match,1: Capture"
bitfld.long 0x00 6. "REGMOD_L6,Register Mode Low n" "0: Match,1: Capture"
newline
bitfld.long 0x00 5. "REGMOD_L5,Register Mode Low n" "0: Match,1: Capture"
bitfld.long 0x00 4. "REGMOD_L4,Register Mode Low n" "0: Match,1: Capture"
newline
bitfld.long 0x00 3. "REGMOD_L3,Register Mode Low n" "0: Match,1: Capture"
bitfld.long 0x00 2. "REGMOD_L2,Register Mode Low n" "0: Match,1: Capture"
newline
bitfld.long 0x00 1. "REGMOD_L1,Register Mode Low n" "0: Match,1: Capture"
bitfld.long 0x00 0. "REGMOD_L0,Register Mode Low n" "0: Match,1: Capture"
group.long 0x50++0x03
line.long 0x00 "OUTPUT,Output"
bitfld.long 0x00 9. "OUT9,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
bitfld.long 0x00 8. "OUT8,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
newline
bitfld.long 0x00 7. "OUT7,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
bitfld.long 0x00 6. "OUT6,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
newline
bitfld.long 0x00 5. "OUT5,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
bitfld.long 0x00 4. "OUT4,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
newline
bitfld.long 0x00 3. "OUT3,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
bitfld.long 0x00 2. "OUT2,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
newline
bitfld.long 0x00 1. "OUT1,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
bitfld.long 0x00 0. "OUT0,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.."
group.long 0x54++0x03
line.long 0x00 "OUTPUTDIRCTRL,Output Counter Direction Control"
bitfld.long 0x00 18.--19. "SETCLR9,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 16.--17. "SETCLR8,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
newline
bitfld.long 0x00 14.--15. "SETCLR7,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 12.--13. "SETCLR6,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
newline
bitfld.long 0x00 10.--11. "SETCLR5,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 8.--9. "SETCLR4,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
newline
bitfld.long 0x00 6.--7. "SETCLR3,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 4.--5. "SETCLR2,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
newline
bitfld.long 0x00 2.--3. "SETCLR1,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 0.--1. "SETCLR0,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
group.long 0x58++0x03
line.long 0x00 "RES,Output Conflict Resolution"
bitfld.long 0x00 18.--19. "O9RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
bitfld.long 0x00 16.--17. "O8RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
newline
bitfld.long 0x00 14.--15. "O7RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
bitfld.long 0x00 12.--13. "O6RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
newline
bitfld.long 0x00 10.--11. "O5RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
bitfld.long 0x00 8.--9. "O4RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
newline
bitfld.long 0x00 6.--7. "O3RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
bitfld.long 0x00 4.--5. "O2RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
newline
bitfld.long 0x00 2.--3. "O1RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
bitfld.long 0x00 0.--1. "O0RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT"
group.long 0x5C++0x03
line.long 0x00 "DMAREQ0,DMA Request 0"
rbitfld.long 0x00 31. "DRQ0,DMA Request 0 State" "0,1"
bitfld.long 0x00 30. "DRL0,A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers" "0,1"
newline
bitfld.long 0x00 15. "DEV_15,DMA Request Event n" "0,1"
bitfld.long 0x00 14. "DEV_14,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 13. "DEV_13,DMA Request Event n" "0,1"
bitfld.long 0x00 12. "DEV_12,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 11. "DEV_11,DMA Request Event n" "0,1"
bitfld.long 0x00 10. "DEV_10,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 9. "DEV_9,DMA Request Event n" "0,1"
bitfld.long 0x00 8. "DEV_8,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 7. "DEV_7,DMA Request Event n" "0,1"
bitfld.long 0x00 6. "DEV_6,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 5. "DEV_5,DMA Request Event n" "0,1"
bitfld.long 0x00 4. "DEV_4,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 3. "DEV_3,DMA Request Event n" "0,1"
bitfld.long 0x00 2. "DEV_2,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 1. "DEV_1,DMA Request Event n" "0,1"
bitfld.long 0x00 0. "DEV_0,DMA Request Event n" "0,1"
group.long 0x60++0x03
line.long 0x00 "DMAREQ1,DMA Request 1"
rbitfld.long 0x00 31. "DRQ1,DMA Request 1 State" "0,1"
bitfld.long 0x00 30. "DRL1,A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers" "0,1"
newline
bitfld.long 0x00 15. "DEV_15,DMA Request Event n" "0,1"
bitfld.long 0x00 14. "DEV_14,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 13. "DEV_13,DMA Request Event n" "0,1"
bitfld.long 0x00 12. "DEV_12,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 11. "DEV_11,DMA Request Event n" "0,1"
bitfld.long 0x00 10. "DEV_10,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 9. "DEV_9,DMA Request Event n" "0,1"
bitfld.long 0x00 8. "DEV_8,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 7. "DEV_7,DMA Request Event n" "0,1"
bitfld.long 0x00 6. "DEV_6,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 5. "DEV_5,DMA Request Event n" "0,1"
bitfld.long 0x00 4. "DEV_4,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 3. "DEV_3,DMA Request Event n" "0,1"
bitfld.long 0x00 2. "DEV_2,DMA Request Event n" "0,1"
newline
bitfld.long 0x00 1. "DEV_1,DMA Request Event n" "0,1"
bitfld.long 0x00 0. "DEV_0,DMA Request Event n" "0,1"
group.long 0xF0++0x03
line.long 0x00 "EVEN,Event Interrupt Enable"
bitfld.long 0x00 15. "IEN15,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 14. "IEN14,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 13. "IEN13,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 12. "IEN12,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 11. "IEN11,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 10. "IEN10,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 9. "IEN9,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 8. "IEN8,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 7. "IEN7,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 6. "IEN6,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 5. "IEN5,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 4. "IEN4,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 3. "IEN3,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 2. "IEN2,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "IEN1,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "IEN0,Event Interrupt Enable n" "0: DISABLE,1: ENABLE"
group.long 0xF4++0x03
line.long 0x00 "EVFLAG,Event Flag"
bitfld.long 0x00 15. "FLAG15,Event Flag n" "0: NO_FLAG,1: Event n Flag"
bitfld.long 0x00 14. "FLAG14,Event Flag n" "0: NO_FLAG,1: Event n Flag"
newline
bitfld.long 0x00 13. "FLAG13,Event Flag n" "0: NO_FLAG,1: Event n Flag"
bitfld.long 0x00 12. "FLAG12,Event Flag n" "0: NO_FLAG,1: Event n Flag"
newline
bitfld.long 0x00 11. "FLAG11,Event Flag n" "0: NO_FLAG,1: Event n Flag"
bitfld.long 0x00 10. "FLAG10,Event Flag n" "0: NO_FLAG,1: Event n Flag"
newline
bitfld.long 0x00 9. "FLAG9,Event Flag n" "0: NO_FLAG,1: Event n Flag"
bitfld.long 0x00 8. "FLAG8,Event Flag n" "0: NO_FLAG,1: Event n Flag"
newline
bitfld.long 0x00 7. "FLAG7,Event Flag n" "0: NO_FLAG,1: Event n Flag"
bitfld.long 0x00 6. "FLAG6,Event Flag n" "0: NO_FLAG,1: Event n Flag"
newline
bitfld.long 0x00 5. "FLAG5,Event Flag n" "0: NO_FLAG,1: Event n Flag"
bitfld.long 0x00 4. "FLAG4,Event Flag n" "0: NO_FLAG,1: Event n Flag"
newline
bitfld.long 0x00 3. "FLAG3,Event Flag n" "0: NO_FLAG,1: Event n Flag"
bitfld.long 0x00 2. "FLAG2,Event Flag n" "0: NO_FLAG,1: Event n Flag"
newline
bitfld.long 0x00 1. "FLAG1,Event Flag n" "0: NO_FLAG,1: Event n Flag"
bitfld.long 0x00 0. "FLAG0,Event Flag n" "0: NO_FLAG,1: Event n Flag"
group.long 0xF8++0x03
line.long 0x00 "CONEN,Conflict Interrupt Enable"
bitfld.long 0x00 9. "NCEN9,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
bitfld.long 0x00 8. "NCEN8,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
newline
bitfld.long 0x00 7. "NCEN7,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
bitfld.long 0x00 6. "NCEN6,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
newline
bitfld.long 0x00 5. "NCEN5,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
bitfld.long 0x00 4. "NCEN4,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
newline
bitfld.long 0x00 3. "NCEN3,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
bitfld.long 0x00 2. "NCEN2,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
newline
bitfld.long 0x00 1. "NCEN1,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
bitfld.long 0x00 0. "NCEN0,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT"
group.long 0xFC++0x03
line.long 0x00 "CONFLAG,Conflict Flag"
bitfld.long 0x00 31. "BUSERRH,Bus Error High" "0,1"
bitfld.long 0x00 30. "BUSERRL,Bus Error Low/Unified" "0,1"
newline
bitfld.long 0x00 9. "NCFLAG9,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0x00 8. "NCFLAG8,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
newline
bitfld.long 0x00 7. "NCFLAG7,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0x00 6. "NCFLAG6,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
newline
bitfld.long 0x00 5. "NCFLAG5,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0x00 4. "NCFLAG4,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
newline
bitfld.long 0x00 3. "NCFLAG3,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0x00 2. "NCFLAG2,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
newline
bitfld.long 0x00 1. "NCFLAG1,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0x00 0. "NCFLAG0,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
group.long 0x100++0x03
line.long 0x00 "CAP0,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x100++0x03
line.long 0x00 "MATCH0,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x104++0x03
line.long 0x00 "CAP1,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x104++0x03
line.long 0x00 "MATCH1,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x108++0x03
line.long 0x00 "CAP2,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x108++0x03
line.long 0x00 "MATCH2,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x10C++0x03
line.long 0x00 "CAP3,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x10C++0x03
line.long 0x00 "MATCH3,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x110++0x03
line.long 0x00 "CAP4,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x110++0x03
line.long 0x00 "MATCH4,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x114++0x03
line.long 0x00 "CAP5,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x114++0x03
line.long 0x00 "MATCH5,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x118++0x03
line.long 0x00 "CAP6,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x118++0x03
line.long 0x00 "MATCH6,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x11C++0x03
line.long 0x00 "CAP7,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x11C++0x03
line.long 0x00 "MATCH7,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x120++0x03
line.long 0x00 "CAP8,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x120++0x03
line.long 0x00 "MATCH8,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x124++0x03
line.long 0x00 "CAP9,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x124++0x03
line.long 0x00 "MATCH9,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x128++0x03
line.long 0x00 "CAP10,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x128++0x03
line.long 0x00 "MATCH10,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x12C++0x03
line.long 0x00 "CAP11,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x12C++0x03
line.long 0x00 "MATCH11,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x130++0x03
line.long 0x00 "CAP12,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x130++0x03
line.long 0x00 "MATCH12,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x134++0x03
line.long 0x00 "CAP13,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x134++0x03
line.long 0x00 "MATCH13,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x138++0x03
line.long 0x00 "CAP14,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x138++0x03
line.long 0x00 "MATCH14,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x13C++0x03
line.long 0x00 "CAP15,Capture Value"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low"
group.long 0x13C++0x03
line.long 0x00 "MATCH15,Match Value"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low"
group.long 0x200++0x03
line.long 0x00 "CAPCTRL0,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x200++0x03
line.long 0x00 "MATCHREL0,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x204++0x03
line.long 0x00 "CAPCTRL1,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x204++0x03
line.long 0x00 "MATCHREL1,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x208++0x03
line.long 0x00 "CAPCTRL2,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x208++0x03
line.long 0x00 "MATCHREL2,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x20C++0x03
line.long 0x00 "CAPCTRL3,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x20C++0x03
line.long 0x00 "MATCHREL3,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x210++0x03
line.long 0x00 "CAPCTRL4,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x210++0x03
line.long 0x00 "MATCHREL4,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x214++0x03
line.long 0x00 "CAPCTRL5,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x214++0x03
line.long 0x00 "MATCHREL5,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x218++0x03
line.long 0x00 "CAPCTRL6,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x218++0x03
line.long 0x00 "MATCHREL6,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x21C++0x03
line.long 0x00 "CAPCTRL7,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x21C++0x03
line.long 0x00 "MATCHREL7,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x220++0x03
line.long 0x00 "CAPCTRL8,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x220++0x03
line.long 0x00 "MATCHREL8,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x224++0x03
line.long 0x00 "CAPCTRL9,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x224++0x03
line.long 0x00 "MATCHREL9,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x228++0x03
line.long 0x00 "CAPCTRL10,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x228++0x03
line.long 0x00 "MATCHREL10,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x22C++0x03
line.long 0x00 "CAPCTRL11,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x22C++0x03
line.long 0x00 "MATCHREL11,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x230++0x03
line.long 0x00 "CAPCTRL12,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x230++0x03
line.long 0x00 "MATCHREL12,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x234++0x03
line.long 0x00 "CAPCTRL13,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x234++0x03
line.long 0x00 "MATCHREL13,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x238++0x03
line.long 0x00 "CAPCTRL14,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x238++0x03
line.long 0x00 "MATCHREL14,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
group.long 0x23C++0x03
line.long 0x00 "CAPCTRL15,Capture Control"
hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High"
hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low"
group.long 0x23C++0x03
line.long 0x00 "MATCHREL15,Match Reload Value"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low"
endif
repeat 16. (increment 0 1)(increment 0 0x08)
tree "EV[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0x300)++0x03
line.long 0x00 "EV_STATE,Event n State"
hexmask.long 0x00 0.--31. 1. "STATEMSKn,Event State Mask n"
group.long ($2+0x304)++0x03
line.long 0x00 "EV_CTRL,Event n Control"
bitfld.long 0x00 21.--22. "DIRECTION,Direction" "0: Direction independent,1: Counting up,2: Counting down,?..."
bitfld.long 0x00 20. "MATCHMEM,Match Mem" "0,1"
newline
bitfld.long 0x00 15.--19. "STATEV,State Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "STATELD,State Load" "0: Add,1: Load"
newline
bitfld.long 0x00 12.--13. "COMBMODE,Combination Mode" "0: OR,1: MATCH,2: IO,3: AND"
bitfld.long 0x00 10.--11. "IOCOND,Input/Output Condition" "0: LOW,1: RISE,2: FALL,3: HIGH"
newline
bitfld.long 0x00 6.--9. "IOSEL,Input/Output Signal Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. "OUTSEL,Input/Output Select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
newline
bitfld.long 0x00 4. "HEVENT,High Event" "0: Low Counter,1: High Counter"
bitfld.long 0x00 0.--3. "MATCHSEL,Match Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
tree.end
repeat.end
repeat 10. (increment 0 1)(increment 0 0x208)
tree "OUT[$1]"
sif cpuis("IMXRT595-CM33")
group.long ($2+0x500)++0x03
line.long 0x00 "OUT_SET,Output n Set"
hexmask.long.word 0x00 0.--15. 1. "SET,Set"
group.long ($2+0x504)++0x03
line.long 0x00 "OUT_CLR,Output n Clear"
hexmask.long.word 0x00 0.--15. 1. "CLR,Clear"
endif
tree.end
repeat.end
tree.end
tree "SEMA42"
base ad:0x40112000
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "GATE$1,Gate Register"
bitfld.byte 0x00 0.--3. "GTFSM,Gate finite state machine" "0: The gate is unlocked (free),1: Domain 0 locked the gate,2: Domain 1 locked the gate,3: Domain 2 locked the gate,4: Domain 3 locked the gate,5: Domain 4 locked the gate,6: Domain 5 locked the gate,7: Domain 6 locked the gate,8: Domain 7 locked the gate,9: Domain 8 locked the gate,10: Domain 9 locked the gate,11: Domain 10 locked the gate,12: Domain 11 locked the gate,13: Domain 12 locked the gate,14: Domain 13 locked the gate,15: Domain 14 locked the gate"
repeat.end
rgroup.word 0x42++0x01
line.word 0x00 "RSTGT_R,Reset Gate"
bitfld.word 0x00 14.--15. "ROZ,ROZ" "0,1,2,3"
bitfld.word 0x00 12.--13. "RSTGSM,Reset gate finite state machine" "0: Idle waiting for the first data pattern,1: Waiting for the second data pattern,2: The 2-write sequence has completed,?..."
newline
bitfld.word 0x00 8.--11. "RSTGMS,Reset gate domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset gate number"
wgroup.word 0x42++0x01
line.word 0x00 "RSTGT_W,Reset Gate"
hexmask.word.byte 0x00 8.--15. 1. "RSTGDP,Reset gate data pattern"
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset gate number"
tree.end
tree "SPI (Serial Peripheral Interfaces (SPI))"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 16.) (list ad:0x40106000 ad:0x40107000 ad:0x40108000 ad:0x40109000 ad:0x40122000 ad:0x40123000 ad:0x40124000 ad:0x40125000 ad:0x40209000 ad:0x4020A000 ad:0x4020B000 ad:0x4020C000 ad:0x4020D000 ad:0x4020E000 ad:0x40126000 ad:0x40128000)
tree "SPI$1"
base $2
group.long 0x400++0x03
line.long 0x00 "CFG,Configuration Register"
bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity Select" "0: Low,1: High"
bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity Select" "0: Low,1: High"
newline
bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity Select" "0: Low,1: High"
bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity Select" "0: Low,1: High"
newline
bitfld.long 0x00 7. "LOOP,Loopback Mode Enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 5. "CPOL,Clock Polarity Select" "0: Low,1: High"
newline
bitfld.long 0x00 4. "CPHA,Clock Phase Select" "0: CHANGE,1: CAPTURE"
bitfld.long 0x00 3. "LSBF,LSB First Mode Enable" "0: Standard,1: Reverse"
newline
bitfld.long 0x00 2. "MASTER,Master Mode Select" "0: Slave mode,1: Master mode"
bitfld.long 0x00 0. "ENABLE,SPI Enable" "0: Disabled,1: Enabled"
group.long 0x404++0x03
line.long 0x00 "DLY,Delay Register"
bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Transfer Delay" "0: The minimum time that SSEL is deasserted is 1..,1: The minimum time that SSEL is deasserted is 2..,2: The minimum time that SSEL is deasserted is 3..,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is.."
bitfld.long 0x00 8.--11. "FRAME_DELAY,Frame Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
newline
bitfld.long 0x00 4.--7. "POST_DELAY,Post-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
bitfld.long 0x00 0.--3. "PRE_DELAY,Pre-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
group.long 0x408++0x03
line.long 0x00 "STAT,Status Register"
rbitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag" "0,1"
bitfld.long 0x00 7. "ENDTRANSFER,End Transfer Control" "0,1"
newline
rbitfld.long 0x00 6. "STALLED,Stalled Status Flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,Interrupt Enable Register"
bitfld.long 0x00 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled,1: Enabled"
wgroup.long 0x410++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x00 8. "MSTIDLE,Master Idle Interrupt Enable" "0: NO_EFFECT,1: Clear the Master Idle Interrupt Enable bit.."
bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Deassert Interrupt.."
newline
bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Assert Interrupt.."
group.long 0x424++0x03
line.long 0x00 "DIV,Clock Divider Register"
hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate Divider Value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,Interrupt Status Register"
bitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: MSTIDLE_INTERRUPT_DISABLED,1: MSTIDLE_INTERRUPT_ENABLED"
bitfld.long 0x00 5. "SSD,Slave Select Deassert Interrupt" "0: SSD_INTERRUPT_DISABLED,1: SSD_INTERRUPT_ENABLED"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert Interrupt" "0: SSA_INTERRUPT_DISABLED,1: SSA_INTERRUPT_ENABLED"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO Configuration Register"
bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop"
bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied"
newline
bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied"
bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Issues a DMA request for the receive function.."
newline
bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function.."
rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: FIFO is configured as 8 entries of 16 bits,2: SIZEINVALID2,3: SIZEINVALID3"
newline
bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO Status Register"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data.."
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.."
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.."
bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.."
newline
bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO Trigger Register"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.."
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Register"
bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt.."
bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt.."
newline
bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register"
bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive FIFO Level Interrupt Enable.."
bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Transmit FIFO Level Interrupt.."
newline
bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive Error Interrupt Enable bit.."
bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: NO_EFFECT,1: Clear the TX Error Interrupt Enable bit.."
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status Register"
bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING"
bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING"
bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO Write Data Register"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
bitfld.long 0x00 21. "EOF,End of Frame" "0: Data not EOF,1: Data EOF"
newline
bitfld.long 0x00 20. "EOT,End of Transfer" "0: SSEL is not deasserted,1: SSEL is deasserted"
bitfld.long 0x00 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted"
newline
bitfld.long 0x00 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted"
bitfld.long 0x00 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted"
newline
bitfld.long 0x00 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted"
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO Read Data Register"
bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went.."
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register"
bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: SOT_NOT_ACTIVE,1: SOT_ACTIVE"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: NOT_SELECTED,1: RXSSEL3_N_SELECTED"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: NOT_SELECTED,1: RXSSEL2_N_SELECTED"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: NOT_SELECTED,1: RXSSEL1_N_SELECTED"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: NOT_SELECTED,1: RXSSEL0_N_SELECTED"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO Size Register"
bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral Identification Register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture"
tree.end
repeat.end
tree.end
tree "SYSCTL (SYSCTL0)"
tree "SYSCTL0"
base ad:0x40002000
group.long 0x04++0x03
line.long 0x00 "DSP_VECT_REMAP,DSP Vector Remap"
bitfld.long 0x00 12. "STATVECSELECT,Static Vector Select" "0: Selects the primary static vector base..,1: Selects the alternate static vector base.."
newline
hexmask.long.word 0x00 0.--11. 1. "DSP_VECT_REMAP,DSP_VECT_REMAP"
group.long 0x0C++0x03
line.long 0x00 "DSPSTALL,DSP Stall Control"
bitfld.long 0x00 0. "DSPSTALL,DSPSTALL" "0: Run(Normal mode),1: DSPSTALL_1"
group.long 0x10++0x03
line.long 0x00 "AHBMATRIXPRIOR,AHB MAX Priority"
bitfld.long 0x00 22.--23. "M11,Master 10 Priority" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "M10,Master 10 Priority" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "M9,Master 9 Priority" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "M8,Master 8 Priority" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "M7,Master 7 Priority" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "M6,Master 6 Priority" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "M5,Master 5 Priority" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "M4,Master 4 Priority" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "M3,Master 3 Priority" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "M2,Master 2 Priority" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "M1,Master 1 Priority" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "M0,Master 0 Priority" "0,1,2,3"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x20)++0x03
line.long 0x00 "AHBBRIDGEBUFFER[$1],AHB Buffer $1"
bitfld.long 0x00 31. "SLAVE31,SLAVE31 buffering" "0: No Buffering,1: SLAVE31_1"
newline
bitfld.long 0x00 30. "SLAVE30,SLAVE30 buffering" "0: No Buffering,1: SLAVE30_1"
newline
bitfld.long 0x00 29. "SLAVE29,SLAVE29 buffering" "0: No Buffering,1: SLAVE29_1"
newline
bitfld.long 0x00 28. "SLAVE28,SLAVE28 buffering" "0: No Buffering,1: SLAVE28_1"
newline
bitfld.long 0x00 27. "SLAVE27,SLAVE27 buffering" "0: No Buffering,1: SLAVE27_1"
newline
bitfld.long 0x00 26. "SLAVE26,SLAVE26 buffering" "0: No Buffering,1: SLAVE26_1"
newline
bitfld.long 0x00 25. "SLAVE25,SLAVE25 buffering" "0: No Buffering,1: SLAVE25_1"
newline
bitfld.long 0x00 24. "SLAVE24,SLAVE24 buffering" "0: No Buffering,1: SLAVE24_1"
newline
bitfld.long 0x00 23. "SLAVE23,SLAVE23 buffering" "0: No Buffering,1: SLAVE23_1"
newline
bitfld.long 0x00 22. "SLAVE22,SLAVE22 buffering" "0: No Buffering,1: SLAVE22_1"
newline
bitfld.long 0x00 21. "SLAVE21,SLAVE21 buffering" "0: No Buffering,1: SLAVE21_1"
newline
bitfld.long 0x00 20. "SLAVE20,SLAVE20 buffering" "0: No Buffering,1: SLAVE20_1"
newline
bitfld.long 0x00 19. "SLAVE19,SLAVE19 buffering" "0: No Buffering,1: SLAVE19_1"
newline
bitfld.long 0x00 18. "SLAVE18,SLAVE18 buffering" "0: No Buffering,1: SLAVE18_1"
newline
bitfld.long 0x00 17. "SLAVE17,SLAVE17 buffering" "0: No Buffering,1: SLAVE17_1"
newline
bitfld.long 0x00 16. "SLAVE16,SLAVE16 buffering" "0: No Buffering,1: SLAVE16_1"
newline
bitfld.long 0x00 15. "SLAVE15,SLAVE15 buffering" "0: No Buffering,1: SLAVE15_1"
newline
bitfld.long 0x00 14. "SLAVE14,SLAVE14 buffering" "0: No Buffering,1: SLAVE14_1"
newline
bitfld.long 0x00 13. "SLAVE13,SLAVE13 buffering" "0: No Buffering,1: SLAVE13_1"
newline
bitfld.long 0x00 12. "SLAVE12,SLAVE12 buffering" "0: No Buffering,1: SLAVE12_1"
newline
bitfld.long 0x00 11. "SLAVE11,SLAVE11 buffering" "0: No Buffering,1: SLAVE11_1"
newline
bitfld.long 0x00 10. "SLAVE10,SLAVE10 buffering" "0: No Buffering,1: SLAVE10_1"
newline
bitfld.long 0x00 9. "SLAVE9,SLAVE9 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 8. "SLAVE8,SLAVE8 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 7. "SLAVE7,SLAVE7 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 6. "SLAVE6,SLAVE6 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 5. "SLAVE5,SLAVE5 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 4. "SLAVE4,SLAVE4 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 3. "SLAVE3,SLAVE3 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 2. "SLAVE2,SLAVE2 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 1. "SLAVE1,SLAVE1 buffering" "0: No Buffering,1: Buffering"
newline
bitfld.long 0x00 0. "SLAVE0,SLAVE0 buffering" "0: No Buffering,1: Buffering"
repeat.end
group.long 0x2C++0x03
line.long 0x00 "BOOTROM_LCKOUT,BOOT ROM lockout"
eventfld.long 0x00 30.--31. "WRITE_LOCK,Self Write Disable" "0: Write_Lock_00,1: Write_Lock_01,2: Write_Lock_11,3: Write_Lock_10"
newline
hexmask.long.tbyte 0x00 0.--16. 1. "READ_LCKOUT_SPACE,Read Lockout"
group.long 0x30++0x03
line.long 0x00 "M33NMISRCSEL,M33 NMI source selection"
eventfld.long 0x00 31. "NMI_Enable,Self Write Disable" "0: Disable NMI interrupt,1: Enable NMI interrupt"
newline
hexmask.long.byte 0x00 0.--6. 1. "NMISRCSEL,Selects one of the M33 interrupt sources as the NMI source interrupt"
group.long 0x34++0x03
line.long 0x00 "SYSTEM_STICK_CALIB,System secure tick calibration"
hexmask.long 0x00 0.--26. 1. "SYSTEM_STICK_CALIB,M33 secure tick calibration"
group.long 0x38++0x03
line.long 0x00 "SYSTEM_NSTICK_CALIB,System non-secure tick calibration"
hexmask.long 0x00 0.--26. 1. "SYSTEM_NSTICK_CALIB,M33 non secure tick calibration"
group.long 0x60++0x03
line.long 0x00 "PRODUCT_ID,Product ID"
hexmask.long.word 0x00 0.--15. 1. "PRODUCT_ID,PRODUCT ID"
rgroup.long 0x64++0x03
line.long 0x00 "SILICONREV_ID,Silicon Revision ID"
bitfld.long 0x00 16.--19. "MAJOR,MAJOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "MINOR,MINOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x68++0x03
line.long 0x00 "JTAG_ID,JTAG ID"
bitfld.long 0x00 28.--31. "CHIPREV,JTAG ID 4-Bit Chip Silicon Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 12.--27. 1. "PRODUCT_ID,JTAG ID Product ID as defined in the Product ID register"
newline
hexmask.long.word 0x00 1.--11. 1. "MANU,JTAG ID Manufacturer"
newline
bitfld.long 0x00 0. "FIXBIT,JTAG ID fix bit" "0,1"
group.long 0x70++0x03
line.long 0x00 "NSGPIO_PSYNC,Non-secure GPIO PSYNC"
bitfld.long 0x00 0. "PSYNC,Synchronization Stage Setting" "0,1"
group.long 0x74++0x03
line.long 0x00 "SGPIO_PSYNC,Secure GPIO PSYNC"
bitfld.long 0x00 0. "PSYNC,Synchronization Stage Setting" "0: 2-Stage Sync,1: 1-Stage Sync"
group.long 0x80++0x03
line.long 0x00 "AUTOCLKGATEOVERRIDE0,Auto clock gate override 0"
bitfld.long 0x00 5. "DMAC1,DMAC1" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 4. "DMAC0,DMAC0" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 3. "CASPER,CASPER" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 2. "CRC_ENGINE,CRC_ENGINE" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 1. "AHB2APB1,AHB2APB1" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 0. "AHB2APB0,AHB2APB0" "0: Enable clock gating,1: Continuous Clocking"
group.long 0x84++0x03
line.long 0x00 "AUTOCLKGATEOVERRIDE1,Auto clock gate override 1"
bitfld.long 0x00 29. "SRAM29_IF,SRAM29_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 28. "SRAM28_IF,SRAM28_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 27. "SRAM27_IF,SRAM27_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 26. "SRAM26_IF,SRAM26_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 25. "SRAM25_IF,SRAM25_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 24. "SRAM24_IF,SRAM24_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 23. "SRAM23_IF,SRAM23_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 22. "SRAM22_IF,SRAM22_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 21. "SRAM21_IF,SRAM21_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 20. "SRAM20_IF,SRAM20_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 19. "SRAM19_IF,SRAM19_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 18. "SRAM18_IF,SRAM18_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 17. "SRAM17_IF,SRAM17_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 16. "SRAM16_IF,SRAM16_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 15. "SRAM15_IF,SRAM15_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 14. "SRAM14_IF,SRAM14_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 13. "SRAM13_IF,SRAM13_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 12. "SRAM12_IF,SRAM12_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 11. "SRAM11_IF,SRAM11_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 10. "SRAM10_IF,SRAM10_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 9. "SRAM9_IF,SRAM9_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 8. "SRAM8_IF,SRAM8_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 7. "SRAM7_IF,SRAM7_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 6. "SRAM6_IF,SRAM6_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 5. "SRAM5_IF,SRAM5_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 4. "SRAM4_IF,SRAM4_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 3. "SRAM3_IF,SRAM3_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 2. "SRAM2_IF,SRAM2_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 1. "SRAM1_IF,SRAM1_IF" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 0. "SRAM0_IF,SRAM0_IF" "0: Enable clock gating,1: Continuous Clocking"
group.long 0xA0++0x03
line.long 0x00 "CLKGATEOVERRIDE0,Clock gate override 0"
bitfld.long 0x00 6. "PMC,PMC" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 5. "ACMP,ACMP" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 4. "MU,MU" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 3. "ADC,ADC" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 2. "USBPHY,USBPHY" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 1. "SDIO1,SDIO1" "0: Enable clock gating,1: Continuous Clocking"
newline
bitfld.long 0x00 0. "SDIO0,SDIO0" "0: Enable clock gating,1: Continuous Clocking"
group.long 0xFC++0x03
line.long 0x00 "AHB_SRAM_ACCESS_DISABLE,AHB SRAM access disable"
bitfld.long 0x00 31. "SRAM031_IF,Control AHB access to SRAM partition 31" "0: SRAM031_IF_0,1: SRAM031_IF_1"
newline
bitfld.long 0x00 30. "SRAM030_IF,Control AHB access to SRAM partition 30" "0: SRAM030_IF_0,1: SRAM030_IF_1"
newline
bitfld.long 0x00 29. "SRAM029_IF,Control AHB access to SRAM partition 29" "0: SRAM029_IF_0,1: SRAM029_IF_1"
newline
bitfld.long 0x00 28. "SRAM028_IF,Control AHB access to SRAM partition 28" "0: SRAM028_IF_0,1: SRAM028_IF_1"
newline
bitfld.long 0x00 27. "SRAM027_IF,Control AHB access to SRAM partition 27" "0: SRAM027_IF_0,1: SRAM027_IF_1"
newline
bitfld.long 0x00 26. "SRAM026_IF,Control AHB access to SRAM partition 26" "0: SRAM026_IF_0,1: SRAM026_IF_1"
newline
bitfld.long 0x00 25. "SRAM025_IF,Control AHB access to SRAM partition 25" "0: SRAM025_IF_0,1: SRAM025_IF_1"
newline
bitfld.long 0x00 24. "SRAM024_IF,Control AHB access to SRAM partition 24" "0: SRAM024_IF_0,1: SRAM024_IF_1"
newline
bitfld.long 0x00 23. "SRAM023_IF,Control AHB access to SRAM partition 23" "0: SRAM023_IF_0,1: SRAM023_IF_1"
newline
bitfld.long 0x00 22. "SRAM022_IF,Control AHB access to SRAM partition 22" "0: SRAM022_IF_0,1: SRAM022_IF_1"
newline
bitfld.long 0x00 21. "SRAM021_IF,Control AHB access to SRAM partition 21" "0: SRAM021_IF_0,1: SRAM021_IF_1"
newline
bitfld.long 0x00 20. "SRAM020_IF,Control AHB access to SRAM partition 20" "0: SRAM020_IF_0,1: SRAM020_IF_1"
newline
bitfld.long 0x00 19. "SRAM019_IF,Control AHB access to SRAM partition 19" "0: SRAM019_IF_0,1: SRAM019_IF_1"
newline
bitfld.long 0x00 18. "SRAM018_IF,Control AHB access to SRAM partition 18" "0: SRAM018_IF_0,1: SRAM018_IF_1"
newline
bitfld.long 0x00 17. "SRAM017_IF,Control AHB access to SRAM partition 17" "0: SRAM017_IF_0,1: SRAM017_IF_1"
newline
bitfld.long 0x00 16. "SRAM016_IF,Control AHB access to SRAM partition 16" "0: SRAM016_IF_0,1: SRAM016_IF_1"
newline
bitfld.long 0x00 15. "SRAM015_IF,Control AHB access to SRAM partition 15" "0: SRAM015_IF_0,1: SRAM015_IF_1"
newline
bitfld.long 0x00 14. "SRAM014_IF,Control AHB access to SRAM partition 14" "0: SRAM014_IF_0,1: SRAM014_IF_1"
newline
bitfld.long 0x00 13. "SRAM013_IF,Control AHB access to SRAM partition 13" "0: SRAM013_IF_0,1: SRAM013_IF_1"
newline
bitfld.long 0x00 12. "SRAM012_IF,Control AHB access to SRAM partition 12" "0: SRAM012_IF_0,1: SRAM012_IF_1"
newline
bitfld.long 0x00 11. "SRAM011_IF,Control AHB access to SRAM partition 11" "0: SRAM011_IF_0,1: SRAM011_IF_1"
newline
bitfld.long 0x00 10. "SRAM010_IF,Control AHB access to SRAM partition 10" "0: SRAM010_IF_0,1: SRAM010_IF_1"
newline
bitfld.long 0x00 9. "SRAM09_IF,Control AHB access to SRAM partition 9" "0: SRAM09_IF_0,1: SRAM09_IF_1"
newline
bitfld.long 0x00 8. "SRAM08_IF,Control AHB access to SRAM partition 8" "0: SRAM08_IF_0,1: SRAM08_IF_1"
newline
bitfld.long 0x00 7. "SRAM07_IF,Control AHB access to SRAM partition 7" "0: SRAM07_IF_0,1: SRAM07_IF_1"
newline
bitfld.long 0x00 6. "SRAM06_IF,Control AHB access to SRAM partition 6" "0: SRAM06_IF_0,1: SRAM06_IF_1"
newline
bitfld.long 0x00 5. "SRAM05_IF,Control AHB access to SRAM partition 5" "0: SRAM05_IF_0,1: SRAM05_IF_1"
newline
bitfld.long 0x00 4. "SRAM04_IF,Control AHB access to SRAM partition 4" "0: SRAM04_IF_0,1: SRAM04_IF_1"
newline
bitfld.long 0x00 3. "SRAM03_IF,Control AHB access to SRAM partition 3" "0: SRAM03_IF_0,1: SRAM03_IF_1"
newline
bitfld.long 0x00 2. "SRAM02_IF,Control AHB access to SRAM partition 2" "0: SRAM02_IF_0,1: SRAM02_IF_1"
newline
bitfld.long 0x00 1. "SRAM01_IF,Control AHB access to SRAM partition 1" "0: SRAM01_IF_0,1: SRAM01_IF_1"
newline
bitfld.long 0x00 0. "SRAM00_IF,Control AHB access to SRAM partition 0" "0: SRAM00_IF_0,1: SRAM00_IF_1"
group.long 0x100++0x03
line.long 0x00 "AXI_SRAM_ACCESS_DISABLE,AXI SRAM access disable"
bitfld.long 0x00 31. "SRAM031_IF,Control AXB access to SRAM partition" "0: SRAM031_IF_0,1: SRAM031_IF_1"
newline
bitfld.long 0x00 30. "SRAM030_IF,Control AXB access to SRAM partition" "0: SRAM030_IF_0,1: SRAM030_IF_1"
newline
bitfld.long 0x00 29. "SRAM029_IF,Control AXB access to SRAM partition" "0: SRAM029_IF_0,1: SRAM029_IF_1"
newline
bitfld.long 0x00 28. "SRAM028_IF,Control AXB access to SRAM partition" "0: SRAM028_IF_0,1: SRAM028_IF_1"
newline
bitfld.long 0x00 27. "SRAM027_IF,Control AXB access to SRAM partition" "0: SRAM027_IF_0,1: SRAM027_IF_1"
newline
bitfld.long 0x00 26. "SRAM026_IF,Control AXB access to SRAM partition" "0: SRAM026_IF_0,1: SRAM026_IF_1"
newline
bitfld.long 0x00 25. "SRAM025_IF,Control AXB access to SRAM partition" "0: SRAM025_IF_0,1: SRAM025_IF_1"
newline
bitfld.long 0x00 24. "SRAM024_IF,Control AXB access to SRAM partition" "0: SRAM024_IF_0,1: SRAM024_IF_1"
newline
bitfld.long 0x00 23. "SRAM023_IF,Control AXB access to SRAM partition" "0: SRAM023_IF_0,1: SRAM023_IF_1"
newline
bitfld.long 0x00 22. "SRAM022_IF,Control AXB access to SRAM partition" "0: SRAM022_IF_0,1: SRAM022_IF_1"
newline
bitfld.long 0x00 21. "SRAM021_IF,Control AXB access to SRAM partition" "0: SRAM021_IF_0,1: SRAM021_IF_1"
newline
bitfld.long 0x00 20. "SRAM020_IF,Control AXB access to SRAM partition" "0: SRAM020_IF_0,1: SRAM020_IF_1"
newline
bitfld.long 0x00 19. "SRAM019_IF,Control AXB access to SRAM partition" "0: SRAM019_IF_0,1: SRAM019_IF_1"
newline
bitfld.long 0x00 18. "SRAM018_IF,Control AXB access to SRAM partition" "0: SRAM018_IF_0,1: SRAM018_IF_1"
newline
bitfld.long 0x00 17. "SRAM017_IF,Control AXB access to SRAM partition" "0: SRAM017_IF_0,1: SRAM017_IF_1"
newline
bitfld.long 0x00 16. "SRAM016_IF,Control AXB access to SRAM partition" "0: SRAM016_IF_0,1: SRAM016_IF_1"
newline
bitfld.long 0x00 15. "SRAM015_IF,Control AXB access to SRAM partition" "0: SRAM015_IF_0,1: SRAM015_IF_1"
newline
bitfld.long 0x00 14. "SRAM014_IF,Control AXB access to SRAM partition" "0: SRAM014_IF_0,1: SRAM014_IF_1"
newline
bitfld.long 0x00 13. "SRAM013_IF,Control AXB access to SRAM partition" "0: SRAM013_IF_0,1: SRAM013_IF_1"
newline
bitfld.long 0x00 12. "SRAM012_IF,Control AXB access to SRAM partition" "0: SRAM012_IF_0,1: SRAM012_IF_1"
newline
bitfld.long 0x00 11. "SRAM011_IF,Control AXB access to SRAM partition" "0: SRAM011_IF_0,1: SRAM011_IF_1"
newline
bitfld.long 0x00 10. "SRAM010_IF,Control AXB access to SRAM partition" "0: SRAM010_IF_0,1: SRAM010_IF_1"
newline
bitfld.long 0x00 9. "SRAM09_IF,Control AXB access to SRAM partition" "0: SRAM09_IF_0,1: SRAM09_IF_1"
newline
bitfld.long 0x00 8. "SRAM08_IF,Control AXB access to SRAM partition" "0: SRAM08_IF_0,1: SRAM08_IF_1"
newline
bitfld.long 0x00 7. "SRAM07_IF,Control AXB access to SRAM partition" "0: SRAM07_IF_0,1: SRAM07_IF_1"
newline
bitfld.long 0x00 6. "SRAM06_IF,Control AXB access to SRAM partition" "0: SRAM06_IF_0,1: SRAM06_IF_1"
newline
bitfld.long 0x00 5. "SRAM05_IF,Control AXB access to SRAM partition" "0: SRAM05_IF_0,1: SRAM05_IF_1"
newline
bitfld.long 0x00 4. "SRAM04_IF,Control AXB access to SRAM partition" "0: SRAM04_IF_0,1: SRAM04_IF_1"
newline
bitfld.long 0x00 3. "SRAM03_IF,Control AXB access to SRAM partition" "0: SRAM03_IF_0,1: SRAM03_IF_1"
newline
bitfld.long 0x00 2. "SRAM02_IF,Control AXB access to SRAM partition" "0: SRAM02_IF_0,1: SRAM02_IF_1"
newline
bitfld.long 0x00 1. "SRAM01_IF,Control AXB access to SRAM partition" "0: SRAM01_IF_0,1: SRAM01_IF_1"
newline
bitfld.long 0x00 0. "SRAM00_IF,Control AXB access to SRAM partition" "0: SRAM00_IF_0,1: SRAM00_IF_1"
group.long 0x104++0x03
line.long 0x00 "DSP_SRAM_ACCESS_DISABLE,DSP SRAM access disable"
bitfld.long 0x00 31. "SRAM31_IF,SRAM31_IF" "0: SRAM031_IF_0,1: SRAM031_IF_1"
newline
bitfld.long 0x00 30. "SRAM30_IF,SRAM30_IF" "0: SRAM030_IF_0,1: SRAM030_IF_1"
newline
bitfld.long 0x00 29. "SRAM29_IF,SRAM29_IF" "0: SRAM029_IF_0,1: SRAM029_IF_1"
newline
bitfld.long 0x00 28. "SRAM28_IF,SRAM28_IF" "0: SRAM028_IF_0,1: SRAM028_IF_1"
newline
bitfld.long 0x00 27. "SRAM27_IF,SRAM27_IF" "0: SRAM027_IF_0,1: SRAM027_IF_1"
newline
bitfld.long 0x00 26. "SRAM26_IF,SRAM26_IF" "0: SRAM026_IF_0,1: SRAM026_IF_1"
newline
bitfld.long 0x00 25. "SRAM25_IF,SRAM25_IF" "0: SRAM025_IF_0,1: SRAM025_IF_1"
newline
bitfld.long 0x00 24. "SRAM24_IF,SRAM24_IF" "0: SRAM024_IF_0,1: SRAM024_IF_1"
newline
bitfld.long 0x00 23. "SRAM23_IF,SRAM23_IF" "0: SRAM023_IF_0,1: SRAM023_IF_1"
newline
bitfld.long 0x00 22. "SRAM22_IF,SRAM22_IF" "0: SRAM022_IF_0,1: SRAM022_IF_1"
newline
bitfld.long 0x00 21. "SRAM21_IF,SRAM21_IF" "0: SRAM021_IF_0,1: SRAM021_IF_1"
newline
bitfld.long 0x00 20. "SRAM20_IF,SRAM20_IF" "0: SRAM020_IF_0,1: SRAM020_IF_1"
newline
bitfld.long 0x00 19. "SRAM19_IF,SRAM19_IF" "0: SRAM019_IF_0,1: SRAM019_IF_1"
newline
bitfld.long 0x00 18. "SRAM18_IF,SRAM18_IF" "0: SRAM018_IF_0,1: SRAM018_IF_1"
newline
bitfld.long 0x00 17. "SRAM17_IF,SRAM17_IF" "0: SRAM017_IF_0,1: SRAM017_IF_1"
newline
bitfld.long 0x00 16. "SRAM16_IF,SRAM16_IF" "0: SRAM016_IF_0,1: SRAM016_IF_1"
newline
bitfld.long 0x00 15. "SRAM15_IF,SRAM15_IF" "0: SRAM015_IF_0,1: SRAM015_IF_1"
newline
bitfld.long 0x00 14. "SRAM14_IF,SRAM14_IF" "0: SRAM014_IF_0,1: SRAM014_IF_1"
newline
bitfld.long 0x00 13. "SRAM13_IF,SRAM13_IF" "0: SRAM013_IF_0,1: SRAM013_IF_1"
newline
bitfld.long 0x00 12. "SRAM12_IF,SRAM12_IF" "0: SRAM012_IF_0,1: SRAM012_IF_1"
newline
bitfld.long 0x00 11. "SRAM11_IF,SRAM11_IF" "0: SRAM011_IF_0,1: SRAM011_IF_1"
newline
bitfld.long 0x00 10. "SRAM10_IF,SRAM10_IF" "0: SRAM010_IF_0,1: SRAM010_IF_1"
newline
bitfld.long 0x00 9. "SRAM9_IF,SRAM9_IF" "0: SRAM09_IF_0,1: SRAM09_IF_1"
newline
bitfld.long 0x00 8. "SRAM8_IF,SRAM8_IF" "0: SRAM08_IF_0,1: SRAM08_IF_1"
newline
bitfld.long 0x00 7. "SRAM7_IF,SRAM7_IF" "0: SRAM07_IF_0,1: SRAM07_IF_1"
newline
bitfld.long 0x00 6. "SRAM6_IF,SRAM6_IF" "0: SRAM06_IF_0,1: SRAM06_IF_1"
newline
bitfld.long 0x00 5. "SRAM5_IF,SRAM5_IF" "0: SRAM05_IF_0,1: SRAM05_IF_1"
newline
bitfld.long 0x00 4. "SRAM4_IF,SRAM4_IF" "0: SRAM04_IF_0,1: SRAM04_IF_1"
newline
bitfld.long 0x00 3. "SRAM3_IF,SRAM3_IF" "0: SRAM03_IF_0,1: SRAM03_IF_1"
newline
bitfld.long 0x00 2. "SRAM2_IF,SRAM2_IF" "0: SRAM02_IF_0,1: SRAM02_IF_1"
newline
bitfld.long 0x00 1. "SRAM1_IF,SRAM1_IF" "0: SRAM01_IF_0,1: SRAM01_IF_1"
newline
bitfld.long 0x00 0. "SRAM0_IF,SRAM0_IF" "0: SRAM00_IF_0,1: SRAM00_IF_1"
group.long 0x110++0x03
line.long 0x00 "PQ_MEM_CTRL,Power-Quad Memory Control"
bitfld.long 0x00 1. "SRAM_STDBY,SRAM Standby - Powers the driver to dual-port memory" "0: SRAM_STDBY_0,1: SRAM_STDBY_1"
newline
bitfld.long 0x00 0. "SRAM_IG,SRAM Input Gate - Blocks the read input signals to dual-port memory" "0: SRAM_IG_0,1: SRAM_IG_1"
group.long 0x114++0x03
line.long 0x00 "FLEXSPI0_MEM_CTRL,FlexSPI0 Memory Control"
bitfld.long 0x00 2. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 1. "MEM_WIG,Memory Write Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_WIG_0,1: MEM_WIG_1"
newline
bitfld.long 0x00 0. "MEM_RIG,Memory Read Input Gate - Blocks the read input signals to dual-port memory" "0: MEM_RIG_0,1: MEM_RIG_1"
group.long 0x118++0x03
line.long 0x00 "USBHS_MEM_CTRL,USBHS Memory Control"
bitfld.long 0x00 1. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 0. "MEM_IG,Memory Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_IG_0,1: MEM_IG_1"
group.long 0x11C++0x03
line.long 0x00 "USDHC0_MEM_CTRL,USDHC0 Memory Control"
bitfld.long 0x00 2. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 1. "MEM_WIG,Memory Write Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_WIG_0,1: MEM_WIG_1"
newline
bitfld.long 0x00 0. "MEM_RIG,Memory Read Input Gate - Blocks the read input signals to dual-port memory" "0: MEM_RIG_0,1: MEM_RIG_1"
group.long 0x120++0x03
line.long 0x00 "USDHC1_MEM_CTRL,USDHC1 Memory Control"
bitfld.long 0x00 2. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 1. "MEM_WIG,Memory Write Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_WIG_0,1: MEM_WIG_1"
newline
bitfld.long 0x00 0. "MEM_RIG,Memory Read Input Gate - Blocks the read input signals to dual-port memory" "0: MEM_RIG_0,1: MEM_RIG_1"
group.long 0x124++0x03
line.long 0x00 "CASPER_MEM_CTRL,CASPER Memory Control"
bitfld.long 0x00 1. "MEM_STDBY,Auto Standby Control Disable" "0: STDBY is controlled by auto clock gating signal,1: STDBY Is forced low"
newline
bitfld.long 0x00 0. "MEM_IG,Auto Input Gate Control Disable" "0: Input Gate is controlled by auto clock gating..,1: Input Gate Is forced low"
group.long 0x128++0x03
line.long 0x00 "ROM_MEM_CTRL,ROM Memory Control"
bitfld.long 0x00 2. "MEM_LS,MEM LS" "0: MEM_LS_0,1: MEM_LS_1"
newline
bitfld.long 0x00 1. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 0. "MEM_IG,Memory Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_IG_0,1: MEM_IG_1"
group.long 0x12C++0x03
line.long 0x00 "FlexSPI1_MEM_CTRL,FlexSPI1 Memory Control"
bitfld.long 0x00 2. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 1. "MEM_WIG,Memory Write Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_WIG_0,1: MEM_WIG_1"
newline
bitfld.long 0x00 0. "MEM_RIG,Memory Read Input Gate - Blocks the read input signals to dual-port memory" "0: MEM_RIG_0,1: MEM_RIG_1"
group.long 0x130++0x03
line.long 0x00 "GPU_MEM_CTRL,GPU Memory Control"
bitfld.long 0x00 2. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 1. "MEM_WIG,Memory Write Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_WIG_0,1: MEM_WIG_1"
newline
bitfld.long 0x00 0. "MEM_RIG,Memory Read Input Gate - Blocks the read input signals to dual-port memory" "0: MEM_RIG_0,1: MEM_RIG_1"
group.long 0x134++0x03
line.long 0x00 "MIPI_MEM_CTRL,MIPI Memory Control"
bitfld.long 0x00 2. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 1. "MEM_WIG,Memory Write Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_WIG_0,1: MEM_WIG_1"
newline
bitfld.long 0x00 0. "MEM_RIG,Memory Read Input Gate - Blocks the read input signals to dual-port memory" "0: MEM_RIG_0,1: MEM_RIG_1"
group.long 0x138++0x03
line.long 0x00 "DCN_MEM_CTRL,LCDIF Memory Control"
bitfld.long 0x00 2. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: MEM_STDBY_0,1: MEM_STDBY_1"
newline
bitfld.long 0x00 1. "MEM_WIG,Memory Write Input Gate - Blocks the write input signals to dual-port memory" "0: MEM_WIG_0,1: MEM_WIG_1"
newline
bitfld.long 0x00 0. "MEM_RIG,Memory Read Input Gate - Blocks the read input signals to dual-port memory" "0: MEM_RIG_0,1: MEM_RIG_1"
group.long 0x13C++0x03
line.long 0x00 "SMARTDMA_MEM_CTRL,SMARTDMA Memory Control"
bitfld.long 0x00 1. "MEM_STDBY,Memory Standby - Powers the driver to dual-port memory" "0: Enable,1: Disable"
newline
bitfld.long 0x00 0. "MEM_IG,Memory Input Gate" "0: MEM_IG_0,1: MEM_IG_1"
group.long 0x400++0x03
line.long 0x00 "MIPI_DSI_CTRL,MIPI DSI Control"
rbitfld.long 0x00 2. "DSI_TX_ACTIVE,DSI TX ACTIVE" "0,1"
newline
bitfld.long 0x00 1. "DSI_CM,DSI Color Mode Control" "0: Normal mode (full color) (default),1: Low color mode (8-bit)"
newline
bitfld.long 0x00 0. "DSI_SD,DSI Shutdown Control" "0: Shutdown command not to be sent to the Type-4..,1: Shutdown command to be sent to the Type-4.."
group.long 0x40C++0x03
line.long 0x00 "USB0CLKCTRL,USB Clock Control"
bitfld.long 0x00 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode" "0: Forces USB0 PHY to wake-up,1: Normal USB0 PHY behavior"
newline
bitfld.long 0x00 3. "POL_FS_HOST_CLK,USB0 HOST need clock polarity for triggering the USB0 wake-up interrupt" "0: Falling edge of host need_clock triggers..,1: Rising edge of host need_clock triggers wake-up"
newline
bitfld.long 0x00 2. "AP_FS_HOST_CLK,USB0 Host need clock signal control" "0: Under hardware control,1: AP_FS_HOST_CLK_1"
newline
bitfld.long 0x00 1. "POL_FS_DEV_CLK,USB0 Device need clock polarity for triggering the USB0 wake-up interrupt" "0: Falling edge of device need_clock triggers..,1: Rising edge of device need_clock triggers.."
newline
bitfld.long 0x00 0. "AP_FS_DEV_CLK,USB0 Device need clock signal control" "0: Under hardware control,1: AP_FS_DEV_CLK_1"
rgroup.long 0x410++0x03
line.long 0x00 "USB0CLKSTAT,USB Clock Status"
bitfld.long 0x00 1. "HOST_NEED_CLKST,USB0 Device Host USB0_NEEDCLK signal status" "0: HOST_NEED_CLKST_0,1: HOST_NEED_CLKST_1"
newline
bitfld.long 0x00 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status" "0: Low,1: High"
group.long 0x414++0x03
line.long 0x00 "USBPHYPLL0LOCKTIMEDIV2,USB PHY PLL0 lock time division"
hexmask.long.word 0x00 0.--15. 1. "LOCKTIMEDIV2,USBPHYPLL0 Lock Time"
group.long 0x600++0x03
line.long 0x00 "PDSLEEPCFG0,Sleep configuration 0"
bitfld.long 0x00 31. "HSPAD_FSPI1_REF_PD,Hi speed pad sleep mode" "0: High speed pad refs in normal mode,1: High speed pad refs in sleep mode"
newline
bitfld.long 0x00 30. "HSPAD_FSPI1_VDET_LP,Hi speed pad voltage detect sleep mode" "0: High speed pad vdet in normal mode,1: High speed pad vdet in normal mode"
newline
bitfld.long 0x00 29. "HSPAD_SDIO0_REF_PD,High Speed Pad VREF" "0: HSPAD_SDIO0_REF_PD_0,1: HSPAD_SDIO0_REF_PD_1"
newline
bitfld.long 0x00 28. "HSPAD_SDIO0_VDET_LP,High Speed Pad VDET" "0: HSPAD_SDIO0_VDET_LP_0,1: HSPAD_SDIO0_VDET_LP_1"
newline
bitfld.long 0x00 27. "HSPAD_FSPI0_REF_PD,High speed pad sleep mode" "0: High speed pad refs in normal mode,1: High speed pad refs in sleep mode"
newline
bitfld.long 0x00 26. "HSPAD_FSPI0_VDET_LP,High speed pad voltage detect sleep mode" "0: High speed pad vdet in normal mode,1: High speed pad vdet in sleep mode"
newline
bitfld.long 0x00 25. "ACMP_PD,Analog comparator" "0: ACMP_PD_0,1: ACMP_PD_1"
newline
bitfld.long 0x00 24. "PMC_TEMPSNS_PD,PMC temperature sensor" "0: PMC_TEMPSNS_PD_0,1: PMC_TEMPSNS_PD_1"
newline
bitfld.long 0x00 23. "ADC_TEMPSNS_PD,ADC temperature sensor" "0: ADC_TEMPSNS_PD_0,1: ADC_TEMPSNS_PD_1"
newline
bitfld.long 0x00 22. "ADC_LP,ADC low power mode" "0: ADC_LP_0,1: Powerdown"
newline
bitfld.long 0x00 21. "ADC_PD,ADC analog functions" "0: ADC_PD_0,1: Powerdown"
newline
bitfld.long 0x00 20. "AUDPLLANA_PD,Audio PLL analog functions" "0: AUDPLLANA_PD_0,1: AUDPLLANA_PD_1"
newline
bitfld.long 0x00 19. "AUDPLLLDO_PD,Audio PLL internal regulator" "0: AUDPLLLDO_PD_0,1: AUDPLLLDO_PD_1"
newline
bitfld.long 0x00 18. "SYSPLLANA_PD,System PLL analog functions" "0: SYSPLLANA_PD_0,1: SYSPLLANA_PD_1"
newline
bitfld.long 0x00 17. "SYSPLLLDO_PD,System PLL internal regulator" "0: SYSPLLLDO_PD_0,1: SYSPLLLDO_PD_1"
newline
bitfld.long 0x00 16. "FFRO_PD,FRO 192/96 MHz internal oscillator" "0: FFRO_PD_0,1: FFRO_PD_1"
newline
bitfld.long 0x00 15. "RBBSRAM_PD,RBBSRAM" "0: Enables SRAM Reverse Body Bias,1: Disables SRAM Reverse Body Bias"
newline
bitfld.long 0x00 14. "LPOSC_PD,1 MHz Low-Power oscillator" "0: LPOSC_PD_0,1: LPOSC_PD_1"
newline
bitfld.long 0x00 13. "SYSXTAL_PD,Main crystal oscillator" "0: SYSXTAL_PD_0,1: SYSXTAL_PD_1"
newline
bitfld.long 0x00 12. "FBB_PD,Forward body-bias" "0: FBB_PD_0,1: Powerdown"
newline
bitfld.long 0x00 11. "RBB_PD,Reverse body-bias" "0: RBB_PD_0,1: Powerdown"
newline
bitfld.long 0x00 10. "HVDCORE_PD,HVD" "0: HVDCORE_PD_0,1: HVDCORE_PD_1"
newline
bitfld.long 0x00 9. "LVDCORE_LP,LVD" "0: LVDCORE_LP_0,1: LVDCORE_LP_1"
newline
bitfld.long 0x00 7. "HVD1V8_PD,HVD" "0: HVD1V8_PD_0,1: HVD1V8_PD_1"
newline
bitfld.long 0x00 6. "PMCREF_LP,Internal PMC references LP mode" "0: PMCREF_LP_0,1: PMCREF_LP_1"
newline
bitfld.long 0x00 4. "VDDCOREREG_LP,Vddcore regulator mode" "0: VDDCOREREG_LP_0,1: VDDCOREREG_LP_1"
newline
bitfld.long 0x00 3. "DEEP_PD,Deep power-down mode" "0: VDDCORE supply remains on during WFI..,1: VDDCORE powered-off during WFI.."
newline
bitfld.long 0x00 2. "PMIC_MODE1,PMIC_MODE1 device pin" "0: Set mode to 0,1: Set mode to 1"
newline
bitfld.long 0x00 1. "PMIC_MODE0,PMIC_MODE0 device pin" "0: Set mode to 0,1: Set mode to 1"
newline
bitfld.long 0x00 0. "MAINCLK_SHUTOFF,Main clock shut off" "0: MAINCLK_SHUTOFF_0,1: MAINCLK_SHUTOFF_1"
group.long 0x604++0x03
line.long 0x00 "PDSLEEPCFG1,Sleep configuration 1"
bitfld.long 0x00 31. "SRAM_SLEEP,SRAM sleep mode" "0: RAM Normal mode,1: RAM Sleep mode"
newline
bitfld.long 0x00 30. "HSPAD_SDIO1_REF_PD,High speed pad SDIO1 sleep mode" "0: HSPAD_SDIO1_REF_PD_0,1: HSPAD_SDIO1_REF_PD_1"
newline
bitfld.long 0x00 29. "HSPAD_SDIO1_VDET_LP,High speed pad SDIO1 voltage detect sleep mode" "0: HSPAD_SDIO1_VDET_LP_0,1: HSPAD_SDIO1_VDET_LP_1"
newline
bitfld.long 0x00 28. "ROM_PD,ROM" "0: ROM Powered,1: ROM not Powered"
newline
bitfld.long 0x00 27. "OTP_PD,OTP" "0: OTP_PD_0,1: Not Powered"
newline
bitfld.long 0x00 26. "MIPIDSI_PD,MIPIDSI" "0: MIPI DSI not power gated,1: MIPI DSI power gated"
newline
bitfld.long 0x00 25. "DSP_PD,DSP" "0: DSP not power gated,1: DSP power gated"
newline
bitfld.long 0x00 21. "LCDIF_SRAM_PPD,Periphery Power for LCDIF SRAM" "0: Power down disabled or Powered ON,1: _LCDIF_SRAM_PPD1_1"
newline
bitfld.long 0x00 20. "LCDIF_SRAM_APD,Array Power for LCDIF SRAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 19. "MIPIDSI_SRAM_PPD,Periphery Power for MIPIDSI SRAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 18. "MIPIDSI_SRAM_APD,Array Power for MIPIDSI SRAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 17. "SMARTDMA_SRAM_PPD,Periphery Power for SMARTDMA SRAM" "0: SMARTDMA_SRAM_PPD0,1: SMARTDMA_SRAM_PPD1"
newline
bitfld.long 0x00 16. "SMARTDMA_SRAM_APD,Array Power for SMARTDMA SRAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 15. "GPU_SRAM_PPD,Periphery Power for GPU SRAM" "0: GPU_SRAM_PPD0,1: GPU_SRAM_PPD1"
newline
bitfld.long 0x00 14. "GPU_SRAM_APD,Array Power for GPU SRAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 13. "CASPER_SRAM_PPD,Periphery power for Casper RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 11. "USDHC1_SRAM_PPD,Periphery power for uSDHC1 (SD/MMC/SDIO interface) RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 10. "USDHC1_SRAM_APD,Array power for Casper RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 9. "USDHC0_SRAM_PPD,Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 8. "USDHC0_SRAM_APD,Array power for uSDHC0 (SD/MMC/SDIO interface) RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 7. "USBHS_SRAM_PPD,Periphery power for USB RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 6. "USBHS_SRAM_APD,Array power for USB RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 5. "FLEXSPI1_SRAM_PPD,Periphery power for FLEXSPI1 RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 4. "FLEXSPI1_SRAM_APD,Array power for FLEXSPI1 RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 3. "FLEXSPI0_SRAM_PPD,Periphery power for FLEXSPI0 RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 2. "FLEXSPI0_SRAM_APD,Array power for FLEXSPI0 RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 1. "PQ_SRAM_PPD,Periphery power for PowerQuad RAM" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
group.long 0x608++0x03
line.long 0x00 "PDSLEEPCFG2,Sleep configuration 2"
bitfld.long 0x00 31. "SRAM_IF31_APD,Array power for RAM interface 31" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 30. "SRAM_IF30_APD,Array power for RAM interface 30" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
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bitfld.long 0x00 29. "SRAM_IF29_APD,Array power for RAM interface 29" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 28. "SRAM_IF28_APD,Array power for RAM interface 28" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 27. "SRAM_IF27_APD,Array power for RAM interface 27" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 26. "SRAM_IF26_APD,Array power for RAM interface 26" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 25. "SRAM_IF25_APD,Array power for RAM interface 25" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 24. "SRAM_IF24_APD,Array power for RAM interface 24" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 23. "SRAM_IF23_APD,Array power for RAM interface 23" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 22. "SRAM_IF22_APD,Array power for RAM interface 22" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 21. "SRAM_IF21_APD,Array power for RAM interface 21" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 20. "SRAM_IF20_APD,Array power for RAM interface 20" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 19. "SRAM_IF19_APD,Array power for RAM interface 19" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 18. "SRAM_IF18_APD,Array power for RAM interface 18" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 17. "SRAM_IF17_APD,Array power for RAM interface 17" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 16. "SRAM_IF16_APD,Array power for RAM interface 16" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 15. "SRAM_IF15_APD,Array power for RAM interface 15" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 14. "SRAM_IF14_APD,Array power for RAM interface 14" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 13. "SRAM_IF13_APD,Array power for RAM interface 13" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 12. "SRAM_IF12_APD,Array power for RAM interface 12" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
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bitfld.long 0x00 11. "SRAM_IF11_APD,Array power for RAM interface 11" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 10. "SRAM_IF10_APD,Array power for RAM interface 10" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 9. "SRAM_IF9_APD,Array power for RAM interface 9" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
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bitfld.long 0x00 8. "SRAM_IF8_APD,Array power for RAM interface 8" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 7. "SRAM_IF7_APD,Array power for RAM interface 7" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 6. "SRAM_IF6_APD,Array power for RAM interface 6" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 5. "SRAM_IF5_APD,Array power for RAM interface 5" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
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bitfld.long 0x00 4. "SRAM_IF4_APD,Array power for RAM interface 4" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 3. "SRAM_IF3_APD,Array power for RAM interface 3" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 2. "SRAM_IF2_APD,Array power for RAM interface 2" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
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bitfld.long 0x00 1. "SRAM_IF1_APD,Array power for RAM interface 1" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
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bitfld.long 0x00 0. "SRAM_IF0_APD,Array power for RAM interface 0" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
group.long 0x60C++0x03
line.long 0x00 "PDSLEEPCFG3,Sleep configuration 3"
bitfld.long 0x00 31. "SRAM_IF31_PPD,Periphery power for RAM interface 31" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 30. "SRAM_IF30_PPD,Periphery power for RAM interface 30" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 29. "SRAM_IF29_PPD,Periphery power for RAM interface 29" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 28. "SRAM_IF28_PPD,Periphery power for RAM interface 28" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
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bitfld.long 0x00 27. "SRAM_IF27_PPD,Periphery power for RAM interface 27" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 26. "SRAM_IF26_PPD,Periphery power for RAM interface 26" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
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bitfld.long 0x00 25. "SRAM_IF25_PPD,Periphery power for RAM interface 25" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 24. "SRAM_IF24_PPD,Periphery power for RAM interface 24" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 23. "SRAM_IF23_PPD,Periphery power for RAM interface 23" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 22. "SRAM_IF22_PPD,Periphery power for RAM interface 22" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 21. "SRAM_IF21_PPD,Periphery power for RAM interface 21" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 20. "SRAM_IF20_PPD,Periphery power for RAM interface 20" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 19. "SRAM_IF19_PPD,Periphery power for RAM interface 19" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 18. "SRAM_IF18_PPD,Periphery power for RAM interface 18" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 17. "SRAM_IF17_PPD,Periphery power for RAM interface 17" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 16. "SRAM_IF16_PPD,Periphery power for RAM interface 16" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 15. "SRAM_IF15_PPD,Periphery power for RAM interface 15" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 14. "SRAM_IF14_PPD,Periphery power for RAM interface 14" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 13. "SRAM_IF13_PPD,Periphery power for RAM interface 13" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 12. "SRAM_IF12_PPD,Periphery power for RAM interface 12" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 11. "SRAM_IF11_PPD,Periphery power for RAM interface 11" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 10. "SRAM_IF10_PPD,Periphery power for RAM interface 10" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 9. "SRAM_IF9_PPD,Periphery power for RAM interface 9" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 8. "SRAM_IF8_PPD,Periphery power for RAM interface 8" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 7. "SRAM_IF7_PPD,Periphery power for RAM interface 7" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 6. "SRAM_IF6_PPD,Periphery power for RAM interface 6" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 5. "SRAM_IF5_PPD,Periphery power for RAM interface 5" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 4. "SRAM_IF4_PPD,Periphery power for RAM interface 4" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 3. "SRAM_IF3_PPD,Periphery power for RAM interface 3" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 2. "SRAM_IF2_PPD,Periphery power for RAM interface 2" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 1. "SRAM_IF1_PPD,Periphery power for RAM interface 1" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 0. "SRAM_IF0_PPD,Periphery power for RAM interface 0" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
group.long 0x610++0x03
line.long 0x00 "PDRUNCFG0,Run configuration 0"
bitfld.long 0x00 31. "HSPAD_FSPI1_REF_PD,Hi speed pad sleep mode" "0: High speed pad refs in normal mode,1: High speed pad refs in sleep mode"
newline
bitfld.long 0x00 30. "HSPAD_FSPI1_VDET_LP,Hi speed pad voltage detect sleep mode" "0: High speed pad vdet in normal mode,1: High speed pad vdet in normal mode"
newline
bitfld.long 0x00 29. "HSPAD_SDIO0_REF_PD,High Speed Pad VREF" "0: HSPAD_SDIO0_REF_PD_0,1: HSPAD_SDIO0_REF_PD_1"
newline
bitfld.long 0x00 28. "HSPAD_SDIO0_VDET_LP,High Speed Pad VDET" "0: HSPAD_SDIO0_VDET_LP_0,1: HSPAD_SDIO0_VDET_LP_1"
newline
bitfld.long 0x00 27. "HSPAD_FSPI0_REF_PD,Hi-speed pad sleep mode" "0: High speed pad refs in normal mode,1: High speed pad refs in sleep mode"
newline
bitfld.long 0x00 26. "HSPAD_FSPI0_VDET_LP,Hi-speed pad voltage detect sleep mode" "0: High speed pad vdet in normal mode,1: High speed pad vdet in sleep mode"
newline
bitfld.long 0x00 25. "ACMP_PD,Analog comparator" "0: ACMP_PD_0,1: ACMP_PD_1"
newline
bitfld.long 0x00 24. "PMC_TEMPSNS_PD,PMC temperature sensor" "0: PMC_TEMPSNS_PD_0,1: PMC_TEMPSNS_PD_1"
newline
bitfld.long 0x00 23. "ADC_TEMPSNS_PD,ADC temperature sensor" "0: ADC_TEMPSNS_PD_0,1: ADC_TEMPSNS_PD_1"
newline
bitfld.long 0x00 22. "ADC_LP,ADC low power mode" "0: ADC_LP_0,1: Powerdown"
newline
bitfld.long 0x00 21. "ADC_PD,ADC analog functions" "0: ADC_PD_0,1: Powerdown"
newline
bitfld.long 0x00 20. "AUDPLLANA_PD,Audio PLL analog functions" "0: AUDPLLANA_PD_0,1: AUDPLLANA_PD_1"
newline
bitfld.long 0x00 19. "AUDPLLLDO_PD,Audio PLL internal regulator" "0: AUDPLLLDO_PD_0,1: AUDPLLLDO_PD_1"
newline
bitfld.long 0x00 18. "SYSPLLANA_PD,System PLL analog functions" "0: SYSPLLANA_PD_0,1: SYSPLLANA_PD_1"
newline
bitfld.long 0x00 17. "SYSPLLLDO_PD,System PLL internal regulator" "0: SYSPLLLDO_PD_0,1: SYSPLLLDO_PD_1"
newline
bitfld.long 0x00 16. "FFRO_PD,FFRO 192/96 MHz internal oscillator" "0: FFRO_PD_0,1: FFRO_PD_1"
newline
bitfld.long 0x00 15. "RBBSRAM_PD,Reverse body-bias SRAM" "0: Enables SRAM Reverse Body Bias,1: Disables SRAM Reverse Body Bias"
newline
bitfld.long 0x00 14. "LPOSC_PD,1 MHz Low-Power oscillator" "0: LPOSC_PD_0,1: LPOSC_PD_1"
newline
bitfld.long 0x00 13. "SYSXTAL_PD,Main crystal oscillator" "0: SYSXTAL_PD_0,1: SYSXTAL_PD_1"
newline
bitfld.long 0x00 12. "FBB_PD,Forward body-bias" "0: FBB_PD_0,1: Powerdown"
newline
bitfld.long 0x00 11. "RBB_PD,Reverse body-bias" "0: RBB_PD_0,1: Powerdown"
newline
bitfld.long 0x00 10. "HVDCORE_PD,HVD" "0: HVDCORE_PD_0,1: HVDCORE_PD_1"
newline
bitfld.long 0x00 9. "LVDCORE_LP,LVD" "0: LVDCORE_LP_0,1: LVDCORE_LP_1"
newline
bitfld.long 0x00 7. "HVD1V8_PD,HVD" "0: HVD1V8_PD_0,1: HVD1V8_PD_1"
newline
bitfld.long 0x00 6. "PMCREF_LP,Internal PMC references LP mode" "0: PMCREF_LP_0,1: PMCREF_LP_1"
newline
bitfld.long 0x00 4. "VDDCOREREG_LP,Vddcore regulator mode" "0: VDDCOREREG_LP_0,1: VDDCOREREG_LP_1"
newline
bitfld.long 0x00 3. "DEEP_PD,Deep power-down mode" "0: VDDCORE supply remains on during WFI..,1: VDDCORE powered-off during WFI.."
newline
bitfld.long 0x00 2. "PMIC_MODE1,PMIC_MODE1 device pin" "0: Set mode to 0,1: Set mode to 1"
newline
bitfld.long 0x00 1. "PMIC_MODE0,PMIC_MODE0 device pin" "0: Set mode to 0,1: Set mode to 1"
newline
bitfld.long 0x00 0. "MAINCLK_SHUTOFF,Main clock shut off" "0: MAINCLK_SHUTOFF_0,1: MAINCLK_SHUTOFF_1"
group.long 0x614++0x03
line.long 0x00 "PDRUNCFG1,Run configuration 1"
bitfld.long 0x00 31. "SRAM_SLEEP,SRAM sleep mode" "0: RAM Normal mode,1: RAM Sleep mode"
newline
bitfld.long 0x00 30. "HSPAD_SDIO1_REF_PD,High speed pad SDIO1 sleep mode" "0: HSPAD_SDIO1_REF_PD_0,1: HSPAD_SDIO1_REF_PD_1"
newline
bitfld.long 0x00 29. "HSPAD_SDIO1_VDET_LP,High speed pad SDIO1 voltage detect sleep mode" "0: HSPAD_SDIO1_VDET_LP_0,1: HSPAD_SDIO1_VDET_LP_1"
newline
bitfld.long 0x00 28. "ROM_PD,Array periphery power for ROM" "0: ROM Powered,1: ROM not Powered"
newline
bitfld.long 0x00 27. "OTP_PD,OTP" "0: OTP_PD_0,1: Not Powered"
newline
bitfld.long 0x00 26. "MIPIDSI_PD,MIPIDSI" "0: MIPI DSI not power gated,1: MIPI DSI power gated"
newline
bitfld.long 0x00 25. "DSP_PD,DSP" "0: DSP not power gated,1: DSP power gated"
newline
bitfld.long 0x00 21. "LCDIF_SRAM_PPD,LCDIF SRAM Periphery Power" "0: Power down disabled or Powered ON,1: _LCDIF_SRAM_PPD1_1"
newline
bitfld.long 0x00 20. "LCDIF_SRAM_APD,LCDIF SRAM Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 19. "MIPIDSI_SRAM_PPD,MIPIDSI SRAM Periphery Power" "0: MIPIDSI_SRAM_PPD0,1: MIPIDSI_SRAM_PPD1"
newline
bitfld.long 0x00 18. "MIPIDSI_SRAM_APD,MIPIDSI SRAM Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 17. "SMARTDMA_SRAM_PPD,SMARTDMA SRAM Periphery Power" "0: SMARTDMA_SRAM_PPD0,1: SMARTDMA_SRAM_PPD1"
newline
bitfld.long 0x00 16. "SMARTDMA_SRAM_APD,SMARTDMA SRAM Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 15. "GPU_SRAM_PPD,GPU Periphery Power" "0: GPU_SRAM_PPD0,1: GPU_SRAM_PPD1"
newline
bitfld.long 0x00 14. "GPU_SRAM_APD,GPU Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 13. "CASPER_SRAM_PPD,CASPER SRAM Periphery Power" "0: CASPER_SRAM_PPD0,1: CASPER_SRAM_PPD1"
newline
bitfld.long 0x00 11. "USDHC1_SRAM_PPD,USDHC1 SRAM Periphery Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 10. "USDHC1_SRAM_APD,USDHC1 SRAM Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 9. "USDHC0_SRAM_PPD,USDHC0 SRAM_ Periphery Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 8. "USDHC0_SRAM_APD,USDHC0 SRAM Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 7. "USBHS_SRAM_PPD,USBHS SRAM Periphery Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 6. "USBHS_SRAM_APD,USBHS SRAM Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 5. "FLEXSPI1_SRAM_PPD,FLEXSPI1 SRAM Periphery Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 4. "FLEXSPI1_SRAM_APD,FLEXSPI1 SRAM Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 3. "FLEXSPI0_SRAM_PPD,FLEXSPI0 SRAM Periphery Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 2. "FLEXSPI0_SRAM_APD,FLEXSPI0 SRAM Array Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 1. "PQ_SRAM_PPD,Power Quad SRAM Periphery Power" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
group.long 0x618++0x03
line.long 0x00 "PDRUNCFG2,Run configuration 2"
bitfld.long 0x00 31. "SRAM_IF31_APD,Array Power for RAM interface 31" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 30. "SRAM_IF30_APD,Array Power for RAM interface 30" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 29. "SRAM_IF29_APD,Array Power for RAM interface 29" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 28. "SRAM_IF28_APD,Array Power for RAM interface 28" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 27. "SRAM_IF27_APD,Array Power for RAM interface 27" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 26. "SRAM_IF26_APD,Array Power for RAM interface 26" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 25. "SRAM_IF25_APD,Array Power for RAM interface 25" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 24. "SRAM_IF24_APD,Array Power for RAM interface 24" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 23. "SRAM_IF23_APD,Array Power for RAM interface 23" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 22. "SRAM_IF22_APD,Array Power for RAM interface 22" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 21. "SRAM_IF21_APD,Array Power for RAM interface 21" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 20. "SRAM_IF20_APD,Array Power for RAM interface 20" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 19. "SRAM_IF19_APD,Array Power for RAM interface 19" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 18. "SRAM_IF18_APD,Array Power for RAM interface 18" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 17. "SRAM_IF17_APD,Array Power for RAM interface 17" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 16. "SRAM_IF16_APD,Array Power for RAM interface 16" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 15. "SRAM_IF15_APD,Array Power for RAM interface 15" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 14. "SRAM_IF14_APD,Array Power for RAM interface 14" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 13. "SRAM_IF13_APD,Array Power for RAM interface 13" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 12. "SRAM_IF12_APD,Array Power for RAM interface 12" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 11. "SRAM_IF11_APD,Array Power for RAM interface 11" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 10. "SRAM_IF10_APD,Array Power for RAM interface 10" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 9. "SRAM_IF9_APD,Array Power for RAM interface 9" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 8. "SRAM_IF8_APD,Array Power for RAM interface 8" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 7. "SRAM_IF7_APD,Array Power for RAM interface 7" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 6. "SRAM_IF6_APD,Array Power for RAM interface 6" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 5. "SRAM_IF5_APD,Array Power for RAM interface 5" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 4. "SRAM_IF4_APD,Array Power for RAM interface 4" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 3. "SRAM_IF3_APD,Array Power for RAM interface 3" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 2. "SRAM_IF2_APD,Array Power for RAM interface 2" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 1. "SRAM_IF1_APD,Array Power for RAM interface 1" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 0. "SRAM_IF0_APD,Array Power for RAM interface 0" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
group.long 0x61C++0x03
line.long 0x00 "PDRUNCFG3,Run configuration 3"
bitfld.long 0x00 31. "SRAM_IF31_PPD,Periphery power for RAM interface 31" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 30. "SRAM_IF30_PPD,Periphery power for RAM interface 30" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 29. "SRAM_IF29_PPD,Periphery power for RAM interface 29" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 28. "SRAM_IF28_PPD,Periphery power for RAM interface 28" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 27. "SRAM_IF27_PPD,Periphery power for RAM interface 27" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 26. "SRAM_IF26_PPD,Periphery power for RAM interface 26" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 25. "SRAM_IF25_PPD,Periphery power for RAM interface 25" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 24. "SRAM_IF24_PPD,Periphery power for RAM interface 24" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 23. "SRAM_IF23_PPD,Periphery power for RAM interface 23" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 22. "SRAM_IF22_PPD,Periphery power for RAM interface 22" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 21. "SRAM_IF21_PPD,Periphery power for RAM interface 21" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 20. "SRAM_IF20_PPD,Periphery power for RAM interface 20" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 19. "SRAM_IF19_PPD,Periphery power for RAM interface 19" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 18. "SRAM_IF18_PPD,Periphery power for RAM interface 18" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 17. "SRAM_IF17_PPD,Periphery power for RAM interface 17" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 16. "SRAM_IF16_PPD,Periphery power for RAM interface 16" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 15. "SRAM_IF15_PPD,Periphery power for RAM interface 15" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 14. "SRAM_IF14_PPD,Periphery power for RAM interface 14" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 13. "SRAM_IF13_PPD,Periphery power for RAM interface 13" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 12. "SRAM_IF12_PPD,Periphery power for RAM interface 12" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 11. "SRAM_IF11_PPD,Periphery power for RAM interface 11" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 10. "SRAM_IF10_PPD,Periphery power for RAM interface 10" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 9. "SRAM_IF9_PPD,Periphery power for RAM interface 9" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 8. "SRAM_IF8_PPD,Periphery power for RAM interface 8" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 7. "SRAM_IF7_PPD,Periphery power for RAM interface 7" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 6. "SRAM_IF6_PPD,Periphery power for RAM interface 6" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 5. "SRAM_IF5_PPD,Periphery power for RAM interface 5" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 4. "SRAM_IF4_PPD,Periphery power for RAM interface 4" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 3. "SRAM_IF3_PPD,Periphery power for RAM interface 3" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 2. "SRAM_IF2_PPD,Periphery power for RAM interface 2" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 1. "SRAM_IF1_PPD,Periphery power for RAM interface 1" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
newline
bitfld.long 0x00 0. "SRAM_IF0_PPD,Periphery power for RAM interface 0" "0: Power down disabled or Powered ON,1: Power down enabled or Powered OFF"
wgroup.long 0x620++0x03
line.long 0x00 "PDRUNCFG0_SET,Run configuration 0 set"
bitfld.long 0x00 31. "HSPAD_FSPI1_REF_PD,High speed pad FSPI1 sleep mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 30. "HSPAD_FSPI1_VDET_LP,High speed pad FSPI1 voltage detect sleep mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 29. "HSPADREF_PD,High speed pad sleep mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 28. "HSPADVDET_LP,High speed pad FSPI0 voltage detect sleep mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 27. "HSPAD_FSPI0_REF_PD,High speed pad FSPI0 voltage detect sleep mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 26. "HSPAD_FSPI0_VDET_LP,High speed pad voltage detect sleep mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 25. "ACMP_PD,Analog comparator" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 24. "PMC_TEMPSNS_PD,PMC temperature sensor" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 23. "ADC_TEMPSNS_PD,ADC temperature sensor" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 22. "ADC_LP,ADC low power mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 21. "ADC_PD,ADC analog functions" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 20. "AUDPLLANA_PD,Audio PLL analog functions" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 19. "AUDPLLLDO_PD,Audio PLL internal regulator" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 18. "SYSPLLANA_PD,System PLL analog functions" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 17. "SYSPLLLDO_PD,System PLL internal regulator" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 16. "FFRO_PD,FFRO 19296 MHz internal oscillator" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 15. "RBBSRAM_PD,Reverse body-bias SRAM" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 14. "LPOSC_PD,1 MHz Low-Power oscillator" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 13. "SYSXTAL_PD,Main crystal oscillator" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 12. "FBB_PD,Forward body-bias" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 11. "RBB_PD,Reverse body-bias" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 10. "HVDCORE_PD,HVD" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 9. "LVDCORE_LP,LVD" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 7. "HVD1V8_PD,HVD" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 6. "PMCREF_LP,Internal PMC references LP mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 4. "VDDCOREREG_LP,Vddcore regulator mode" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 3. "DEEP_PD,Deep power-down mode" "0: VDDCORE supply remains on during WFI..,1: VDDCORE powered-off during WFI.."
newline
bitfld.long 0x00 2. "PMIC_MODE1,PMIC_MODE1 pin" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 1. "PMIC_MODE0,PMIC_MODE0 pin" "0: No effect,1: Sets the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 0. "MAINCLK_SHUTOFF,Main clock shut off" "0: No effect,1: Sets the PDRUNCFG0 Bit"
wgroup.long 0x624++0x03
line.long 0x00 "PDRUNCFG1_SET,Run configuration 1 set"
bitfld.long 0x00 31. "SRAM_SLEEP,SRAM sleep mode" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 30. "HSPAD_SDIO1_REF_PD,High speed pad sleep mode" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 29. "HSPAD_SDIO1_VDET_LP,High speed pad voltage detect sleep mode" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 28. "ROM_PD,Array and periphery power for ROM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 27. "OTP_PD,Array and periphery power for OTP" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 26. "MIPIDSI_PD,Array and periphery power for MIPIDSI" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 25. "DSP_PD,Array and periphery power for DSP" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 21. "LCDIF_SRAM_PPD,Periphery power for LCDIF" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 20. "LCDIF_SRAM_APD,Array power for LCDIF" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 19. "MIPIDSI_SRAM_PPD,Periphery power for MIPIDSI SRAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 18. "MIPIDSI_SRAM_APD,Array power for MIPIDSI SRAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 17. "SMARTDMA_SRAM_PPD,Periphery power for SMARTDMA SRAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 16. "SMARTDMA_SRAM_APD,Array power for SMARTDMA SRAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 15. "GPU_SRAM_PPD,Periphery power for GPU SRAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 14. "GPU_SRAM_APD,Array power for GPU SRAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 13. "CASPER_SRAM_PPD,Periphery power for Casper RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 11. "USDHC1_SRAM_PPD,Periphery power for uSDHC1 (SD/MMC/SDIO interface) RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 10. "USDHC1_SRAM_APD,Array power for uSDHC1 (SD/MMC/SDIO interface) RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 9. "USDHC0_SRAM_PPD,Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 8. "USDHC0_SRAM_APD,Array power for uSDHC0 (SD/MMC/SDIO interface) RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 7. "USBHS_SRAM_PPD,Periphery power for USB RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 6. "USBHS_SRAM_APD,Array power for USB RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 5. "FLEXSPI1_SRAM_PPD,Periphery power for FLEXSPI1" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 4. "FLEXSPI1_SRAM_APD,Array power for FLEXSPI1" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 3. "FLEXSPI0_SRAM_PPD,Periphery power for FLEXSPI0" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 2. "FLEXSPI0_SRAM_APD,Array power for FLEXSPI0" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 1. "PQ_SRAM_PPD,Periphery power for PowerQuad RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 0. "PQ_SRAM_APD,Array power for PowerQuad RAM" "0: No effect,1: Sets the PDRUNCFG1 Bit"
wgroup.long 0x628++0x03
line.long 0x00 "PDRUNCFG2_SET,Run configuration 2 set"
bitfld.long 0x00 31. "SRAM_IF31_APD,Array power for SRAM interface 31" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 30. "SRAM_IF30_APD,Array power for SRAM interface 30" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 29. "SRAM_IF29_APD,Array power for SRAM interface 29" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 28. "SRAM_IF28_APD,Array power for SRAM interface 28" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 27. "SRAM_IF27_APD,Array power for SRAM interface 27" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 26. "SRAM_IF26_APD,Array power for SRAM interface 26" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 25. "SRAM_IF25_APD,Array power for SRAM interface 25" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 24. "SRAM_IF24_APD,Array power for SRAM interface 24" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 23. "SRAM_IF23_APD,Array power for SRAM interface 23" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 22. "SRAM_IF22_APD,Array power for SRAM interface 22" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 21. "SRAM_IF21_APD,Array power for SRAM interface 21" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 20. "SRAM_IF20_APD,Array power for SRAM interface 20" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 19. "SRAM_IF19_APD,Array power for SRAM interface 19" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 18. "SRAM_IF18_APD,Array power for SRAM interface 18" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 17. "SRAM_IF17_APD,Array power for SRAM interface 17" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 16. "SRAM_IF16_APD,Array power for SRAM interface 16" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 15. "SRAM_IF15_APD,Array power for SRAM interface 15" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 14. "SRAM_IF14_APD,Array power for SRAM interface 14" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 13. "SRAM_IF13_APD,Array power for SRAM interface 13" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 12. "SRAM_IF12_APD,Array power for SRAM interface 12" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 11. "SRAM_IF11_APD,Array power for SRAM interface 11" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 10. "SRAM_IF10_APD,Array power for SRAM interface 10" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 9. "SRAM_IF9_APD,Array power for SRAM interface 9" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 8. "SRAM_IF8_APD,Array power for SRAM interface 8" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 7. "SRAM_IF7_APD,Array power for SRAM interface 7" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 6. "SRAM_IF6_APD,Array power for SRAM interface 6" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 5. "SRAM_IF5_APD,Array power for SRAM interface 5" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 4. "SRAM_IF4_APD,Array power for SRAM interface 4" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 3. "SRAM_IF3_APD,Array power for SRAM interface 3" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 2. "SRAM_IF2_APD,Array power for SRAM interface 2" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 1. "SRAM_IF1_APD,Array power for SRAM interface 1" "0: No effect,1: Sets the PDRUNCFG2 Bit"
newline
bitfld.long 0x00 0. "SRAM_IF0_APD,Array power for SRAM interface 0" "0: No effect,1: Sets the PDRUNCFG2 Bit"
wgroup.long 0x62C++0x03
line.long 0x00 "PDRUNCFG3_SET,Run configuration 3 set"
bitfld.long 0x00 31. "SRAM_IF31_PPD,Periphery power for RAM interface 31" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 30. "SRAM_IF30_PPD,Periphery power for RAM interface 30" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 29. "SRAM_IF29_PPD,Periphery power for RAM interface 29" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 28. "SRAM_IF28_PPD,Periphery power for RAM interface 28" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 27. "SRAM_IF27_PPD,Periphery power for RAM interface 27" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 26. "SRAM_IF26_PPD,Periphery power for RAM interface 26" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 25. "SRAM_IF25_PPD,Periphery power for RAM interface 25" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 24. "SRAM_IF24_PPD,Periphery power for RAM interface 24" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 23. "SRAM_IF23_PPD,Periphery power for RAM interface 23" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 22. "SRAM_IF22_PPD,Periphery power for RAM interface 22" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 21. "SRAM_IF21_PPD,Periphery power for RAM interface 21" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 20. "SRAM_IF20_PPD,Periphery power for RAM interface 20" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 19. "SRAM_IF19_PPD,Periphery power for RAM interface 19" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 18. "SRAM_IF18_PPD,Periphery power for RAM interface 18" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 17. "SRAM_IF17_PPD,Periphery power for RAM interface 17" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 16. "SRAM_IF16_PPD,Periphery power for RAM interface 16" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 15. "SRAM_IF15_PPD,Periphery power for RAM interface 15" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 14. "SRAM_IF14_PPD,Periphery power for RAM interface 14" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 13. "SRAM_IF13_PPD,Periphery power for RAM interface 13" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 12. "SRAM_IF12_PPD,Periphery power for RAM interface 12" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 11. "SRAM_IF11_PPD,Periphery power for RAM interface 11" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 10. "SRAM_IF10_PPD,Periphery power for RAM interface 10" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 9. "SRAM_IF9_PPD,Periphery power for RAM interface 9" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 8. "SRAM_IF8_PPD,Periphery power for RAM interface 8" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 7. "SRAM_IF7_PPD,Periphery power for RAM interface 7" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 6. "SRAM_IF6_PPD,Periphery power for RAM interface 6" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 5. "SRAM_IF5_PPD,Periphery power for RAM interface 5" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 4. "SRAM_IF4_PPD,Periphery power for RAM interface 4" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 3. "SRAM_IF3_PPD,Periphery power for RAM interface 3" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 2. "SRAM_IF2_PPD,Periphery power for RAM interface 2" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 1. "SRAM_IF1_PPD,Periphery power for RAM interface 1" "0: No effect,1: Sets the PDRUNCFG3 Bit"
newline
bitfld.long 0x00 0. "SRAM_IF0_PPD,Periphery power for RAM interface 0" "0: No effect,1: Sets the PDRUNCFG3 Bit"
wgroup.long 0x630++0x03
line.long 0x00 "PDRUNCFG0_CLR,Run configuration 0 clear"
bitfld.long 0x00 31. "HSPAD_FSPI1_REF_PD,High speed pad FSPIO1 sleep mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 30. "HSPAD_FSPI1_VDET_LP,High speed pad FSPI1 voltage detect sleep mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 29. "HSPADREF_PD,High speed pad sleep mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 28. "HSPADVDET_LP,High speed pad voltage detect sleep mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 27. "HSPAD_FSPI0_REF_PD,High speed pad FSPIO0 sleep mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 26. "HSPAD_FSPI0_VDET_LP,High speed pad FSPI0 voltage detect sleep mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 25. "ACMP_PD,Analog comparator" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 24. "PMC_TEMPSNS_PD,PMC temperature sensor" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 23. "ADC_TEMPSNS_PD,ADC temperature sensor" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 22. "ADC_LP,ADC low power mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 21. "ADC_PD,ADC analog functions" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 20. "AUDPLLANA_PD,Audio PLL analog functions" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 19. "AUDPLLLDO_PD,Audio PLL internal regulator" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 18. "SYSPLLANA_PD,System PLL analog functions" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 17. "SYSPLLLDO_PD,System PLL internal regulator" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 16. "FFRO_PD,FRO 16 MHz internal oscillator" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 15. "RBBSRAM_PD,Reverse body-bias SRAM" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 14. "LPOSC_PD,1 MHz Low-Power oscillator" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 13. "SYSXTAL_PD,Main crystal oscillator" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 12. "FBB_PD,Forward body-bias" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 11. "RBB_PD,Reverse body-bias" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 10. "HVDCORE_PD,HVD" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 9. "LVDCORE_LP,LVD" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 7. "HVD1V8_PD,HVD" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 6. "PMCREF_LP,Internal PMC references LP mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 4. "VDDCOREREG_LP,Vddcore regulator mode" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 3. "DEEP_PD,Deep power-down mode" "0: VDDCORE supply remains on during WFI..,1: VDDCORE powered-off during WFI.."
newline
bitfld.long 0x00 2. "PMIC_MODE1,PMIC_MODE1 device pin" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 1. "PMIC_MODE0,PMIC_MODE0 device pin" "0: No effect,1: Clears the PDRUNCFG0 Bit"
newline
bitfld.long 0x00 0. "MAINCLK_SHUTOFF,Main clock shut off" "0: No effect,1: Clears the PDRUNCFG0 Bit"
wgroup.long 0x634++0x03
line.long 0x00 "PDRUNCFG1_CLR,Run configuration 1 clear"
bitfld.long 0x00 31. "SRAM_SLEEP,SRAM sleep mode" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 30. "HSPAD_SDIO1_REF_PD,High speed pad sleep mode" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 29. "HSPAD_SDIO1_VDET_LP,High speed pad voltage detect sleep mode" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 28. "ROM_PD,Array and periphery power for ROM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 27. "OTP_PD,Array and periphery power for OTP" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 26. "MIPIDSI_PD,Array and periphery power for MIPIDSI" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 25. "DSP_PD,Array and periphery power for DSP" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 21. "LCDIF_SRAM_PPD,Periphery power for LCDIF" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 20. "LCDIF_SRAM_APD,Array power for LCDIF" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 19. "MIPIDSI_SRAM_PPD,Periphery power for MIPIDSI SRAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 18. "MIPIDSI_SRAM_APD,Array power for MIPIDSI SRAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 17. "SMARTDMA_SRAM_PPD,Periphery power for SMARTDMA SRAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 16. "SMARTDMA_SRAM_APD,Array power for SMARTDMA SRAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 15. "GPU_SRAM_PPD,Periphery power for GPU RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 14. "GPU_SRAM_APD,Array power for GPU SRAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 13. "CASPER_SRAM_PPD,Periphery power for Casper RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 11. "USDHC1_SRAM_PPD,Periphery power for uSDHC1 (SD/MMC/SDIO interface) RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 10. "USDHC1_SRAM_APD,Array power for uSDHC1 (SD/MMC/SDIO interface) RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 9. "USDHC0_SRAM_PPD,Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 8. "USDHC0_SRAM_APD,Array power for uSDHC0 (SD/MMC/SDIO interface) RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 7. "USBHS_SRAM_PPD,Periphery power for USB RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 6. "USBHS_SRAM_APD,Array power for USB RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 5. "FLEXSPI1_SRAM_PPD,Periphery power for FlexSPI1" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 4. "FLEXSPI1_SRAM_APD,Array power for FlexSPI1" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 3. "FLEXSPI0_SRAM_PPD,Periphery power for FlexSPI0" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 2. "FLEXSPI0_SRAM_APD,Array power for FlexSPI0" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 1. "PQ_SRAM_PPD,Periphery power for PowerQuad RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
newline
bitfld.long 0x00 0. "PQ_SRAM_APD,Array power for PowerQuad RAM" "0: No effect,1: Clears the PDRUNCFG1 Bit"
group.long 0x638++0x03
line.long 0x00 "PDRUNCFG2_CLR,Run configuration 2 clear"
eventfld.long 0x00 31. "SRAM_IF31_APD,Array power for RAM interface 31" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 30. "SRAM_IF30_APD,Array power for RAM interface 30" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 29. "SRAM_IF29_APD,Array power for RAM interface 29" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 28. "SRAM_IF28_APD,Array power for RAM interface 28" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 27. "SRAM_IF27_APD,Array power for RAM interface 27" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 26. "SRAM_IF26_APD,Array power for RAM interface 26" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 25. "SRAM_IF25_APD,Array power for RAM interface 25" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 24. "SRAM_IF24_APD,Array power for RAM interface 24" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 23. "SRAM_IF23_APD,Array power for RAM interface 23" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 22. "SRAM_IF22_APD,Array power for RAM interface 22" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 21. "SRAM_IF21_APD,Array power for RAM interface 21" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 20. "SRAM_IF20_APD,Array power for RAM interface 20" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 19. "SRAM_IF19_APD,Array power for RAM interface 19" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 18. "SRAM_IF18_APD,Array power for RAM interface 18" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 17. "SRAM_IF17_APD,Array power for RAM interface 17" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 16. "SRAM_IF16_APD,Array power for RAM interface 16" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 15. "SRAM_IF15_APD,Array power for RAM interface 15" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 14. "SRAM_IF14_APD,Array power for RAM interface 14" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 13. "SRAM_IF13_APD,Array power for RAM interface 13" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 12. "SRAM_IF12_APD,Array power for RAM interface 12" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 11. "SRAM_IF11_APD,Array power for RAM interface 11" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 10. "SRAM_IF10_APD,Array power for RAM interface 10" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 9. "SRAM_IF9_APD,Array power for RAM interface 9" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 8. "SRAM_IF8_APD,Array power for RAM interface 8" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 7. "SRAM_IF7_APD,Array power for RAM interface 7" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 6. "SRAM_IF6_APD,Array power for RAM interface 6" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 5. "SRAM_IF5_APD,Array power for RAM interface 5" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 4. "SRAM_IF4_APD,Array power for RAM interface 4" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 3. "SRAM_IF3_APD,Array power for RAM interface 3" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 2. "SRAM_IF2_APD,Array power for RAM interface 2" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 1. "SRAM_IF1_APD,Array power for RAM interface 1" "0: No effect,1: Clears the PDRUNCFG2 Bit"
newline
eventfld.long 0x00 0. "SRAM_IF0_APD,Array power for RAM interface 0" "0: No effect,1: Clears the PDRUNCFG2 Bit"
group.long 0x63C++0x03
line.long 0x00 "PDRUNCFG3_CLR,Run configuration 3 clear"
eventfld.long 0x00 31. "SRAM_IF31_PPD,Periphery power for RAM interface 31" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 30. "SRAM_IF30_PPD,Periphery power for RAM interface 30" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 29. "SRAM_IF29_PPD,Periphery power for RAM interface 29" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 28. "SRAM_IF28_PPD,Periphery power for RAM interface 28" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 27. "SRAM_IF27_PPD,Periphery power for RAM interface 27" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 26. "SRAM_IF26_PPD,Periphery power for RAM interface 26" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 25. "SRAM_IF25_PPD,Periphery power for RAM interface 25" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 24. "SRAM_IF24_PPD,Periphery power for RAM interface 24" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 23. "SRAM_IF23_PPD,Periphery power for RAM interface 23" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 22. "SRAM_IF22_PPD,Periphery power for RAM interface 22" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 21. "SRAM_IF21_PPD,Periphery power for RAM interface 21" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 20. "SRAM_IF20_PPD,Periphery power for RAM interface 20" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 19. "SRAM_IF19_PPD,Periphery power for RAM interface 19" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 18. "SRAM_IF18_PPD,Periphery power for RAM interface 18" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 17. "SRAM_IF17_PPD,Periphery power for RAM interface 17" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 16. "SRAM_IF16_PPD,Periphery power for RAM interface 16" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 15. "SRAM_IF15_PPD,Periphery power for RAM interface 15" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 14. "SRAM_IF14_PPD,Periphery power for RAM interface 14" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 13. "SRAM_IF13_PPD,Periphery power for RAM interface 13" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 12. "SRAM_IF12_PPD,Periphery power for RAM interface 12" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 11. "SRAM_IF11_PPD,Periphery power for RAM interface 11" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 10. "SRAM_IF10_PPD,Periphery power for RAM interface 10" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 9. "SRAM_IF9_PPD,Periphery power for RAM interface 9" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 8. "SRAM_IF8_PPD,Periphery power for RAM interface 8" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 7. "SRAM_IF7_PPD,Periphery power for RAM interface 7" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 6. "SRAM_IF6_PPD,Periphery power for RAM interface 6" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 5. "SRAM_IF5_PPD,Periphery power for RAM interface 5" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 4. "SRAM_IF4_PPD,Periphery power for RAM interface 4" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 3. "SRAM_IF3_PPD,Periphery power for RAM interface 3" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 2. "SRAM_IF2_PPD,Periphery power for RAM interface 2" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 1. "SRAM_IF1_PPD,Periphery power for RAM interface 1" "0: No effect,1: Clears the PDRUNCFG3 Bit"
newline
eventfld.long 0x00 0. "SRAM_IF0_PPD,Periphery power for RAM interface 0" "0: No effect,1: Clears the PDRUNCFG3 Bit"
group.long 0x660++0x03
line.long 0x00 "PDWAKECFG,PD Wake Configuration"
bitfld.long 0x00 5. "OTPPDKEEPST,OTP_PD value on wakeup" "0: Use value of OTP_PD in PDRUNCFG on wakeup,1: Copy PDSLEEPCFG OTP_PD value to PDRUNCFG.."
newline
bitfld.long 0x00 4. "DSPPDKEEPST,DSP_PD value on wakeup" "0: Use value of DSP_PD in PDRUNCFG on wakeup,1: Copy PDSLEEPCFG DSP_PD value to PDRUNCFG.."
newline
bitfld.long 0x00 3. "MIPIPDKEEPST,MIPI_PD value on wakeup" "0: Use value of MIPI_PD in PDRUNCFG on wakeup,1: Copy PDSLEEPCFG MIPI_PD value to PDRUNCFG.."
newline
bitfld.long 0x00 2. "RBBSRAMKEEPST,RBB SRAM mode on wakeup" "0: Use value of RBBSRAM_PD in PDRUNCFG on wakeup,1: Copy PDSLEEPCFG RBBSRAM_PD value to PDRUNCFG.."
newline
bitfld.long 0x00 1. "FBBKEEPST,FBB mode on wakeup" "0: Use value of FBB_PD in PDRUNCFG on wakeup,1: Copy PDSLEEPCFG FBB_PD value to PDRUNCFG.."
newline
bitfld.long 0x00 0. "RBBKEEPST,RBB mode on wakeup" "0: Use value of RBB_PD in PDRUNCFG on wakeup,1: Copy PDSLEEPCFG RBB_PD value to PDRUNCFG.."
group.long 0x680++0x03
line.long 0x00 "STARTEN0,Start Enable 0"
bitfld.long 0x00 31. "RNG,RNG wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 30. "PMC,PMC wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 29. "HWVAD0,Hardware VAD wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 28. "SECUREVIOLATION,Secure Violation wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 27. "HYPERVISOR,Hypervisor interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 25. "DMIC0,DMIC wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 24. "ACMP,ACMP wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 22. "ADC0,ADC wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 21. "FLEXCOMM15,Flexcomm 15 (PMIC I2C) peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 20. "FLEXCOMM14,Flexcomm 14 (High Speed SPI) peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 19. "FLEXCOMM5,Flexcomm 5 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 18. "FLEXCOMM4,Flexcomm 4 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 17. "FLEXCOMM3,Flexcomm 3 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 16. "FLEXCOMM2,Flexcomm 2 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 15. "FLEXCOMM1,Flexcomm 1 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 14. "FLEXCOMM0,Flexcomm 0 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 13. "CT32BIT3,CTIMER 3 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 12. "SCT0,SCTimer/PWM wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 11. "CT32BIT1,CTIMER 1 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 10. "CT32BIT0,CTIMER 0 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 9. "MRT0,MRT wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 8. "UTICK0,UTICK wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 7. "GPIO_INT0_IRQ3,GPIO pin interrupt 3 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "GPIO_INT0_IRQ2,GPIO pin interrupt 2 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 5. "GPIO_INT0_IRQ1,GPIO pin interrupt 1 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 4. "GPIO_INT0_IRQ0,GPIO pin interrupt 0 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "GPIO_INTB,Non-secure GPIO interrupt B wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 2. "GPIO_INTA,Non-secure GPIO interrupt A wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "DMAC0,DMA controller 0 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "WDT0,Watchdog timer 0 wake-up" "0: Disabled,1: Enabled"
group.long 0x684++0x03
line.long 0x00 "STARTEN1,Start Enable 1"
bitfld.long 0x00 31. "FLEXCOMM11,FLEXCOMM 11 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 30. "FLEXCOMM10,FLEXCOMM 10 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 29. "FLEXCOMM9,FLEXCOMM 9 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 28. "FLEXCOMM8,FLEXCOMM 8 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 27. "SHA,Hash-AES wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 26. "PMIC,Wake-up from on-chip PMC or off-chip PMIC" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 25. "CASPER,CASPER co-processor wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 24. "POWERQUAD,POWERQUAD co-processor wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 23. "PUF,PUF wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 22. "DMAC1,DMA controller 1 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 21. "USB_PHYDCD,USB PHY DCD interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 19. "USB0_NEEDCLK,USB activity wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 16. "SGPIO_INTB,Secure GPIO interrupt B wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 15. "SGPIO_INTA,Secure GPIO interrupt A wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 14. "SDIO1,SDIO0 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 13. "SDIO0,SDIO0 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 12. "FLEXCOMM7,FLEXCOMM 7 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 11. "FLEXCOMM6,FLEXCOMM 6 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 10. "FLEXSPI,Quad/octal SPI wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 9. "OS_EVENT_TIMER_WU,OS Event Timer wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 8. "CT32BIT4,CTIMER 4 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 7. "CT32BIT2,CTIMER 2 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "GPIO_INT0_IRQ7,GPIO pin interrupt 7 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 5. "GPIO_INT0_IRQ6,GPIO pin interrupt 6 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 4. "GPIO_INT0_IRQ5,GPIO pin interrupt 5 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "GPIO_INT0_IRQ4,GPIO pin interrupt 4 wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 2. "MU,Message Unit wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "DSP_TIE_EXPSTATE1,DSP wake-up" "0: No effect,1: Sets the corresponding STARTEN1 bit"
newline
bitfld.long 0x00 0. "RTC_LITE0_WAKEUP,RTC wake-up" "0: Disabled,1: Enabled"
group.long 0x688++0x03
line.long 0x00 "STARTEN2,Start Enable 2"
bitfld.long 0x00 2. "FLEXCOMM16,FlexComm 16 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "FLEXCOMM13,FlexComm 13 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "FLEXCOMM12,FlexComm 12 peripheral interrupt wake-up" "0: Disabled,1: Enabled"
group.long 0x6A0++0x03
line.long 0x00 "STARTEN0_SET,Start Enable 0 Set"
bitfld.long 0x00 31. "RNG,RNG wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 30. "PMC,PMC wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 29. "HWVAD0,Hardware VAD wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 28. "SECUREVIOLATION,Secure Violation wake-up" "0: SECUREVIOLATION_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 27. "HYPERVISOR,Hypervisor interrupt wake-up" "0: HYPERVISOR_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 25. "DMIC0,DMIC wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 24. "ACMP,ACMP wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 22. "ADC0,ADC wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 21. "FLEXCOMM15,FlexComm 15 (PMIC I2C) peripheral interrupt wake-up" "0: FLEXCOMM15_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 20. "FLEXCOMM14,FlexComm 14 (High Speed SPI) peripheral interrupt wake-up" "0: FLEXCOMM14_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 13. "CT32BIT3,CTIMER 3 wake-up" "0: CT32BIT3_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 12. "SCT0,SCTimer/PWM wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 11. "CT32BIT1,CTIMER 1 wake-up" "0: CT32BIT1_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 10. "CT32BIT0,CTIMER 0 wake-up" "0: CT32BIT0_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 9. "MRT0,MRT wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 8. "UTICK0,UTICK wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 7. "GPIO_INT0_IRQ3,GPIO pin interrupt 3 wake-up" "0: GPIO_INT0_IRQ3_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 6. "GPIO_INT0_IRQ2,GPIO pin interrupt 2 wake-up" "0: GPIO_INT0_IRQ2_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 5. "GPIO_INT0_IRQ1,GPIO pin interrupt 1 wake-up" "0: GPIO_INT0_IRQ1_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 4. "GPIO_INT0_IRQ0,GPIO pin interrupt 0 wake-up" "0: GPIO_INT0_IRQ0_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 3. "GPIO_INTB,Non-secure GPIO interrupt B wake-up" "0: GPIO_INTB_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 2. "GPIO_INTA,Non-secure GPIO interrupt A wake-up" "0: GPIO_INTA_0,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 1. "DMAC0,DMA controller 0 wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
bitfld.long 0x00 0. "WDT0,Watchdog timer 0 wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
group.long 0x6A4++0x03
line.long 0x00 "STARTEN1_SET,Start Enable 1 Set"
bitfld.long 0x00 31. "FLEXCOMM11,FLEXCOMM 11 peripheral interrupt wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 30. "FLEXCOMM10,FLEXCOMM 10 peripheral interrupt wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 29. "FLEXCOMM9,FLEXCOMM 9 peripheral interrupt wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 28. "FLEXCOMM8,FLEXCOMM 8 peripheral interrupt wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 27. "SHA,Hash-AES wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 26. "PMIC,Wake-up from on-chip PMC or off-chip PMIC" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 25. "CASPER,CASPER co-processor wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 24. "POWERQUAD,POWERQUAD co-processor wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 23. "PUF,PUF wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 22. "DMAC1,DMA controller 1 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 21. "USB_PHYDCD,USB PHY DCD interrupt wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 19. "USB0_NEEDCLK,USB activity wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 16. "SGPIO_INTB,Secure GPIO interrupt B wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 15. "SGPIO_INTA,Secure GPIO interrupt A wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 14. "SDIO1,SDIO01 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 13. "SDIO0,SDIO0 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 12. "FLEXCOMM7,FLEXCOMM7 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 11. "FLEXCOMM6,FLEXCOMM6 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 10. "FLEXSPI,Quad/octal SPI wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 9. "OS_EVENT_TIMER_WU,OS Event Timer wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 8. "CT32BIT4,CTIMER 4 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 7. "CT32BIT2,CTIMER 2 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 6. "GPIO_INT0_IRQ7,GPIO pin interrupt 7 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 5. "GPIO_INT0_IRQ6,GPIO pin interrupt 6 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 4. "GPIO_INT0_IRQ5,GPIO pin interrupt 5 wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 3. "GPIO_INT0_IRQ4,Message Unit wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 2. "MU,Message Unit wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
newline
bitfld.long 0x00 1. "DSP_TIE_EXPSTATE1,DSP wake-up" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "RTC_LITE0_WAKEUP,RTC wake-up" "0: No Effect,1: Sets the STARTEN1 Bit"
group.long 0x6A8++0x03
line.long 0x00 "STARTEN2_SET,Start Enable 2"
bitfld.long 0x00 2. "FLEXCOMM16,FlexComm16 interrupt wake-up" "0: No effect,1: Sets the STARTEN2 bit"
newline
bitfld.long 0x00 1. "FLEXCOMM13,FlexComm 13 interrupt wake-up" "0: No effect,1: Sets the STARTEN2 bit"
newline
bitfld.long 0x00 0. "FLEXCOMMC12,FlexComm 12 interrupt wake-up" "0: No effect,1: Sets the STARTEN2 bit"
group.long 0x6C0++0x03
line.long 0x00 "STARTEN0_CLR,Start Enable 0 clear"
eventfld.long 0x00 31. "RNG,RNG wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 30. "PMC,PMC wake-up" "0: No effect,1: Sets the STARTEN0 Bit"
newline
eventfld.long 0x00 29. "HWVAD0,Hardware VAD wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 28. "SECUREVIOLATION,Secure Violation wake-up" "0: SECUREVIOLATION_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 27. "HYPERVISOR,Hypervisor interrupt wake-up" "0: HYPERVISOR_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 25. "DMIC0,DMIC wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 24. "ACMP,ACMP wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 22. "ADC0,ADC wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 21. "FLEXCOMM15,FlexComm 15 (PMIC I2C) peripheral interrupt wake-up" "0: FLEXCOMM15_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 20. "FLEXCOMM14,FlexComm 14 (High Speed SPI) peripheral interrupt wake-up" "0: FLEXCOMM14_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 13. "CT32BIT3,CTIMER 3 wake-up" "0: CT32BIT3_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 12. "SCT0,SCTimer/PWM wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 11. "CT32BIT1,CTIMER 1 wake-up" "0: CT32BIT1_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 10. "CT32BIT0,CTIMER 0 wake-up" "0: CT32BIT0_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 9. "MRT0,MRT wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 8. "UTICK0,UTICK wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 7. "GPIO_INT0_IRQ3,GPIO pin interrupt 3 wake-up" "0: GPIO_INT0_IRQ3_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 6. "GPIO_INT0_IRQ2,GPIO pin interrupt 2 wake-up" "0: GPIO_INT0_IRQ2_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 5. "GPIO_INT0_IRQ1,GPIO pin interrupt 1 wake-up" "0: GPIO_INT0_IRQ1_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 4. "GPIO_INT0_IRQ0,GPIO pin interrupt 0 wake-up" "0: GPIO_INT0_IRQ0_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 3. "GPIO_INTB,Non-secure GPIO interrupt B wake-up" "0: GPIO_INTB_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 2. "GPIO_INTA,Non-secure GPIO interrupt A wake-up" "0: GPIO_INTA_0,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 1. "DMAC0,DMA controller 0 wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
newline
eventfld.long 0x00 0. "WDT0,Watchdog timer 0 wake-up" "0: No effect,1: Clears the STARTEN0 Bit"
group.long 0x6C4++0x03
line.long 0x00 "STARTEN1_CLR,Start Enable 1 clear"
bitfld.long 0x00 31. "FLEXCOMM11,FLEXCOMM 11 peripheral interrupt wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
bitfld.long 0x00 30. "FLEXCOMM10,FLEXCOMM 10 peripheral interrupt wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
bitfld.long 0x00 29. "FLEXCOMM9,FLEXCOMM 9 peripheral interrupt wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
bitfld.long 0x00 28. "FLEXCOMM8,FLEXCOMM 8 peripheral interrupt wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 27. "SHA,Hash-AES wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 26. "PMIC,Wake-up from on-chip PMC or off-chip PMIC" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 25. "CASPER,CASPER co-processor wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 24. "POWERQUAD,POWERQUAD co-processor wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 23. "PUF,PUF wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 22. "DMAC1,DMA controller 1 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 21. "USB_PHYDCD,USB PHY DCD interrupt wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 19. "USB0_NEEDCLK,USB activity wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 16. "SGPIO_INTB,Secure GPIO interrupt B wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 15. "SGPIO_INTA,Secure GPIO interrupt A wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 14. "SDIO1,SDIO01 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 13. "SDIO0,SDIO0 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 12. "FLEXCOMM7,FLEXCOMM7 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 11. "FLEXCOMM6,FLEXCOMM6 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 10. "FLEXSPI,Quad/octal SPI wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 9. "OS_EVENT_TIMER_WU,OS Event Timer wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 8. "CT32BIT4,CTIMER 4 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 7. "CT32BIT2,CTIMER 2 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 6. "GPIO_INT0_IRQ7,GPIO pin interrupt 7 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 5. "GPIO_INT0_IRQ6,GPIO pin interrupt 6 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 4. "GPIO_INT0_IRQ5,GPIO pin interrupt 5 wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 3. "GPIO_INT0_IRQ4,Message Unit wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 2. "MU,Message Unit wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
newline
eventfld.long 0x00 0. "RTC_LITE0_WAKEUP,RTC wake-up" "0: No Effect,1: Clears the STARTEN1 Bit"
group.long 0x6C8++0x03
line.long 0x00 "STARTEN2_CLR,Start Enable 2"
eventfld.long 0x00 2. "FLEXCOMM16,FlexComm 16 interrupt wake-up" "0: No effect,1: Clears the STARTEN2 bit"
newline
eventfld.long 0x00 1. "FLEXCOMM13,FlexComm 13 interrupt wake-up" "0: No effect,1: Clears the STARTEN2 bit"
newline
eventfld.long 0x00 0. "FLEXCOMM12,FlexComm 12 interrupt wake-up" "0: No effect,1: Clears the STARTEN2 bit"
group.long 0x710++0x03
line.long 0x00 "MAINCLKSAFETY,Main Clock Safety"
hexmask.long.word 0x00 0.--15. 1. "DELAY,Main Clock turn on delay for Deep Sleep wake up"
group.long 0x780++0x03
line.long 0x00 "HWWAKE,Hardware Wake"
bitfld.long 0x00 4. "DMAC1WAKE,Wake for DMAC1" "0,1"
newline
bitfld.long 0x00 3. "DMAC0WAKE,Wake for DMAC0" "0,1"
newline
bitfld.long 0x00 2. "DMICWAKE,Wake for Digital Microphone" "0,1"
newline
bitfld.long 0x00 1. "FCWAKE,Wake for FlexComm Interfaces" "0,1"
newline
bitfld.long 0x00 0. "FORCEWAKE,Force peripheral clocking to stay on during deep-sleep mode" "0,1"
group.long 0xE0C++0x03
line.long 0x00 "TEMPSENSORCTL,Temperature Sensor Control"
bitfld.long 0x00 0. "TSSRC,Temperature Sensor Source" "0: ADC Built-in Temperature Sensor,1: PMC Temperature Sensor"
group.long 0xE40++0x03
line.long 0x00 "BOOTSTATELOCK,Boot State Lock"
bitfld.long 0x00 1. "BOOTSTATEHMACLOCK,Boot State HMA Lockout" "0: BOOTSTATEHMAC[0:7] can be changed,1: BOOTSTATEHMAC[0:7] cannot be changed"
newline
bitfld.long 0x00 0. "BOOTSTATESEEDLOCK,Boot State Seed Lockout" "0: BOOTSTATESEED[0:7] can be changed,1: BOOTSTATESEED[0:7] cannot be changed"
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0xE50)++0x03
line.long 0x00 "BOOTSTATESEED[$1],Boot State Seed $1"
hexmask.long 0x00 0.--31. 1. "BOOTSTATESEED,BOOTSTATESEED[0:7]"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0xE70)++0x03
line.long 0x00 "BOOTSTATEHMAC[$1],HMAC of boot state used for attestation $1"
hexmask.long 0x00 0.--31. 1. "BOOTSTATEHMAC,BOOTSTATEHMAC[0:7]"
repeat.end
group.long 0xEF0++0x03
line.long 0x00 "FLEXSPI0PADCTL,FLEXSPI0 Pad Control"
rbitfld.long 0x00 24. "COMPOK,FLEXSPI0 Pad Compensation Circuit Status" "0,1"
newline
rbitfld.long 0x00 20.--23. "NASRCP,FLEXSPI0 Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "NASRCN,FLEXSPI0 Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "COMPEN,Drives FLEXSPI0 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 10. "COMPTQ,Drives FLEXSPI0 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 9. "FREEZE,Drives FLEXSPI0 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 8. "FASTFRZ,Drives FLEXSPI0 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 4.--7. "RASRCP_3_0,Drives FLEXSPI0 Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RASRCN_3_0,Drives FLEXSPI0 Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xEF4++0x03
line.long 0x00 "FLEXSPI1PADCTL,FLEXSPI1 Pad Control"
rbitfld.long 0x00 24. "COMPOK,FLEXSPI1 Pad Compensation Circuit Status" "0,1"
newline
rbitfld.long 0x00 20.--23. "NASRCP_3_0,FLEXSPI1 Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "NASRCN_3_0,FLEXSPI1 Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "COMPEN,Drives FLEXSPI1 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 10. "COMPTQ,Drives FLEXSPI1 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 9. "FREEZE,Drives FLEXSPI1 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 8. "FASTFRZ,Drives FLEXSPI1 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 4.--7. "RASRCP_3_0,Drives FLEXSPI1 Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RASRCN_3_0,Drives FLEXSPI1 Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xEF8++0x03
line.long 0x00 "SDIO0PADCTL,SDIO0 Pad Control"
rbitfld.long 0x00 24. "COMPOK,SDIO0 Pad Compensation Circuit Status" "0,1"
newline
rbitfld.long 0x00 20.--23. "NASRCP,SDIO0 Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "NASRCN,SDIO0 Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "COMPEN,Drives SDIO0 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 10. "COMPTQ,Drives SDIO0 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 9. "FREEZE,Drives SDIO0 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 8. "FASTFRZ,Drives SDIO0 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 4.--7. "RASRCP,Drives SDIO0 Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RASRCN,Drives SDIO0 Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xEFC++0x03
line.long 0x00 "SDIO1PADCTL,SDIO1 Pad Control"
rbitfld.long 0x00 24. "COMPOK,SDIO1 Pad Compensation Circuit Status" "0,1"
newline
rbitfld.long 0x00 20.--23. "NASRCP,SDIO1 Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "NASRCN,SDIO1 Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "COMPEN,Drives SDIO1 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 10. "COMPTQ,Drives SDIO1 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 9. "FREEZE,Drives SDIO1 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 8. "FASTFRZ,Drives SDIO1 Pad Compensation Circuit" "0,1"
newline
bitfld.long 0x00 4.--7. "RASRCP,Drives SDIO1 Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RASRCN,Drives SDIO1 Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF00++0x03
line.long 0x00 "DICEHWREGn,Compound Device Identifier (CDI)"
hexmask.long 0x00 0.--31. 1. "DICEHWREGN,DICE General Purpose 32-Bit Data Register"
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0xF50)++0x03
line.long 0x00 "UUID[$1],UUID $1"
hexmask.long 0x00 0.--31. 1. "UUIDN,UUIDn 32-Bit Data Register"
repeat.end
group.long 0xF80++0x03
line.long 0x00 "AESKEY_SRCSEL,AES Key Source Select"
bitfld.long 0x00 0.--1. "AESKEY_SRCSEL,AES Key Source Select" "0: AESKEY_SRCSEL_0,1: AESKEY_SRCSEL_1,2: AESKEY_SRCSEL_2,3: AESKEY_SRCSEL_3"
group.long 0xF84++0x03
line.long 0x00 "OTFADKEY_SRCSEL,OTFAD Key Source Select"
bitfld.long 0x00 0.--1. "OTFADKEY_SRCSEL,OTFAD Key Source Select" "0: OTFADKEY_SRCSEL_0,1: OTFADKEY_SRCSEL_1,2: OTFADKEY_SRCSEL_2,3: OTFADKEY_SRCSEL_3"
group.long 0xF88++0x03
line.long 0x00 "HASHHWKEYDISABLE,HASH Hardware Key Disable"
hexmask.long 0x00 0.--31. 1. "HASHHWKEYDISABLE,HASH Hardware Key Disable"
group.long 0xFA0++0x03
line.long 0x00 "DBG_LOCKEN,Debug Lock Enable"
bitfld.long 0x00 0.--3. "DBG_LOCKEN,Debug Write Lock the following registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFA4++0x03
line.long 0x00 "DBG_FEATURES,Debug Features"
bitfld.long 0x00 6.--7. "SPNIDEN1,CM33 SPNIDEN Enable Control" "0: SPNIDEN_00,1: SPNIDEN_01,2: SPNIDEN_10,3: SPNIDEN_11"
newline
bitfld.long 0x00 4.--5. "SPIDEN1,CM33 SPID Enable Control" "0: SPIDEN1_00,1: SPIDEN1_01,2: SPIDEN1_10,3: SPIDEN1_11"
newline
bitfld.long 0x00 2.--3. "NIDEN1,CM33 NID Enable Control" "0: NIDEN1_00,1: NIDEN1_01,2: NIDEN1_10,3: NIDEN1_11"
newline
bitfld.long 0x00 0.--1. "DBGEN1,CM33 Debug Enable Control" "0: DBGEN1_00,1: DBGEN1_01,2: DBGEN1_10,3: DBGEN1_11"
group.long 0xFA8++0x03
line.long 0x00 "DBG_FEATURES_DP,Debug Features Duplicate"
bitfld.long 0x00 6.--7. "SPNIDEN1,CM33 SPNIDEN Enable Control" "0: SPNIDEN_00,1: SPNIDEN_01,2: SPNIDEN_10,3: SPNIDEN_11"
newline
bitfld.long 0x00 4.--5. "SPIDEN1,CM33 SPID Enable Control" "0: SPIDEN1_00,1: SPIDEN1_01,2: SPIDEN1_10,3: SPIDEN1_11"
newline
bitfld.long 0x00 2.--3. "NIDEN1,CM33 NID Enable Control" "0: DP_NIDEN1_00,1: DP_NIDEN1_01,2: DP_NIDEN1_10,3: DP_NIDEN1_11"
newline
bitfld.long 0x00 0.--1. "DBGEN1,CM33 Debug Enable Control" "0: DBGEN1_00,1: DBGEN1_01,2: DBGEN1_10,3: DBGEN1_11"
group.long 0xFB4++0x03
line.long 0x00 "CS_PROTCPU0,Code Security for CPU0"
hexmask.long 0x00 0.--31. 1. "CS_PROTCPU0,Controls M33 AP Enable"
group.long 0xFB8++0x03
line.long 0x00 "CS_PROTCPU1,Code Security for CPU1"
hexmask.long 0x00 0.--31. 1. "CS_PROTCPU1,Controls AP Enable"
group.long 0xFC0++0x03
line.long 0x00 "DBG_AUTH_SCRATCH,Debug authorization scratch"
hexmask.long 0x00 0.--31. 1. "DBG_AUTH_SCRATCH,Debug authorization scratch register for S/W"
group.long 0xFD0++0x03
line.long 0x00 "KEY_BLOCK,Key block"
hexmask.long 0x00 0.--31. 1. "KEY_BLOCK,PUF key and data output"
tree.end
tree "SYSCTL1"
base ad:0x40022000
group.long 0x00++0x03
line.long 0x00 "UPDATELCKOUT,Update Clock Lockout"
bitfld.long 0x00 0. "UPDATELCKOUT,Update Clock Lockout" "0: UPDATELCKOUT_0,1: Protected Mode"
group.long 0x10++0x03
line.long 0x00 "MCLKPINDIR,MCLK direction control"
bitfld.long 0x00 0. "MCLKPINDIR,MCLK direction control" "0: I2S MCLK is in input direction,1: I2S MCLK is in the output direction"
group.long 0x30++0x03
line.long 0x00 "DSPNMISRCSEL,DSP NMI source selection"
bitfld.long 0x00 31. "NMIEN,NMI Enable" "0: Disable NMI Interrupt,1: Enable NMI Interrupt"
newline
bitfld.long 0x00 0.--4. "NMISRCSEL,DSP NMI source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 14. (increment 0 1) (increment 0 0x4)
group.long ($2+0x40)++0x03
line.long 0x00 "FCCTRLSEL[$1],Flexcomm control selection $1"
bitfld.long 0x00 24.--25. "DATAOUTSEL,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: Shared Set0 I2S signals,2: Shared Set1 I2S signals,?..."
newline
bitfld.long 0x00 16.--17. "DATAINSEL,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: Shared Set0 I2S signals,2: Shared Set1 I2S signals,?..."
newline
bitfld.long 0x00 8.--9. "WSINSEL,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: Shared Set0 I2S signals,2: Shared Set1 I2S signals,?..."
newline
bitfld.long 0x00 0.--1. "SCKINSEL,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: Shared Set0 I2S signals,2: Shared Set1 I2S signals,?..."
repeat.end
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "SHAREDCTRLSET[$1],Shared control set $1"
bitfld.long 0x00 23. "FC7DATAOUTEN,FLEXCOMM7 DATAOUT Output Enable" "0: FC0DATAOUTEN7_0,1: FC0DATAOUTEN7_1"
newline
bitfld.long 0x00 22. "FC6DATAOUTEN,FLEXCOMM6 DATAOUT Output Enable" "0: FC0DATAOUTEN6_0,1: FC0DATAOUTEN6_1"
newline
bitfld.long 0x00 21. "FC5DATAOUTEN,FLEXCOMM5 DATAOUT Output Enable" "0: FC0DATAOUTEN5_0,1: FC0DATAOUTEN5_1"
newline
bitfld.long 0x00 20. "FC4DATAOUTEN,FLEXCOMM4 DATAOUT Output Enable" "0: FC0DATAOUTEN4_0,1: FC0DATAOUTEN4_1"
newline
bitfld.long 0x00 19. "FC3DATAOUTEN,FLEXCOMM3 DATAOUT Output Enable" "0: FC0DATAOUTEN3_0,1: FC0DATAOUTEN3_1"
newline
bitfld.long 0x00 18. "FC2DATAOUTEN,FLEXCOMM2 DATAOUT Output Enable" "0: FC0DATAOUTEN2_0,1: FC0DATAOUTEN2_1"
newline
bitfld.long 0x00 17. "FC1DATAOUTEN,FLEXCOMM1 DATAOUT Output Enable" "0: FC0DATAOUTEN1_0,1: FC0DATAOUTEN1_1"
newline
bitfld.long 0x00 16. "FC0DATAOUTEN,FLEXCOMM0 DATAOUT Output Enable" "0: FC0DATAOUTEN0_0,1: FC0DATAOUTEN0_1"
newline
bitfld.long 0x00 8.--10. "SHAREDDATASEL,Shared DATA Select" "0: SHAREDWSSEL_0,1: SHAREDDATASEL_1,2: SHAREDDATASEL_2,3: SHAREDDATASEL_3,4: SHAREDDATASEL_4,5: SHAREDDATASEL_5,6: SHAREDDATASEL_6,7: SHAREDDATASEL_7"
newline
bitfld.long 0x00 4.--6. "SHAREDWSSEL,Shared WS Select" "0: SHAREDWSSEL_0,1: SHAREDWSSEL_1,2: SHAREDWSSEL_2,3: SHAREDWSSEL_3,4: SHAREDWSSEL_4,5: SHAREDWSSEL_5,6: SHAREDWSSEL_6,7: SHAREDWSSEL_7"
newline
bitfld.long 0x00 0.--2. "SHAREDSCKSEL,Shared SCK Select" "0: SHAREDSCKSEL_0,1: SHAREDSCKSEL_1,2: SHAREDSCKSEL_2,3: SHAREDSCKSEL_3,4: SHAREDSCKSEL_4,5: SHAREDSCKSEL_5,6: SHAREDSCKSEL_6,7: SHAREDSCKSEL_7"
repeat.end
wgroup.long 0x200++0x03
line.long 0x00 "RXEVPULSEGEN,RX Event Pulse Generator"
bitfld.long 0x00 0. "RXEVPULSEGEN,RX Event Pulse Generator" "0: RXEVPULSEGEN_0,1: Pulse RXEV High for one PSCLK cycle"
tree.end
tree.end
tree "TRNG"
base ad:0x40138000
group.long 0x00++0x03
line.long 0x00 "MCTL,Miscellaneous Control Register"
bitfld.long 0x00 16. "PRGM,Programming Mode Select" "0,1"
rbitfld.long 0x00 13. "TSTOP_OK,TRNG_OK_TO_STOP" "0,1"
newline
bitfld.long 0x00 12. "ERR,Read: Error status" "0,1"
rbitfld.long 0x00 11. "TST_OUT,Read only: Test point inside ring oscillator" "0,1"
newline
rbitfld.long 0x00 10. "ENT_VAL,Read only: Entropy Valid" "0,1"
rbitfld.long 0x00 9. "FCT_VAL,Read only: Frequency Count Valid" "0,1"
newline
rbitfld.long 0x00 8. "FCT_FAIL,Read only: Frequency Count Fail" "0,1"
bitfld.long 0x00 7. "FOR_SCLK,Force System Clock" "0,1"
newline
bitfld.long 0x00 6. "RST_DEF,Reset Defaults" "0,1"
bitfld.long 0x00 5. "TRNG_ACC,TRNG Access Mode" "0,1"
newline
rbitfld.long 0x00 4. "UNUSED4,This bit is unused" "0,1"
bitfld.long 0x00 2.--3. "OSC_DIV,Oscillator Divide" "0: use ring oscillator with no divide,1: use ring oscillator divided-by-2,2: use ring oscillator divided-by-4,3: use ring oscillator divided-by-8"
newline
bitfld.long 0x00 0.--1. "SAMP_MODE,Sample Mode" "0: use Von Neumann data into both Entropy..,1: use raw data into both Entropy shifter and..,2: use Von Neumann data into Entropy shifter,3: undefined/reserved"
group.long 0x04++0x03
line.long 0x00 "SCMISC,Statistical Check Miscellaneous Register"
bitfld.long 0x00 16.--19. "RTY_CT,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "LRUN_MAX,LONG RUN MAX LIMIT"
group.long 0x08++0x03
line.long 0x00 "PKRRNG,Poker Range Register"
hexmask.long.word 0x00 0.--15. 1. "PKR_RNG,Poker Range"
group.long 0x0C++0x03
line.long 0x00 "PKRMAX,Poker Maximum Limit Register"
hexmask.long.tbyte 0x00 0.--23. 1. "PKR_MAX,Poker Maximum Limit"
rgroup.long 0x0C++0x03
line.long 0x00 "PKRSQ,Poker Square Calculation Result Register"
hexmask.long.tbyte 0x00 0.--23. 1. "PKR_SQ,Poker Square Calculation Result"
group.long 0x10++0x03
line.long 0x00 "SDCTL,Seed Control Register"
hexmask.long.word 0x00 16.--31. 1. "ENT_DLY,Entropy Delay"
hexmask.long.word 0x00 0.--15. 1. "SAMP_SIZE,Sample Size"
group.long 0x14++0x03
line.long 0x00 "SBLIM,Sparse Bit Limit Register"
hexmask.long.word 0x00 0.--9. 1. "SB_LIM,Sparse Bit Limit"
rgroup.long 0x14++0x03
line.long 0x00 "TOTSAM,Total Samples Register"
hexmask.long.tbyte 0x00 0.--19. 1. "TOT_SAM,Total Samples"
group.long 0x18++0x03
line.long 0x00 "FRQMIN,Frequency Count Minimum Limit Register"
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_MIN,Frequency Count Minimum Limit"
rgroup.long 0x1C++0x03
line.long 0x00 "FRQCNT,Frequency Count Register"
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_CT,Frequency Count"
group.long 0x1C++0x03
line.long 0x00 "FRQMAX,Frequency Count Maximum Limit Register"
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_MAX,Frequency Counter Maximum Limit"
rgroup.long 0x20++0x03
line.long 0x00 "SCMC,Statistical Check Monobit Count Register"
hexmask.long.word 0x00 0.--15. 1. "MONO_CT,Monobit Count"
group.long 0x20++0x03
line.long 0x00 "SCML,Statistical Check Monobit Limit Register"
hexmask.long.word 0x00 16.--31. 1. "MONO_RNG,Monobit Range"
hexmask.long.word 0x00 0.--15. 1. "MONO_MAX,Monobit Maximum Limit"
rgroup.long 0x24++0x03
line.long 0x00 "SCR1C,Statistical Check Run Length 1 Count Register"
hexmask.long.word 0x00 16.--30. 1. "R1_1_CT,Runs of One Length 1 Count"
hexmask.long.word 0x00 0.--14. 1. "R1_0_CT,Runs of Zero Length 1 Count"
group.long 0x24++0x03
line.long 0x00 "SCR1L,Statistical Check Run Length 1 Limit Register"
hexmask.long.word 0x00 16.--30. 1. "RUN1_RNG,Run Length 1 Range"
hexmask.long.word 0x00 0.--14. 1. "RUN1_MAX,Run Length 1 Maximum Limit"
rgroup.long 0x28++0x03
line.long 0x00 "SCR2C,Statistical Check Run Length 2 Count Register"
hexmask.long.word 0x00 16.--29. 1. "R2_1_CT,Runs of One Length 2 Count"
hexmask.long.word 0x00 0.--13. 1. "R2_0_CT,Runs of Zero Length 2 Count"
group.long 0x28++0x03
line.long 0x00 "SCR2L,Statistical Check Run Length 2 Limit Register"
hexmask.long.word 0x00 16.--29. 1. "RUN2_RNG,Run Length 2 Range"
hexmask.long.word 0x00 0.--13. 1. "RUN2_MAX,Run Length 2 Maximum Limit"
rgroup.long 0x2C++0x03
line.long 0x00 "SCR3C,Statistical Check Run Length 3 Count Register"
hexmask.long.word 0x00 16.--28. 1. "R3_1_CT,Runs of Ones Length 3 Count"
hexmask.long.word 0x00 0.--12. 1. "R3_0_CT,Runs of Zeroes Length 3 Count"
group.long 0x2C++0x03
line.long 0x00 "SCR3L,Statistical Check Run Length 3 Limit Register"
hexmask.long.word 0x00 16.--28. 1. "RUN3_RNG,Run Length 3 Range"
hexmask.long.word 0x00 0.--12. 1. "RUN3_MAX,Run Length 3 Maximum Limit"
rgroup.long 0x30++0x03
line.long 0x00 "SCR4C,Statistical Check Run Length 4 Count Register"
hexmask.long.word 0x00 16.--27. 1. "R4_1_CT,Runs of One Length 4 Count"
hexmask.long.word 0x00 0.--11. 1. "R4_0_CT,Runs of Zero Length 4 Count"
group.long 0x30++0x03
line.long 0x00 "SCR4L,Statistical Check Run Length 4 Limit Register"
hexmask.long.word 0x00 16.--27. 1. "RUN4_RNG,Run Length 4 Range"
hexmask.long.word 0x00 0.--11. 1. "RUN4_MAX,Run Length 4 Maximum Limit"
rgroup.long 0x34++0x03
line.long 0x00 "SCR5C,Statistical Check Run Length 5 Count Register"
hexmask.long.word 0x00 16.--26. 1. "R5_1_CT,Runs of One Length 5 Count"
hexmask.long.word 0x00 0.--10. 1. "R5_0_CT,Runs of Zero Length 5 Count"
group.long 0x34++0x03
line.long 0x00 "SCR5L,Statistical Check Run Length 5 Limit Register"
hexmask.long.word 0x00 16.--26. 1. "RUN5_RNG,Run Length 5 Range"
hexmask.long.word 0x00 0.--10. 1. "RUN5_MAX,Run Length 5 Maximum Limit"
rgroup.long 0x38++0x03
line.long 0x00 "SCR6PC,Statistical Check Run Length 6+ Count Register"
hexmask.long.word 0x00 16.--26. 1. "R6P_1_CT,Runs of One Length 6+ Count"
hexmask.long.word 0x00 0.--10. 1. "R6P_0_CT,Runs of Zero Length 6+ Count"
group.long 0x38++0x03
line.long 0x00 "SCR6PL,Statistical Check Run Length 6+ Limit Register"
hexmask.long.word 0x00 16.--26. 1. "RUN6P_RNG,Run Length 6+ Range"
hexmask.long.word 0x00 0.--10. 1. "RUN6P_MAX,Run Length 6+ Maximum Limit"
rgroup.long 0x3C++0x03
line.long 0x00 "STATUS,Status Register"
bitfld.long 0x00 16.--19. "RETRY_CT,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "TFMB,Test Fail Mono Bit" "0,1"
newline
bitfld.long 0x00 14. "TFP,Test Fail Poker" "0,1"
bitfld.long 0x00 13. "TFLR,Test Fail Long Run" "0,1"
newline
bitfld.long 0x00 12. "TFSB,Test Fail Sparse Bit" "0,1"
bitfld.long 0x00 11. "TF6PBR1,Test Fail 6 Plus Bit Run Sampling 1s" "0,1"
newline
bitfld.long 0x00 10. "TF6PBR0,Test Fail 6 Plus Bit Run Sampling 0s" "0,1"
bitfld.long 0x00 9. "TF5BR1,Test Fail 5-Bit Run Sampling 1s" "0,1"
newline
bitfld.long 0x00 8. "TF5BR0,Test Fail 5-Bit Run Sampling 0s" "0,1"
bitfld.long 0x00 7. "TF4BR1,Test Fail 4-Bit Run Sampling 1s" "0,1"
newline
bitfld.long 0x00 6. "TF4BR0,Test Fail 4-Bit Run Sampling 0s" "0,1"
bitfld.long 0x00 5. "TF3BR1,Test Fail 3-Bit Run Sampling 1s" "0,1"
newline
bitfld.long 0x00 4. "TF3BR0,Test Fail 3-Bit Run Sampling 0s" "0,1"
bitfld.long 0x00 3. "TF2BR1,Test Fail 2-Bit Run Sampling 1s" "0,1"
newline
bitfld.long 0x00 2. "TF2BR0,Test Fail 2-Bit Run Sampling 0s" "0,1"
bitfld.long 0x00 1. "TF1BR1,Test Fail 1-Bit Run Sampling 1s" "0,1"
newline
bitfld.long 0x00 0. "TF1BR0,Test Fail 1-Bit Run Sampling 0s" "0,1"
repeat 16. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x40)++0x03
line.long 0x00 "ENT[$1],Entropy Read Register $1"
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
repeat.end
rgroup.long 0x80++0x03
line.long 0x00 "PKRCNT10,Statistical Check Poker Count 1 and 0 Register"
hexmask.long.word 0x00 16.--31. 1. "PKR_1_CT,Poker 1h Count"
hexmask.long.word 0x00 0.--15. 1. "PKR_0_CT,Poker 0h Count"
rgroup.long 0x84++0x03
line.long 0x00 "PKRCNT32,Statistical Check Poker Count 3 and 2 Register"
hexmask.long.word 0x00 16.--31. 1. "PKR_3_CT,Poker 3h Count"
hexmask.long.word 0x00 0.--15. 1. "PKR_2_CT,Poker 2h Count"
rgroup.long 0x88++0x03
line.long 0x00 "PKRCNT54,Statistical Check Poker Count 5 and 4 Register"
hexmask.long.word 0x00 16.--31. 1. "PKR_5_CT,Poker 5h Count"
hexmask.long.word 0x00 0.--15. 1. "PKR_4_CT,Poker 4h Count"
rgroup.long 0x8C++0x03
line.long 0x00 "PKRCNT76,Statistical Check Poker Count 7 and 6 Register"
hexmask.long.word 0x00 16.--31. 1. "PKR_7_CT,Poker 7h Count"
hexmask.long.word 0x00 0.--15. 1. "PKR_6_CT,Poker 6h Count"
rgroup.long 0x90++0x03
line.long 0x00 "PKRCNT98,Statistical Check Poker Count 9 and 8 Register"
hexmask.long.word 0x00 16.--31. 1. "PKR_9_CT,Poker 9h Count"
hexmask.long.word 0x00 0.--15. 1. "PKR_8_CT,Poker 8h Count"
rgroup.long 0x94++0x03
line.long 0x00 "PKRCNTBA,Statistical Check Poker Count B and A Register"
hexmask.long.word 0x00 16.--31. 1. "PKR_B_CT,Poker Bh Count"
hexmask.long.word 0x00 0.--15. 1. "PKR_A_CT,Poker Ah Count"
rgroup.long 0x98++0x03
line.long 0x00 "PKRCNTDC,Statistical Check Poker Count D and C Register"
hexmask.long.word 0x00 16.--31. 1. "PKR_D_CT,Poker Dh Count"
hexmask.long.word 0x00 0.--15. 1. "PKR_C_CT,Poker Ch Count"
rgroup.long 0x9C++0x03
line.long 0x00 "PKRCNTFE,Statistical Check Poker Count F and E Register"
hexmask.long.word 0x00 16.--31. 1. "PKR_F_CT,Poker Fh Count"
hexmask.long.word 0x00 0.--15. 1. "PKR_E_CT,Poker Eh Count"
group.long 0xA0++0x03
line.long 0x00 "SEC_CFG,Security Configuration Register"
bitfld.long 0x00 2. "UNUSED2,This bit is unused" "0,1"
bitfld.long 0x00 1. "NO_PRGM,If set the TRNG registers cannot be programmed regardless of the TRNG access mode in the TRNG Miscellaneous Control Register" "0: Programability of registers controlled only..,1: Overides Miscellaneous Control Register.."
newline
bitfld.long 0x00 0. "UNUSED0,This bit is unused" "0,1"
group.long 0xA4++0x03
line.long 0x00 "INT_CTRL,Interrupt Control Register"
hexmask.long 0x00 3.--31. 1. "UNUSED,Reserved but writeable"
bitfld.long 0x00 2. "FRQ_CT_FAIL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
newline
bitfld.long 0x00 1. "ENT_VAL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
bitfld.long 0x00 0. "HW_ERR,Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted" "0: Corresponding bit of INT_STATUS register..,1: Corresponding bit of INT_STATUS register active"
group.long 0xA8++0x03
line.long 0x00 "INT_MASK,Mask Register"
bitfld.long 0x00 2. "FRQ_CT_FAIL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
bitfld.long 0x00 1. "ENT_VAL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
newline
bitfld.long 0x00 0. "HW_ERR,Bit position that can be cleared or set to enable the corresponding bit of INT_STATUS to show interupt status" "0: Corresponding interrupt of INT_STATUS is masked,1: Corresponding bit of INT_STATUS is active"
rgroup.long 0xAC++0x03
line.long 0x00 "INT_STATUS,Interrupt Status Register"
bitfld.long 0x00 2. "FRQ_CT_FAIL,Read only: Frequency Count Fail" "0: No hardware nor self test frequency errors,1: The frequency counter has detected a failure"
bitfld.long 0x00 1. "ENT_VAL,Read only: Entropy Valid" "0: Busy generation entropy,1: TRNG can be stopped and entropy is valid if"
newline
bitfld.long 0x00 0. "HW_ERR,Read: Error status" "0: HW_ERR_NO,1: error detected"
rgroup.long 0xF0++0x03
line.long 0x00 "VID1,Version ID Register (MS)"
hexmask.long.word 0x00 16.--31. 1. "IP_ID,Shows the IP ID"
hexmask.long.byte 0x00 8.--15. 1. "MAJ_REV,Shows the IP's Major revision of the TRNG"
newline
hexmask.long.byte 0x00 0.--7. 1. "MIN_REV,Shows the IP's Minor revision of the TRNG"
rgroup.long 0xF4++0x03
line.long 0x00 "VID2,Version ID Register (LS)"
hexmask.long.byte 0x00 24.--31. 1. "ERA,Shows the compile options for the TRNG"
hexmask.long.byte 0x00 16.--23. 1. "INTG_OPT,Shows the integration options for the TRNG"
newline
hexmask.long.byte 0x00 8.--15. 1. "ECO_REV,Shows the IP's ECO revision of the TRNG"
hexmask.long.byte 0x00 0.--7. 1. "CONFIG_OPT,Shows the IP's Configuaration options for the TRNG"
tree.end
tree "USART (Flexcomm USART)"
repeat 14. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.) (list ad:0x40106000 ad:0x40107000 ad:0x40108000 ad:0x40109000 ad:0x40122000 ad:0x40123000 ad:0x40124000 ad:0x40125000 ad:0x40209000 ad:0x4020A000 ad:0x4020B000 ad:0x4020C000 ad:0x4020D000 ad:0x4020E000)
tree "USART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration"
bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED"
bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED"
newline
bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High"
bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485"
newline
bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode"
bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master"
newline
bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge"
bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
newline
bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled"
bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED"
bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits"
newline
bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY"
bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..."
newline
bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control"
bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR"
newline
bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled"
newline
bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED"
bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status"
eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1"
eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
eventfld.long 0x00 12. "START,Start" "0,1"
eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1"
newline
rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1"
rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle"
newline
eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1"
rbitfld.long 0x00 4. "CTS,CTS value" "0,1"
newline
rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data"
rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status"
bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.."
bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected"
newline
bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.."
bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.."
newline
bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.."
bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE"
newline
bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.."
bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.."
newline
bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.."
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear"
bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1"
bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1"
newline
bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1"
bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1"
newline
bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1"
bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1"
newline
bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1"
bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1"
newline
bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator"
hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value"
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt Status"
bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1"
bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1"
bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1"
newline
bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1"
bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1"
newline
bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication"
bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.."
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address Register for Automatic Address Matching"
hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO Configuration"
bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop"
bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied"
newline
bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied"
bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.."
newline
bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.."
rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3"
newline
bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO Status"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.."
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt"
bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.."
newline
bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.."
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable"
bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.."
bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.."
newline
bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear"
bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt"
bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt"
newline
bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt"
bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING"
bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING"
bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO Write Data"
hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO Read Data"
bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1"
bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1"
hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1"
bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1"
hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO Size"
bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral Identification"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture"
tree.end
repeat.end
tree.end
tree "USBHSD (USB2.0 HS Device Controller)"
base ad:0x40144000
group.long 0x00++0x03
line.long 0x00 "DEVCMDSTAT,USB Device Command/Status"
bitfld.long 0x00 29.--31. "PHY_TEST_MODE,PHY test mode" "0: Test mode disabled,1: PHY_TEST_MODE_1,2: PHY_TEST_MODE_2,3: PHY_TEST_MODE_3,4: PHY_TEST_MODE_4,5: Test_Force_Enable,?..."
rbitfld.long 0x00 28. "VBUS_DEBOUNCED,VBUS detect" "0,1"
newline
eventfld.long 0x00 26. "DRES_C,Device status - reset change" "0,1"
eventfld.long 0x00 25. "DSUS_C,Device status - suspend change" "0,1"
newline
eventfld.long 0x00 24. "DCON_C,Device status - connect change" "0,1"
rbitfld.long 0x00 22.--23. "SPEED,This field indicates the speed at which the device operates" "?,1: Full-speed,2: High-speed,?..."
newline
bitfld.long 0x00 20. "LPM_REWP,LPM Remote Wake-up Enabled by USB host" "0,1"
bitfld.long 0x00 19. "LPM_SUS,Device status - LPM Suspend" "0: Software can only write a 0 to this bit when..,1: When the device is in the LPM suspended state.."
newline
bitfld.long 0x00 17. "DSUS,Device status suspend" "0: When the device is not connected or not..,1: It is set to 1 when the device has not seen.."
bitfld.long 0x00 16. "DCON,Device status - connect" "0,1"
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bitfld.long 0x00 15. "INTONNAK_CI,Interrupt on NAK for interrupt and bulk OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
bitfld.long 0x00 14. "INTONNAK_CO,Interrupt on NAK for interrupt and bulk OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
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bitfld.long 0x00 13. "INTONNAK_AI,Interrupt on NAK for interrupt and bulk IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
bitfld.long 0x00 12. "INTONNAK_AO,Interrupt on NAK for interrupt and bulk OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
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bitfld.long 0x00 11. "LPM_SUP,LPM Support" "0: LPM not supported,1: LPM supported"
bitfld.long 0x00 10. "FORCE_VBUS,Force VBUS" "0,1"
newline
bitfld.long 0x00 9. "FORCE_NEEDCLK,Force the NEEDCLK output to always be on" "0: USB_NEEDCLK has normal function,1: USB_NEEDCLK always 1"
bitfld.long 0x00 8. "SETUP,SETUP token received" "0,1"
newline
bitfld.long 0x00 7. "DEV_EN,USB device enable" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "DEV_ADDR,USB Device Address"
group.long 0x04++0x03
line.long 0x00 "INFO,USB Info"
hexmask.long.byte 0x00 24.--31. 1. "MAJREV,Major revision"
hexmask.long.byte 0x00 16.--23. 1. "MINREV,Minor revision"
newline
bitfld.long 0x00 11.--14. "ERR_CODE,The error code which last occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "FRAME_NR,Frame number"
group.long 0x08++0x03
line.long 0x00 "EPLISTSTART,USB EP Command/Status List Start Address"
hexmask.long.word 0x00 20.--31. 1. "EP_LIST_FIXED,Fixed portion of the USB EP Command/Status List address"
hexmask.long.word 0x00 8.--19. 1. "EP_LIST_PRG,Programmable portion of the USB EP Command/Status List address"
group.long 0x0C++0x03
line.long 0x00 "DATABUFSTART,USB Data Buffer List Start Address"
hexmask.long.word 0x00 18.--31. 1. "DA_BUF,Programmable portion of the the data buffer start address"
hexmask.long.tbyte 0x00 0.--17. 1. "DA_BUF_FIXED,Fixed portion of the data buffer start address"
group.long 0x10++0x03
line.long 0x00 "LPM,USB Link Power Management"
bitfld.long 0x00 8. "DATA_PENDING,Data pending" "0,1"
bitfld.long 0x00 4.--7. "HIRD_SW,Host Initiated Resume Duration - SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "HIRD_HW,Host Initiated Resume Duration - HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "EPSKIP,USB Endpoint Skip"
hexmask.long.word 0x00 0.--11. 1. "SKIP,Endpoint skip"
group.long 0x18++0x03
line.long 0x00 "EPINUSE,USB Endpoint Buffer in use"
hexmask.long.word 0x00 2.--11. 1. "BUF,Buffer in use"
group.long 0x1C++0x03
line.long 0x00 "EPBUFCFG,USB Endpoint Buffer Configuration"
hexmask.long.word 0x00 2.--11. 1. "BUF_SB,Buffer in use"
group.long 0x20++0x03
line.long 0x00 "INTSTAT,USB Interrupt Status"
bitfld.long 0x00 31. "DEV_INT,Device status interrupt" "0,1"
bitfld.long 0x00 30. "FRAME_INT,Frame interrupt" "0,1"
newline
eventfld.long 0x00 11. "EP5IN,Control EP5 IN direction" "0,1"
eventfld.long 0x00 10. "EP5OUT,Control EP5 OUT direction" "0,1"
newline
eventfld.long 0x00 9. "EP4IN,Control EP4 IN direction" "0,1"
eventfld.long 0x00 8. "EP4OUT,Control EP4 OUT direction" "0,1"
newline
eventfld.long 0x00 7. "EP3IN,Control EP3 IN direction" "0,1"
eventfld.long 0x00 6. "EP3OUT,Control EP3 OUT direction" "0,1"
newline
eventfld.long 0x00 5. "EP2IN,Control EP2 IN direction" "0,1"
eventfld.long 0x00 4. "EP2OUT,Control EP2 OUT direction" "0,1"
newline
eventfld.long 0x00 3. "EP1IN,Control EP1 IN direction" "0,1"
eventfld.long 0x00 2. "EP1OUT,Control EP1 OUT direction" "0,1"
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eventfld.long 0x00 1. "EP0IN,Control EP0 IN direction" "0,1"
eventfld.long 0x00 0. "EP0OUT,Control EP0 OUT direction" "0,1"
group.long 0x24++0x03
line.long 0x00 "INTEN,USB Interrupt Enable"
bitfld.long 0x00 31. "DEV_INT_EN,Device status interrupt" "0,1"
bitfld.long 0x00 30. "FRAME_INT_EN,Frame interrupt" "0,1"
newline
hexmask.long.word 0x00 0.--11. 1. "EP_INT_EN,End Point Interrupt Enable"
group.long 0x28++0x03
line.long 0x00 "INTSETSTAT,USB Set Interrupt Status"
bitfld.long 0x00 31. "DEV_SET_INT,Device status interrupt" "0,1"
bitfld.long 0x00 30. "FRAME_SET_INT,Frame interrupt" "0,1"
newline
hexmask.long.word 0x00 0.--11. 1. "EP_SET_INT,End Point Set Interrupt Enable"
rgroup.long 0x34++0x03
line.long 0x00 "EPTOGGLE,USB Endpoint Toggle"
hexmask.long 0x00 0.--29. 1. "TOGGLE,Endpoint data toggle"
tree.end
tree "USBHSDCD (USBDCD)"
base ad:0x4013B800
group.long 0x00++0x03
line.long 0x00 "CONTROL,Control register"
bitfld.long 0x00 25. "SR,Software Reset" "0: Do not perform a software reset,1: Perform a software reset"
bitfld.long 0x00 24. "START,Start Change Detection Sequence" "0: Do not start the sequence,1: Initiate the charger detection sequence"
newline
bitfld.long 0x00 17. "BC12,BC12" "0: Compatible with BC1.1 (default),1: Compatible with BC1.2"
bitfld.long 0x00 16. "IE,Interrupt Enable" "0: Disable interrupts to the system,1: Enable interrupts to the system"
newline
rbitfld.long 0x00 8. "IF,Interrupt Flag" "0: No interrupt is pending,1: An interrupt is pending"
bitfld.long 0x00 0. "IACK,Interrupt Acknowledge" "0: Do not clear the interrupt,1: Clear the IF bit (interrupt flag)"
group.long 0x04++0x03
line.long 0x00 "CLOCK,Clock register"
hexmask.long.word 0x00 2.--11. 1. "CLOCK_SPEED,Numerical Value of Clock Speed in Binary"
bitfld.long 0x00 0. "CLOCK_UNIT,Unit of Measurement Encoding for Clock Speed" "0: kHz Speed (between 1 kHz and 1023 kHz),1: MHz Speed (between 1 MHz and 1023 MHz)"
rgroup.long 0x08++0x03
line.long 0x00 "STATUS,Status register"
bitfld.long 0x00 22. "ACTIVE,Active Status Indicator" "0: The sequence is not running,1: The sequence is running"
bitfld.long 0x00 21. "TO,Timeout Flag" "0: The detection sequence has not been running..,1: It has been over 1 s since the data pin.."
newline
bitfld.long 0x00 20. "ERR,Error Flag" "0: No sequence errors,1: Error in the detection sequence"
bitfld.long 0x00 18.--19. "SEQ_STAT,Charger Detection Sequence Status" "0: The module is either not enabled or the..,1: Data pin contact detection is complete,2: Charging port detection is complete,3: Charger type detection is complete"
newline
bitfld.long 0x00 16.--17. "SEQ_RES,Charger Detection Sequence Results" "0: No results to report,1: Attached to an SDP,2: Attached to a charging port,3: Attached to a DCP"
group.long 0x0C++0x03
line.long 0x00 "SIGNAL_OVERRIDE,Signal Override Register"
bitfld.long 0x00 0.--1. "PS,Phase Selection" "0: No overrides,?,2: Enables VDP_SRC voltage source for the USB_DP..,?..."
group.long 0x10++0x03
line.long 0x00 "TIMER0,TIMER0 register"
hexmask.long.word 0x00 16.--25. 1. "TSEQ_INIT,Sequence Initiation Time"
hexmask.long.word 0x00 0.--11. 1. "TUNITCON,Unit Connection Timer Elapse (in ms)"
group.long 0x14++0x03
line.long 0x00 "TIMER1,TIMER1 register"
hexmask.long.word 0x00 16.--25. 1. "TDCD_DBNC,Time Period to Debounce D+ Signal"
hexmask.long.word 0x00 0.--9. 1. "TVDPSRC_ON,Time Period Comparator Enabled"
group.long 0x18++0x03
line.long 0x00 "TIMER2_BC11,TIMER2_BC11 register"
hexmask.long.word 0x00 16.--25. 1. "TVDPSRC_CON,Time Period Before Enabling D+ Pullup"
bitfld.long 0x00 0.--3. "CHECK_DM,Time Before Check of D- Line" "?,1: 1ms - 15ms,2: 1ms - 15ms,3: 1ms - 15ms,4: 1ms - 15ms,5: 1ms - 15ms,6: 1ms - 15ms,7: 1ms - 15ms,8: 1ms - 15ms,9: 1ms - 15ms,10: 1ms - 15ms,?..."
group.long 0x18++0x03
line.long 0x00 "TIMER2_BC12,TIMER2_BC12 register"
hexmask.long.word 0x00 16.--25. 1. "TWAIT_AFTER_PRD,TWAIT_AFTER_PRD"
hexmask.long.word 0x00 0.--9. 1. "TVDMSRC_ON,TVDMSRC_ON"
tree.end
tree "USBHSH (USB2.0 HS Host Controller)"
base ad:0x40145000
rgroup.long 0x00++0x03
line.long 0x00 "CAPLENGTH_CHIPID,Version ID Register"
hexmask.long.word 0x00 16.--31. 1. "CHIPID,Chip identification"
hexmask.long.byte 0x00 0.--7. 1. "CAPLENGTH,Capability Length"
rgroup.long 0x04++0x03
line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters"
bitfld.long 0x00 16. "P_INDICATOR,Port Indicator Control" "0,1"
bitfld.long 0x00 4. "PPC,Port Power Control" "0,1"
newline
bitfld.long 0x00 0.--3. "N_PORTS,Number of Physical downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "HCCPARAMS,INT PTD Base Address"
bitfld.long 0x00 17. "LPMC,Link Power Management Capability" "0,1"
group.long 0x0C++0x03
line.long 0x00 "FLADJ_FRINDEX,Frame Length Adjustment"
hexmask.long.word 0x00 16.--29. 1. "FRINDEX,Frame Index"
bitfld.long 0x00 0.--5. "FLADJ,Frame Length Timing Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "ATL_PTD_BASE_ADDRESS,ATL PTD Base Address"
hexmask.long.tbyte 0x00 9.--31. 1. "ATL_BASE,Start of ATL list"
bitfld.long 0x00 4.--8. "ATL_CUR,Current PTD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "ISO_PTD_BASE_ADDRESS,ISO PTD Base Address"
hexmask.long.tbyte 0x00 10.--31. 1. "ISO_BASE,Start of ISO PTD list"
bitfld.long 0x00 5.--9. "ISO_FIRST,First PTD in the ISO list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x03
line.long 0x00 "INT_PTD_BASE_ADDRESS,INT PTD Base Address"
hexmask.long.tbyte 0x00 10.--31. 1. "INT_BASE,Start of INT PTD list"
bitfld.long 0x00 5.--9. "INT_FIRST,First PTD in the INT list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x03
line.long 0x00 "DATA_PAYLOAD_BASE_ADDRESS,DATA PAYLOAD Base Address"
hexmask.long.word 0x00 16.--31. 1. "DAT_BASE,Data Payload Section Base Address"
group.long 0x20++0x03
line.long 0x00 "USBCMD,USB Command"
bitfld.long 0x00 28. "LPM_RWU,Remote wake up" "0,1"
bitfld.long 0x00 24.--27. "HIRD,Host-Initiated Resume Duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10. "INT_EN,INT List enabled" "0,1"
bitfld.long 0x00 9. "ISO_EN,ISO List enabled" "0,1"
newline
bitfld.long 0x00 8. "ATL_EN,ATL List enabled" "0,1"
bitfld.long 0x00 7. "LHCR,Light Host Controller Reset" "0,1"
newline
bitfld.long 0x00 2.--3. "FLS,Frame List Size" "0: 1024 elements,1: 512 elements,2: 256 elements,?..."
bitfld.long 0x00 1. "HCRESET,Host Controller Reset" "0,1"
newline
bitfld.long 0x00 0. "RS,Run/Stop" "0: DISABLE,1: ENABLE"
group.long 0x24++0x03
line.long 0x00 "USBSTS,USB Interrupt Status"
eventfld.long 0x00 19. "SOF_IRQ,SOF Interrupt Request" "0,1"
eventfld.long 0x00 18. "INT_IRQ,INT Interrupt Request" "0: No INT PTD event occurred,1: INT PTD event occurred"
newline
eventfld.long 0x00 17. "ISO_IRQ,ISO Interrupt Request" "0: No ISO PTD event occurred,1: ISO PTD event occurred"
eventfld.long 0x00 16. "ATL_IRQ,ATL Interrupt Request Interrupt Request" "0: No ATL PTD event occurred,1: ATL PTD event occurred"
newline
bitfld.long 0x00 3. "FLR,Frame List Rollover Interrupt Request" "0,1"
bitfld.long 0x00 2. "PCD,Port Change Detect Interrupt Request" "0: DISABLE,1: ENABLE"
group.long 0x28++0x03
line.long 0x00 "USBINTR,USB Interrupt Status"
eventfld.long 0x00 19. "SOF_E,SOF Interrupt Request" "0,1"
eventfld.long 0x00 18. "INT_IRQ_E,INT Interrupt Enable" "0: DISABLE,1: ENABLE"
newline
eventfld.long 0x00 17. "ISO_IRQ_E,ISO Interrupt Enable" "0: DISABLE,1: ENABLE"
eventfld.long 0x00 16. "ATL_IRQ_E,ATL Interrupt Enable" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 3. "FLRE,Frame List Rollover Interrupt Enable" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 2. "PCDE,Port Change Detect Interrupt Enable" "0: DISABLE,1: ENABLE"
group.long 0x2C++0x03
line.long 0x00 "PORTSC1,Port Status and Control"
hexmask.long.byte 0x00 25.--31. 1. "DEV_ADD,Device Address for LPM tokens"
rbitfld.long 0x00 23.--24. "SUS_STAT,Suspend Status" "0: State transition was successful (ACK),1: Device was unable to enter the L1 state at..,2: Device does not support the L1 state (STALL),3: Timeout/Error - Device failed to respond or.."
newline
bitfld.long 0x00 22. "WOO,Wake on overcurrent enable" "0,1"
rbitfld.long 0x00 20.--21. "PSPD,Port Speed" "?,1: Full-speed,2: High-speed,?..."
newline
bitfld.long 0x00 16.--19. "PTC,Port Test Control" "0: Test mode not enabled,1: Test J_STATE,2: Test K_STATE,3: TEST SE0_NAK,4: Test_Packet,5: Test Force_Enable,?..."
bitfld.long 0x00 14.--15. "PIC,Port Indicator Control" "0: Port Indicators are off,1: ENABLE1,2: ENABLE2,3: Undefined"
newline
bitfld.long 0x00 12. "PP,Port Power" "0,1"
rbitfld.long 0x00 10.--11. "LS,Line Status" "0,1,2,3"
newline
bitfld.long 0x00 9. "SUS_L1,Suspend using L1" "0: Suspend using L2,1: Suspend using L1"
bitfld.long 0x00 8. "PR,Port Reset" "0: Port is not in the reset state,1: Port is in the reset state"
newline
bitfld.long 0x00 7. "SUSP,Suspend" "0: Enabled port is not suspended,1: Enabled port is in the L1 or L2 suspend state"
bitfld.long 0x00 6. "FPR,Force Port Resume" "0: No Resume (K-state) detected or driven on the..,1: Resume (K-state) detected or driven on the port"
newline
eventfld.long 0x00 5. "OCC,Over-current active" "0: OCA value has not changed,1: OCA value has changed"
rbitfld.long 0x00 4. "OCA,Over-current active" "0: Port does not have an over-current condition,1: Port has an over-current condition"
newline
eventfld.long 0x00 3. "PEDC,Port Enabled/Disabled Change" "0: PED value has not changed,1: PED value has changed"
bitfld.long 0x00 2. "PED,Port Enabled/Disabled" "0: Port Disabled,1: Port Enabled"
newline
eventfld.long 0x00 1. "CSC,Connect Status Change" "0: CCS value has not changed,1: CCS value has changed"
rbitfld.long 0x00 0. "CCS,Current Connect Status" "0: No Device is present,1: Device is present"
group.long 0x30++0x03
line.long 0x00 "ATL_DONE,ATL PTD Done Map"
hexmask.long 0x00 0.--31. 1. "ATL_DONE,ATL Done"
group.long 0x34++0x03
line.long 0x00 "ATL_SKIP,ATL PTD Skip Map"
hexmask.long 0x00 0.--31. 1. "ATL_SKIP,ATL PTD Skip Map"
group.long 0x38++0x03
line.long 0x00 "ISO_DONE,ISO PTD Done Map"
hexmask.long 0x00 0.--31. 1. "ISO_DONE,ISO Done"
group.long 0x3C++0x03
line.long 0x00 "ISO_SKIP,ISO PTD Skip Map"
hexmask.long 0x00 0.--31. 1. "ISO_SKIP,ISO Skip"
group.long 0x40++0x03
line.long 0x00 "INT_DONE,INT PTD Done Map"
hexmask.long 0x00 0.--31. 1. "INT_DONE,INT Done"
group.long 0x44++0x03
line.long 0x00 "INT_SKIP,INT PTD Skip Map"
hexmask.long 0x00 0.--31. 1. "INT_SKIP,INT Skip"
group.long 0x48++0x03
line.long 0x00 "LAST_PTD,Last PTD in use"
eventfld.long 0x00 16.--20. "INT_LAST,Last PTD in INT list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
eventfld.long 0x00 8.--12. "ISO_LAST,Last PTD in ISO list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "ATL_LAST,Last PTD in ATL list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x50++0x03
line.long 0x00 "PORT_MODE,Port Mode"
bitfld.long 0x00 16. "DEV_ENABLE,If this bit is set to one the port will behave as a USB device" "0,1"
tree.end
tree "USBPHY (USB2.0 HS PHY)"
base ad:0x4013B000
group.long 0x00++0x03
line.long 0x00 "PWD,Power Down"
bitfld.long 0x00 20. "RXPWDRX,Power down USB PHY receiver except the FS differential" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
newline
bitfld.long 0x00 19. "RXPWDDIFF,Power down USB HS differential receiver" "0: Normal operation,1: Power down the USB high-speed differential.."
newline
bitfld.long 0x00 18. "RXPWD1PT1,Power down USB FS differential receiver" "0: Normal operation,1: Power down the USB full-speed differential.."
newline
bitfld.long 0x00 17. "RXPWDENV,Power down USB HS receiver envelope detector" "0: Normal operation,1: Power down the USB high-speed receiver.."
newline
bitfld.long 0x00 12. "TXPWDV2I,Power down USB PHY V-I converter and current mirror" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
newline
bitfld.long 0x00 11. "TXPWDIBIAS,Power down USB PHY current bias block" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
newline
bitfld.long 0x00 10. "TXPWDFS,Power down USB FS drivers" "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x04++0x03
line.long 0x00 "PWD_SET,Power Down Register Set"
bitfld.long 0x00 20. "RXPWDRX,Power down USB PHY receiver except the FS differential" "0: No effect,1: Sets the corresponding PWD bit"
newline
bitfld.long 0x00 19. "RXPWDDIFF,Power down USB HS differential receiver" "0: No effect,1: Sets the corresponding PWD bit"
newline
bitfld.long 0x00 18. "RXPWD1PT1,Power down USB FS differential receiver" "0: No effect,1: Sets the corresponding PWD bit"
newline
bitfld.long 0x00 17. "RXPWDENV,Power down USB HS receiver envelope detector" "0: No effect,1: Sets the corresponding PWD bit"
newline
bitfld.long 0x00 12. "TXPWDV2I,Power down USB PHY V-I converter and current mirror" "0: No effect,1: Sets the corresponding PWD bit"
newline
bitfld.long 0x00 11. "TXPWDIBIAS,Power down USB PHY current bias block" "0: No effect,1: Sets the corresponding PWD bit"
newline
bitfld.long 0x00 10. "TXPWDFS,Power down USB FS drivers" "0: No effect,1: Sets the corresponding PWD bit"
group.long 0x08++0x03
line.long 0x00 "PWD_CLR,Power Down Register Clear"
bitfld.long 0x00 20. "RXPWDRX,Power down USB PHY receiver except the FS differential" "0: No effect,1: Clears the corresponding PWD bit"
newline
bitfld.long 0x00 19. "RXPWDDIFF,Power down USB HS differential receiver" "0: No effect,1: Clears the corresponding PWD bit"
newline
bitfld.long 0x00 18. "RXPWD1PT1,Power down USB FS differential receiver" "0: No effect,1: Clears the corresponding PWD bit"
newline
bitfld.long 0x00 17. "RXPWDENV,Power down USB HS receiver envelope detector" "0: No effect,1: Clears the corresponding PWD bit"
newline
bitfld.long 0x00 12. "TXPWDV2I,Power down USB PHY V-I converter and current mirror" "0: No effect,1: Clears the corresponding PWD bit"
newline
bitfld.long 0x00 11. "TXPWDIBIAS,Power down USB PHY current bias block" "0: No effect,1: Clears the corresponding PWD bit"
newline
bitfld.long 0x00 10. "TXPWDFS,Power down USB FS drivers" "0: No effect,1: Clears the corresponding PWD bit"
group.long 0x0C++0x03
line.long 0x00 "PWD_TOG,Power Down Register Toggle"
bitfld.long 0x00 20. "RXPWDRX,Power down USB PHY receiver except the FS differential" "0: No effect,1: Toggles the corresponding PWD bit"
newline
bitfld.long 0x00 19. "RXPWDDIFF,Power down USB HS differential receiver" "0: No effect,1: Toggles the corresponding PWD bit"
newline
bitfld.long 0x00 18. "RXPWD1PT1,Power down USB FS differential receiver" "0: No effect,1: Toggles the corresponding PWD bit"
newline
bitfld.long 0x00 17. "RXPWDENV,Power down USB HS receiver envelope detector" "0: No effect,1: Toggles the corresponding PWD bit"
newline
bitfld.long 0x00 12. "TXPWDV2I,Power down USB PHY V-I converter and current mirror" "0: No effect,1: Toggles the corresponding PWD bit"
newline
bitfld.long 0x00 11. "TXPWDIBIAS,Power down USB PHY current bias block" "0: No effect,1: Toggles the corresponding PWD bit"
newline
bitfld.long 0x00 10. "TXPWDFS,Power down USB FS drivers" "0,1"
group.long 0x10++0x03
line.long 0x00 "TX,TX Control"
bitfld.long 0x00 21. "TXENCAL45DP,DP series resistance calibration" "0,1"
newline
bitfld.long 0x00 16.--19. "TXCAL45DP,DP series termination resistance trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "TXENCAL45DN,DN series Resistance calibration" "0,1"
newline
bitfld.long 0x00 8.--11. "TXCAL45DM,DM series termination resistance trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "D_CAL,Current Trim decode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "TX_SET,TX Control Set"
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0: No effect,1: Sets the corresponding TX bit"
newline
bitfld.long 0x00 16.--19. "TXCAL45DP,DP series termination resistance trim" "0: No effect,1: Sets the corresponding TX bit,?..."
newline
bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0: No effect,1: Sets the corresponding TX bit"
newline
bitfld.long 0x00 8.--11. "TXENCAL45DM,DM series termination resistance trim" "0: No effect,1: Sets the corresponding TX bit,?..."
newline
bitfld.long 0x00 0.--3. "D_CAL,Current Trim decode" "0: No effect,1: Sets the corresponding TX bit,?..."
group.long 0x18++0x03
line.long 0x00 "TX_CLR,TX Control Clear"
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0: No effect,1: Clears the corresponding TX bit"
newline
bitfld.long 0x00 16.--19. "TXCAL45DP,DP series termination resistance trim" "0: No effect,1: Clears the corresponding TX bit,?..."
newline
bitfld.long 0x00 13. "TXENCAL45DN,Clears Enable resistance calibration on DN" "0: No effect,1: Clears the corresponding TX bit"
newline
bitfld.long 0x00 8.--11. "TXENCAL45DM,DM series termination resistance trim" "0: No effect,1: Clears the corresponding TX bit,?..."
newline
bitfld.long 0x00 0.--3. "D_CAL,Current Trim decode" "0: No effect,1: Clears the corresponding TX bit,?..."
group.long 0x1C++0x03
line.long 0x00 "TX_TOG,TX Control Toggle"
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0: No effect,1: Toggles the corresponding TX bit"
newline
bitfld.long 0x00 16.--19. "TXCAL45DP,DP series termination resistance trim" "0: No effect,1: Toggles the corresponding TX bit,?..."
newline
bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0: No effect,1: Toggles the corresponding TX bit"
newline
bitfld.long 0x00 8.--11. "TXENCAL45DM,DM series termination resistance trim" "0: No effect,1: Toggles the corresponding TX bit,?..."
newline
bitfld.long 0x00 0.--3. "D_CAL,Current Trim decode" "0: No effect,1: Toggles the corresponding TX bit,?..."
group.long 0x20++0x03
line.long 0x00 "RX,RX Control"
bitfld.long 0x00 22. "RXDBYPASS,DM bypass" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
newline
bitfld.long 0x00 4.--6. "DISCONADJ,Disconnect detector trip point" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
newline
bitfld.long 0x00 0.--2. "ENVADJ,Envelope detector trip point" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
group.long 0x24++0x03
line.long 0x00 "RX_SET,RX Control Set"
bitfld.long 0x00 22. "RXDBYPASS,DM bypass" "0: No effect,1: Sets the corresponding TX bit"
newline
bitfld.long 0x00 4.--6. "DISCONADJ,Disconnect detector trip point" "0: No effect,1: Sets the corresponding TX bit,?..."
newline
bitfld.long 0x00 0.--2. "ENVADJ,Envelope detector trip point" "0: No effect,1: Sets the corresponding TX bit,?..."
group.long 0x28++0x03
line.long 0x00 "RX_CLR,RX Control Clear"
bitfld.long 0x00 22. "RXDBYPASS,DM bypass" "0: No effect,1: Clears the corresponding TX bit"
newline
bitfld.long 0x00 4.--6. "DISCONADJ,Disconnect detector trip point" "0: No effect,1: Clears the corresponding TX bit,?..."
newline
bitfld.long 0x00 0.--2. "ENVADJ,Envelope detector trip point" "0: No effect,1: Clears the corresponding TX bit,?..."
group.long 0x2C++0x03
line.long 0x00 "RX_TOG,RX Control Toggle"
bitfld.long 0x00 22. "RXDBYPASS,DM bypass" "0: No effect,1: Toggles the corresponding TX bit"
newline
bitfld.long 0x00 4.--6. "DISCONADJ,Disconnect detector trip point" "0: No effect,1: Toggles the corresponding TX bit,?..."
newline
bitfld.long 0x00 0.--2. "ENVADJ,Envelope detector trip point" "0: No effect,1: Toggles the corresponding TX bit,?..."
group.long 0x30++0x03
line.long 0x00 "CTRL,General Purpose Control"
bitfld.long 0x00 31. "SFTRST,Software reset" "0,1"
newline
bitfld.long 0x00 30. "CLKGATE,UTMI clock gate" "0,1"
newline
rbitfld.long 0x00 29. "UTMI_SUSPENDM,UTMI suspend" "0,1"
newline
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,FS EOP low-speed timing" "0,1"
newline
bitfld.long 0x00 24. "FSDLL_RST_EN,Reset FSDLL lock" "0,1"
newline
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Autoclear PWD register bits" "0,1"
newline
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Autoclear clock gate" "0,1"
newline
bitfld.long 0x00 18. "AUTORESUME_EN,Enable autoresume" "0,1"
newline
bitfld.long 0x00 15. "ENUTMILEVEL3,Enable level 2 operation" "0,1"
newline
bitfld.long 0x00 14. "ENUTMILEVEL2,Enable level 2 operation" "0,1"
newline
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Device connected indicator" "0,1"
newline
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
newline
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Device disconnect indication" "0,1"
newline
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,Disconnect detect" "0,1"
group.long 0x34++0x03
line.long 0x00 "CTRL_SET,General Purpose Control Set"
bitfld.long 0x00 31. "SFTRST,Software reset" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 30. "CLKGATE,UTMI clock gate" "0: No effect,1: the corresponding CTRL bit"
newline
rbitfld.long 0x00 29. "UTMI_SUSPENDM,UTMI suspend" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,FS EOP low-speed timing" "0,1"
newline
bitfld.long 0x00 24. "FSDLL_RST_EN,Reset FSDLL lock" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Autoclear PWD register bits" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Autoclear clock gate" "0: No effect,1: the corresponding CTRL bit"
newline
bitfld.long 0x00 18. "AUTORESUME_EN,Enable autoresume" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 15. "ENUTMILEVEL3,Enable level 2 operation" "0: No effect,1: the corresponding CTRL bit"
newline
bitfld.long 0x00 14. "ENUTMILEVEL2,Enable level 2 operation" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Device connected indicator" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Device disconnect indication" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,Disconnect detect" "0: No effect,1: Sets the corresponding CTRL bit"
group.long 0x38++0x03
line.long 0x00 "CTRL_CLR,General Purpose Control Clear"
bitfld.long 0x00 31. "SFTRST,Software reset" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 30. "CLKGATE,UTMI clock gate" "0: No effect,1: Clears the corresponding CTRL bit"
newline
rbitfld.long 0x00 29. "UTMI_SUSPENDM,UTMI suspend" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,FS EOP low-speed timing" "0,1"
newline
bitfld.long 0x00 24. "FSDLL_RST_EN,Reset FSDLL lock" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Autoclear PWD register bits" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Autoclear clock gate" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 18. "AUTORESUME_EN,Enable autoresume" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 15. "ENUTMILEVEL3,Enable level 2 operation" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 14. "ENUTMILEVEL2,Enable level 2 operation" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Device connected indicator" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Device disconnect indication" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,Disconnect detect" "0: No effect,1: Clears the corresponding CTRL bit"
group.long 0x3C++0x03
line.long 0x00 "CTRL_TOG,General Purpose Control Toggle"
bitfld.long 0x00 31. "SFTRST,Software reset" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 30. "CLKGATE,UTMI clock gate" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
rbitfld.long 0x00 29. "UTMI_SUSPENDM,UTMI suspend" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,FS EOP low-speed timing" "0,1"
newline
bitfld.long 0x00 24. "FSDLL_RST_EN,Reset FSDLL lock" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Autoclear PWD register bits" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Autoclear clock gate" "0: No effect,1: the corresponding CTRL bit"
newline
bitfld.long 0x00 18. "AUTORESUME_EN,Enable autoresume" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 15. "ENUTMILEVEL3,Enable level 2 operation" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 14. "ENUTMILEVEL2,Enable level 2 operation" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Device connected indicator" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Device disconnect indication" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,Disconnect detect" "0: No effect,1: Toggles the corresponding CTRL bit"
rgroup.long 0x40++0x03
line.long 0x00 "STATUS,Status"
bitfld.long 0x00 10. "RESUME_STATUS,Resume status" "0,1"
newline
bitfld.long 0x00 6. "DEVPLUGIN_STATUS,Status indicator for non-standard resistive plugged-in detection" "0: No attachment to a USB host is detected,1: Cable attachment to a USB host is detected"
newline
bitfld.long 0x00 3. "HOSTDISCONDETECT_STATUS,Host disconnect status" "0: USB cable disconnect has not been detected at..,1: USB cable disconnect has been detected at the.."
group.long 0x50++0x03
line.long 0x00 "DEBUG0,Debug 0"
bitfld.long 0x00 30. "CLKGATE,Test clock gate" "0,1"
newline
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Host resume" "0,1"
newline
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Squelch reset length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 24. "ENSQUELCHRESET,Enable squelch reset" "0,1"
newline
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Squelch reset count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
newline
bitfld.long 0x00 8.--11. "TX2RXCOUNT,TX2RXCOUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,Enable Host pulldown" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "HSTPULLDOWN,HS DP/DM pulldown resistance select" "0,1,2,3"
newline
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Debug interface" "0,1"
group.long 0x54++0x03
line.long 0x00 "DEBUG0_SET,Debug 0 Set"
bitfld.long 0x00 30. "CLKGATE,Test clock gate" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Host resume" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Squelch reset length" "0: No effect,1: Sets the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 24. "ENSQUELCHRESET,Enable squelch reset" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Squelch reset count" "0: No effect,1: Sets the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 12. "ENTX2RXCOUNT,ENTX2RXCOUNT" "0: No effect,1: Sets the corresponding CTRL bit"
newline
bitfld.long 0x00 8.--11. "TX2RXCOUNT,TX2RXCOUNT" "0: No effect,1: Sets the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,Enable Host pulldown" "0: No effect,1: Sets the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 2.--3. "HSTPULLDOWN,HS DP/DM pulldown resistance select" "0: No effect,1: Sets the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Debug interface" "0: No effect,1: Sets the corresponding CTRL bit"
group.long 0x58++0x03
line.long 0x00 "DEBUG0_CLR,Debug Clear"
bitfld.long 0x00 30. "CLKGATE,Test clock gate" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Host resume" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Squelch reset length" "0: No effect,1: Clears the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 24. "ENSQUELCHRESET,Enable squelch reset" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Squelch reset count" "0: No effect,1: Clears the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 12. "ENTX2RXCOUNT,ENTX2RXCOUNT" "0: No effect,1: Clears the corresponding CTRL bit"
newline
bitfld.long 0x00 8.--11. "TX2RXCOUNT,TX2RXCOUNT" "0: No effect,1: Clears the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,Enable Host pulldown" "0: No effect,1: Clears the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 2.--3. "HSTPULLDOWN,HS DP/DM pulldown resistance select" "0: No effect,1: Clears the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Debug interface" "0: No effect,1: Clears the corresponding CTRL bit"
group.long 0x5C++0x03
line.long 0x00 "DEBUG0_TOG,Debug Toggle"
bitfld.long 0x00 30. "CLKGATE,Test clock gate" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Host resume" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Squelch reset length" "0: No effect,1: the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 24. "ENSQUELCHRESET,Enable squelch reset" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Squelch reset count" "0: No effect,1: Toggles the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 12. "ENTX2RXCOUNT,ENTX2RXCOUNT" "0: No effect,1: Toggles the corresponding CTRL bit"
newline
bitfld.long 0x00 8.--11. "TX2RXCOUNT,TX2RXCOUNT" "0: No effect,1: Toggles the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,Enable Host pulldown" "0: No effect,1: Toggles the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 2.--3. "HSTPULLDOWN,HS DP/DM pulldown resistance select" "0: No effect,1: Toggles the corresponding CTRL bit,?..."
newline
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Debug interface" "0: No effect,1: Toggles the corresponding CTRL bit"
group.long 0x70++0x03
line.long 0x00 "DEBUG1,UTMI Debug 1"
bitfld.long 0x00 21.--22. "USB2_REFBIAS_TST,Bias current control" "0,1,2,3"
newline
bitfld.long 0x00 18.--20. "USB2_REFBIAS_VBGADJ,Bandgap adjustment" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13.--14. "ENTAILADJVD,Enable delay increment" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
group.long 0x74++0x03
line.long 0x00 "DEBUG1_SET,UTMI Debug 1 Set"
bitfld.long 0x00 21.--22. "USB2_REFBIAS_TST,Bias current control" "0: No effect,1: Sets the corresponding DEBUG1 bit,?..."
newline
bitfld.long 0x00 18.--20. "USB2_REFBIAS_VBGADJ,Bandgap adjustment" "0: No effect,1: Sets the corresponding DEBUG1 bit,?..."
newline
bitfld.long 0x00 13.--14. "ENTAILADJVD,Enable delay increment" "0: No effect,1: Sets the corresponding DEBUG1 bit,?..."
group.long 0x78++0x03
line.long 0x00 "DEBUG1_CLR,UTMI Debug 1 Clear"
bitfld.long 0x00 21.--22. "USB2_REFBIAS_TST,Bias current control" "0: No effect,1: Clears the corresponding DEBUG1 bit,?..."
newline
bitfld.long 0x00 18.--20. "USB2_REFBIAS_VBGADJ,Bandgap adjustment" "0: No effect,1: Clears the corresponding DEBUG1 bit,?..."
newline
bitfld.long 0x00 13.--14. "ENTAILADJVD,Enable delay increment" "0: No effect,1: Clears the corresponding DEBUG1 bit,?..."
group.long 0x7C++0x03
line.long 0x00 "DEBUG1_TOG,UTMI Debug 1 Toggle"
bitfld.long 0x00 21.--22. "USB2_REFBIAS_TST,Bias current control" "0: No effect,1: Toggles the corresponding DEBUG1 bit,?..."
newline
bitfld.long 0x00 18.--20. "USB2_REFBIAS_VBGADJ,Bandgap adjustment" "0: No effect,1: Toggles the corresponding DEBUG1 bit,?..."
newline
bitfld.long 0x00 13.--14. "ENTAILADJVD,Enable delay increment" "0: No effect,1: Clears the corresponding DEBUG1 bit,?..."
rgroup.long 0x80++0x03
line.long 0x00 "VERSION,Version"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR"
newline
hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR"
newline
hexmask.long.word 0x00 0.--15. 1. "STEP,STEP"
group.long 0xA0++0x03
line.long 0x00 "PLL_SIC,PLL Control/Status"
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
newline
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,PLL Divider value" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240"
newline
bitfld.long 0x00 21. "PLL_REG_ENABLE,Enable PLL regulator" "0,1"
newline
bitfld.long 0x00 20. "REFBIAS_PWD,Power down Reference bias" "0,1"
newline
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power control" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
newline
bitfld.long 0x00 16. "PLL_BYPASS,Bypass USB PLL" "0: Use USB PLL,1: Bypass USB PLL"
newline
bitfld.long 0x00 13. "PLL_ENABLE,PLL enable" "0,1"
newline
bitfld.long 0x00 12. "PLL_POWER,Power PLL" "0,1"
newline
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,PLL clock enable" "0,1"
group.long 0xA4++0x03
line.long 0x00 "PLL_SIC_SET,PLL Control/Status Set"
rbitfld.long 0x00 31. "PLL_LOCK,PLL_LOCK" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,PLL_DIV_SEL" "0: No effect,1: Sets the corresponding bit,?..."
newline
bitfld.long 0x00 21. "PLL_REG_ENABLE,PLL_REG_ENABLE" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 20. "REFBIAS_PWD,REFBIAS_PWD" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,REFBIAS_PWD_SEL" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 16. "PLL_BYPASS,Bypass USB PLL" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 13. "PLL_ENABLE,ENABLE" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 12. "PLL_POWER,POWER" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,PLL_EN_USB_CLKS" "0: No effect,1: Sets the corresponding bit"
group.long 0xA8++0x03
line.long 0x00 "PLL_SIC_CLR,PLL Control/Status Clear"
rbitfld.long 0x00 31. "PLL_LOCK,PLL_LOCK" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,PLL_DIV_SEL" "0: No effect,1: Clears the corresponding bit,?..."
newline
bitfld.long 0x00 21. "PLL_REG_ENABLE,PLL_REG_ENABLE" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 20. "REFBIAS_PWD,REFBIAS_PWD" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,REFBIAS_PWD_SEL" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 16. "PLL_BYPASS,Bypass USB PLL" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 13. "PLL_ENABLE,ENABLE" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 12. "PLL_POWER,POWER" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,PLL_EN_USB_CLKS" "0: No effect,1: Clears the corresponding bit"
group.long 0xAC++0x03
line.long 0x00 "PLL_SIC_TOG,PLL Control/Status Toggle"
rbitfld.long 0x00 31. "PLL_LOCK,PLL_LOCK" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,PLL_DIV_SEL" "0: No effect,1: Toggles the corresponding bit,?..."
newline
bitfld.long 0x00 21. "PLL_REG_ENABLE,PLL_REG_ENABLE" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 20. "REFBIAS_PWD,REFBIAS_PWD" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,REFBIAS_PWD_SEL" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 16. "PLL_BYPASS,Bypass USB PLL" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 13. "PLL_ENABLE,PLL ENABLE" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 12. "PLL_POWER,POWER" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,PLL_EN_USB_CLKS" "0: No effect,1: Toggles the corresponding bit"
group.long 0xC0++0x03
line.long 0x00 "USB1_VBUS_DETECT,VBUS detect"
bitfld.long 0x00 31. "EN_CHARGER_RESISTOR,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors..,1: Enable resistive charger detection resistors.."
newline
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
newline
bitfld.long 0x00 20. "PWRUP_CMPS,Enables the VBUS_VALID comparator" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
newline
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
newline
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
newline
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
newline
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller" "0,1"
newline
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid" "0,1"
newline
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid" "0,1"
newline
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND" "0,1"
newline
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
newline
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,VBUS comparator threshold" "0,1,2,3,4,5,6,7"
group.long 0xC4++0x03
line.long 0x00 "USB1_VBUS_DETECT_SET,VBUS detect Set"
bitfld.long 0x00 31. "EN_CHARGER_RESISTOR,Enables resistors used for an older method of resistive battery charger detection" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 20. "PWRUP_CMPS,Enables the VBUS_VALID comparator" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0,1,2,3"
newline
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,VBUS comparator threshold" "0: No effect,1: Sets the corresponding bit,?..."
group.long 0xC8++0x03
line.long 0x00 "USB1_VBUS_DETECT_CLR,VBUS detect Clear"
bitfld.long 0x00 31. "EN_CHARGER_RESISTOR,Enables resistors used for an older method of resistive battery charger detection" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 20. "PWRUP_CMPS,Enables the VBUS_VALID comparator" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0,1,2,3"
newline
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override" "0: No effect,1: clears the corresponding bit"
newline
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,VBUS comparator threshold" "0: No effect,1: clears the corresponding bit,?..."
group.long 0xCC++0x03
line.long 0x00 "USB1_VBUS_DETECT_TOG,VBUS detect Toggle"
bitfld.long 0x00 31. "EN_CHARGER_RESISTOR,Enables resistors used for an older method of resistive battery charger detection" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 20. "PWRUP_CMPS,Enables the VBUS_VALID comparator" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0,1,2,3"
newline
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,VBUS comparator threshold" "0: No effect,1: Toggles the corresponding bit,?..."
rgroup.long 0xD0++0x03
line.long 0x00 "USB1_VBUS_DET_STAT,VBUS Detect Status"
bitfld.long 0x00 4. "VBUS_VALID_3V,VBUS_VALID_3V detector status" "0: VBUS voltage is below VBUS_VALID_3V threshold,1: VBUS voltage is above VBUS_VALID_3V threshold"
newline
bitfld.long 0x00 3. "VBUS_VALID,VBUS voltage status" "0: VBUS is below the comparator threshold,1: VBUS is above the comparator threshold"
newline
bitfld.long 0x00 2. "AVALID,A-Device Session Valid status" "0: The VBUS voltage is below the Session Valid..,1: The VBUS voltage is above the Session Valid.."
newline
bitfld.long 0x00 1. "BVALID,B-Device Session Valid status" "0: The VBUS voltage is below the Session Valid..,1: The VBUS voltage is above the Session Valid.."
newline
bitfld.long 0x00 0. "SESSEND,Session End indicator" "0: The VBUS voltage is above the Session Valid..,1: The VBUS voltage is below the Session Valid.."
group.long 0xE0++0x03
line.long 0x00 "USB1_CHRG_DETECT,Charger Detect Control"
bitfld.long 0x00 23. "BGR_IBIAS,USB charge detector bias current reference" "0: Bias current is derived from the USB PHY..,1: Bias current is derived from the reference.."
newline
bitfld.long 0x00 2. "PULLUP_DP,PULLUP_DP" "0,1"
group.long 0xE4++0x03
line.long 0x00 "USB1_CHRG_DETECT_SET,Charger Detect Control Set"
bitfld.long 0x00 23. "BGR_IBIAS,BGR_IBIAS" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 2. "PULLUP_DP,PULLUP_DP" "0: No effect,1: Sets the corresponding bit"
group.long 0xE8++0x03
line.long 0x00 "USB1_CHRG_DETECT_CLR,Charger Detect Control Clear"
bitfld.long 0x00 23. "BGR_IBIAS,BGR_IBIAS" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 2. "PULLUP_DP,PULLUP_DP" "0: No effect,1: Clears the corresponding bit"
group.long 0xEC++0x03
line.long 0x00 "USB1_CHRG_DETECT_TOG,Charger Detect Control Toggle"
bitfld.long 0x00 23. "BGR_IBIAS,BGR_IBIAS" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 2. "PULLUP_DP,PULLUP_DP" "0: No effect,1: Toggles the corresponding bit"
rgroup.long 0xF0++0x03
line.long 0x00 "USB1_CHRG_DET_STAT,Charge Detect Status"
bitfld.long 0x00 4. "SECDET_DCP,Battery Charging Secondary Detection phase output" "0: Charging Downstream Port (CDP) has been..,1: Downstream Charging Port (DCP) has been.."
newline
bitfld.long 0x00 3. "DP_STATE,DP_STATE" "0: DP pin voltage is < 0.8V,1: DP pin voltage is > 2.0V"
newline
bitfld.long 0x00 2. "DM_STATE,DM_STATE" "0: DM pin voltage is < 0.8V,1: DM pin voltage is > 2.0V"
newline
bitfld.long 0x00 1. "CHRG_DETECTED,Battery Charging Primary Detection phase output" "0: Standard Downstream Port (SDP) has been..,1: Charging Port has been detected"
newline
bitfld.long 0x00 0. "PLUG_CONTACT,Battery Charging Data Contact Detection phase output" "0: No USB cable attachment has been detected,1: A USB cable attachment between the device and.."
group.long 0x100++0x03
line.long 0x00 "ANACTRL,Analog Control"
bitfld.long 0x00 10. "DEV_PULLDOWN,Device Pull-down" "0,1"
group.long 0x104++0x03
line.long 0x00 "ANACTRL_SET,Analog Control Set"
bitfld.long 0x00 10. "DEV_PULLDOWN,Device Pull-down" "0: No effect,1: Sets the corresponding bit"
group.long 0x108++0x03
line.long 0x00 "ANACTRL_CLR,Analog Control Clear"
bitfld.long 0x00 10. "DEV_PULLDOWN,Device Pull-down" "0: No effect,1: Clears the corresponding bit"
group.long 0x10C++0x03
line.long 0x00 "ANACTRL_TOG,Analog Control Toggle"
bitfld.long 0x00 10. "DEV_PULLDOWN,Device Pull-down" "0: No effect,1: Toggles the corresponding bit"
group.long 0x110++0x03
line.long 0x00 "USB1_LOOPBACK,USB PHY Loopback Control/Status"
hexmask.long.byte 0x00 16.--23. 1. "TSTPKT,Test packet"
newline
bitfld.long 0x00 15. "TSTI_HSFS_MODE_EN,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet speed" "0,1"
newline
rbitfld.long 0x00 8. "UTMO_DIG_TST1,Status bit for USB loopback test" "0,1"
newline
rbitfld.long 0x00 7. "UTMO_DIG_TST0,Status bit for USB loopback test" "0,1"
newline
bitfld.long 0x00 6. "TSTI_TX_HIZ,Sets TX Hi-Z for USB loopback test" "0,1"
newline
bitfld.long 0x00 5. "TSTI_TX_EN,Enable TX for USB loopback test" "0,1"
newline
bitfld.long 0x00 4. "TSTI_TX_LS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
newline
bitfld.long 0x00 3. "TSTI_TX_HS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
newline
bitfld.long 0x00 2. "UTMI_DIG_TST1,Mode control for USB loopback test" "0,1"
newline
bitfld.long 0x00 1. "UTMI_DIG_TST0,Mode control for USB loopback test" "0,1"
newline
bitfld.long 0x00 0. "UTMI_TESTSTART,USB loopback test" "0,1"
group.long 0x114++0x03
line.long 0x00 "USB1_LOOPBACK_SET,USB PHY Loopback Control/Status Set"
hexmask.long.byte 0x00 16.--23. 1. "TSTPKT,Test packet"
newline
bitfld.long 0x00 15. "TSTI_HSFS_MODE_EN,TSTI_HSFS_MODE_EN" "0: No effect,1: Sets the corresponding bit"
newline
rbitfld.long 0x00 8. "UTMO_DIG_TST1,Status bit for USB loopback test" "0: No effect,1: Sets the corresponding bit"
newline
rbitfld.long 0x00 7. "UTMO_DIG_TST0,Status bit for USB loopback test" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 6. "TSTI_TX_HIZ,Sets TX Hi-Z for USB loopback test" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 5. "TSTI_TX_EN,Enable TX for USB loopback test" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 4. "TSTI_TX_LS_MODE,Select HS or FS mode for USB loopback testing" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 3. "TSTI_TX_HS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
newline
bitfld.long 0x00 2. "UTMI_DIG_TST1,Mode control for USB loopback test" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 1. "UTMI_DIG_TST0,Mode control for USB loopback test" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 0. "UTMI_TESTSTART,USB loopback test" "0: No effect,1: Sets the corresponding bit"
group.long 0x118++0x03
line.long 0x00 "USB1_LOOPBACK_CLR,USB PHY Loopback Control/Status Clear"
hexmask.long.byte 0x00 16.--23. 1. "TSTPKT,Test packet"
newline
bitfld.long 0x00 15. "TSTI_HSFS_MODE_EN,TSTI_HSFS_MODE_EN" "0: No effect,1: Clears the corresponding bit"
newline
rbitfld.long 0x00 8. "UTMO_DIG_TST1,Status bit for USB loopback test" "0: No effect,1: Clears the corresponding bit"
newline
rbitfld.long 0x00 7. "UTMO_DIG_TST0,Status bit for USB loopback test" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 6. "TSTI_TX_HIZ,Sets TX Hi-Z for USB loopback test" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 5. "TSTI_TX_EN,Enable TX for USB loopback test" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 4. "TSTI_TX_LS_MODE,Select HS or FS mode for USB loopback testing" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 3. "TSTI_TX_HS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
newline
bitfld.long 0x00 2. "UTMI_DIG_TST1,Mode control for USB loopback test" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 1. "UTMI_DIG_TST0,Mode control for USB loopback test" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 0. "UTMI_TESTSTART,USB loopback test" "0: No effect,1: Clears the corresponding bit"
group.long 0x11C++0x03
line.long 0x00 "USB1_LOOPBACK_TOG,USB PHY Loopback Control/Status Toggle"
hexmask.long.byte 0x00 16.--23. 1. "TSTPKT,Test packet"
newline
bitfld.long 0x00 15. "TSTI_HSFS_MODE_EN,TSTI_HSFS_MODE_EN" "0: No effect,1: Toggles the corresponding bit"
newline
rbitfld.long 0x00 8. "UTMO_DIG_TST1,Status bit for USB loopback test" "0: No effect,1: Toggles the corresponding bit"
newline
rbitfld.long 0x00 7. "UTMO_DIG_TST0,Status bit for USB loopback test" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 6. "TSTI_TX_HIZ,Sets TX Hi-Z for USB loopback test" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 5. "TSTI_TX_EN,Enable TX for USB loopback test" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 4. "TSTI_TX_LS_MODE,Select HS or FS mode for USB loopback testing" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 3. "TSTI_TX_HS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
newline
bitfld.long 0x00 2. "UTMI_DIG_TST1,Mode control for USB loopback test" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 1. "UTMI_DIG_TST0,Mode control for USB loopback test" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 0. "UTMI_TESTSTART,USB loopback test" "0: No effect,1: Toggles the corresponding bit"
group.long 0x120++0x03
line.long 0x00 "USB1_LOOPBACK_HSFSCNT,Loopback Packet Number Select"
hexmask.long.word 0x00 16.--31. 1. "TSTI_FS_NUMBER,USB loopback test FS CNT"
newline
hexmask.long.word 0x00 0.--15. 1. "TSTI_HS_NUMBER,USB loopback test HS CNT"
group.long 0x124++0x03
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_SET,USB PHY Loopback Packet Number Select Set"
hexmask.long.word 0x00 16.--31. 1. "TSTI_FS_NUMBER,USB loopback test FS CNT"
newline
hexmask.long.word 0x00 0.--15. 1. "TSTI_HS_NUMBER,USB loopback test HS CNT"
group.long 0x128++0x03
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_CLR,USB PHY Loopback Packet Number Select Clear"
hexmask.long.word 0x00 16.--31. 1. "TSTI_FS_NUMBER,USB loopback test FS CNT"
newline
hexmask.long.word 0x00 0.--15. 1. "TSTI_HS_NUMBER,USB loopback test HS CNT"
group.long 0x12C++0x03
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_TOG,USB PHY Loopback Packet Number Select Toggle"
hexmask.long.word 0x00 16.--31. 1. "TSTI_FS_NUMBER,USB loopback test FS CNT"
newline
hexmask.long.word 0x00 0.--15. 1. "TSTI_HS_NUMBER,USB loopback test HS CNT"
group.long 0x130++0x03
line.long 0x00 "TRIM_OVERRIDE_EN,Trim Override Enable"
rbitfld.long 0x00 28.--31. "USBPHY_TX_CAL45DN,Default value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 24.--27. "USBPHY_TX_CAL45DP,Default value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20.--23. "USBPHY_TX_D_CAL,Default value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 18.--19. "USB_REG_ENV_TAIL_ADJ_VD,Default value of ENV_TAIL_ADJ" "0,1,2,3"
newline
rbitfld.long 0x00 15.--17. "PLL_CTRL0_DIV_SEL,Default value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 13.--14. "USB2_REFBIAS_TST,Bias current control for usb2_phy and usb_PLL" "0,1,2,3"
newline
rbitfld.long 0x00 10.--12. "USB2_REFBIAS_VBGADJ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6. "REFBIAS_TST_OVERRIDE,Override enable for bias current control" "0,1"
newline
bitfld.long 0x00 5. "REFBIAS_VBGADJ_OVERRIDE,Override enable for bandgap adjustment" "0,1"
newline
bitfld.long 0x00 4. "TX_CAL45DM_OVERRIDE,TX_CAL45DM_OVERRIDE" "0,1"
newline
bitfld.long 0x00 3. "TX_CAL45DP_OVERRIDE,TX_CAL45DP_OVERRIDE" "0,1"
newline
bitfld.long 0x00 2. "TX_D_CAL_OVERRIDE,TX_D_CAL_OVERRIDE" "0,1"
newline
bitfld.long 0x00 1. "ENV_TAIL_ADJ_VD_OVERRIDE,ENV_TAIL_ADJ_VD_OVERRIDE" "0,1"
newline
bitfld.long 0x00 0. "DIV_SEL_OVERRIDE,DIV_SEL_OVERRIDE" "0,1"
group.long 0x134++0x03
line.long 0x00 "TRIM_OVERRIDE_EN_SET,Trim Set"
rbitfld.long 0x00 28.--31. "USBPHY_TX_CAL45DN,Default value of TX_CAL45DM" "0: No effect,1: Sets the corresponding bit,?..."
newline
rbitfld.long 0x00 24.--27. "USBPHY_TX_CAL45DP,Default value of TX_CAL45DP" "0: No effect,1: Sets the corresponding bit,?..."
newline
rbitfld.long 0x00 20.--23. "USBPHY_TX_D_CAL,Default value of TX_D_CAL" "0: No effect,1: Sets the corresponding bit,?..."
newline
rbitfld.long 0x00 18.--19. "USB_REG_ENV_TAIL_ADJ_VD,Default value of ENV_TAIL_ADJ" "0: No effect,1: Sets the corresponding bit,?..."
newline
rbitfld.long 0x00 15.--17. "PLL_CTRL0_DIV_SEL,Default value of PLL_DIV_SEL" "0: No effect,1: Sets the corresponding bit,?..."
newline
rbitfld.long 0x00 13.--14. "USB2_REFBIAS_TST,Bias current control for usb2_phy and usb_PLL" "0: No effect,1: Sets the corresponding bit,?..."
newline
rbitfld.long 0x00 10.--12. "USB2_REFBIAS_VBGADJ,Adjustment bits for bandgap" "0: No effect,1: Sets the corresponding bit,?..."
newline
bitfld.long 0x00 6. "REFBIAS_TST_OVERRIDE,Override enable for bias current control" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 5. "REFBIAS_VBGADJ_OVERRIDE,Override enable for bandgap adjustment" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 4. "TX_CAL45DM_OVERRIDE,TX_CAL45DM_OVERRIDE" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 3. "TX_CAL45DP_OVERRIDE,TX_CAL45DP_OVERRIDE" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 2. "TX_D_CAL_OVERRIDE,TX_D_CAL_OVERRIDE" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 1. "ENV_TAIL_ADJ_VD_OVERRIDE,ENV_TAIL_ADJ_VD_OVERRIDE" "0: No effect,1: Sets the corresponding bit"
newline
bitfld.long 0x00 0. "DIV_SEL_OVERRIDE,DIV_SEL_OVERRIDE" "0: No effect,1: Sets the corresponding bit"
group.long 0x138++0x03
line.long 0x00 "TRIM_OVERRIDE_EN_CLR,Trim Clear"
rbitfld.long 0x00 28.--31. "USBPHY_TX_CAL45DN,Default value of TX_CAL45DM" "0: No effect,1: Clears the corresponding bit,?..."
newline
rbitfld.long 0x00 24.--27. "USBPHY_TX_CAL45DP,Default value of TX_CAL45DP" "0: No effect,1: Clears the corresponding bit,?..."
newline
rbitfld.long 0x00 20.--23. "USBPHY_TX_D_CAL,Default value of TX_D_CAL" "0: No effect,1: Clears the corresponding bit,?..."
newline
rbitfld.long 0x00 18.--19. "USB_REG_ENV_TAIL_ADJ_VD,Default value of ENV_TAIL_ADJ" "0: No effect,1: Clears the corresponding bit,?..."
newline
rbitfld.long 0x00 15.--17. "PLL_CTRL0_DIV_SEL,Default value of PLL_DIV_SEL" "0: No effect,1: Clears the corresponding bit,?..."
newline
rbitfld.long 0x00 13.--14. "USB2_REFBIAS_TST,Bias current control for usb2_phy and usb_PLL" "0: No effect,1: Clears the corresponding bit,?..."
newline
rbitfld.long 0x00 10.--12. "USB2_REFBIAS_VBGADJ,Adjustment bits for bandgap" "0: No effect,1: Clears the corresponding bit,?..."
newline
bitfld.long 0x00 6. "REFBIAS_TST_OVERRIDE,Override enable for bias current control" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 5. "REFBIAS_VBGADJ_OVERRIDE,Override enable for bandgap adjustment" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 4. "TX_CAL45DM_OVERRIDE,TX_CAL45DM_OVERRIDE" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 3. "TX_CAL45DP_OVERRIDE,TX_CAL45DP_OVERRIDE" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 2. "TX_D_CAL_OVERRIDE,TX_D_CAL_OVERRIDE" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 1. "ENV_TAIL_ADJ_VD_OVERRIDE,ENV_TAIL_ADJ_VD_OVERRIDE" "0: No effect,1: Clears the corresponding bit"
newline
bitfld.long 0x00 0. "DIV_SEL_OVERRIDE,DIV_SEL_OVERRIDE" "0: No effect,1: Clears the corresponding bit"
group.long 0x13C++0x03
line.long 0x00 "TRIM_OVERRIDE_EN_TOG,Trim Toggle"
rbitfld.long 0x00 28.--31. "USBPHY_TX_CAL45DN,Default value of TX_CAL45DM" "0: No effect,1: Toggles the corresponding bit,?..."
newline
rbitfld.long 0x00 24.--27. "USBPHY_TX_CAL45DP,Default value of TX_CAL45DP" "0: No effect,1: Toggles the corresponding bit,?..."
newline
rbitfld.long 0x00 20.--23. "USBPHY_TX_D_CAL,Default value of TX_D_CAL" "0: No effect,1: Toggles the corresponding bit,?..."
newline
rbitfld.long 0x00 18.--19. "USB_REG_ENV_TAIL_ADJ_VD,Default value of ENV_TAIL_ADJ" "0: No effect,1: Toggles the corresponding bit,?..."
newline
rbitfld.long 0x00 15.--17. "PLL_CTRL0_DIV_SEL,Default value of PLL_DIV_SEL" "0: No effect,1: Toggles the corresponding bit,?..."
newline
rbitfld.long 0x00 13.--14. "USB2_REFBIAS_TST,Bias current control for usb2_phy and usb_PLL" "0: No effect,1: Toggles the corresponding bit,?..."
newline
rbitfld.long 0x00 10.--12. "USB2_REFBIAS_VBGADJ,Adjustment bits for bandgap" "0: No effect,1: Toggles the corresponding bit,?..."
newline
bitfld.long 0x00 6. "REFBIAS_TST_OVERRIDE,Override enable for bias current control" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 5. "REFBIAS_VBGADJ_OVERRIDE,Override enable for bandgap adjustment" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 4. "TX_CAL45DM_OVERRIDE,TX_CAL45DM_OVERRIDE" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 3. "TX_CAL45DP_OVERRIDE,TX_CAL45DP_OVERRIDE" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 2. "TX_D_CAL_OVERRIDE,TX_D_CAL_OVERRIDE" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 1. "ENV_TAIL_ADJ_VD_OVERRIDE,ENV_TAIL_ADJ_VD_OVERRIDE" "0: No effect,1: Toggles the corresponding bit"
newline
bitfld.long 0x00 0. "DIV_SEL_OVERRIDE,DIV_SEL_OVERRIDE" "0: No effect,1: Toggles the corresponding bit"
tree.end
tree "USDHC (Ultra Secured Digital Host Controller)"
tree "USDHC0"
base ad:0x40136000
group.long 0x00++0x03
line.long 0x00 "DS_ADDR,DMA System Address"
hexmask.long 0x00 0.--31. 1. "DS_ADDR,System address"
group.long 0x04++0x03
line.long 0x00 "BLK_ATT,Block Attributes"
hexmask.long.word 0x00 16.--31. 1. "BLKCNT,Blocks count for current transfer"
newline
hexmask.long.word 0x00 0.--12. 1. "BLKSIZE,Transfer block size"
group.long 0x08++0x03
line.long 0x00 "CMD_ARG,Command Argument"
hexmask.long 0x00 0.--31. 1. "CMDARG,Command argument"
group.long 0x0C++0x03
line.long 0x00 "CMD_XFR_TYP,Command Transfer Type"
bitfld.long 0x00 24.--29. "CMDINX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 22.--23. "CMDTYP,Command type" "0: Normal other commands,1: Suspend CMD52 for writing bus suspend in CCCR,2: Resume CMD52 for writing function select in..,3: Abort CMD12 CMD52 for writing I/O Abort in CCCR"
newline
bitfld.long 0x00 21. "DPSEL,Data present select" "0: No data present,1: Data present"
newline
bitfld.long 0x00 20. "CICEN,Command index check enable" "0: Disable command index check,1: Enables command index check"
newline
bitfld.long 0x00 19. "CCCEN,Command CRC check enable" "0: Disables command CRC check,1: Enables command CRC check"
newline
bitfld.long 0x00 16.--17. "RSPTYP,Response type select" "0: No response,1: Response length 136,2: Response length 48,3: Response length 48 check busy after response"
rgroup.long 0x10++0x03
line.long 0x00 "CMD_RSP0,Command Response0"
hexmask.long 0x00 0.--31. 1. "CMDRSP0,Command response 0"
rgroup.long 0x14++0x03
line.long 0x00 "CMD_RSP1,Command Response1"
hexmask.long 0x00 0.--31. 1. "CMDRSP1,Command response 1"
rgroup.long 0x18++0x03
line.long 0x00 "CMD_RSP2,Command Response2"
hexmask.long 0x00 0.--31. 1. "CMDRSP2,Command response 2"
rgroup.long 0x1C++0x03
line.long 0x00 "CMD_RSP3,Command Response3"
hexmask.long 0x00 0.--31. 1. "CMDRSP3,Command response 3"
group.long 0x20++0x03
line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port"
hexmask.long 0x00 0.--31. 1. "DATCONT,Data content"
rgroup.long 0x24++0x03
line.long 0x00 "PRES_STATE,Present State"
hexmask.long.byte 0x00 24.--31. 1. "DLSL,DATA[7:0] line signal level"
newline
bitfld.long 0x00 23. "CLSL,CMD line signal level" "0,1"
newline
bitfld.long 0x00 19. "WPSPL,Write protect switch pin level" "0: Write protected (WP = 1),1: Write enabled (WP = 0)"
newline
bitfld.long 0x00 18. "CDPL,Card detect pin level" "0: No card present (CD_B = 1),1: Card present (CD_B = 0)"
newline
bitfld.long 0x00 16. "CINST,Card inserted" "0: Power on reset or no card,1: Card inserted"
newline
bitfld.long 0x00 15. "TSCD,Tape select change done" "0: Delay cell select change is not finished,1: Delay cell select change is finished"
newline
bitfld.long 0x00 12. "RTR,Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Fixed or well tuned sampling clock,1: Sampling clock needs re-tuning"
newline
bitfld.long 0x00 11. "BREN,Buffer read enable" "0: Read disable,1: Read enable"
newline
bitfld.long 0x00 10. "BWEN,Buffer write enable" "0: Write disable,1: Write enable"
newline
bitfld.long 0x00 9. "RTA,Read transfer active" "0: No valid data,1: Transferring data"
newline
bitfld.long 0x00 8. "WTA,Write transfer active" "0: No valid data,1: Transferring data"
newline
bitfld.long 0x00 7. "SDOFF,SD clock gated off internally" "0: SD clock is active,1: SD clock is gated off"
newline
bitfld.long 0x00 6. "PEROFF,IPG_PERCLK gated off internally" "0: IPG_PERCLK is active,1: IPG_PERCLK is gated off"
newline
bitfld.long 0x00 5. "HCKOFF,HCLK gated off internally" "0: HCLK is active,1: HCLK is gated off"
newline
bitfld.long 0x00 4. "IPGOFF,Peripheral clock gated off internally" "0: Peripheral clock is active,1: Peripheral clock is gated off"
newline
bitfld.long 0x00 3. "SDSTB,SD clock stable" "0: Clock is changing frequency and not stable,1: Clock is stable"
newline
bitfld.long 0x00 2. "DLA,Data line active" "0: DATA line inactive,1: DATA line active"
newline
bitfld.long 0x00 1. "CDIHB,Command inhibit (DATA)" "0: Can issue command that uses the DATA line,1: Cannot issue command that uses the DATA line"
newline
bitfld.long 0x00 0. "CIHB,Command inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
group.long 0x28++0x03
line.long 0x00 "PROT_CTRL,Protocol Control"
bitfld.long 0x00 30. "NON_EXACT_BLK_RD,Non-exact block" "0: The block read is exact block,1: The block read is non-exact block"
newline
bitfld.long 0x00 27.--29. "BURST_LEN_EN,BURST length enable for INCR INCR4 / INCR8 / INCR16 INCR4-WRAP / INCR8-WRAP / INCR16-WRAP" "?,1: Burst length is enabled for INCR,?,3: Burst length is enabled for INCR,?,5: Burst length is enabled for INCR,?,7: Burst length is enabled for INCR"
newline
bitfld.long 0x00 26. "WECRM,Wakeup event enable on SD card removal" "0: Disables wakeup event enable on SD card removal,1: Enables wakeup event enable on SD card removal"
newline
bitfld.long 0x00 25. "WECINS,Wakeup event enable on SD card insertion" "0: Disable wakeup event enable on SD card..,1: Enable wakeup event enable on SD card insertion"
newline
bitfld.long 0x00 24. "WECINT,Wakeup event enable on card interrupt" "0: Disables wakeup event enable on card interrupt,1: Enables wakeup event enable on card interrupt"
newline
bitfld.long 0x00 20. "RD_DONE_NO_8CLK,Read performed number 8 clock" "0,1"
newline
bitfld.long 0x00 19. "IABG,Interrupt at block gap" "0: Disables interrupt at block gap,1: Enables interrupt at block gap"
newline
bitfld.long 0x00 18. "RWCTL,Read wait control" "0: Disables read wait control and stop SD clock..,1: Enables read wait control and assert read.."
newline
bitfld.long 0x00 17. "CREQ,Continue request" "0: No effect,1: Restart"
newline
bitfld.long 0x00 16. "SABGREQ,Stop at block gap request" "0: SABGREQ_0,1: SABGREQ_1"
newline
bitfld.long 0x00 8.--9. "DMASEL,DMA select" "0: No DMA or simple DMA is selected,1: ADMA1 is selected,2: ADMA2 is selected,?..."
newline
bitfld.long 0x00 7. "CDSS,Card detect signal selection" "0: Card detection level is selected (for normal..,1: Card detection test level is selected (for.."
newline
bitfld.long 0x00 6. "CDTL,Card detect test level" "0: Card detect test level is 0 no card inserted,1: Card detect test level is 1 card inserted"
newline
bitfld.long 0x00 4.--5. "EMODE,Endian mode" "0: Big endian mode,1: Half word big endian mode,2: Little endian mode,?..."
newline
bitfld.long 0x00 3. "D3CD,DATA3 as card detection pin" "0: DATA3 does not monitor card insertion,1: DATA3 as card detection pin"
newline
bitfld.long 0x00 1.--2. "DTW,Data transfer width" "0: 1-bit mode,1: 4-bit mode,2: 8-bit mode,?..."
group.long 0x2C++0x03
line.long 0x00 "SYS_CTRL,System Control"
bitfld.long 0x00 28. "RSTT,Reset tuning" "0,1"
newline
bitfld.long 0x00 27. "INITA,Initialization active" "0,1"
newline
bitfld.long 0x00 26. "RSTD,Software reset for data line" "0: No reset,1: RSTD_1"
newline
bitfld.long 0x00 25. "RSTC,Software reset for CMD line" "0: No reset,1: RSTC_1"
newline
bitfld.long 0x00 24. "RSTA,Software reset for all" "0: No reset,1: RSTA_1"
newline
bitfld.long 0x00 23. "IPP_RST_N,Hardware reset" "0,1"
newline
bitfld.long 0x00 16.--19. "DTOCV,Data timeout counter value" "0: SDCLK x 2 14,1: SDCLK x 2 15,2: SDCLK x 2 16,3: SDCLK x 2 17,4: SDCLK x 2 18,5: SDCLK x 2 19,6: SDCLK x 2 20,7: SDCLK x 2 21,8: SDCLK x 2 22,9: SDCLK x 2 23,10: SDCLK x 2 24,11: SDCLK x 2 25,12: SDCLK x 2 26,13: SDCLK x 2 27,14: SDCLK x 2 28,15: SDCLK x 2 29 + SDCLK x 2 28 + SDCLK x 2 27 +.."
newline
hexmask.long.byte 0x00 8.--15. 1. "SDCLKFS,SDCLK frequency select"
newline
bitfld.long 0x00 4.--7. "DVS,Divisor" "0: Divide-by-1,1: Divide-by-2,?,?,?,?,?,?,?,?,?,?,?,?,14: Divide-by-15,15: Divide-by-16"
group.long 0x30++0x03
line.long 0x00 "INT_STATUS,Interrupt Status"
eventfld.long 0x00 28. "DMAE,DMA error" "0: No error,1: DMAE_1"
newline
eventfld.long 0x00 26. "TNE,Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
newline
eventfld.long 0x00 24. "AC12E,Auto CMD12 error" "0: No error,1: AC12E_1"
newline
eventfld.long 0x00 22. "DEBE,Data end bit error" "0: No error,1: DEBE_1"
newline
eventfld.long 0x00 21. "DCE,Data CRC error" "0: No error,1: DCE_1"
newline
eventfld.long 0x00 20. "DTOE,Data timeout error" "0: No error,1: Time out"
newline
eventfld.long 0x00 19. "CIE,Command index error" "0: No error,1: CIE_1"
newline
eventfld.long 0x00 18. "CEBE,Command end bit error" "0: No error,1: End bit error generated"
newline
eventfld.long 0x00 17. "CCE,Command CRC error" "0: No error,1: CRC error generated"
newline
eventfld.long 0x00 16. "CTOE,Command timeout error" "0: No error,1: Time out"
newline
eventfld.long 0x00 14. "TP,Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
newline
eventfld.long 0x00 12. "RTE,Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Re-tuning is not required,1: Re-tuning should be performed"
newline
eventfld.long 0x00 8. "CINT,Card interrupt" "0: No card interrupt,1: Generate card interrupt"
newline
eventfld.long 0x00 7. "CRM,Card removal" "0: Card state unstable or inserted,1: Card removed"
newline
eventfld.long 0x00 6. "CINS,Card insertion" "0: Card state unstable or removed,1: Card inserted"
newline
eventfld.long 0x00 5. "BRR,Buffer read ready" "0: Not ready to read buffer,1: Ready to read buffer"
newline
eventfld.long 0x00 4. "BWR,Buffer write ready" "0: Not ready to write buffer,1: Ready to write buffer"
newline
eventfld.long 0x00 3. "DINT,DMA interrupt" "0: No DMA interrupt,1: DMA interrupt is generated"
newline
eventfld.long 0x00 2. "BGE,Block gap event" "0: No block gap event,1: Transaction stopped at block gap"
newline
eventfld.long 0x00 1. "TC,Transfer complete" "0: Transfer does not complete,1: Transfer complete"
newline
eventfld.long 0x00 0. "CC,Command complete" "0: Command not complete,1: Command complete"
group.long 0x34++0x03
line.long 0x00 "INT_STATUS_EN,Interrupt Status Enable"
bitfld.long 0x00 28. "DMAESEN,DMA error status enable" "0: DMAESEN_0,1: DMAESEN_1"
newline
bitfld.long 0x00 26. "TNESEN,Tuning error status enable" "0: TNESEN_0,1: TNESEN_1"
newline
bitfld.long 0x00 24. "AC12ESEN,Auto CMD12 error status enable" "0: AC12ESEN_0,1: AC12ESEN_1"
newline
bitfld.long 0x00 22. "DEBESEN,Data end bit error status enable" "0: DEBESEN_0,1: DEBESEN_1"
newline
bitfld.long 0x00 21. "DCESEN,Data CRC error status enable" "0: DCESEN_0,1: DCESEN_1"
newline
bitfld.long 0x00 20. "DTOESEN,Data timeout error status enable" "0: DTOESEN_0,1: DTOESEN_1"
newline
bitfld.long 0x00 19. "CIESEN,Command index error status enable" "0: CIESEN_0,1: CIESEN_1"
newline
bitfld.long 0x00 18. "CEBESEN,Command end bit error status enable" "0: CEBESEN_0,1: CEBESEN_1"
newline
bitfld.long 0x00 17. "CCESEN,Command CRC error status enable" "0: CCESEN_0,1: CCESEN_1"
newline
bitfld.long 0x00 16. "CTOESEN,Command timeout error status enable" "0: CTOESEN_0,1: CTOESEN_1"
newline
bitfld.long 0x00 14. "TPSEN,Tuning pass status enable" "0: TPSEN_0,1: TPSEN_1"
newline
bitfld.long 0x00 12. "RTESEN,Re-tuning event status enable" "0: RTESEN_0,1: RTESEN_1"
newline
bitfld.long 0x00 8. "CINTSEN,Card interrupt status enable" "0: CINTSEN_0,1: CINTSEN_1"
newline
bitfld.long 0x00 7. "CRMSEN,Card removal status enable" "0: CRMSEN_0,1: CRMSEN_1"
newline
bitfld.long 0x00 6. "CINSSEN,Card insertion status enable" "0: CINSSEN_0,1: CINSSEN_1"
newline
bitfld.long 0x00 5. "BRRSEN,Buffer read ready status enable" "0: BRRSEN_0,1: BRRSEN_1"
newline
bitfld.long 0x00 4. "BWRSEN,Buffer write ready status enable" "0: BWRSEN_0,1: BWRSEN_1"
newline
bitfld.long 0x00 3. "DINTSEN,DMA interrupt status enable" "0: DINTSEN_0,1: DINTSEN_1"
newline
bitfld.long 0x00 2. "BGESEN,Block gap event status enable" "0: BGESEN_0,1: BGESEN_1"
newline
bitfld.long 0x00 1. "TCSEN,Transfer complete status enable" "0: TCSEN_0,1: TCSEN_1"
newline
bitfld.long 0x00 0. "CCSEN,Command complete status enable" "0: CCSEN_0,1: CCSEN_1"
group.long 0x38++0x03
line.long 0x00 "INT_SIGNAL_EN,Interrupt Signal Enable"
bitfld.long 0x00 28. "DMAEIEN,DMA error interrupt enable" "0: DMAEIEN_0,1: DMAEIEN_1"
newline
bitfld.long 0x00 26. "TNEIEN,Tuning error interrupt enable" "0: TNEIEN_0,1: TNEIEN_1"
newline
bitfld.long 0x00 24. "AC12EIEN,Auto CMD12 error interrupt enable" "0: AC12EIEN_0,1: AC12EIEN_1"
newline
bitfld.long 0x00 22. "DEBEIEN,Data end bit error interrupt enable" "0: DEBEIEN_0,1: DEBEIEN_1"
newline
bitfld.long 0x00 21. "DCEIEN,Data CRC error interrupt enable" "0: DCEIEN_0,1: DCEIEN_1"
newline
bitfld.long 0x00 20. "DTOEIEN,Data timeout error interrupt enable" "0: DTOEIEN_0,1: DTOEIEN_1"
newline
bitfld.long 0x00 19. "CIEIEN,Command index error interrupt enable" "0: CIEIEN_0,1: CIEIEN_1"
newline
bitfld.long 0x00 18. "CEBEIEN,Command end bit error interrupt enable" "0: CEBEIEN_0,1: CEBEIEN_1"
newline
bitfld.long 0x00 17. "CCEIEN,Command CRC error interrupt enable" "0: CCEIEN_0,1: CCEIEN_1"
newline
bitfld.long 0x00 16. "CTOEIEN,Command timeout error interrupt enable" "0: CTOEIEN_0,1: CTOEIEN_1"
newline
bitfld.long 0x00 14. "TPIEN,Tuning Pass interrupt enable" "0: TPIEN_0,1: TPIEN_1"
newline
bitfld.long 0x00 12. "RTEIEN,Re-tuning event interrupt enable" "0: RTEIEN_0,1: RTEIEN_1"
newline
bitfld.long 0x00 8. "CINTIEN,Card interrupt enable" "0: CINTIEN_0,1: CINTIEN_1"
newline
bitfld.long 0x00 7. "CRMIEN,Card removal interrupt enable" "0: CRMIEN_0,1: CRMIEN_1"
newline
bitfld.long 0x00 6. "CINSIEN,Card insertion interrupt enable" "0: CINSIEN_0,1: CINSIEN_1"
newline
bitfld.long 0x00 5. "BRRIEN,Buffer read ready interrupt enable" "0: BRRIEN_0,1: BRRIEN_1"
newline
bitfld.long 0x00 4. "BWRIEN,Buffer write ready interrupt enable" "0: BWRIEN_0,1: BWRIEN_1"
newline
bitfld.long 0x00 3. "DINTIEN,DMA interrupt enable" "0: DINTIEN_0,1: DINTIEN_1"
newline
bitfld.long 0x00 2. "BGEIEN,Block gap event interrupt enable" "0: BGEIEN_0,1: BGEIEN_1"
newline
bitfld.long 0x00 1. "TCIEN,Transfer complete interrupt enable" "0: TCIEN_0,1: TCIEN_1"
newline
bitfld.long 0x00 0. "CCIEN,Command complete interrupt enable" "0: CCIEN_0,1: CCIEN_1"
group.long 0x3C++0x03
line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status"
bitfld.long 0x00 23. "SMP_CLK_SEL,Sample clock select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
newline
bitfld.long 0x00 22. "EXECUTE_TUNING,Execute tuning" "0,1"
newline
rbitfld.long 0x00 7. "CNIBAC12E,Command not issued by Auto CMD12 error" "0: CNIBAC12E_0,1: CNIBAC12E_1"
newline
rbitfld.long 0x00 4. "AC12IE,Auto CMD12 / 23 index error" "0: AC12IE_0,1: Error the CMD index in response is not CMD12/23"
newline
rbitfld.long 0x00 3. "AC12CE,Auto CMD12 / 23 CRC error" "0: No CRC error,1: CRC error met in Auto CMD12/23 response"
newline
rbitfld.long 0x00 2. "AC12EBE,Auto CMD12 / 23 end bit error" "0: AC12EBE_0,1: End bit error generated"
newline
rbitfld.long 0x00 1. "AC12TOE,Auto CMD12 / 23 timeout error" "0: AC12TOE_0,1: AC12TOE_1"
newline
rbitfld.long 0x00 0. "AC12NE,Auto CMD12 not executed" "0: AC12NE_0,1: Not executed"
group.long 0x40++0x03
line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities"
rbitfld.long 0x00 26. "VS18,Voltage support 1.8 V" "0: 1.8 V not supported,1: 1.8 V supported"
newline
rbitfld.long 0x00 25. "VS30,Voltage support 3.0 V" "0: 3.0 V not supported,1: 3.0 V supported"
newline
rbitfld.long 0x00 24. "VS33,Voltage support 3.3 V" "0: 3.3 V not supported,1: 3.3 V supported"
newline
rbitfld.long 0x00 23. "SRS,Suspend / resume support" "0: Not supported,1: Supported"
newline
rbitfld.long 0x00 22. "DMAS,DMA support" "0: DMA not supported,1: DMA supported"
newline
rbitfld.long 0x00 21. "HSS,High speed support" "0: High speed not supported,1: High speed supported"
newline
rbitfld.long 0x00 20. "ADMAS,ADMA support" "0: Advanced DMA not supported,1: Advanced DMA supported"
newline
rbitfld.long 0x00 16.--18. "MBL,Max block length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,3: 4096 bytes,?..."
newline
rbitfld.long 0x00 14.--15. "RETUNING_MODE,Retuning Mode" "0: RETUNING_MODE_0,1: RETUNING_MODE_1,2: RETUNING_MODE_2,?..."
newline
bitfld.long 0x00 13. "USE_TUNING_SDR50,Use Tuning for SDR50" "0: SDR does not require tuning,1: SDR50 requires tuning"
newline
bitfld.long 0x00 8.--11. "TIME_COUNT_RETUNING,Time counter for retuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2. "DDR50_SUPPORT,DDR50 support" "0,1"
newline
rbitfld.long 0x00 1. "SDR104_SUPPORT,SDR104 support" "0,1"
newline
rbitfld.long 0x00 0. "SDR50_SUPPORT,SDR50 support" "0,1"
group.long 0x44++0x03
line.long 0x00 "WTMK_LVL,Watermark Level"
bitfld.long 0x00 24.--28. "WR_BRST_LEN,Write burst length due to system restriction the actual burst length might not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 16.--23. 1. "WR_WML,Write watermark level"
newline
bitfld.long 0x00 8.--12. "RD_BRST_LEN,Read burst length due to system restriction the actual burst length might not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 0.--7. 1. "RD_WML,Read watermark level"
group.long 0x48++0x03
line.long 0x00 "MIX_CTRL,Mixer Control"
bitfld.long 0x00 26. "HS400_MODE,Enable HS400 mode" "0,1"
newline
bitfld.long 0x00 25. "FBCLK_SEL,Feedback clock source selection (Only used for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Feedback clock comes from the loopback CLK,1: Feedback clock comes from the ipp_card_clk_out"
newline
bitfld.long 0x00 24. "AUTO_TUNE_EN,Auto tuning enable (Only used for SD3.0 SDR104 mode and and EMMC HS200 mode)" "0: Disable auto tuning,1: Enable auto tuning"
newline
bitfld.long 0x00 23. "SMP_CLK_SEL,Clock selection" "0: Fixed clock is used to sample data / cmd,1: Tuned clock is used to sample data / cmd"
newline
bitfld.long 0x00 22. "EXE_TUNE,Execute tuning: (Only used for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Not tuned or tuning completed,1: Execute tuning"
newline
bitfld.long 0x00 7. "AC23EN,Auto CMD23 enable" "0,1"
newline
bitfld.long 0x00 6. "NIBBLE_POS,Nibble position indication" "0,1"
newline
bitfld.long 0x00 5. "MSBSEL,Multi / Single block select" "0: Single block,1: Multiple blocks"
newline
bitfld.long 0x00 4. "DTDSEL,Data transfer direction select" "0: Write (Host to card),1: Read (Card to host)"
newline
bitfld.long 0x00 3. "DDR_EN,Dual data rate mode selection" "0,1"
newline
bitfld.long 0x00 2. "AC12EN,Auto CMD12 enable" "0: AC12EN_0,1: AC12EN_1"
newline
bitfld.long 0x00 1. "BCEN,Block count enable" "0: Disable,1: BCEN_1"
newline
bitfld.long 0x00 0. "DMAEN,DMA enable" "0: DMAEN_0,1: DMAEN_1"
group.long 0x50++0x03
line.long 0x00 "FORCE_EVENT,Force Event"
bitfld.long 0x00 31. "FEVTCINT,Force event card interrupt" "0,1"
newline
bitfld.long 0x00 28. "FEVTDMAE,Force event DMA error" "0,1"
newline
bitfld.long 0x00 26. "FEVTTNE,Force tuning error" "0,1"
newline
bitfld.long 0x00 24. "FEVTAC12E,Force event Auto Command 12 error" "0,1"
newline
bitfld.long 0x00 22. "FEVTDEBE,Force event data end bit error" "0,1"
newline
bitfld.long 0x00 21. "FEVTDCE,Force event data CRC error" "0,1"
newline
bitfld.long 0x00 20. "FEVTDTOE,Force event data time out error" "0,1"
newline
bitfld.long 0x00 19. "FEVTCIE,Force event command index error" "0,1"
newline
bitfld.long 0x00 18. "FEVTCEBE,Force event command end bit error" "0,1"
newline
bitfld.long 0x00 17. "FEVTCCE,Force event command CRC error" "0,1"
newline
bitfld.long 0x00 16. "FEVTCTOE,Force event command time out error" "0,1"
newline
bitfld.long 0x00 7. "FEVTCNIBAC12E,Force event command not executed by Auto Command 12 error" "0,1"
newline
bitfld.long 0x00 4. "FEVTAC12IE,Force event Auto Command 12 index error" "0,1"
newline
bitfld.long 0x00 3. "FEVTAC12EBE,Force event Auto Command 12 end bit error" "0,1"
newline
bitfld.long 0x00 2. "FEVTAC12CE,Force event auto command 12 CRC error" "0,1"
newline
bitfld.long 0x00 1. "FEVTAC12TOE,Force event auto command 12 time out error" "0,1"
newline
bitfld.long 0x00 0. "FEVTAC12NE,Force event auto command 12 not executed" "0,1"
rgroup.long 0x54++0x03
line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status"
bitfld.long 0x00 3. "ADMADCE,ADMA descriptor error" "0: ADMADCE_0,1: ADMADCE_1"
newline
bitfld.long 0x00 2. "ADMALME,ADMA length mismatch error" "0: ADMALME_0,1: ADMALME_1"
newline
bitfld.long 0x00 0.--1. "ADMAES,ADMA error state (when ADMA error is occurred)" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address"
hexmask.long 0x00 2.--31. 1. "ADS_ADDR,ADMA system address"
group.long 0x60++0x03
line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control"
bitfld.long 0x00 28.--31. "DLL_CTRL_REF_UPDATE_INT,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 20.--27. 1. "DLL_CTRL_SLV_UPDATE_INT,Slave delay line update interval"
newline
bitfld.long 0x00 16.--18. "DLL_CTRL_SLV_DLY_TARGET1,DLL slave delay target1" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 9.--15. 1. "DLL_CTRL_SLV_OVERRIDE_VAL,DLL slave override val"
newline
bitfld.long 0x00 8. "DLL_CTRL_SLV_OVERRIDE,DLL slave override" "0,1"
newline
bitfld.long 0x00 7. "DLL_CTRL_GATE_UPDATE,DLL gate update" "0,1"
newline
bitfld.long 0x00 3.--6. "DLL_CTRL_SLV_DLY_TARGET0,DLL slave delay target0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "DLL_CTRL_SLV_FORCE_UPD,DLL slave delay line" "0,1"
newline
bitfld.long 0x00 1. "DLL_CTRL_RESET,DLL reset" "0,1"
newline
bitfld.long 0x00 0. "DLL_CTRL_ENABLE,DLL and delay chain" "0,1"
rgroup.long 0x64++0x03
line.long 0x00 "DLL_STATUS,DLL Status"
hexmask.long.byte 0x00 9.--15. 1. "DLL_STS_REF_SEL,Reference delay line select taps"
newline
hexmask.long.byte 0x00 2.--8. 1. "DLL_STS_SLV_SEL,Slave delay line select status"
newline
bitfld.long 0x00 1. "DLL_STS_REF_LOCK,Reference DLL lock status" "0,1"
newline
bitfld.long 0x00 0. "DLL_STS_SLV_LOCK,Slave delay-line lock status" "0,1"
group.long 0x68++0x03
line.long 0x00 "CLK_TUNE_CTRL_STATUS,CLK Tuning Control and Status"
rbitfld.long 0x00 31. "PRE_ERR,PRE error" "0,1"
newline
hexmask.long.byte 0x00 24.--30. 1. "TAP_SEL_PRE,TAP_SEL_PRE"
newline
rbitfld.long 0x00 20.--23. "TAP_SEL_OUT,Delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TAP_SEL_POST,Delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 15. "NXT_ERR,NXT error" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "DLY_CELL_SET_PRE,delay cells on the feedback clock between the feedback clock and CLK_PRE"
newline
bitfld.long 0x00 4.--7. "DLY_CELL_SET_OUT,Delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DLY_CELL_SET_POST,Delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x03
line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL control"
bitfld.long 0x00 28.--31. "STROBE_DLL_CTRL_REF_UPDATE_INT,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 20.--27. 1. "STROBE_DLL_CTRL_SLV_UPDATE_INT,Strobe DLL control slave update interval"
newline
hexmask.long.byte 0x00 9.--15. 1. "STROBE_DLL_CTRL_SLV_OVERRIDE_VAL,Strobe DLL control slave Override value"
newline
bitfld.long 0x00 8. "STROBE_DLL_CTRL_SLV_OVERRIDE,Strobe DLL control slave override" "0,1"
newline
bitfld.long 0x00 7. "STROBE_DLL_CTRL_GATE_UPDATE_1,Strobe DLL control gate update" "0,1"
newline
bitfld.long 0x00 6. "STROBE_DLL_CTRL_GATE_UPDATE_0,Strobe DLL control gate update" "0,1"
newline
bitfld.long 0x00 3.--5. "STROBE_DLL_CTRL_SLV_DLY_TARGET,Strobe DLL Control Slave Delay Target" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2. "STROBE_DLL_CTRL_SLV_FORCE_UPD,Strobe DLL control slave force updated" "0,1"
newline
bitfld.long 0x00 1. "STROBE_DLL_CTRL_RESET,Strobe DLL control reset" "0,1"
newline
bitfld.long 0x00 0. "STROBE_DLL_CTRL_ENABLE,Strobe DLL control enable" "0,1"
rgroup.long 0x74++0x03
line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL status"
hexmask.long.byte 0x00 9.--15. 1. "STROBE_DLL_STS_REF_SEL,Strobe DLL status reference select"
newline
hexmask.long.byte 0x00 2.--8. 1. "STROBE_DLL_STS_SLV_SEL,Strobe DLL status slave select"
newline
bitfld.long 0x00 1. "STROBE_DLL_STS_REF_LOCK,Strobe DLL status reference lock" "0,1"
newline
bitfld.long 0x00 0. "STROBE_DLL_STS_SLV_LOCK,Strobe DLL status slave lock" "0,1"
group.long 0xC0++0x03
line.long 0x00 "VEND_SPEC,Vendor Specific Register"
bitfld.long 0x00 31. "CMD_BYTE_EN,Byte access" "0: CMD_BYTE_EN_0,1: CMD_BYTE_EN_1"
newline
bitfld.long 0x00 15. "CRC_CHK_DIS,CRC Check Disable" "0: Check CRC16 for every read data packet and..,1: Ignore CRC16 check for every read data packet.."
newline
bitfld.long 0x00 8. "FRC_SDCLK_ON,Force CLK" "0: CLK active or inactive is fully controlled by..,1: Force CLK active"
newline
bitfld.long 0x00 3. "AC12_WR_CHKBUSY_EN,Check busy enable" "0: Do not check busy after auto CMD12 for write..,1: Check busy after auto CMD12 for write data.."
newline
bitfld.long 0x00 2. "CONFLICT_CHK_EN,Conflict check enable" "0: Conflict check disable,1: Conflict check enable"
newline
bitfld.long 0x00 1. "VSELECT,Voltage selection" "0: Change the voltage to high voltage range..,1: Change the voltage to low voltage range.."
group.long 0xC4++0x03
line.long 0x00 "MMC_BOOT,MMC Boot"
hexmask.long.word 0x00 16.--31. 1. "BOOT_BLK_CNT,Stop At Block Gap value of automatic mode"
newline
bitfld.long 0x00 8. "DISABLE_TIME_OUT,Time out" "0: DISABLE_TIME_OUT_0,1: DISABLE_TIME_OUT_1"
newline
bitfld.long 0x00 7. "AUTO_SABG_EN,Auto stop at block gap" "0,1"
newline
bitfld.long 0x00 6. "BOOT_EN,Boot enable" "0: Fast boot disable,1: Fast boot enable"
newline
bitfld.long 0x00 5. "BOOT_MODE,Boot mode" "0: BOOT_MODE_0,1: Alternative boot"
newline
bitfld.long 0x00 4. "BOOT_ACK,BOOT ACK" "0: BOOT_ACK_0,1: BOOT_ACK_1"
newline
bitfld.long 0x00 0.--3. "DTOCV_ACK,Boot ACK time out" "0: SDCLK x 2^14,1: SDCLK x 2^15,2: SDCLK x 2^16,3: SDCLK x 2^17,4: SDCLK x 2^18,5: SDCLK x 2^19,6: SDCLK x 2^20,7: SDCLK x 2^21,?,?,?,?,?,?,14: DTOCV_ACK_14,15: DTOCV_ACK_15"
group.long 0xC8++0x03
line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register"
bitfld.long 0x00 12. "ACMD23_ARGU2_EN,Argument2 register enable for ACMD23" "0: ACMD23_ARGU2_EN_0,1: Argument2 register enable for ACMD23 sharing.."
newline
bitfld.long 0x00 11. "HS400_RD_CLK_STOP_EN,HS400 read clock stop enable" "0,1"
newline
bitfld.long 0x00 10. "HS400_WR_CLK_STOP_EN,HS400 write clock stop enable" "0,1"
newline
bitfld.long 0x00 6. "TUNING_CMD_EN,Tuning command enable" "0: Auto tuning circuit does not check the CMD line,1: Auto tuning circuit checks the CMD line"
newline
bitfld.long 0x00 5. "TUNING_1bit_EN,Tuning 1bit enable" "0,1"
newline
bitfld.long 0x00 4. "TUNING_8bit_EN,Tuning 8bit enable" "0,1"
newline
bitfld.long 0x00 3. "CARD_INT_D3_TEST,Card interrupt detection test" "0: Check the card interrupt only when DATA3 is..,1: Check the card interrupt by ignoring the.."
group.long 0xCC++0x03
line.long 0x00 "TUNING_CTRL,Tuning Control"
bitfld.long 0x00 24. "STD_TUNING_EN,Standard tuning circuit and procedure enable" "0,1"
newline
bitfld.long 0x00 20.--22. "TUNING_WINDOW,Data window" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "TUNING_STEP,TUNING_STEP" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 8.--15. 1. "TUNING_COUNTER,Tuning counter"
newline
hexmask.long.byte 0x00 0.--7. 1. "TUNING_START_TAP,Tuning start"
tree.end
tree "USDHC1"
base ad:0x40137000
group.long 0x00++0x03
line.long 0x00 "DS_ADDR,DMA System Address"
hexmask.long 0x00 0.--31. 1. "DS_ADDR,System address"
group.long 0x04++0x03
line.long 0x00 "BLK_ATT,Block Attributes"
hexmask.long.word 0x00 16.--31. 1. "BLKCNT,Blocks count for current transfer"
newline
hexmask.long.word 0x00 0.--12. 1. "BLKSIZE,Transfer block size"
group.long 0x08++0x03
line.long 0x00 "CMD_ARG,Command Argument"
hexmask.long 0x00 0.--31. 1. "CMDARG,Command argument"
group.long 0x0C++0x03
line.long 0x00 "CMD_XFR_TYP,Command Transfer Type"
bitfld.long 0x00 24.--29. "CMDINX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 22.--23. "CMDTYP,Command type" "0: Normal other commands,1: Suspend CMD52 for writing bus suspend in CCCR,2: Resume CMD52 for writing function select in..,3: Abort CMD12 CMD52 for writing I/O Abort in CCCR"
newline
bitfld.long 0x00 21. "DPSEL,Data present select" "0: No data present,1: Data present"
newline
bitfld.long 0x00 20. "CICEN,Command index check enable" "0: Disable command index check,1: Enables command index check"
newline
bitfld.long 0x00 19. "CCCEN,Command CRC check enable" "0: Disables command CRC check,1: Enables command CRC check"
newline
bitfld.long 0x00 16.--17. "RSPTYP,Response type select" "0: No response,1: Response length 136,2: Response length 48,3: Response length 48 check busy after response"
rgroup.long 0x10++0x03
line.long 0x00 "CMD_RSP0,Command Response0"
hexmask.long 0x00 0.--31. 1. "CMDRSP0,Command response 0"
rgroup.long 0x14++0x03
line.long 0x00 "CMD_RSP1,Command Response1"
hexmask.long 0x00 0.--31. 1. "CMDRSP1,Command response 1"
rgroup.long 0x18++0x03
line.long 0x00 "CMD_RSP2,Command Response2"
hexmask.long 0x00 0.--31. 1. "CMDRSP2,Command response 2"
rgroup.long 0x1C++0x03
line.long 0x00 "CMD_RSP3,Command Response3"
hexmask.long 0x00 0.--31. 1. "CMDRSP3,Command response 3"
group.long 0x20++0x03
line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port"
hexmask.long 0x00 0.--31. 1. "DATCONT,Data content"
rgroup.long 0x24++0x03
line.long 0x00 "PRES_STATE,Present State"
hexmask.long.byte 0x00 24.--31. 1. "DLSL,DATA[7:0] line signal level"
newline
bitfld.long 0x00 23. "CLSL,CMD line signal level" "0,1"
newline
bitfld.long 0x00 19. "WPSPL,Write protect switch pin level" "0: Write protected (WP = 1),1: Write enabled (WP = 0)"
newline
bitfld.long 0x00 18. "CDPL,Card detect pin level" "0: No card present (CD_B = 1),1: Card present (CD_B = 0)"
newline
bitfld.long 0x00 16. "CINST,Card inserted" "0: Power on reset or no card,1: Card inserted"
newline
bitfld.long 0x00 15. "TSCD,Tape select change done" "0: Delay cell select change is not finished,1: Delay cell select change is finished"
newline
bitfld.long 0x00 12. "RTR,Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Fixed or well tuned sampling clock,1: Sampling clock needs re-tuning"
newline
bitfld.long 0x00 11. "BREN,Buffer read enable" "0: Read disable,1: Read enable"
newline
bitfld.long 0x00 10. "BWEN,Buffer write enable" "0: Write disable,1: Write enable"
newline
bitfld.long 0x00 9. "RTA,Read transfer active" "0: No valid data,1: Transferring data"
newline
bitfld.long 0x00 8. "WTA,Write transfer active" "0: No valid data,1: Transferring data"
newline
bitfld.long 0x00 7. "SDOFF,SD clock gated off internally" "0: SD clock is active,1: SD clock is gated off"
newline
bitfld.long 0x00 6. "PEROFF,IPG_PERCLK gated off internally" "0: IPG_PERCLK is active,1: IPG_PERCLK is gated off"
newline
bitfld.long 0x00 5. "HCKOFF,HCLK gated off internally" "0: HCLK is active,1: HCLK is gated off"
newline
bitfld.long 0x00 4. "IPGOFF,Peripheral clock gated off internally" "0: Peripheral clock is active,1: Peripheral clock is gated off"
newline
bitfld.long 0x00 3. "SDSTB,SD clock stable" "0: Clock is changing frequency and not stable,1: Clock is stable"
newline
bitfld.long 0x00 2. "DLA,Data line active" "0: DATA line inactive,1: DATA line active"
newline
bitfld.long 0x00 1. "CDIHB,Command inhibit (DATA)" "0: Can issue command that uses the DATA line,1: Cannot issue command that uses the DATA line"
newline
bitfld.long 0x00 0. "CIHB,Command inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
group.long 0x28++0x03
line.long 0x00 "PROT_CTRL,Protocol Control"
bitfld.long 0x00 30. "NON_EXACT_BLK_RD,Non-exact block" "0: The block read is exact block,1: The block read is non-exact block"
newline
bitfld.long 0x00 27.--29. "BURST_LEN_EN,BURST length enable for INCR INCR4 / INCR8 / INCR16 INCR4-WRAP / INCR8-WRAP / INCR16-WRAP" "?,1: Burst length is enabled for INCR,?,3: Burst length is enabled for INCR,?,5: Burst length is enabled for INCR,?,7: Burst length is enabled for INCR"
newline
bitfld.long 0x00 26. "WECRM,Wakeup event enable on SD card removal" "0: Disables wakeup event enable on SD card removal,1: Enables wakeup event enable on SD card removal"
newline
bitfld.long 0x00 25. "WECINS,Wakeup event enable on SD card insertion" "0: Disable wakeup event enable on SD card..,1: Enable wakeup event enable on SD card insertion"
newline
bitfld.long 0x00 24. "WECINT,Wakeup event enable on card interrupt" "0: Disables wakeup event enable on card interrupt,1: Enables wakeup event enable on card interrupt"
newline
bitfld.long 0x00 20. "RD_DONE_NO_8CLK,Read performed number 8 clock" "0,1"
newline
bitfld.long 0x00 19. "IABG,Interrupt at block gap" "0: Disables interrupt at block gap,1: Enables interrupt at block gap"
newline
bitfld.long 0x00 18. "RWCTL,Read wait control" "0: Disables read wait control and stop SD clock..,1: Enables read wait control and assert read.."
newline
bitfld.long 0x00 17. "CREQ,Continue request" "0: No effect,1: Restart"
newline
bitfld.long 0x00 16. "SABGREQ,Stop at block gap request" "0: SABGREQ_0,1: SABGREQ_1"
newline
bitfld.long 0x00 8.--9. "DMASEL,DMA select" "0: No DMA or simple DMA is selected,1: ADMA1 is selected,2: ADMA2 is selected,?..."
newline
bitfld.long 0x00 7. "CDSS,Card detect signal selection" "0: Card detection level is selected (for normal..,1: Card detection test level is selected (for.."
newline
bitfld.long 0x00 6. "CDTL,Card detect test level" "0: Card detect test level is 0 no card inserted,1: Card detect test level is 1 card inserted"
newline
bitfld.long 0x00 4.--5. "EMODE,Endian mode" "0: Big endian mode,1: Half word big endian mode,2: Little endian mode,?..."
newline
bitfld.long 0x00 3. "D3CD,DATA3 as card detection pin" "0: DATA3 does not monitor card insertion,1: DATA3 as card detection pin"
newline
bitfld.long 0x00 1.--2. "DTW,Data transfer width" "0: 1-bit mode,1: 4-bit mode,2: 8-bit mode,?..."
group.long 0x2C++0x03
line.long 0x00 "SYS_CTRL,System Control"
bitfld.long 0x00 28. "RSTT,Reset tuning" "0,1"
newline
bitfld.long 0x00 27. "INITA,Initialization active" "0,1"
newline
bitfld.long 0x00 26. "RSTD,Software reset for data line" "0: No reset,1: RSTD_1"
newline
bitfld.long 0x00 25. "RSTC,Software reset for CMD line" "0: No reset,1: RSTC_1"
newline
bitfld.long 0x00 24. "RSTA,Software reset for all" "0: No reset,1: RSTA_1"
newline
bitfld.long 0x00 23. "IPP_RST_N,Hardware reset" "0,1"
newline
bitfld.long 0x00 16.--19. "DTOCV,Data timeout counter value" "0: SDCLK x 2 14,1: SDCLK x 2 15,2: SDCLK x 2 16,3: SDCLK x 2 17,4: SDCLK x 2 18,5: SDCLK x 2 19,6: SDCLK x 2 20,7: SDCLK x 2 21,8: SDCLK x 2 22,9: SDCLK x 2 23,10: SDCLK x 2 24,11: SDCLK x 2 25,12: SDCLK x 2 26,13: SDCLK x 2 27,14: SDCLK x 2 28,15: SDCLK x 2 29 + SDCLK x 2 28 + SDCLK x 2 27 +.."
newline
hexmask.long.byte 0x00 8.--15. 1. "SDCLKFS,SDCLK frequency select"
newline
bitfld.long 0x00 4.--7. "DVS,Divisor" "0: Divide-by-1,1: Divide-by-2,?,?,?,?,?,?,?,?,?,?,?,?,14: Divide-by-15,15: Divide-by-16"
group.long 0x30++0x03
line.long 0x00 "INT_STATUS,Interrupt Status"
eventfld.long 0x00 28. "DMAE,DMA error" "0: No error,1: DMAE_1"
newline
eventfld.long 0x00 26. "TNE,Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
newline
eventfld.long 0x00 24. "AC12E,Auto CMD12 error" "0: No error,1: AC12E_1"
newline
eventfld.long 0x00 22. "DEBE,Data end bit error" "0: No error,1: DEBE_1"
newline
eventfld.long 0x00 21. "DCE,Data CRC error" "0: No error,1: DCE_1"
newline
eventfld.long 0x00 20. "DTOE,Data timeout error" "0: No error,1: Time out"
newline
eventfld.long 0x00 19. "CIE,Command index error" "0: No error,1: CIE_1"
newline
eventfld.long 0x00 18. "CEBE,Command end bit error" "0: No error,1: End bit error generated"
newline
eventfld.long 0x00 17. "CCE,Command CRC error" "0: No error,1: CRC error generated"
newline
eventfld.long 0x00 16. "CTOE,Command timeout error" "0: No error,1: Time out"
newline
eventfld.long 0x00 14. "TP,Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
newline
eventfld.long 0x00 12. "RTE,Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Re-tuning is not required,1: Re-tuning should be performed"
newline
eventfld.long 0x00 8. "CINT,Card interrupt" "0: No card interrupt,1: Generate card interrupt"
newline
eventfld.long 0x00 7. "CRM,Card removal" "0: Card state unstable or inserted,1: Card removed"
newline
eventfld.long 0x00 6. "CINS,Card insertion" "0: Card state unstable or removed,1: Card inserted"
newline
eventfld.long 0x00 5. "BRR,Buffer read ready" "0: Not ready to read buffer,1: Ready to read buffer"
newline
eventfld.long 0x00 4. "BWR,Buffer write ready" "0: Not ready to write buffer,1: Ready to write buffer"
newline
eventfld.long 0x00 3. "DINT,DMA interrupt" "0: No DMA interrupt,1: DMA interrupt is generated"
newline
eventfld.long 0x00 2. "BGE,Block gap event" "0: No block gap event,1: Transaction stopped at block gap"
newline
eventfld.long 0x00 1. "TC,Transfer complete" "0: Transfer does not complete,1: Transfer complete"
newline
eventfld.long 0x00 0. "CC,Command complete" "0: Command not complete,1: Command complete"
group.long 0x34++0x03
line.long 0x00 "INT_STATUS_EN,Interrupt Status Enable"
bitfld.long 0x00 28. "DMAESEN,DMA error status enable" "0: DMAESEN_0,1: DMAESEN_1"
newline
bitfld.long 0x00 26. "TNESEN,Tuning error status enable" "0: TNESEN_0,1: TNESEN_1"
newline
bitfld.long 0x00 24. "AC12ESEN,Auto CMD12 error status enable" "0: AC12ESEN_0,1: AC12ESEN_1"
newline
bitfld.long 0x00 22. "DEBESEN,Data end bit error status enable" "0: DEBESEN_0,1: DEBESEN_1"
newline
bitfld.long 0x00 21. "DCESEN,Data CRC error status enable" "0: DCESEN_0,1: DCESEN_1"
newline
bitfld.long 0x00 20. "DTOESEN,Data timeout error status enable" "0: DTOESEN_0,1: DTOESEN_1"
newline
bitfld.long 0x00 19. "CIESEN,Command index error status enable" "0: CIESEN_0,1: CIESEN_1"
newline
bitfld.long 0x00 18. "CEBESEN,Command end bit error status enable" "0: CEBESEN_0,1: CEBESEN_1"
newline
bitfld.long 0x00 17. "CCESEN,Command CRC error status enable" "0: CCESEN_0,1: CCESEN_1"
newline
bitfld.long 0x00 16. "CTOESEN,Command timeout error status enable" "0: CTOESEN_0,1: CTOESEN_1"
newline
bitfld.long 0x00 14. "TPSEN,Tuning pass status enable" "0: TPSEN_0,1: TPSEN_1"
newline
bitfld.long 0x00 12. "RTESEN,Re-tuning event status enable" "0: RTESEN_0,1: RTESEN_1"
newline
bitfld.long 0x00 8. "CINTSEN,Card interrupt status enable" "0: CINTSEN_0,1: CINTSEN_1"
newline
bitfld.long 0x00 7. "CRMSEN,Card removal status enable" "0: CRMSEN_0,1: CRMSEN_1"
newline
bitfld.long 0x00 6. "CINSSEN,Card insertion status enable" "0: CINSSEN_0,1: CINSSEN_1"
newline
bitfld.long 0x00 5. "BRRSEN,Buffer read ready status enable" "0: BRRSEN_0,1: BRRSEN_1"
newline
bitfld.long 0x00 4. "BWRSEN,Buffer write ready status enable" "0: BWRSEN_0,1: BWRSEN_1"
newline
bitfld.long 0x00 3. "DINTSEN,DMA interrupt status enable" "0: DINTSEN_0,1: DINTSEN_1"
newline
bitfld.long 0x00 2. "BGESEN,Block gap event status enable" "0: BGESEN_0,1: BGESEN_1"
newline
bitfld.long 0x00 1. "TCSEN,Transfer complete status enable" "0: TCSEN_0,1: TCSEN_1"
newline
bitfld.long 0x00 0. "CCSEN,Command complete status enable" "0: CCSEN_0,1: CCSEN_1"
group.long 0x38++0x03
line.long 0x00 "INT_SIGNAL_EN,Interrupt Signal Enable"
bitfld.long 0x00 28. "DMAEIEN,DMA error interrupt enable" "0: DMAEIEN_0,1: DMAEIEN_1"
newline
bitfld.long 0x00 26. "TNEIEN,Tuning error interrupt enable" "0: TNEIEN_0,1: TNEIEN_1"
newline
bitfld.long 0x00 24. "AC12EIEN,Auto CMD12 error interrupt enable" "0: AC12EIEN_0,1: AC12EIEN_1"
newline
bitfld.long 0x00 22. "DEBEIEN,Data end bit error interrupt enable" "0: DEBEIEN_0,1: DEBEIEN_1"
newline
bitfld.long 0x00 21. "DCEIEN,Data CRC error interrupt enable" "0: DCEIEN_0,1: DCEIEN_1"
newline
bitfld.long 0x00 20. "DTOEIEN,Data timeout error interrupt enable" "0: DTOEIEN_0,1: DTOEIEN_1"
newline
bitfld.long 0x00 19. "CIEIEN,Command index error interrupt enable" "0: CIEIEN_0,1: CIEIEN_1"
newline
bitfld.long 0x00 18. "CEBEIEN,Command end bit error interrupt enable" "0: CEBEIEN_0,1: CEBEIEN_1"
newline
bitfld.long 0x00 17. "CCEIEN,Command CRC error interrupt enable" "0: CCEIEN_0,1: CCEIEN_1"
newline
bitfld.long 0x00 16. "CTOEIEN,Command timeout error interrupt enable" "0: CTOEIEN_0,1: CTOEIEN_1"
newline
bitfld.long 0x00 14. "TPIEN,Tuning Pass interrupt enable" "0: TPIEN_0,1: TPIEN_1"
newline
bitfld.long 0x00 12. "RTEIEN,Re-tuning event interrupt enable" "0: RTEIEN_0,1: RTEIEN_1"
newline
bitfld.long 0x00 8. "CINTIEN,Card interrupt enable" "0: CINTIEN_0,1: CINTIEN_1"
newline
bitfld.long 0x00 7. "CRMIEN,Card removal interrupt enable" "0: CRMIEN_0,1: CRMIEN_1"
newline
bitfld.long 0x00 6. "CINSIEN,Card insertion interrupt enable" "0: CINSIEN_0,1: CINSIEN_1"
newline
bitfld.long 0x00 5. "BRRIEN,Buffer read ready interrupt enable" "0: BRRIEN_0,1: BRRIEN_1"
newline
bitfld.long 0x00 4. "BWRIEN,Buffer write ready interrupt enable" "0: BWRIEN_0,1: BWRIEN_1"
newline
bitfld.long 0x00 3. "DINTIEN,DMA interrupt enable" "0: DINTIEN_0,1: DINTIEN_1"
newline
bitfld.long 0x00 2. "BGEIEN,Block gap event interrupt enable" "0: BGEIEN_0,1: BGEIEN_1"
newline
bitfld.long 0x00 1. "TCIEN,Transfer complete interrupt enable" "0: TCIEN_0,1: TCIEN_1"
newline
bitfld.long 0x00 0. "CCIEN,Command complete interrupt enable" "0: CCIEN_0,1: CCIEN_1"
group.long 0x3C++0x03
line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status"
bitfld.long 0x00 23. "SMP_CLK_SEL,Sample clock select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
newline
bitfld.long 0x00 22. "EXECUTE_TUNING,Execute tuning" "0,1"
newline
rbitfld.long 0x00 7. "CNIBAC12E,Command not issued by Auto CMD12 error" "0: CNIBAC12E_0,1: CNIBAC12E_1"
newline
rbitfld.long 0x00 4. "AC12IE,Auto CMD12 / 23 index error" "0: AC12IE_0,1: Error the CMD index in response is not CMD12/23"
newline
rbitfld.long 0x00 3. "AC12CE,Auto CMD12 / 23 CRC error" "0: No CRC error,1: CRC error met in Auto CMD12/23 response"
newline
rbitfld.long 0x00 2. "AC12EBE,Auto CMD12 / 23 end bit error" "0: AC12EBE_0,1: End bit error generated"
newline
rbitfld.long 0x00 1. "AC12TOE,Auto CMD12 / 23 timeout error" "0: AC12TOE_0,1: AC12TOE_1"
newline
rbitfld.long 0x00 0. "AC12NE,Auto CMD12 not executed" "0: AC12NE_0,1: Not executed"
group.long 0x40++0x03
line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities"
rbitfld.long 0x00 26. "VS18,Voltage support 1.8 V" "0: 1.8 V not supported,1: 1.8 V supported"
newline
rbitfld.long 0x00 25. "VS30,Voltage support 3.0 V" "0: 3.0 V not supported,1: 3.0 V supported"
newline
rbitfld.long 0x00 24. "VS33,Voltage support 3.3 V" "0: 3.3 V not supported,1: 3.3 V supported"
newline
rbitfld.long 0x00 23. "SRS,Suspend / resume support" "0: Not supported,1: Supported"
newline
rbitfld.long 0x00 22. "DMAS,DMA support" "0: DMA not supported,1: DMA supported"
newline
rbitfld.long 0x00 21. "HSS,High speed support" "0: High speed not supported,1: High speed supported"
newline
rbitfld.long 0x00 20. "ADMAS,ADMA support" "0: Advanced DMA not supported,1: Advanced DMA supported"
newline
rbitfld.long 0x00 16.--18. "MBL,Max block length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,3: 4096 bytes,?..."
newline
rbitfld.long 0x00 14.--15. "RETUNING_MODE,Retuning Mode" "0: RETUNING_MODE_0,1: RETUNING_MODE_1,2: RETUNING_MODE_2,?..."
newline
bitfld.long 0x00 13. "USE_TUNING_SDR50,Use Tuning for SDR50" "0: SDR does not require tuning,1: SDR50 requires tuning"
newline
bitfld.long 0x00 8.--11. "TIME_COUNT_RETUNING,Time counter for retuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2. "DDR50_SUPPORT,DDR50 support" "0,1"
newline
rbitfld.long 0x00 1. "SDR104_SUPPORT,SDR104 support" "0,1"
newline
rbitfld.long 0x00 0. "SDR50_SUPPORT,SDR50 support" "0,1"
group.long 0x44++0x03
line.long 0x00 "WTMK_LVL,Watermark Level"
bitfld.long 0x00 24.--28. "WR_BRST_LEN,Write burst length due to system restriction the actual burst length might not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 16.--23. 1. "WR_WML,Write watermark level"
newline
bitfld.long 0x00 8.--12. "RD_BRST_LEN,Read burst length due to system restriction the actual burst length might not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 0.--7. 1. "RD_WML,Read watermark level"
group.long 0x48++0x03
line.long 0x00 "MIX_CTRL,Mixer Control"
bitfld.long 0x00 25. "FBCLK_SEL,Feedback clock source selection (Only used for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Feedback clock comes from the loopback CLK,1: Feedback clock comes from the ipp_card_clk_out"
newline
bitfld.long 0x00 24. "AUTO_TUNE_EN,Auto tuning enable (Only used for SD3.0 SDR104 mode and and EMMC HS200 mode)" "0: Disable auto tuning,1: Enable auto tuning"
newline
bitfld.long 0x00 23. "SMP_CLK_SEL,Clock selection" "0: Fixed clock is used to sample data / cmd,1: Tuned clock is used to sample data / cmd"
newline
bitfld.long 0x00 22. "EXE_TUNE,Execute tuning: (Only used for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Not tuned or tuning completed,1: Execute tuning"
newline
bitfld.long 0x00 7. "AC23EN,Auto CMD23 enable" "0,1"
newline
bitfld.long 0x00 6. "NIBBLE_POS,Nibble position indication" "0,1"
newline
bitfld.long 0x00 5. "MSBSEL,Multi / Single block select" "0: Single block,1: Multiple blocks"
newline
bitfld.long 0x00 4. "DTDSEL,Data transfer direction select" "0: Write (Host to card),1: Read (Card to host)"
newline
bitfld.long 0x00 3. "DDR_EN,Dual data rate mode selection" "0,1"
newline
bitfld.long 0x00 2. "AC12EN,Auto CMD12 enable" "0: AC12EN_0,1: AC12EN_1"
newline
bitfld.long 0x00 1. "BCEN,Block count enable" "0: Disable,1: BCEN_1"
newline
bitfld.long 0x00 0. "DMAEN,DMA enable" "0: DMAEN_0,1: DMAEN_1"
group.long 0x50++0x03
line.long 0x00 "FORCE_EVENT,Force Event"
bitfld.long 0x00 31. "FEVTCINT,Force event card interrupt" "0,1"
newline
bitfld.long 0x00 28. "FEVTDMAE,Force event DMA error" "0,1"
newline
bitfld.long 0x00 26. "FEVTTNE,Force tuning error" "0,1"
newline
bitfld.long 0x00 24. "FEVTAC12E,Force event Auto Command 12 error" "0,1"
newline
bitfld.long 0x00 22. "FEVTDEBE,Force event data end bit error" "0,1"
newline
bitfld.long 0x00 21. "FEVTDCE,Force event data CRC error" "0,1"
newline
bitfld.long 0x00 20. "FEVTDTOE,Force event data time out error" "0,1"
newline
bitfld.long 0x00 19. "FEVTCIE,Force event command index error" "0,1"
newline
bitfld.long 0x00 18. "FEVTCEBE,Force event command end bit error" "0,1"
newline
bitfld.long 0x00 17. "FEVTCCE,Force event command CRC error" "0,1"
newline
bitfld.long 0x00 16. "FEVTCTOE,Force event command time out error" "0,1"
newline
bitfld.long 0x00 7. "FEVTCNIBAC12E,Force event command not executed by Auto Command 12 error" "0,1"
newline
bitfld.long 0x00 4. "FEVTAC12IE,Force event Auto Command 12 index error" "0,1"
newline
bitfld.long 0x00 3. "FEVTAC12EBE,Force event Auto Command 12 end bit error" "0,1"
newline
bitfld.long 0x00 2. "FEVTAC12CE,Force event auto command 12 CRC error" "0,1"
newline
bitfld.long 0x00 1. "FEVTAC12TOE,Force event auto command 12 time out error" "0,1"
newline
bitfld.long 0x00 0. "FEVTAC12NE,Force event auto command 12 not executed" "0,1"
rgroup.long 0x54++0x03
line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status"
bitfld.long 0x00 3. "ADMADCE,ADMA descriptor error" "0: ADMADCE_0,1: ADMADCE_1"
newline
bitfld.long 0x00 2. "ADMALME,ADMA length mismatch error" "0: ADMALME_0,1: ADMALME_1"
newline
bitfld.long 0x00 0.--1. "ADMAES,ADMA error state (when ADMA error is occurred)" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address"
hexmask.long 0x00 2.--31. 1. "ADS_ADDR,ADMA system address"
group.long 0x60++0x03
line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control"
bitfld.long 0x00 28.--31. "DLL_CTRL_REF_UPDATE_INT,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 20.--27. 1. "DLL_CTRL_SLV_UPDATE_INT,Slave delay line update interval"
newline
bitfld.long 0x00 16.--18. "DLL_CTRL_SLV_DLY_TARGET1,DLL slave delay target1" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 9.--15. 1. "DLL_CTRL_SLV_OVERRIDE_VAL,DLL slave override val"
newline
bitfld.long 0x00 8. "DLL_CTRL_SLV_OVERRIDE,DLL slave override" "0,1"
newline
bitfld.long 0x00 7. "DLL_CTRL_GATE_UPDATE,DLL gate update" "0,1"
newline
bitfld.long 0x00 3.--6. "DLL_CTRL_SLV_DLY_TARGET0,DLL slave delay target0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "DLL_CTRL_SLV_FORCE_UPD,DLL slave delay line" "0,1"
newline
bitfld.long 0x00 1. "DLL_CTRL_RESET,DLL reset" "0,1"
newline
bitfld.long 0x00 0. "DLL_CTRL_ENABLE,DLL and delay chain" "0,1"
rgroup.long 0x64++0x03
line.long 0x00 "DLL_STATUS,DLL Status"
hexmask.long.byte 0x00 9.--15. 1. "DLL_STS_REF_SEL,Reference delay line select taps"
newline
hexmask.long.byte 0x00 2.--8. 1. "DLL_STS_SLV_SEL,Slave delay line select status"
newline
bitfld.long 0x00 1. "DLL_STS_REF_LOCK,Reference DLL lock status" "0,1"
newline
bitfld.long 0x00 0. "DLL_STS_SLV_LOCK,Slave delay-line lock status" "0,1"
group.long 0x68++0x03
line.long 0x00 "CLK_TUNE_CTRL_STATUS,CLK Tuning Control and Status"
rbitfld.long 0x00 31. "PRE_ERR,PRE error" "0,1"
newline
hexmask.long.byte 0x00 24.--30. 1. "TAP_SEL_PRE,TAP_SEL_PRE"
newline
rbitfld.long 0x00 20.--23. "TAP_SEL_OUT,Delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TAP_SEL_POST,Delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 15. "NXT_ERR,NXT error" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "DLY_CELL_SET_PRE,delay cells on the feedback clock between the feedback clock and CLK_PRE"
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bitfld.long 0x00 4.--7. "DLY_CELL_SET_OUT,Delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DLY_CELL_SET_POST,Delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0++0x03
line.long 0x00 "VEND_SPEC,Vendor Specific Register"
bitfld.long 0x00 31. "CMD_BYTE_EN,Byte access" "0: CMD_BYTE_EN_0,1: CMD_BYTE_EN_1"
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bitfld.long 0x00 15. "CRC_CHK_DIS,CRC Check Disable" "0: Check CRC16 for every read data packet and..,1: Ignore CRC16 check for every read data packet.."
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bitfld.long 0x00 8. "FRC_SDCLK_ON,Force CLK" "0: CLK active or inactive is fully controlled by..,1: Force CLK active"
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bitfld.long 0x00 3. "AC12_WR_CHKBUSY_EN,Check busy enable" "0: Do not check busy after auto CMD12 for write..,1: Check busy after auto CMD12 for write data.."
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bitfld.long 0x00 2. "CONFLICT_CHK_EN,Conflict check enable" "0: Conflict check disable,1: Conflict check enable"
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bitfld.long 0x00 1. "VSELECT,Voltage selection" "0: Change the voltage to high voltage range..,1: Change the voltage to low voltage range.."
group.long 0xC4++0x03
line.long 0x00 "MMC_BOOT,MMC Boot"
hexmask.long.word 0x00 16.--31. 1. "BOOT_BLK_CNT,Stop At Block Gap value of automatic mode"
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bitfld.long 0x00 8. "DISABLE_TIME_OUT,Time out" "0: DISABLE_TIME_OUT_0,1: DISABLE_TIME_OUT_1"
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bitfld.long 0x00 7. "AUTO_SABG_EN,Auto stop at block gap" "0,1"
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bitfld.long 0x00 6. "BOOT_EN,Boot enable" "0: Fast boot disable,1: Fast boot enable"
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bitfld.long 0x00 5. "BOOT_MODE,Boot mode" "0: BOOT_MODE_0,1: Alternative boot"
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bitfld.long 0x00 4. "BOOT_ACK,BOOT ACK" "0: BOOT_ACK_0,1: BOOT_ACK_1"
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bitfld.long 0x00 0.--3. "DTOCV_ACK,Boot ACK time out" "0: SDCLK x 2^14,1: SDCLK x 2^15,2: SDCLK x 2^16,3: SDCLK x 2^17,4: SDCLK x 2^18,5: SDCLK x 2^19,6: SDCLK x 2^20,7: SDCLK x 2^21,?,?,?,?,?,?,14: DTOCV_ACK_14,15: DTOCV_ACK_15"
group.long 0xC8++0x03
line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register"
bitfld.long 0x00 12. "ACMD23_ARGU2_EN,Argument2 register enable for ACMD23" "0: ACMD23_ARGU2_EN_0,1: Argument2 register enable for ACMD23 sharing.."
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bitfld.long 0x00 6. "TUNING_CMD_EN,Tuning command enable" "0: Auto tuning circuit does not check the CMD line,1: Auto tuning circuit checks the CMD line"
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bitfld.long 0x00 5. "TUNING_1bit_EN,Tuning 1bit enable" "0,1"
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bitfld.long 0x00 4. "TUNING_8bit_EN,Tuning 8bit enable" "0,1"
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bitfld.long 0x00 3. "CARD_INT_D3_TEST,Card interrupt detection test" "0: Check the card interrupt only when DATA3 is..,1: Check the card interrupt by ignoring the.."
group.long 0xCC++0x03
line.long 0x00 "TUNING_CTRL,Tuning Control"
bitfld.long 0x00 24. "STD_TUNING_EN,Standard tuning circuit and procedure enable" "0,1"
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bitfld.long 0x00 20.--22. "TUNING_WINDOW,Data window" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "TUNING_STEP,TUNING_STEP" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 8.--15. 1. "TUNING_COUNTER,Tuning counter"
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hexmask.long.byte 0x00 0.--7. 1. "TUNING_START_TAP,Tuning start"
tree.end
tree.end
tree "UTICK"
base ad:0x4000F000
group.long 0x00++0x03
line.long 0x00 "CTRL,Control"
bitfld.long 0x00 31. "REPEAT,Repeat delay" "0: One-time delay,1: Delay repeats continuously"
hexmask.long 0x00 0.--30. 1. "DELAYVAL,Tick interval"
group.long 0x04++0x03
line.long 0x00 "STAT,Status"
bitfld.long 0x00 1. "ACTIVE,Timer active flag" "0: The Micro-Tick Timer is not active (stopped),1: The Micro-Tick Timer is currently active"
bitfld.long 0x00 0. "INTR,Interrupt flag" "0: No interrupt is pending,1: An interrupt is pending"
group.long 0x08++0x03
line.long 0x00 "CFG,Capture Configuration"
bitfld.long 0x00 11. "CAPPOL3,Capture Polarity 3" "0: CAPPOL3POSEDGECAPTURE,1: CAPPOL3NEGEDGECAPTURE"
bitfld.long 0x00 10. "CAPPOL2,Capture Polarity 2" "0: CAPPOL2POSEDGECAPTURE,1: CAPPOL2NEGEDGECAPTURE"
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bitfld.long 0x00 9. "CAPPOL1,Capture Polarity 1" "0: CAPPOL1POSEDGECAPTURE,1: CAPPOL1NEGEDGECAPTURE"
bitfld.long 0x00 8. "CAPPOL0,Capture Polarity 0" "0: CAPPOL0POSEDGECAPTURE,1: CAPPOL0NEGEDGECAPTURE"
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bitfld.long 0x00 3. "CAPEN3,Enable Capture 3" "0: CAPEN3ISDISABLED,1: CAPEN3ISENABLED"
bitfld.long 0x00 2. "CAPEN2,Enable Capture 2" "0: CAPEN2ISDISABLED,1: CAPEN2ISENABLED"
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bitfld.long 0x00 1. "CAPEN1,Enable Capture 1" "0: CAPEN1ISDISABLED,1: CAPEN1ISENABLED"
bitfld.long 0x00 0. "CAPEN0,Enable Capture 0" "0: CAPEN0ISDISABLED,1: CAPEN0ISENABLED"
wgroup.long 0x0C++0x03
line.long 0x00 "CAPCLR,Capture Clear"
bitfld.long 0x00 3. "CAPCLR3,Clear capture 3" "0: CAPCLR3NOTHING,1: Write 1 to clear the CAP3 register value"
bitfld.long 0x00 2. "CAPCLR2,Clear capture 2" "0: CAPCLR2NOTHING,1: Write 1 to clear the CAP2 register value"
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bitfld.long 0x00 1. "CAPCLR1,Clear capture 1" "0: CAPCLR1NOTHING,1: Write 1 to clear the CAP1 register value"
bitfld.long 0x00 0. "CAPCLR0,Clear capture 0" "0: CAPCLR0NOTHING,1: Write 1 to clear the CAP0 register value"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x10)++0x03
line.long 0x00 "CAP[$1],Capture $1"
bitfld.long 0x00 31. "VALID,Captured value is valid" "0: A valid value has been not been captured,1: A valid value has been captured based on a.."
hexmask.long 0x00 0.--30. 1. "CAP_VALUE,Captured value for the related capture event"
repeat.end
tree.end
tree "WWDT"
repeat 2. (list 0. 1.) (list ad:0x4000E000 ad:0x4002E000)
tree "WWDT$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MOD,Mode"
bitfld.long 0x00 5. "LOCK,Lock" "0: NO_LOCK,1: LOCK"
bitfld.long 0x00 4. "WDPROTECT,Watchdog Update Mode" "0: FLEXIBLE,1: THRESHOLD"
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eventfld.long 0x00 3. "WDINT,Warning Interrupt Flag" "0: No flag,1: Flag"
bitfld.long 0x00 2. "WDTOF,Watchdog Timeout Flag" "0: Clear,1: Reset"
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bitfld.long 0x00 1. "WDRESET,Watchdog Reset Enable" "0: Interrupt,1: Reset"
bitfld.long 0x00 0. "WDEN,Watchdog Enable" "0: Stop,1: Run"
group.long 0x04++0x03
line.long 0x00 "TC,Timer Constant"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Watchdog Timeout Value"
wgroup.long 0x08++0x03
line.long 0x00 "FEED,Feed Sequence"
hexmask.long.byte 0x00 0.--7. 1. "FEED,Feed Value"
rgroup.long 0x0C++0x03
line.long 0x00 "TV,Timer Value"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Counter Timer Value"
group.long 0x14++0x03
line.long 0x00 "WARNINT,Warning Interrupt Compare Value"
hexmask.long.word 0x00 0.--9. 1. "WARNINT,Watchdog Warning Interrupt Compare Value"
group.long 0x18++0x03
line.long 0x00 "WINDOW,Window Compare Value"
hexmask.long.tbyte 0x00 0.--23. 1. "WINDOW,Watchdog Window Value"
tree.end
repeat.end
tree.end
autoindent.off
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