10604 lines
803 KiB
Plaintext
10604 lines
803 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: EM359x On-Chip Peripherals
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; @Props: Released
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; @Author: KKW
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; @Changelog: 2016-30-09 KKW
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; @Manufacturer: SILICONLABS - Silicon Laboratories Inc.
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; @Doc: R-EM359x-RM.pdf, EM359x.pdf
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; @Core: Cortex-M3
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; @Chip: EM3591, EM3592, EM3595, EM3596, EM3597, EM3598
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perem359x.per 17736 2024-04-08 09:26:07Z kwisniewski $
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; Known problems:
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; Module Register Description
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; USB Device USB_STALLIN The same address for USB_STALLOUT register
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; TPIU Missing core module
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; SWJ Missing core module
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; DWT PCSR Missing register
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; DWT DWT_FUNCTION MATCHED bit missing
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; ITM ITMCON BUSY bit missing
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; FPB CID0..3 Registers missing
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
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bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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textline " "
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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tree "CoreSight Identification Registers"
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width 6.
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "PID0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "PID1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "PID2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "Power Management"
|
|
base ad:0x40004038
|
|
width 20.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RAM_RETAIN,RAM_RETAIN"
|
|
bitfld.long 0x00 15. " RETAIN[15] ,Sets the retention option for 0x2000F000 to 0x2000FFFF" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Sets the retention option for 0x2000E000 to 0x2000EFFF" "0,1"
|
|
bitfld.long 0x00 13. " [13] ,Sets the retention option for 0x2000D000 to 0x2000DFFF" "0,1"
|
|
bitfld.long 0x00 12. " [12] ,Sets the retention option for 0x2000C000 to 0x2000CFFF" "0,1"
|
|
bitfld.long 0x00 11. " [11] ,Sets the retention option for 0x2000B000 to 0x2000BFFF" "0,1"
|
|
bitfld.long 0x00 10. " [10] ,Sets the retention option for 0x2000A000 to 0x2000AFFF" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Sets the retention option for 0x20009000 to 0x20009FFF" "0,1"
|
|
bitfld.long 0x00 8. " [8] ,Sets the retention option for 0x20008000 to 0x20008FFF" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Sets the retention option for 0x20007000 to 0x20007FFF" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Sets the retention option for 0x20006000 to 0x20006FFF" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Sets the retention option for 0x20005000 to 0x20005FFF" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,Sets the retention option for 0x20004000 to 0x20004FFF" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,Sets the retention option for 0x20003000 to 0x20003FFF" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Sets the retention option for 0x20002000 to 0x20002FFF" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,Sets the retention option for 0x20001000 to 0x20001FFF" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Sets the retention option for 0x20000000 to 0x20000FFF" "0,1"
|
|
textline ""
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PERIPHERAL_DISABLE,PERIPHERAL_DISABLE"
|
|
sif cpuis("EM3592")||cpuis("EM3596")||cpuis("EM3598")
|
|
bitfld.long 0x00 8. " PERIDIS_USB ,Disable the clock to the USB periperal" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " PERIDIS_SC3 ,Disable the clock to the SC3 periperal" "No,Yes"
|
|
bitfld.long 0x00 6. " PERIDIS_SC4 ,Disable the clock to the SC4 periperal" "No,Yes"
|
|
bitfld.long 0x00 4. " PERIDIS_ADC ,Disable the clock to the ADC periperal" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PERIDIS_TIM2 ,Disable the clock to the TIM2 periperal" "No,Yes"
|
|
bitfld.long 0x00 2. " PERIDIS_TIM1 ,Disable the clock to the TIM1 periperal" "No,Yes"
|
|
bitfld.long 0x00 1. " PERIDIS_SC1 ,Disable the clock to the SC1 periperal" "No,Yes"
|
|
bitfld.long 0x00 0. " PERIDIS_SC2 ,Disable the clock to the SC2 periperal" "No,Yes"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "GPIO (General Purpose Input/Output)"
|
|
tree "GPIO Common Registers"
|
|
base ad:0x4000A800
|
|
width 14.
|
|
group.long 0x1428++0x03
|
|
line.long 0x00 "WAKEFILT,GPIO Wakeup Filtering Register"
|
|
bitfld.long 0x00 3. " IRQD_WAKE_FILTER ,Enable filter on GPIO wakeup source IRQD" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC2_WAKE_FILTER ,Enable filter on GPIO wakeup source SC2 (PA2)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC1_WAKE_FILTER ,Enable filter on GPIO wakeup source SC1 (PB2)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GPIO_WAKE_FILTER ,Enable filter on GPIO wakeup sources enabled by the GPIO_PnWAKE" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INT_GPIOFLAG,GPIO Interrupt Flag Register"
|
|
bitfld.long 0x00 3. " NT_IRQDFLAG ,IRQD interrupt pending clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NT_IRQCFLAG ,IRQC interrupt pending clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NT_IRQBFLAG ,IRQB interrupt pending clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " NT_IRQAFLAG ,IRQA interrupt pending clear" "No effect,Clear"
|
|
group.long 0x1400++0x03
|
|
line.long 0x00 "DBGCFG,GPIO Debug Configuration Register"
|
|
bitfld.long 0x00 5. " GPIO_DEBUGDIS ,Disable debug interface override of normal GPIO configuration" "No,Yes"
|
|
bitfld.long 0x00 4. " GPIO_EXTREGEN ,Enable REG_EN override of PA7's normal GPIO configuration" "Disabled,Enabled"
|
|
rgroup.long 0x1404++0x03
|
|
line.long 0x00 "GPIO_DBGSTAT,GPIO Debug Status Register"
|
|
bitfld.long 0x00 3. " GPIO_BOOTMODE ,State of the nBOOTMODE signal sampled at the end of reset" "Not asserted,Asserted"
|
|
bitfld.long 0x00 1. " GPIO_FORCEDBG ,Status of debugger interface" "Not forced active,Forced active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPIO_SWEN ,Status of serial wire interface (enabled by SWJ-DP)" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO A"
|
|
base ad:0x4000B000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PACFGL,Port A Configuration Register (Low)"
|
|
bitfld.long 0x00 12.--15. " PA3_CFG ,GPIO configuration control 3" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TIM2C2 (Push-pull),,,,TIM2C2 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PA2_CFG ,GPIO configuration control 2" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TIM2C4/SC2SCLK/SC2SCL (Push-pull),,,,TIM2C4/SC2SCLK/SC2SCL (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PA1_CFG ,GPIO configuration control 1" "USBDP I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TIM2C3/SC2MISO/SC2SDA (Push-pull),,,,TIM2C3/SC2MISO/SC2SDA (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PA0_CFG ,GPIO configuration control 0" "USBDM I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TIM2C1/SC2MOSI (Push-pull),,,,TIM2C1/SC2MOSI (Open-drain),?..."
|
|
if (((per.l(ad:0x4000BC00))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PACFGH,Port A Configuration Register"
|
|
bitfld.long 0x00 12.--15. " PA7_CFG ,GPIO configuration control 7" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),TIM1C4/REG_EN (Push-pull),,SPI slave MISO,,TIM1C4/REG_EN (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PA6_CFG ,GPIO configuration control 6" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),TIM1C3 (Push-pull),,SPI slave MISO,,TIM1C3 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PA5_CFG ,GPIO configuration control 5" "ADC5 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),PTI_DATA/TRACEDATA3 (Push-pull),,SPI slave MISO,,PTI_DATA/TRACEDATA3 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PA4_CFG ,GPIO configuration control 4" "ADC4 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),PTI_EN/TRACEDATA2 (Push-pull),,SPI slave MISO,,PTI_EN/TRACEDATA2 (Open-drain),?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PACFGH,Port A Configuration Register"
|
|
bitfld.long 0x00 12.--15. " PA7_CFG ,GPIO configuration control 7" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),TIM1C4/REG_EN (Push-pull),,SPI slave MISO,,TIM1C4/REG_EN (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PA6_CFG ,GPIO configuration control 6" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),TIM1C3 (Push-pull),,SPI slave MISO,,TIM1C3 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PA5_CFG ,GPIO configuration control 5" "ADC5 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),PTI_DATA/TRACEDATA3 (Push-pull),,SPI slave MISO,,PTI_DATA/TRACEDATA3 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PA4_CFG ,GPIO configuration control 4" "ADC4 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),PTI_EN/TRACEDATA2 (Push-pull),,SPI slave MISO,,PTI_EN/TRACEDATA2 (Open-drain),?..."
|
|
endif
|
|
textline ""
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PAIN,Port A Input Data Register"
|
|
bitfld.long 0x00 7. " PA7 ,Input level at pin PA7" "Low,High"
|
|
bitfld.long 0x00 6. " PA6 ,Input level at pin PA6" "Low,High"
|
|
bitfld.long 0x00 5. " PA5 ,Input level at pin PA5" "Low,High"
|
|
bitfld.long 0x00 4. " PA4 ,Input level at pin PA4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PA3 ,Input level at pin PA3" "Low,High"
|
|
bitfld.long 0x00 2. " PA2 ,Input level at pin PA2" "Low,High"
|
|
bitfld.long 0x00 1. " PA1 ,Input level at pin PA1" "Low,High"
|
|
bitfld.long 0x00 0. " PA0 ,Input level at pin PA0" "Low,High"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PAOUT_set/clr,Port A Output Data Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PA7 ,Output data for pin PA7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PA6 ,Output data for pin PA6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PA5 ,Output data for pin PA5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PA4 ,Output data for pin PA4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PA3 ,Output data for pin PA3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PA2 ,Output data for pin PA2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PA1 ,Output data for pin PA1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PA0 ,Output data for pin PA0" "Low,High"
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "PAWAKE,Port A Wakeup Monitor Register"
|
|
bitfld.long 0x00 7. " PA7 ,Enable wakeup monitoring of PA7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PA6 ,Enable wakeup monitoring of PA6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PA5 ,Enable wakeup monitoring of PA5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PA4 ,Enable wakeup monitoring of PA4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PA3 ,Enable wakeup monitoring of PA3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PA2 ,Enable wakeup monitoring of PA2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PA1 ,Enable wakeup monitoring of PA1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PA0 ,Enable wakeup monitoring of PA0" "Disabled,Enabled"
|
|
textline ""
|
|
base ad:0x4000A860
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INTCFGA,GPIO Interrupt A Configuration Register"
|
|
bitfld.long 0x00 8. " GPIO_INTFILT ,Enable digital filtering on IRQA" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " GPIO_INTMOD ,IRQA triggering mode" "Disabled,Rising edge,Falling edge,Rising/falling edge,Active high,Active low,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x4000B200
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PBCFGL,Port B Configuration Register (Low)"
|
|
bitfld.long 0x00 12.--15. " PB3_CFG ,GPIO configuration control 3" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TIM2C3/SC1SCLK (Push-pull),,,,TIM2C3/SC1SCLK (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PB2_CFG ,GPIO configuration control 2" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TIM2C2 (Push-pull),,,,TIM2C2 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PB1_CFG ,GPIO configuration control 1" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TIM2C1/SC1TXD/SC1MOSI/SC1MISO/SC1SDA (Push-pull),,,,TIM2C1/SC1TXD/SC1MOSI/SC1MISO/SC1SDA (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PB0_CFG ,GPIO configuration control 0" "VREF I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TRACEDATA2 (Push-pull),,,,TRACEDATA2 (Open-drain),?..."
|
|
if (((per.l(ad:0x4000BC00))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PBCFGH,Port B Configuration Register"
|
|
bitfld.long 0x00 12.--15. " PB7_CFG ,GPIO configuration control 7" "ADC2 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),TIM1C2 (Push-pull),,SPI slave MISO,,TIM1C2 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PB6_CFG ,GPIO configuration control 6" "ADC1 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),TIM1C1 (Push-pull),,SPI slave MISO,,TIM1C1 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PB5_CFG ,GPIO configuration control 5" "ADC0 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),,,SPI slave MISO,,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PB4_CFG ,GPIO configuration control 4" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),TIM2C4/SC1BRTS (Push-pull),,SPI slave MISO,,TIM2C4/SC1BRTS (Open-drain),?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PBCFGH,Port B Configuration Register"
|
|
bitfld.long 0x00 12.--15. " PB7_CFG ,GPIO configuration control 7" "ADC2 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),TIM1C2 (Push-pull),,SPI slave MISO,,TIM1C2 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PB6_CFG ,GPIO configuration control 6" "ADC1 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),TIM1C1 (Push-pull),,SPI slave MISO,,TIM1C1 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PB5_CFG ,GPIO configuration control 5" "ADC0 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),,,SPI slave MISO,,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PB4_CFG ,GPIO configuration control 4" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),TIM2C4/SC1BRTS (Push-pull),,SPI slave MISO,,TIM2C4/SC1BRTS (Open-drain),?..."
|
|
endif
|
|
textline ""
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PBIN,Port B Input Data Register"
|
|
bitfld.long 0x00 7. " PB7 ,Input level at pin PB7" "Low,High"
|
|
bitfld.long 0x00 6. " PB6 ,Input level at pin PB6" "Low,High"
|
|
bitfld.long 0x00 5. " PB5 ,Input level at pin PB5" "Low,High"
|
|
bitfld.long 0x00 4. " PB4 ,Input level at pin PB4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PB3 ,Input level at pin PB3" "Low,High"
|
|
bitfld.long 0x00 2. " PB2 ,Input level at pin PB2" "Low,High"
|
|
bitfld.long 0x00 1. " PB1 ,Input level at pin PB1" "Low,High"
|
|
bitfld.long 0x00 0. " PB0 ,Input level at pin PB0" "Low,High"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PBOUT_set/clr,Port B Output Data Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PB7 ,Output data for pin PB7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PB6 ,Output data for pin PB6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PB5 ,Output data for pin PB5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PB4 ,Output data for pin PB4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PB3 ,Output data for pin PB3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PB2 ,Output data for pin PB2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PB1 ,Output data for pin PB1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PB0 ,Output data for pin PB0" "Low,High"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "PBWAKE,Port B Wakeup Monitor Register"
|
|
bitfld.long 0x00 7. " PB7 ,Enable wakeup monitoring of PB7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PB6 ,Enable wakeup monitoring of PB6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PB5 ,Enable wakeup monitoring of PB5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PB4 ,Enable wakeup monitoring of PB4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PB3 ,Enable wakeup monitoring of PB3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PB2 ,Enable wakeup monitoring of PB2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PB1 ,Enable wakeup monitoring of PB1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PB0 ,Enable wakeup monitoring of PB0" "Disabled,Enabled"
|
|
textline ""
|
|
base ad:0x4000A864
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INTCFGB,GPIO Interrupt B Configuration Register"
|
|
bitfld.long 0x00 8. " GPIO_INTFILT ,Enable digital filtering on IRQB" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " GPIO_INTMOD ,IRQB triggering mode" "Disabled,Rising edge,Falling edge,Rising/falling edge,Active high,Active low,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO C"
|
|
base ad:0x4000B400
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCCFGL,Port C Configuration Register (Low)"
|
|
bitfld.long 0x00 12.--15. " PC3_CFG ,GPIO configuration control 3" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TRACECLK (Push-pull),,,,TRACECLK (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PC2_CFG ,GPIO configuration control 2" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),JTDO/SWO/TRACEDATA0 (Push-pull),,,,JTDO/SWO/TRACEDATA0 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PC1_CFG ,GPIO configuration control 1" "ADC3 I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TRACEDATA3 (Push-pull),,,,TRACEDATA3 (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PC0_CFG ,GPIO configuration control 0" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),TRACEDATA1 (Push-pull),,,,TRACEDATA1 (Open-drain),?..."
|
|
if (((per.l(ad:0x4000BC00))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCCFGH,Port C Configuration Register"
|
|
bitfld.long 0x00 12.--15. " PC7_CFG ,GPIO configuration control 7" "OSC32A,Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),,,SPI slave MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PC6_CFG ,GPIO configuration control 6" "OSC32B,Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),CTX_ACTIVE (Push-pull),,SPI slave MISO,,CTX_ACTIVE (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PC5_CFG ,GPIO configuration control 5" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),TX_ACTIVE (Push-pull),,SPI slave MISO,,TX_ACTIVE (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PC4_CFG ,GPIO configuration control 4" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),SWDIO (Push-pull),,SPI slave MISO,,SWDIO (Open-drain),?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCCFGH,Port C Configuration Register"
|
|
bitfld.long 0x00 12.--15. " PC7_CFG ,GPIO configuration control 7" "OSC32A I/O,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),,,SPI slave MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PC6_CFG ,GPIO configuration control 6" "OSC32B,Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),CTX_ACTIVE (Push-pull),,SPI slave MISO,,CTX_ACTIVE (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PC5_CFG ,GPIO configuration control 5" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),TX_ACTIVE (Push-pull),,SPI slave MISO,,TX_ACTIVE (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PC4_CFG ,GPIO configuration control 4" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),SWDIO (Push-pull),,SPI slave MISO,,SWDIO (Open-drain),?..."
|
|
endif
|
|
textline ""
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCIN,Port C Input Data Register"
|
|
bitfld.long 0x00 7. " PC7 ,Input level at pin PC7" "Low,High"
|
|
bitfld.long 0x00 6. " PC6 ,Input level at pin PC6" "Low,High"
|
|
bitfld.long 0x00 5. " PC5 ,Input level at pin PC5" "Low,High"
|
|
bitfld.long 0x00 4. " PC4 ,Input level at pin PC4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PC3 ,Input level at pin PC3" "Low,High"
|
|
bitfld.long 0x00 2. " PC2 ,Input level at pin PC2" "Low,High"
|
|
bitfld.long 0x00 1. " PC1 ,Input level at pin PC1" "Low,High"
|
|
bitfld.long 0x00 0. " PC0 ,Input level at pin PC0" "Low,High"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCOUT_set/clr,Port C Output Data Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PC7 ,Output data for pin PC7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PC6 ,Output data for pin PC6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PC5 ,Output data for pin PC5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PC4 ,Output data for pin PC4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PC3 ,Output data for pin PC3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PC2 ,Output data for pin PC2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PC1 ,Output data for pin PC1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PC0 ,Output data for pin PC0" "Low,High"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "PCWAKE,Port C Wakeup Monitor Register"
|
|
bitfld.long 0x00 7. " PC7 ,Enable wakeup monitoring of PC7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PC6 ,Enable wakeup monitoring of PC6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PC5 ,Enable wakeup monitoring of PC5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PC4 ,Enable wakeup monitoring of PC4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PC3 ,Enable wakeup monitoring of PC3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PC2 ,Enable wakeup monitoring of PC2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PC1 ,Enable wakeup monitoring of PC1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PC0 ,Enable wakeup monitoring of PC0" "Disabled,Enabled"
|
|
textline ""
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "IRQCSEL,Interrupt C Select Register"
|
|
bitfld.long 0x00 0.--5. " SEL_GPIO ,Pin assigned to IRQC" "PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,,PD1,PD2,PD3,PD4,,,,PE0,PE1,PE2,PE3,?..."
|
|
base ad:0x4000A868
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INTCFGC,GPIO Interrupt C Configuration Register"
|
|
bitfld.long 0x00 8. " GPIO_INTFILT ,Enable digital filtering on IRQC" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " GPIO_INTMOD ,IRQC triggering mode" "Disabled,Rising edge,Falling edge,Rising/falling edge,Active high,Active low,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO D"
|
|
base ad:0x4000B600
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDCFGL,Port D Configuration Register (Low)"
|
|
bitfld.long 0x00 12.--15. " PD3_CFG ,GPIO configuration control 3" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),SC3SCLK (Push-pull),,,,SC3SCLK (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PD2_CFG ,GPIO configuration control 2" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),,,,,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PD1_CFG ,GPIO configuration control 1" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),SC3TXD/SC3MOSI/SC3MISO/SC3SDA (Push-pull),,,,SC3TXD/SC3MOSI/SC3MISO/SC3SDA (Open-drain),?..."
|
|
if (((per.l(ad:0x4000BC00))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDCFGH,Port D Configuration Register"
|
|
bitfld.long 0x00 0.--3. " PD4_CFG ,GPIO configuration control 4" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),SWDIO (bidirectional),,Input (Pull-up/down),SC3DRTS (Push-pull),,SPI slave MISO,,SC3DRTS (Open-drain),?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDCFGH,Port D Configuration Register"
|
|
bitfld.long 0x00 0.--3. " PD4_CFG ,GPIO configuration control 4" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (Pull-up/down),SC3DRTS (Push-pull),,SPI slave MISO,,SC3DRTS (Open-drain),?..."
|
|
endif
|
|
textline ""
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PDIN,Port D Input Data Register"
|
|
bitfld.long 0x00 4. " PD4 ,Input level at pin PD4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PD3 ,Input level at pin PD3" "Low,High"
|
|
bitfld.long 0x00 2. " PD2 ,Input level at pin PD2" "Low,High"
|
|
bitfld.long 0x00 1. " PD1 ,Input level at pin PD1" "Low,High"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PDOUT_set/clr,Port D Output Data Register"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PD4 ,Output data for pin PD4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PD3 ,Output data for pin PD3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PD2 ,Output data for pin PD2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PD1 ,Output data for pin PD1" "Low,High"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "PDWAKE,Port D Wakeup Monitor Register"
|
|
bitfld.long 0x00 4. " PD4 ,Enable wakeup monitoring of PD4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PD3 ,Enable wakeup monitoring of PD3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PD2 ,Enable wakeup monitoring of PD2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PD1 ,Enable wakeup monitoring of PD1" "Disabled,Enabled"
|
|
textline ""
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "IRQDSEL,Interrupt D Select Register"
|
|
bitfld.long 0x00 0.--5. " SEL_GPIO ,Pin assigned to IRQD" "PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,,PD1,PD2,PD3,PD4,,,,PE0,PE1,PE2,PE3,?..."
|
|
base ad:0x4000A86C
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INTCFGD,GPIO Interrupt D Configuration Register"
|
|
bitfld.long 0x00 8. " GPIO_INTFILT ,Enable digital filtering on IRQD" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--7. " GPIO_INTMOD ,IRQD triggering mode" "Disabled,Rising edge,Falling edge,Rising/falling edge,Active high,Active low,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO E"
|
|
base ad:0x4000B800
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PECFGL,Port E Configuration Register (Low)"
|
|
bitfld.long 0x00 12.--15. " PE3_CFG ,GPIO configuration control 3" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PE2_CFG ,GPIO configuration control 2" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),SC4SCLK/SC4SCL (Push-pull),,,,SC4SCLK/SC4SCL (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PE1_CFG ,GPIO configuration control 1" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),SC4MSIO/SC4SDA (Push-pull),,,,SC4MSIO/SC4SDA (Open-drain),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PE0_CFG ,GPIO configuration control 0" ",Output (Push-pull),,,Input (Floating),Output (Open-drain),,,Input (pullup/down),SC4MOSI (Push-pull),,,,SC4MOSI (Open-drain),?..."
|
|
textline ""
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PEIN,Port E Input Data Register"
|
|
bitfld.long 0x00 3. " PE3 ,Input level at pin PE3" "Low,High"
|
|
bitfld.long 0x00 2. " PE2 ,Input level at pin PE2" "Low,High"
|
|
bitfld.long 0x00 1. " PE1 ,Input level at pin PE1" "Low,High"
|
|
bitfld.long 0x00 0. " PE0 ,Input level at pin PE0" "Low,High"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PEOUT_set/clr,Port E Output Data Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PE3 ,Output data for pin PE3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PE2 ,Output data for pin PE2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PE1 ,Output data for pin PE1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PE0 ,Output data for pin PE0" "Low,High"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "PEWAKE,Port E Wakeup Monitor Register"
|
|
bitfld.long 0x00 3. " PE3 ,Enable wakeup monitoring of PE3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PE2 ,Enable wakeup monitoring of PE2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PE1 ,Enable wakeup monitoring of PE1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE0 ,Enable wakeup monitoring of PE0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "Serial Controllers"
|
|
tree "SC1"
|
|
base ad:0x4000C800
|
|
width 14.
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SC1_MODE,Serial Mode Register"
|
|
bitfld.long 0x00 0.--1. " SC_MODE ,Serial controller mode" "Disabled,UART,SPI,TWI"
|
|
base ad:0x4000A800
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INT_SC1FLAG,Serial Controller 1 Interrupt Flag Register"
|
|
bitfld.long 0x00 14. " INT_SC1PARERR ,Parity error received (for UART) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " INT_SC1FRMERR ,Frame error received (for UART) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " INT_SCTXULDB ,DMA transmit buffer B unloaded interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_SCTXULDA ,DMA transmit buffer A unloaded interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " INT_SCRXULDB ,DMA receive buffer B unloaded interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " INT_SCRXULDA ,DMA receive buffer A unloaded interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INT_SCNAK ,NACK received (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " INT_SCCMDFIN ,START/STOP command complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " INT_SCTXFIN ,Transmit operation complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_SCRXFIN ,Receive operation complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " INT_SCTXUND ,Transmit buffer underrun interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " INT_SCRXOVF ,Receive buffer overrun interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_SCTXIDLE ,Transmitter idle interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " INT_SCTXFREE ,Transmit buffer free interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " INT_SCRXVAL ,Receive buffer has data interrupt pending" "Not pending,Pending"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "INT_SC1CFG,Serial Controller 1 Interrupt Configuration Register"
|
|
bitfld.long 0x00 14. " INT_SC1PARERR ,Parity error received (for UART) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INT_SC1FRMERR ,Frame error received (for UART) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INT_SCTXULDB ,DMA transmit buffer B unloaded interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_SCTXULDA ,DMA transmit buffer A unloaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INT_SCRXULDB ,DMA receive buffer B unloaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INT_SCRXULDA ,DMA receive buffer A unloaded interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INT_SCNAK ,NACK received (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INT_SCCMDFIN ,START/STOP command complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INT_SCTXFIN ,Transmit operation complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_SCRXFIN ,Receive operation complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_SCTXUND ,Transmit buffer underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_SCRXOVF ,Receive buffer overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_SCTXIDLE ,Transmitter idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_SCTXFREE ,Transmit buffer free interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INT_SCRXVAL ,Receive buffer has data interrupt enable" "Disabled,Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SC1_INTMODE,Serial Controller 1 Interrupt Mode Register"
|
|
bitfld.long 0x00 2. " SC_TXIDLELEVEL ,Transmitter idle interrupt mode" "Edge triggered,Level triggered"
|
|
bitfld.long 0x00 1. " SC_TXFREELEVEL ,Transmit buffer free interrupt mode" "Edge triggered,Level triggered"
|
|
bitfld.long 0x00 0. " SC_RXVALLEVEL ,Receive buffer has data interrupt mode" "Edge triggered,Level triggered"
|
|
base ad:0x4000C800
|
|
if (((per.l(ad:0x4000C800+0x54))&0x03)==0x02)
|
|
hgroup.long 0x3C++0x03 "SPI Specific registers"
|
|
hide.long 0x00 "SC1_DATA,Serial Data Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
if (((per.l(ad:0x4000C800+0x58))&0x10)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SC1_SPICFG,SPI Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 4. " SC_SPIMST ,SPI mode select" "Slave,Master"
|
|
bitfld.long 0x00 3. " SC_SPIRPT ,Control behavior when serializer must send data from empty serializer" "Send busy token,Repeat last byte"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_SPIORD ,bit order in which SPI data is transmitted and received" "MSB first,LSB first"
|
|
bitfld.long 0x00 1. " SC_SPIPHA ,Clock phase configuration" "First edge,Second edge"
|
|
bitfld.long 0x00 0. " SC_SPIPOL ,Clock polarity configuration" "Rising leading edge,Falling leading edge"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SC1_SPICFG,SPI Configuration Register"
|
|
bitfld.long 0x00 5. " SC_SPIRXDRV ,Initiate transactions" "Data available,Buffer has space"
|
|
bitfld.long 0x00 4. " SC_SPIMST ,SPI mode select" "Slave,Master"
|
|
bitfld.long 0x00 3. " SC_SPIRPT ,Control behavior when serializer must send data from empty serializer" "Send busy token,Repeat last byte"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_SPIORD ,bit order in which SPI data is transmitted and received" "MSB first,LSB first"
|
|
bitfld.long 0x00 1. " SC_SPIPHA ,Clock phase configuration" "First edge,Second edge"
|
|
bitfld.long 0x00 0. " SC_SPIPOL ,Clock polarity configuration" "Rising leading edge,Falling leading edge"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "SC1_SPISTAT,SPI Status Register"
|
|
bitfld.long 0x00 3. " SC_SPITXIDLE ,Transmit FIFO and the transmit serializer are empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " SC_SPITXFREE ,Transmit FIFO has space to accept at least one byte" "False,True"
|
|
bitfld.long 0x00 1. " SC_SPIRXVAL ,Receive FIFO contains at least one byte" "Not contain,Contain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_SPIRXOVF ,Byte is received when the receive FIFO is full" "Not received,Received"
|
|
if (((per.l(ad:0x4000C800+0x58))&0x10)==0x10)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SC1_RATELIN,Serial Clock Linear Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " SC_RATELIN ,Linear component of the clock rate" "12MHz/(1*2^EXP),12MHz/(2*2^EXP),12MHz/(3*2^EXP),12MHz/(4*2^EXP),12MHz/(5*2^EXP),12MHz/(6*2^EXP),12MHz/(7*2^EXP),12MHz/(8*2^EXP),12MHz/(9*2^EXP),12MHz/(10*2^EXP),12MHz/(11*2^EXP),12MHz/(12*2^EXP),12MHz/(13*2^EXP),12MHz/(14*2^EXP),12MHz/(15*2^EXP),12MHz/(16*2^EXP)"
|
|
line.long 0x04 "SC1_RATEEXP,Serial Clock Exponential Prescaler Register"
|
|
bitfld.long 0x04 0.--3. " SC_RATEEXP ,Exponential component (EXP value) of the clock rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x60++0x07
|
|
hide.long 0x00 "SC1_RATELIN,Serial Clock Linear Prescaler Register"
|
|
hide.long 0x04 "SC1_RATEEXP,Serial Clock Exponential Prescaler Register"
|
|
endif
|
|
elif (((per.l(ad:0x4000C800+0x54))&0x03)==0x03)
|
|
rgroup.long 0x44++0x03 "TWI Specific registers"
|
|
line.long 0x00 "SC1_TWISTAT,TWI Status Register"
|
|
bitfld.long 0x00 3. " SC_TWICMDFIN ,START or STOP command completed" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " SC_TWIRXFIN ,Byte is received" "Not received,Received"
|
|
bitfld.long 0x00 1. " SC_TWITXFIN ,Byte is transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_TWIRXNAK ,NACK is received from the slave" "Not received,Received"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "SC1_TWICTRL1,TWI Control Register 1"
|
|
bitfld.long 0x00 3. " SC_TWISTOP ,Send the STOP command" "Not sent,Sent"
|
|
bitfld.long 0x00 2. " SC_TWISTART ,Send the START or repeated START command" "Not sent,Sent"
|
|
bitfld.long 0x00 1. " SC_TWISEND ,Transmit a byte" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_TWIRECV ,Receives a byte" "Not received,Received"
|
|
line.long 0x04 "SC1_TWICTRL2,TWI Control Register 2"
|
|
bitfld.long 0x04 0. " SC_TWIACK ,Signal ACK time selector" "After,Before"
|
|
elif (((per.l(ad:0x4000C800+0x54))&0x03)==0x01)
|
|
hgroup.long 0x3C++0x03 "UART Specific Registers"
|
|
hide.long 0x00 "SC1_DATA,Serial Data Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SC1_UARTSTAT,UART Status Register"
|
|
bitfld.long 0x00 6. " SC_UARTTXIDLE ,Transmit FIFO and the transmit serializer are empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " SC_UARTPARERR ,Byte in the data register was received with a parity error" "Without error,With error"
|
|
bitfld.long 0x00 4. " SC_UARTFRMERR ,Byte in the data register was received with a frame error" "Without error,With error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTRXOVF ,Receive FIFO has been overrun" "Not overrun,Overrun"
|
|
bitfld.long 0x00 2. " SC_UARTTXFREE ,Transmit FIFO has space for at least one byte" "Not have,Have"
|
|
bitfld.long 0x00 1. " SC_UARTRXVAL ,Receive FIFO contains at least one byte" "Not contain,Contain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_UARTCTS ,Logical state (not voltage level) of the 1CTS input" "Deasserted (high),Asserted (Low)"
|
|
if (((per.l(ad:0x4000C800+0x5C))&0x20)==0x20)
|
|
if (((per.l(ad:0x4000C800+0x5C))&0x20)==0x20)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC1_UARTCFG,UART Configuration Register"
|
|
bitfld.long 0x00 6. " SC_UARTAUTO ,Enable automatic nRTS control by hardware" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 1RTS/1CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_UARTRTS ,Directly controls the output at the 1RTS pin" "Pin is high,Pin is low"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC1_UARTCFG,UART Configuration Register"
|
|
bitfld.long 0x00 6. " SC_UARTAUTO ,Enable automatic nRTS control by hardware" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 1RTS/1CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disbled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline ""
|
|
endif
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC1_UARTCFG,UART Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 1RTS/1CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline ""
|
|
endif
|
|
if (((per.l(ad:0x4000C800+0x6C))&0x01)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SC1_UARTPER,UART Baud Rate Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_UARTPER ,The integer part of baud rate period (N) by equation: rate = 24MHz/(2*N + 0)"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SC1_UARTPER,UART Baud Rate Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_UARTPER ,The integer part of baud rate period (N) by equation: rate = 24MHz/(2*N + 1)"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SC1_UARTFRAC,UART Baud Rate Fractional Period Register"
|
|
bitfld.long 0x00 0. " SC_UARTFRAC ,The fractional part of the baud rate period (F) by equation: rate = 24MHz/(2*N + F)" "0,1"
|
|
endif
|
|
group.long 0x30++0x03 "DMA Channel 1 Registers"
|
|
line.long 0x00 "SC1_DMACTRL,Serial DMA Control Register"
|
|
bitfld.long 0x00 5. " SC_TXDMARST ,Reset the transmit DMA" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SC_RXDMARST ,Reset the receive DMA" "No reset,Reset"
|
|
bitfld.long 0x00 3. " SC_TXLODB ,Load DMA transmit buffer B and allow DMA controller to start processing transmit buffer B" "No effect/Idle,Start/Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXLODA ,Load DMA transmit buffer A and allow DMA controller to start processing transmit buffer A" "No effect/Idle,Start/Pending"
|
|
bitfld.long 0x00 1. " SC_RXLODB ,Load DMA receive buffer B and allow DMA controller to start processing receive buffer B" "No effect/Idle,Start/Pending"
|
|
bitfld.long 0x00 0. " SC_RXLODA ,Load DMA receive buffer A and allow DMA controller to start processing receive buffer A" "No effect/Idle,Start/Pending"
|
|
textline ""
|
|
if (((per.l(ad:0x4000C800+0x54))&0x03)==0x01)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SC1_DMASTAT,Serial DMA Status Register"
|
|
bitfld.long 0x00 10.--12. " SC_RXSSEL ,Status of the receive count saved in SCx_RXCNTSAVED (for SPI slave mode)" "None,,Buffer A's count saved/1SSEL deasserted once,Buffer B's count saved/1SSEL deasserted once,,,Buffer A's count saved/1SSEL deasserted more than once,Buffer B's count saved/1SSEL deasserted more than once"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SC_RXFRMB ,DMA receive buffer B reads a byte with a frame error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SC_RXFRMA ,DMA receive buffer A reads a byte with a frame error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SC_RXPARB ,DMA receive buffer B reads a byte with a parity error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SC_RXPARA ,DMA receive buffer A reads a byte with a parity error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SC_RXOVFB ,DMA receive buffer B was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SC_RXOVFA ,DMA receive buffer A was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_TXACTB ,DMA transmit buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXACTA ,DMA transmit buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC_RXACTB ,DMA receive buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_RXACTA ,DMA receive buffer A is active" "Not active,Active"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SC1_DMASTAT,Serial DMA Status Register"
|
|
bitfld.long 0x00 10.--12. " SC_RXSSEL ,Status of the receive count saved in SCx_RXCNTSAVED (for SPI slave mode)" "None,,Buffer A's count saved/1SSEL deasserted once,Buffer B's count saved/1SSEL deasserted once,,,Buffer A's count saved/1SSEL deasserted more than once,Buffer B's count saved/1SSEL deasserted more than once"
|
|
textline ""
|
|
textline ""
|
|
textline ""
|
|
textline ""
|
|
textline " "
|
|
bitfld.long 0x00 5. " SC_RXOVFB ,DMA receive buffer B was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SC_RXOVFA ,DMA receive buffer A was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_TXACTB ,DMA transmit buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXACTA ,DMA transmit buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC_RXACTB ,DMA receive buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_RXACTA ,DMA receive buffer A is active" "Not active,Active"
|
|
endif
|
|
textline ""
|
|
width 16.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1_TXBEGA,Transmit DMA Begin Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXBEGA ,DMA transmit buffer A start address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1_TXBEGB,Transmit DMA Begin Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXBEGB ,DMA transmit buffer B start address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1_TXENDA,Transmit DMA End Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXENDA ,Address of the last byte that will be read from the DMA transmit buffer A"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1_TXENDB,Transmit DMA End Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXENDB ,Address of the last byte that will be read from the DMA transmit buffer B"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SC1_TXCNT,Transmit DMA Count Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXCNT ,Offset from the start of the active DMA transmit buffer from which the next byte will be read"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC1_RXBEGA,Receive DMA Begin Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXBEGA ,DMA receive buffer A start address"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC1_RXBEGB,Receive DMA Begin Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXBEGB ,DMA receive buffer B start address"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC1_RXENDA,Receive DMA End Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXENDA ,Address of the last byte that will be written in the DMA receive buffer A"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC1_RXENDB,Receive DMA End Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXENDB ,Address of the last byte that will be written in the DMA receive buffer B"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC1_RXCNTA,Receive DMA Count Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXCNTA ,Offset from the start of DMA receive buffer A at which the next byte will be written"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC1_RXCNTB,Receive DMA Count Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXCNTB ,Offset from the start of DMA receive buffer B at which the next byte will be written"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "SC1_RXCNTSAVED,Saved Receive DMA Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_RXCNTSAVED ,Receive DMA count saved in SPI slave mode"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SC1_RXERRA,DMA First Receive Error Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXERRA ,Offset from the start of DMA receive buffer A of the first byte received with a parity, frame, or overflow error"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SC1_RXERRB,DMA First Receive Error Register B"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " SC_RXERRB ,Offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SC2"
|
|
base ad:0x4000C000
|
|
width 14.
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SC2_MODE,Serial Mode Register"
|
|
bitfld.long 0x00 0.--1. " SC_MODE ,Serial controller mode" "Disabled,,SPI,TWI"
|
|
base ad:0x4000A804
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INT_SC2FLAG,Serial Controller 2 Interrupt Flag Register"
|
|
bitfld.long 0x00 14. " INT_SC2PARERR ,Parity error received (for UART) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " INT_SC2FRMERR ,Frame error received (for UART) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " INT_SCTXULDB ,DMA transmit buffer B unloaded interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_SCTXULDA ,DMA transmit buffer A unloaded interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " INT_SCRXULDB ,DMA receive buffer B unloaded interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " INT_SCRXULDA ,DMA receive buffer A unloaded interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INT_SCNAK ,NACK received (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " INT_SCCMDFIN ,START/STOP command complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " INT_SCTXFIN ,Transmit operation complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_SCRXFIN ,Receive operation complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " INT_SCTXUND ,Transmit buffer underrun interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " INT_SCRXOVF ,Receive buffer overrun interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_SCTXIDLE ,Transmitter idle interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " INT_SCTXFREE ,Transmit buffer free interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " INT_SCRXVAL ,Receive buffer has data interrupt pending" "Not pending,Pending"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "INT_SC2CFG,Serial Controller 2 Interrupt Configuration Register"
|
|
bitfld.long 0x00 14. " INT_SC2PARERR ,Parity error received (for UART) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INT_SC2FRMERR ,Frame error received (for UART) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INT_SCTXULDB ,DMA transmit buffer B unloaded interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_SCTXULDA ,DMA transmit buffer A unloaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INT_SCRXULDB ,DMA receive buffer B unloaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INT_SCRXULDA ,DMA receive buffer A unloaded interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INT_SCNAK ,NACK received (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INT_SCCMDFIN ,START/STOP command complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INT_SCTXFIN ,Transmit operation complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_SCRXFIN ,Receive operation complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_SCTXUND ,Transmit buffer underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_SCRXOVF ,Receive buffer overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_SCTXIDLE ,Transmitter idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_SCTXFREE ,Transmit buffer free interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INT_SCRXVAL ,Receive buffer has data interrupt enable" "Disabled,Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SC2_INTMODE,Serial Controller 1 Interrupt Mode Register"
|
|
bitfld.long 0x00 2. " SC_TXIDLELEVEL ,Transmitter idle interrupt mode" "Edge triggered,Level triggered"
|
|
bitfld.long 0x00 1. " SC_TXFREELEVEL ,Transmit buffer free interrupt mode" "Edge triggered,Level triggered"
|
|
bitfld.long 0x00 0. " SC_RXVALLEVEL ,Receive buffer has data interrupt mode" "Edge triggered,Level triggered"
|
|
base ad:0x4000C000
|
|
if (((per.l(ad:0x4000C000+0x54))&0x03)==0x02)
|
|
hgroup.long 0x3C++0x03 "SPI Specific registers"
|
|
hide.long 0x00 "SC2_DATA,Serial Data Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
if (((per.l(ad:0x4000C000+0x58))&0x10)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SC2_SPICFG,SPI Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 4. " SC_SPIMST ,SPI mode select" "Slave,Master"
|
|
bitfld.long 0x00 3. " SC_SPIRPT ,Control behavior when serializer must send data from empty serializer" "Send busy token,Repeat last byte"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_SPIORD ,bit order in which SPI data is transmitted and received" "MSB first,LSB first"
|
|
bitfld.long 0x00 1. " SC_SPIPHA ,Clock phase configuration" "First edge,Second edge"
|
|
bitfld.long 0x00 0. " SC_SPIPOL ,Clock polarity configuration" "Rising leading edge,Falling leading edge"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SC2_SPICFG,SPI Configuration Register"
|
|
bitfld.long 0x00 5. " SC_SPIRXDRV ,Initiate transactions" "Data available,Buffer has space"
|
|
bitfld.long 0x00 4. " SC_SPIMST ,SPI mode select" "Slave,Master"
|
|
bitfld.long 0x00 3. " SC_SPIRPT ,Control behavior when serializer must send data from empty serializer" "Send busy token,Repeat last byte"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_SPIORD ,bit order in which SPI data is transmitted and received" "MSB first,LSB first"
|
|
bitfld.long 0x00 1. " SC_SPIPHA ,Clock phase configuration" "First edge,Second edge"
|
|
bitfld.long 0x00 0. " SC_SPIPOL ,Clock polarity configuration" "Rising leading edge,Falling leading edge"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "SC2_SPISTAT,SPI Status Register"
|
|
bitfld.long 0x00 3. " SC_SPITXIDLE ,Transmit FIFO and the transmit serializer are empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " SC_SPITXFREE ,Transmit FIFO has space to accept at least one byte" "False,True"
|
|
bitfld.long 0x00 1. " SC_SPIRXVAL ,Receive FIFO contains at least one byte" "Not contain,Contain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_SPIRXOVF ,Byte is received when the receive FIFO is full" "Not received,Received"
|
|
if (((per.l(ad:0x4000C000+0x58))&0x10)==0x10)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SC2_RATELIN,Serial Clock Linear Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " SC_RATELIN ,Linear component of the clock rate" "12MHz/(1*2^EXP),12MHz/(2*2^EXP),12MHz/(3*2^EXP),12MHz/(4*2^EXP),12MHz/(5*2^EXP),12MHz/(6*2^EXP),12MHz/(7*2^EXP),12MHz/(8*2^EXP),12MHz/(9*2^EXP),12MHz/(10*2^EXP),12MHz/(11*2^EXP),12MHz/(12*2^EXP),12MHz/(13*2^EXP),12MHz/(14*2^EXP),12MHz/(15*2^EXP),12MHz/(16*2^EXP)"
|
|
line.long 0x04 "SC2_RATEEXP,Serial Clock Exponential Prescaler Register"
|
|
bitfld.long 0x04 0.--3. " SC_RATEEXP ,Exponential component (EXP value) of the clock rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x60++0x07
|
|
hide.long 0x00 "SC2_RATELIN,Serial Clock Linear Prescaler Register"
|
|
hide.long 0x04 "SC2_RATEEXP,Serial Clock Exponential Prescaler Register"
|
|
endif
|
|
elif (((per.l(ad:0x4000C000+0x54))&0x03)==0x03)
|
|
rgroup.long 0x44++0x03 "TWI Specific registers"
|
|
line.long 0x00 "SC2_TWISTAT,TWI Status Register"
|
|
bitfld.long 0x00 3. " SC_TWICMDFIN ,START or STOP command completed" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " SC_TWIRXFIN ,Byte is received" "Not received,Received"
|
|
bitfld.long 0x00 1. " SC_TWITXFIN ,Byte is transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_TWIRXNAK ,NACK is received from the slave" "Not received,Received"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "SC2_TWICTRL1,TWI Control Register 1"
|
|
bitfld.long 0x00 3. " SC_TWISTOP ,Send the STOP command" "Not sent,Sent"
|
|
bitfld.long 0x00 2. " SC_TWISTART ,Send the START or repeated START command" "Not sent,Sent"
|
|
bitfld.long 0x00 1. " SC_TWISEND ,Transmit a byte" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_TWIRECV ,Receives a byte" "Not received,Received"
|
|
line.long 0x04 "SC2_TWICTRL2,TWI Control Register 2"
|
|
bitfld.long 0x04 0. " SC_TWIACK ,Signal ACK time selector" "After,Before"
|
|
elif (((per.l(ad:0x4000C000+0x54))&0x03)==0x01)
|
|
hgroup.long 0x3C++0x03 "UART Specific Registers"
|
|
hide.long 0x00 "SC2_DATA,Serial Data Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SC2_UARTSTAT,UART Status Register"
|
|
bitfld.long 0x00 6. " SC_UARTTXIDLE ,Transmit FIFO and the transmit serializer are empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " SC_UARTPARERR ,Byte in the data register was received with a parity error" "Without error,With error"
|
|
bitfld.long 0x00 4. " SC_UARTFRMERR ,Byte in the data register was received with a frame error" "Without error,With error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTRXOVF ,Receive FIFO has been overrun" "Not overrun,Overrun"
|
|
bitfld.long 0x00 2. " SC_UARTTXFREE ,Transmit FIFO has space for at least one byte" "Not have,Have"
|
|
bitfld.long 0x00 1. " SC_UARTRXVAL ,Receive FIFO contains at least one byte" "Not contain,Contain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_UARTCTS ,Logical state (not voltage level) of the 2CTS input" "Deasserted (high),Asserted (Low)"
|
|
if (((per.l(ad:0x4000C000+0x5C))&0x20)==0x20)
|
|
if (((per.l(ad:0x4000C000+0x5C))&0x20)==0x20)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC2_UARTCFG,UART Configuration Register"
|
|
bitfld.long 0x00 6. " SC_UARTAUTO ,Enable automatic nRTS control by hardware" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 2RTS/2CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_UARTRTS ,Directly controls the output at the 2RTS pin" "Pin is high,Pin is low"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC2_UARTCFG,UART Configuration Register"
|
|
bitfld.long 0x00 6. " SC_UARTAUTO ,Enable automatic nRTS control by hardware" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 2RTS/2CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disbled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline ""
|
|
endif
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC2_UARTCFG,UART Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 2RTS/2CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline ""
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0x6C))&0x01)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SC2_UARTPER,UART Baud Rate Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_UARTPER ,The integer part of baud rate period (N) by equation: rate = 24MHz/(2*N + 0)"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SC2_UARTPER,UART Baud Rate Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_UARTPER ,The integer part of baud rate period (N) by equation: rate = 24MHz/(2*N + 1)"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SC2_UARTFRAC,UART Baud Rate Fractional Period Register"
|
|
bitfld.long 0x00 0. " SC_UARTFRAC ,The fractional part of the baud rate period (F) by equation: rate = 24MHz/(2*N + F)" "0,1"
|
|
endif
|
|
group.long 0x30++0x03 "DMA Channel 2 Registers"
|
|
line.long 0x00 "SC2_DMACTRL,Serial DMA Control Register"
|
|
bitfld.long 0x00 5. " SC_TXDMARST ,Reset the transmit DMA" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SC_RXDMARST ,Reset the receive DMA" "No reset,Reset"
|
|
bitfld.long 0x00 3. " SC_TXLODB ,Load DMA transmit buffer B and allow DMA controller to start processing transmit buffer B" "No effect/Idle,Start/Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXLODA ,Load DMA transmit buffer A and allow DMA controller to start processing transmit buffer A" "No effect/Idle,Start/Pending"
|
|
bitfld.long 0x00 1. " SC_RXLODB ,Load DMA receive buffer B and allow DMA controller to start processing receive buffer B" "No effect/Idle,Start/Pending"
|
|
bitfld.long 0x00 0. " SC_RXLODA ,Load DMA receive buffer A and allow DMA controller to start processing receive buffer A" "No effect/Idle,Start/Pending"
|
|
textline ""
|
|
if (((per.l(ad:0x4000C000+0x54))&0x03)==0x01)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SC2_DMASTAT,Serial DMA Status Register"
|
|
bitfld.long 0x00 10.--12. " SC_RXSSEL ,Status of the receive count saved in SCx_RXCNTSAVED (for SPI slave mode)" "None,,Buffer A's count saved/2SSEL deasserted once,Buffer B's count saved/2SSEL deasserted once,,,Buffer A's count saved/2SSEL deasserted more than once,Buffer B's count saved/2SSEL deasserted more than once"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SC_RXFRMB ,DMA receive buffer B reads a byte with a frame error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SC_RXFRMA ,DMA receive buffer A reads a byte with a frame error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SC_RXPARB ,DMA receive buffer B reads a byte with a parity error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SC_RXPARA ,DMA receive buffer A reads a byte with a parity error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SC_RXOVFB ,DMA receive buffer B was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SC_RXOVFA ,DMA receive buffer A was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_TXACTB ,DMA transmit buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXACTA ,DMA transmit buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC_RXACTB ,DMA receive buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_RXACTA ,DMA receive buffer A is active" "Not active,Active"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SC2_DMASTAT,Serial DMA Status Register"
|
|
bitfld.long 0x00 10.--12. " SC_RXSSEL ,Status of the receive count saved in SCx_RXCNTSAVED (for SPI slave mode)" "None,,Buffer A's count saved/2SSEL deasserted once,Buffer B's count saved/2SSEL deasserted once,,,Buffer A's count saved/2SSEL deasserted more than once,Buffer B's count saved/2SSEL deasserted more than once"
|
|
textline ""
|
|
textline ""
|
|
textline ""
|
|
textline ""
|
|
textline " "
|
|
bitfld.long 0x00 5. " SC_RXOVFB ,DMA receive buffer B was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SC_RXOVFA ,DMA receive buffer A was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_TXACTB ,DMA transmit buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXACTA ,DMA transmit buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC_RXACTB ,DMA receive buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_RXACTA ,DMA receive buffer A is active" "Not active,Active"
|
|
endif
|
|
textline ""
|
|
width 16.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC2_TXBEGA,Transmit DMA Begin Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXBEGA ,DMA transmit buffer A start address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC2_TXBEGB,Transmit DMA Begin Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXBEGB ,DMA transmit buffer B start address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC2_TXENDA,Transmit DMA End Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXENDA ,Address of the last byte that will be read from the DMA transmit buffer A"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC2_TXENDB,Transmit DMA End Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXENDB ,Address of the last byte that will be read from the DMA transmit buffer B"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SC2_TXCNT,Transmit DMA Count Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXCNT ,Offset from the start of the active DMA transmit buffer from which the next byte will be read"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC2_RXBEGA,Receive DMA Begin Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXBEGA ,DMA receive buffer A start address"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC2_RXBEGB,Receive DMA Begin Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXBEGB ,DMA receive buffer B start address"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC2_RXENDA,Receive DMA End Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXENDA ,Address of the last byte that will be written in the DMA receive buffer A"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC2_RXENDB,Receive DMA End Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXENDB ,Address of the last byte that will be written in the DMA receive buffer B"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC2_RXCNTA,Receive DMA Count Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXCNTA ,Offset from the start of DMA receive buffer A at which the next byte will be written"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC2_RXCNTB,Receive DMA Count Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXCNTB ,Offset from the start of DMA receive buffer B at which the next byte will be written"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "SC2_RXCNTSAVED,Saved Receive DMA Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_RXCNTSAVED ,Receive DMA count saved in SPI slave mode"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SC2_RXERRA,DMA First Receive Error Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXERRA ,Offset from the start of DMA receive buffer A of the first byte received with a parity, frame, or overflow error"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SC2_RXERRB,DMA First Receive Error Register B"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " SC_RXERRB ,Offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SC3"
|
|
base ad:0x4000D800
|
|
width 14.
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SC3_MODE,Serial Mode Register"
|
|
bitfld.long 0x00 0.--1. " SC_MODE ,Serial controller mode" "Disabled,UART,SPI,TWI"
|
|
base ad:0x4000A870
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_SC3FLAG,Serial Controller 3 Interrupt Flag Register"
|
|
bitfld.long 0x00 14. " INT_SC3PARERR ,Parity error received (for UART) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " INT_SC3FRMERR ,Frame error received (for UART) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " INT_SCTXULDB ,DMA transmit buffer B unloaded interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_SCTXULDA ,DMA transmit buffer A unloaded interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " INT_SCRXULDB ,DMA receive buffer B unloaded interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " INT_SCRXULDA ,DMA receive buffer A unloaded interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INT_SCNAK ,NACK received (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " INT_SCCMDFIN ,START/STOP command complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " INT_SCTXFIN ,Transmit operation complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_SCRXFIN ,Receive operation complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " INT_SCTXUND ,Transmit buffer underrun interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " INT_SCRXOVF ,Receive buffer overrun interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_SCTXIDLE ,Transmitter idle interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " INT_SCTXFREE ,Transmit buffer free interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " INT_SCRXVAL ,Receive buffer has data interrupt pending" "Not pending,Pending"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INT_SC3CFG,Serial Controller 3 Interrupt Configuration Register"
|
|
bitfld.long 0x00 14. " INT_SC3PARERR ,Parity error received (for UART) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INT_SC3FRMERR ,Frame error received (for UART) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INT_SCTXULDB ,DMA transmit buffer B unloaded interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_SCTXULDA ,DMA transmit buffer A unloaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INT_SCRXULDB ,DMA receive buffer B unloaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INT_SCRXULDA ,DMA receive buffer A unloaded interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INT_SCNAK ,NACK received (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INT_SCCMDFIN ,START/STOP command complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INT_SCTXFIN ,Transmit operation complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_SCRXFIN ,Receive operation complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_SCTXUND ,Transmit buffer underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_SCRXOVF ,Receive buffer overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_SCTXIDLE ,Transmitter idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_SCTXFREE ,Transmit buffer free interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INT_SCRXVAL ,Receive buffer has data interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC3_INTMODE,Serial Controller 1 Interrupt Mode Register"
|
|
bitfld.long 0x00 2. " SC_TXIDLELEVEL ,Transmitter idle interrupt mode" "Edge triggered,Level triggered"
|
|
bitfld.long 0x00 1. " SC_TXFREELEVEL ,Transmit buffer free interrupt mode" "Edge triggered,Level triggered"
|
|
bitfld.long 0x00 0. " SC_RXVALLEVEL ,Receive buffer has data interrupt mode" "Edge triggered,Level triggered"
|
|
base ad:0x4000D800
|
|
if (((per.l(ad:0x4000D800+0x54))&0x03)==0x02)
|
|
hgroup.long 0x3C++0x03 "SPI Specific registers"
|
|
hide.long 0x00 "SC3_DATA,Serial Data Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
if (((per.l(ad:0x4000D800+0x58))&0x10)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SC3_SPICFG,SPI Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 4. " SC_SPIMST ,SPI mode select" "Slave,Master"
|
|
bitfld.long 0x00 3. " SC_SPIRPT ,Control behavior when serializer must send data from empty serializer" "Send busy token,Repeat last byte"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_SPIORD ,bit order in which SPI data is transmitted and received" "MSB first,LSB first"
|
|
bitfld.long 0x00 1. " SC_SPIPHA ,Clock phase configuration" "First edge,Second edge"
|
|
bitfld.long 0x00 0. " SC_SPIPOL ,Clock polarity configuration" "Rising leading edge,Falling leading edge"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SC3_SPICFG,SPI Configuration Register"
|
|
bitfld.long 0x00 5. " SC_SPIRXDRV ,Initiate transactions" "Data available,Buffer has space"
|
|
bitfld.long 0x00 4. " SC_SPIMST ,SPI mode select" "Slave,Master"
|
|
bitfld.long 0x00 3. " SC_SPIRPT ,Control behavior when serializer must send data from empty serializer" "Send busy token,Repeat last byte"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_SPIORD ,bit order in which SPI data is transmitted and received" "MSB first,LSB first"
|
|
bitfld.long 0x00 1. " SC_SPIPHA ,Clock phase configuration" "First edge,Second edge"
|
|
bitfld.long 0x00 0. " SC_SPIPOL ,Clock polarity configuration" "Rising leading edge,Falling leading edge"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "SC3_SPISTAT,SPI Status Register"
|
|
bitfld.long 0x00 3. " SC_SPITXIDLE ,Transmit FIFO and the transmit serializer are empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " SC_SPITXFREE ,Transmit FIFO has space to accept at least one byte" "False,True"
|
|
bitfld.long 0x00 1. " SC_SPIRXVAL ,Receive FIFO contains at least one byte" "Not contain,Contain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_SPIRXOVF ,Byte is received when the receive FIFO is full" "Not received,Received"
|
|
if (((per.l(ad:0x4000D800+0x58))&0x10)==0x10)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SC3_RATELIN,Serial Clock Linear Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " SC_RATELIN ,Linear component of the clock rate" "12MHz/(1*2^EXP),12MHz/(2*2^EXP),12MHz/(3*2^EXP),12MHz/(4*2^EXP),12MHz/(5*2^EXP),12MHz/(6*2^EXP),12MHz/(7*2^EXP),12MHz/(8*2^EXP),12MHz/(9*2^EXP),12MHz/(10*2^EXP),12MHz/(11*2^EXP),12MHz/(12*2^EXP),12MHz/(13*2^EXP),12MHz/(14*2^EXP),12MHz/(15*2^EXP),12MHz/(16*2^EXP)"
|
|
line.long 0x04 "SC3_RATEEXP,Serial Clock Exponential Prescaler Register"
|
|
bitfld.long 0x04 0.--3. " SC_RATEEXP ,Exponential component (EXP value) of the clock rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x60++0x07
|
|
hide.long 0x00 "SC3_RATELIN,Serial Clock Linear Prescaler Register"
|
|
hide.long 0x04 "SC3_RATEEXP,Serial Clock Exponential Prescaler Register"
|
|
endif
|
|
elif (((per.l(ad:0x4000D800+0x54))&0x03)==0x03)
|
|
rgroup.long 0x44++0x03 "TWI Specific registers"
|
|
line.long 0x00 "SC3_TWISTAT,TWI Status Register"
|
|
bitfld.long 0x00 3. " SC_TWICMDFIN ,START or STOP command completed" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " SC_TWIRXFIN ,Byte is received" "Not received,Received"
|
|
bitfld.long 0x00 1. " SC_TWITXFIN ,Byte is transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_TWIRXNAK ,NACK is received from the slave" "Not received,Received"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "SC3_TWICTRL1,TWI Control Register 1"
|
|
bitfld.long 0x00 3. " SC_TWISTOP ,Send the STOP command" "Not sent,Sent"
|
|
bitfld.long 0x00 2. " SC_TWISTART ,Send the START or repeated START command" "Not sent,Sent"
|
|
bitfld.long 0x00 1. " SC_TWISEND ,Transmit a byte" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_TWIRECV ,Receives a byte" "Not received,Received"
|
|
line.long 0x04 "SC3_TWICTRL2,TWI Control Register 2"
|
|
bitfld.long 0x04 0. " SC_TWIACK ,Signal ACK time selector" "After,Before"
|
|
elif (((per.l(ad:0x4000D800+0x54))&0x03)==0x01)
|
|
hgroup.long 0x3C++0x03 "UART Specific Registers"
|
|
hide.long 0x00 "SC3_DATA,Serial Data Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SC3_UARTSTAT,UART Status Register"
|
|
bitfld.long 0x00 6. " SC_UARTTXIDLE ,Transmit FIFO and the transmit serializer are empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " SC_UARTPARERR ,Byte in the data register was received with a parity error" "Without error,With error"
|
|
bitfld.long 0x00 4. " SC_UARTFRMERR ,Byte in the data register was received with a frame error" "Without error,With error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTRXOVF ,Receive FIFO has been overrun" "Not overrun,Overrun"
|
|
bitfld.long 0x00 2. " SC_UARTTXFREE ,Transmit FIFO has space for at least one byte" "Not have,Have"
|
|
bitfld.long 0x00 1. " SC_UARTRXVAL ,Receive FIFO contains at least one byte" "Not contain,Contain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_UARTCTS ,Logical state (not voltage level) of the 3CTS input" "Deasserted (high),Asserted (Low)"
|
|
if (((per.l(ad:0x4000D800+0x5C))&0x20)==0x20)
|
|
if (((per.l(ad:0x4000D800+0x5C))&0x20)==0x20)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC3_UARTCFG,UART Configuration Register"
|
|
bitfld.long 0x00 6. " SC_UARTAUTO ,Enable automatic nRTS control by hardware" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 3RTS/3CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_UARTRTS ,Directly controls the output at the 3RTS pin" "Pin is high,Pin is low"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC3_UARTCFG,UART Configuration Register"
|
|
bitfld.long 0x00 6. " SC_UARTAUTO ,Enable automatic nRTS control by hardware" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 3RTS/3CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disbled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline ""
|
|
endif
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC3_UARTCFG,UART Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 3RTS/3CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline ""
|
|
endif
|
|
if (((per.l(ad:0x4000D800+0x6C))&0x01)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SC3_UARTPER,UART Baud Rate Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_UARTPER ,The integer part of baud rate period (N) by equation: rate = 24MHz/(2*N + 0)"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SC3_UARTPER,UART Baud Rate Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_UARTPER ,The integer part of baud rate period (N) by equation: rate = 24MHz/(2*N + 1)"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SC3_UARTFRAC,UART Baud Rate Fractional Period Register"
|
|
bitfld.long 0x00 0. " SC_UARTFRAC ,The fractional part of the baud rate period (F) by equation: rate = 24MHz/(2*N + F)" "0,1"
|
|
endif
|
|
group.long 0x30++0x03 "DMA Channel 3 Registers"
|
|
line.long 0x00 "SC3_DMACTRL,Serial DMA Control Register"
|
|
bitfld.long 0x00 5. " SC_TXDMARST ,Reset the transmit DMA" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SC_RXDMARST ,Reset the receive DMA" "No reset,Reset"
|
|
bitfld.long 0x00 3. " SC_TXLODB ,Load DMA transmit buffer B and allow DMA controller to start processing transmit buffer B" "No effect/Idle,Start/Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXLODA ,Load DMA transmit buffer A and allow DMA controller to start processing transmit buffer A" "No effect/Idle,Start/Pending"
|
|
bitfld.long 0x00 1. " SC_RXLODB ,Load DMA receive buffer B and allow DMA controller to start processing receive buffer B" "No effect/Idle,Start/Pending"
|
|
bitfld.long 0x00 0. " SC_RXLODA ,Load DMA receive buffer A and allow DMA controller to start processing receive buffer A" "No effect/Idle,Start/Pending"
|
|
textline ""
|
|
if (((per.l(ad:0x4000D800+0x54))&0x03)==0x01)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SC3_DMASTAT,Serial DMA Status Register"
|
|
bitfld.long 0x00 10.--12. " SC_RXSSEL ,Status of the receive count saved in SCx_RXCNTSAVED (for SPI slave mode)" "None,,Buffer A's count saved/3SSEL deasserted once,Buffer B's count saved/3SSEL deasserted once,,,Buffer A's count saved/3SSEL deasserted more than once,Buffer B's count saved/3SSEL deasserted more than once"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SC_RXFRMB ,DMA receive buffer B reads a byte with a frame error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SC_RXFRMA ,DMA receive buffer A reads a byte with a frame error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SC_RXPARB ,DMA receive buffer B reads a byte with a parity error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SC_RXPARA ,DMA receive buffer A reads a byte with a parity error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SC_RXOVFB ,DMA receive buffer B was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SC_RXOVFA ,DMA receive buffer A was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_TXACTB ,DMA transmit buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXACTA ,DMA transmit buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC_RXACTB ,DMA receive buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_RXACTA ,DMA receive buffer A is active" "Not active,Active"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SC3_DMASTAT,Serial DMA Status Register"
|
|
bitfld.long 0x00 10.--12. " SC_RXSSEL ,Status of the receive count saved in SCx_RXCNTSAVED (for SPI slave mode)" "None,,Buffer A's count saved/3SSEL deasserted once,Buffer B's count saved/3SSEL deasserted once,,,Buffer A's count saved/3SSEL deasserted more than once,Buffer B's count saved/3SSEL deasserted more than once"
|
|
textline ""
|
|
textline ""
|
|
textline ""
|
|
textline ""
|
|
textline " "
|
|
bitfld.long 0x00 5. " SC_RXOVFB ,DMA receive buffer B was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SC_RXOVFA ,DMA receive buffer A was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_TXACTB ,DMA transmit buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXACTA ,DMA transmit buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC_RXACTB ,DMA receive buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_RXACTA ,DMA receive buffer A is active" "Not active,Active"
|
|
endif
|
|
textline ""
|
|
width 16.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC3_TXBEGA,Transmit DMA Begin Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXBEGA ,DMA transmit buffer A start address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC3_TXBEGB,Transmit DMA Begin Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXBEGB ,DMA transmit buffer B start address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC3_TXENDA,Transmit DMA End Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXENDA ,Address of the last byte that will be read from the DMA transmit buffer A"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC3_TXENDB,Transmit DMA End Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXENDB ,Address of the last byte that will be read from the DMA transmit buffer B"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SC3_TXCNT,Transmit DMA Count Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXCNT ,Offset from the start of the active DMA transmit buffer from which the next byte will be read"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC3_RXBEGA,Receive DMA Begin Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXBEGA ,DMA receive buffer A start address"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC3_RXBEGB,Receive DMA Begin Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXBEGB ,DMA receive buffer B start address"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC3_RXENDA,Receive DMA End Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXENDA ,Address of the last byte that will be written in the DMA receive buffer A"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC3_RXENDB,Receive DMA End Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXENDB ,Address of the last byte that will be written in the DMA receive buffer B"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC3_RXCNTA,Receive DMA Count Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXCNTA ,Offset from the start of DMA receive buffer A at which the next byte will be written"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC3_RXCNTB,Receive DMA Count Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXCNTB ,Offset from the start of DMA receive buffer B at which the next byte will be written"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "SC3_RXCNTSAVED,Saved Receive DMA Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_RXCNTSAVED ,Receive DMA count saved in SPI slave mode"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SC3_RXERRA,DMA First Receive Error Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXERRA ,Offset from the start of DMA receive buffer A of the first byte received with a parity, frame, or overflow error"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SC3_RXERRB,DMA First Receive Error Register B"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " SC_RXERRB ,Offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SC4"
|
|
base ad:0x4000D000
|
|
width 14.
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SC4_MODE,Serial Mode Register"
|
|
bitfld.long 0x00 0.--1. " SC_MODE ,Serial controller mode" "Disabled,,SPI,TWI"
|
|
base ad:0x4000A874
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_SC4FLAG,Serial Controller 4 Interrupt Flag Register"
|
|
bitfld.long 0x00 14. " INT_SC4PARERR ,Parity error received (for UART) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " INT_SC4FRMERR ,Frame error received (for UART) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " INT_SCTXULDB ,DMA transmit buffer B unloaded interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_SCTXULDA ,DMA transmit buffer A unloaded interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " INT_SCRXULDB ,DMA receive buffer B unloaded interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " INT_SCRXULDA ,DMA receive buffer A unloaded interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INT_SCNAK ,NACK received (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " INT_SCCMDFIN ,START/STOP command complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " INT_SCTXFIN ,Transmit operation complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_SCRXFIN ,Receive operation complete (for TWI) interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " INT_SCTXUND ,Transmit buffer underrun interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " INT_SCRXOVF ,Receive buffer overrun interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_SCTXIDLE ,Transmitter idle interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " INT_SCTXFREE ,Transmit buffer free interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " INT_SCRXVAL ,Receive buffer has data interrupt pending" "Not pending,Pending"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INT_SC4CFG,Serial Controller 4 Interrupt Configuration Register"
|
|
bitfld.long 0x00 14. " INT_SC4PARERR ,Parity error received (for UART) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INT_SC4FRMERR ,Frame error received (for UART) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INT_SCTXULDB ,DMA transmit buffer B unloaded interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_SCTXULDA ,DMA transmit buffer A unloaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INT_SCRXULDB ,DMA receive buffer B unloaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INT_SCRXULDA ,DMA receive buffer A unloaded interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INT_SCNAK ,NACK received (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INT_SCCMDFIN ,START/STOP command complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INT_SCTXFIN ,Transmit operation complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_SCRXFIN ,Receive operation complete (for TWI) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_SCTXUND ,Transmit buffer underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_SCRXOVF ,Receive buffer overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_SCTXIDLE ,Transmitter idle interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_SCTXFREE ,Transmit buffer free interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INT_SCRXVAL ,Receive buffer has data interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC4_INTMODE,Serial Controller 1 Interrupt Mode Register"
|
|
bitfld.long 0x00 2. " SC_TXIDLELEVEL ,Transmitter idle interrupt mode" "Edge triggered,Level triggered"
|
|
bitfld.long 0x00 1. " SC_TXFREELEVEL ,Transmit buffer free interrupt mode" "Edge triggered,Level triggered"
|
|
bitfld.long 0x00 0. " SC_RXVALLEVEL ,Receive buffer has data interrupt mode" "Edge triggered,Level triggered"
|
|
base ad:0x4000D000
|
|
if (((per.l(ad:0x4000D000+0x54))&0x03)==0x02)
|
|
hgroup.long 0x3C++0x03 "SPI Specific registers"
|
|
hide.long 0x00 "SC4_DATA,Serial Data Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
if (((per.l(ad:0x4000D000+0x58))&0x10)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SC4_SPICFG,SPI Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 4. " SC_SPIMST ,SPI mode select" "Slave,Master"
|
|
bitfld.long 0x00 3. " SC_SPIRPT ,Control behavior when serializer must send data from empty serializer" "Send busy token,Repeat last byte"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_SPIORD ,bit order in which SPI data is transmitted and received" "MSB first,LSB first"
|
|
bitfld.long 0x00 1. " SC_SPIPHA ,Clock phase configuration" "First edge,Second edge"
|
|
bitfld.long 0x00 0. " SC_SPIPOL ,Clock polarity configuration" "Rising leading edge,Falling leading edge"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SC4_SPICFG,SPI Configuration Register"
|
|
bitfld.long 0x00 5. " SC_SPIRXDRV ,Initiate transactions" "Data available,Buffer has space"
|
|
bitfld.long 0x00 4. " SC_SPIMST ,SPI mode select" "Slave,Master"
|
|
bitfld.long 0x00 3. " SC_SPIRPT ,Control behavior when serializer must send data from empty serializer" "Send busy token,Repeat last byte"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_SPIORD ,bit order in which SPI data is transmitted and received" "MSB first,LSB first"
|
|
bitfld.long 0x00 1. " SC_SPIPHA ,Clock phase configuration" "First edge,Second edge"
|
|
bitfld.long 0x00 0. " SC_SPIPOL ,Clock polarity configuration" "Rising leading edge,Falling leading edge"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "SC4_SPISTAT,SPI Status Register"
|
|
bitfld.long 0x00 3. " SC_SPITXIDLE ,Transmit FIFO and the transmit serializer are empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " SC_SPITXFREE ,Transmit FIFO has space to accept at least one byte" "False,True"
|
|
bitfld.long 0x00 1. " SC_SPIRXVAL ,Receive FIFO contains at least one byte" "Not contain,Contain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_SPIRXOVF ,Byte is received when the receive FIFO is full" "Not received,Received"
|
|
if (((per.l(ad:0x4000D000+0x58))&0x10)==0x10)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SC4_RATELIN,Serial Clock Linear Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " SC_RATELIN ,Linear component of the clock rate" "12MHz/(1*2^EXP),12MHz/(2*2^EXP),12MHz/(3*2^EXP),12MHz/(4*2^EXP),12MHz/(5*2^EXP),12MHz/(6*2^EXP),12MHz/(7*2^EXP),12MHz/(8*2^EXP),12MHz/(9*2^EXP),12MHz/(10*2^EXP),12MHz/(11*2^EXP),12MHz/(12*2^EXP),12MHz/(13*2^EXP),12MHz/(14*2^EXP),12MHz/(15*2^EXP),12MHz/(16*2^EXP)"
|
|
line.long 0x04 "SC4_RATEEXP,Serial Clock Exponential Prescaler Register"
|
|
bitfld.long 0x04 0.--3. " SC_RATEEXP ,Exponential component (EXP value) of the clock rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x60++0x07
|
|
hide.long 0x00 "SC4_RATELIN,Serial Clock Linear Prescaler Register"
|
|
hide.long 0x04 "SC4_RATEEXP,Serial Clock Exponential Prescaler Register"
|
|
endif
|
|
elif (((per.l(ad:0x4000D000+0x54))&0x03)==0x03)
|
|
rgroup.long 0x44++0x03 "TWI Specific registers"
|
|
line.long 0x00 "SC4_TWISTAT,TWI Status Register"
|
|
bitfld.long 0x00 3. " SC_TWICMDFIN ,START or STOP command completed" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " SC_TWIRXFIN ,Byte is received" "Not received,Received"
|
|
bitfld.long 0x00 1. " SC_TWITXFIN ,Byte is transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_TWIRXNAK ,NACK is received from the slave" "Not received,Received"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "SC4_TWICTRL1,TWI Control Register 1"
|
|
bitfld.long 0x00 3. " SC_TWISTOP ,Send the STOP command" "Not sent,Sent"
|
|
bitfld.long 0x00 2. " SC_TWISTART ,Send the START or repeated START command" "Not sent,Sent"
|
|
bitfld.long 0x00 1. " SC_TWISEND ,Transmit a byte" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_TWIRECV ,Receives a byte" "Not received,Received"
|
|
line.long 0x04 "SC4_TWICTRL2,TWI Control Register 2"
|
|
bitfld.long 0x04 0. " SC_TWIACK ,Signal ACK time selector" "After,Before"
|
|
elif (((per.l(ad:0x4000D000+0x54))&0x03)==0x01)
|
|
hgroup.long 0x3C++0x03 "UART Specific Registers"
|
|
hide.long 0x00 "SC4_DATA,Serial Data Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SC4_UARTSTAT,UART Status Register"
|
|
bitfld.long 0x00 6. " SC_UARTTXIDLE ,Transmit FIFO and the transmit serializer are empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " SC_UARTPARERR ,Byte in the data register was received with a parity error" "Without error,With error"
|
|
bitfld.long 0x00 4. " SC_UARTFRMERR ,Byte in the data register was received with a frame error" "Without error,With error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTRXOVF ,Receive FIFO has been overrun" "Not overrun,Overrun"
|
|
bitfld.long 0x00 2. " SC_UARTTXFREE ,Transmit FIFO has space for at least one byte" "Not have,Have"
|
|
bitfld.long 0x00 1. " SC_UARTRXVAL ,Receive FIFO contains at least one byte" "Not contain,Contain"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_UARTCTS ,Logical state (not voltage level) of the 4CTS input" "Deasserted (high),Asserted (Low)"
|
|
if (((per.l(ad:0x4000D000+0x5C))&0x20)==0x20)
|
|
if (((per.l(ad:0x4000D000+0x5C))&0x20)==0x20)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC4_UARTCFG,UART Configuration Register"
|
|
bitfld.long 0x00 6. " SC_UARTAUTO ,Enable automatic nRTS control by hardware" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 4RTS/4CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_UARTRTS ,Directly controls the output at the 4RTS pin" "Pin is high,Pin is low"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC4_UARTCFG,UART Configuration Register"
|
|
bitfld.long 0x00 6. " SC_UARTAUTO ,Enable automatic nRTS control by hardware" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 4RTS/4CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disbled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline ""
|
|
endif
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SC4_UARTCFG,UART Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 5. " SC_UARTFLOW ,Enable using 4RTS/4CTS flow control signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SC_UARTODD ,Kind of parity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_UARTPAR ,Use parity bits enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SC_UART2STP ,Number of stop bits transmitted" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 1. " SC_UART8BIT ,Number of data bits" "7 data bits,8 data bits"
|
|
textline ""
|
|
endif
|
|
if (((per.l(ad:0x4000D000+0x6C))&0x01)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SC4_UARTPER,UART Baud Rate Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_UARTPER ,The integer part of baud rate period (N) by equation: rate = 24MHz/(2*N + 0)"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SC4_UARTPER,UART Baud Rate Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_UARTPER ,The integer part of baud rate period (N) by equation: rate = 24MHz/(2*N + 1)"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SC4_UARTFRAC,UART Baud Rate Fractional Period Register"
|
|
bitfld.long 0x00 0. " SC_UARTFRAC ,The fractional part of the baud rate period (F) by equation: rate = 24MHz/(2*N + F)" "0,1"
|
|
endif
|
|
group.long 0x30++0x03 "DMA Channel 4 Registers"
|
|
line.long 0x00 "SC4_DMACTRL,Serial DMA Control Register"
|
|
bitfld.long 0x00 5. " SC_TXDMARST ,Reset the transmit DMA" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SC_RXDMARST ,Reset the receive DMA" "No reset,Reset"
|
|
bitfld.long 0x00 3. " SC_TXLODB ,Load DMA transmit buffer B and allow DMA controller to start processing transmit buffer B" "No effect/Idle,Start/Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXLODA ,Load DMA transmit buffer A and allow DMA controller to start processing transmit buffer A" "No effect/Idle,Start/Pending"
|
|
bitfld.long 0x00 1. " SC_RXLODB ,Load DMA receive buffer B and allow DMA controller to start processing receive buffer B" "No effect/Idle,Start/Pending"
|
|
bitfld.long 0x00 0. " SC_RXLODA ,Load DMA receive buffer A and allow DMA controller to start processing receive buffer A" "No effect/Idle,Start/Pending"
|
|
textline ""
|
|
if (((per.l(ad:0x4000D000+0x54))&0x03)==0x01)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SC4_DMASTAT,Serial DMA Status Register"
|
|
bitfld.long 0x00 10.--12. " SC_RXSSEL ,Status of the receive count saved in SCx_RXCNTSAVED (for SPI slave mode)" "None,,Buffer A's count saved/4SSEL deasserted once,Buffer B's count saved/4SSEL deasserted once,,,Buffer A's count saved/4SSEL deasserted more than once,Buffer B's count saved/4SSEL deasserted more than once"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SC_RXFRMB ,DMA receive buffer B reads a byte with a frame error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SC_RXFRMA ,DMA receive buffer A reads a byte with a frame error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SC_RXPARB ,DMA receive buffer B reads a byte with a parity error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SC_RXPARA ,DMA receive buffer A reads a byte with a parity error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SC_RXOVFB ,DMA receive buffer B was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SC_RXOVFA ,DMA receive buffer A was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_TXACTB ,DMA transmit buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXACTA ,DMA transmit buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC_RXACTB ,DMA receive buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_RXACTA ,DMA receive buffer A is active" "Not active,Active"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SC4_DMASTAT,Serial DMA Status Register"
|
|
bitfld.long 0x00 10.--12. " SC_RXSSEL ,Status of the receive count saved in SCx_RXCNTSAVED (for SPI slave mode)" "None,,Buffer A's count saved/4SSEL deasserted once,Buffer B's count saved/4SSEL deasserted once,,,Buffer A's count saved/4SSEL deasserted more than once,Buffer B's count saved/4SSEL deasserted more than once"
|
|
textline ""
|
|
textline ""
|
|
textline ""
|
|
textline ""
|
|
textline " "
|
|
bitfld.long 0x00 5. " SC_RXOVFB ,DMA receive buffer B was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SC_RXOVFA ,DMA receive buffer A was passed an overrun error from FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SC_TXACTB ,DMA transmit buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SC_TXACTA ,DMA transmit buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SC_RXACTB ,DMA receive buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SC_RXACTA ,DMA receive buffer A is active" "Not active,Active"
|
|
endif
|
|
textline ""
|
|
width 16.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC4_TXBEGA,Transmit DMA Begin Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXBEGA ,DMA transmit buffer A start address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC4_TXBEGB,Transmit DMA Begin Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXBEGB ,DMA transmit buffer B start address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC4_TXENDA,Transmit DMA End Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXENDA ,Address of the last byte that will be read from the DMA transmit buffer A"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC4_TXENDB,Transmit DMA End Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXENDB ,Address of the last byte that will be read from the DMA transmit buffer B"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SC4_TXCNT,Transmit DMA Count Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_TXCNT ,Offset from the start of the active DMA transmit buffer from which the next byte will be read"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC4_RXBEGA,Receive DMA Begin Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXBEGA ,DMA receive buffer A start address"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC4_RXBEGB,Receive DMA Begin Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXBEGB ,DMA receive buffer B start address"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC4_RXENDA,Receive DMA End Address Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXENDA ,Address of the last byte that will be written in the DMA receive buffer A"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC4_RXENDB,Receive DMA End Address Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXENDB ,Address of the last byte that will be written in the DMA receive buffer B"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC4_RXCNTA,Receive DMA Count Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXCNTA ,Offset from the start of DMA receive buffer A at which the next byte will be written"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC4_RXCNTB,Receive DMA Count Register B"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXCNTB ,Offset from the start of DMA receive buffer B at which the next byte will be written"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "SC4_RXCNTSAVED,Saved Receive DMA Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SC_RXCNTSAVED ,Receive DMA count saved in SPI slave mode"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SC4_RXERRA,DMA First Receive Error Register A"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SC_RXERRA ,Offset from the start of DMA receive buffer A of the first byte received with a parity, frame, or overflow error"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SC4_RXERRB,DMA First Receive Error Register B"
|
|
hexmask.long.word 0x00 0.--13. 0x01 " SC_RXERRB ,Offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("EM3592")||cpuis("EM3596")||cpuis("EM3598")
|
|
tree "USB Device"
|
|
base ad:0x40011000
|
|
width 19.
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "USB_CTRL,USB Control Register"
|
|
bitfld.long 0x00 23. " USB_RESETCTRL ,Force a reset state internally to the USB core" "No reset,Reset"
|
|
bitfld.long 0x00 22. " USB_ENBUFOUTEP6B ,Enable endpoint 6 buffer B out" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " USB_ENBUFOUTEP5B ,Enable endpoint 5 buffer B out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " USB_ENBUFOUTEP4B ,Enable endpoint 4 buffer B out" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " USB_ENBUFOUTEP3B ,Enable endpoint 3 buffer B out" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USB_ENBUFOUTEP2B ,Enable endpoint 2 buffer B out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " USB_ENBUFOUTEP1B ,Enable endpoint 1 buffer B out" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USB_ENBUFOUTEP0B ,Enable endpoint 0 buffer B out" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USB_ENBUFINEP6B ,Enable endpoint 6 buffer B in" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " USB_ENBUFINEP5B ,Enable endpoint 5 buffer B in" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USB_ENBUFINEP4B ,Enable endpoint 4 buffer B in" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " USB_ENBUFINEP3B ,Enable endpoint 3 buffer B in" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " USB_ENBUFINEP2B ,Enable endpoint 2 buffer B in" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USB_ENBUFINEP1B ,Enable endpoint 1 buffer B in" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USB_ENBUFINEP0B ,Enable endpoint 0 buffer B in" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " USB_REMOTEWKUPEN ,Enable the remote-wakeup feature" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USB_CLRFEP0STALL ,Send command on ClearFeature selecton" "ACK,STALL"
|
|
bitfld.long 0x00 0. " USB_SELFPWRD ,USB is self-powered" "Not self-powered,Self-powered"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "USB_STATUS,USB Status Register"
|
|
bitfld.long 0x00 12. " USB_RESETSTAT ,USB reset is active" "Not active,Active"
|
|
bitfld.long 0x00 11. " USB_SUSPENDED ,Device is suspended" "Not suspended,Suspended"
|
|
hexmask.long.word 0x00 0.--10. 1. " USB_TIMESTAMP ,The timestamp of the reception of the last start of frame packet"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "USB_ENABLEIN,USB Endpoint in Enables Register"
|
|
bitfld.long 0x00 6. " USB_ENABLEINEP6 ,Enable endpoint 6 buffer A in" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " USB_ENABLEINEP5 ,Enable endpoint 5 buffer A in" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " USB_ENABLEINEP4 ,Enable endpoint 4 buffer A in" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_ENABLEINEP3 ,Enable endpoint 3 buffer A in" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USB_ENABLEINEP2 ,Enable endpoint 2 buffer A in" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USB_ENABLEINEP1 ,Enable endpoint 1 buffer A in" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " USB_ENABLEINEP0 ,Enable endpoint 0 buffer A in" ",Enabled"
|
|
line.long 0x04 "USB_ENABLEOUT,USB Endpoint OUT Enables Register"
|
|
bitfld.long 0x04 6. " USB_ENABLEOUTEP6 ,Enable endpoint 6 buffer A out" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " USB_ENABLEOUTEP5 ,Enable endpoint 5 buffer A out" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " USB_ENABLEOUTEP4 ,Enable endpoint 4 buffer A out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " USB_ENABLEOUTEP3 ,Enable endpoint 3 buffer A out" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " USB_ENABLEOUTEP2 ,Enable endpoint 2 buffer A out" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " USB_ENABLEOUTEP1 ,Enable endpoint 1 buffer A out" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " USB_ENABLEOUTEP0 ,Enable endpoint 0 buffer A out" ",Enabled"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "USB_INTF1SEL,USB Endpoint Interface 1 Select Register"
|
|
bitfld.long 0x00 31. " USB_INTF1SELEN ,Associate endpoints to inteface selector" "Interface 0,Interace 1"
|
|
bitfld.long 0x00 6. " USB_INTF1SELEP6 ,Associate endpoint 6 in with Interface selector" "Interface 0,Interace 1"
|
|
bitfld.long 0x00 5. " USB_INTF1SELEP5 ,Associate endpoint 5 in with Interface selector" "Interface 0,Interace 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " USB_INTF1SELEP4 ,Associate endpoint 4 in with Interface selector" "Interface 0,Interace 1"
|
|
bitfld.long 0x00 3. " USB_INTF1SELEP3 ,Associate endpoint 3 in with Interface selector" "Interface 0,Interace 1"
|
|
bitfld.long 0x00 2. " USB_INTF1SELEP2 ,Associate endpoint 2 in with Interface selector" "Interface 0,Interace 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " USB_INTF1SELEP1 ,Associate endpoint 1 in with Interface selector" "Interface 0,Interace 1"
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "USB_BUFBASEA,Base Address of Endpoint A Buffers in Main Memory Register"
|
|
line.long 0x04 "USB_BUFBASEB,Base Address of Endpoint B Buffers in Main Memory Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USB_TXLOAD,USB TX Buffer A and B Load Register"
|
|
bitfld.long 0x00 14. " USB_TXLOADEP6B ,Load endpoint 6, buffer B for transmit" "No effect,Load"
|
|
bitfld.long 0x00 13. " USB_TXLOADEP5B ,Load endpoint 5, buffer B for transmit" "No effect,Load"
|
|
bitfld.long 0x00 12. " USB_TXLOADEP4B ,Load endpoint 4, buffer B for transmit" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USB_TXLOADEP3B ,Load endpoint 3, buffer B for transmit" "No effect,Load"
|
|
bitfld.long 0x00 10. " USB_TXLOADEP2B ,Load endpoint 2, buffer B for transmit" "No effect,Load"
|
|
bitfld.long 0x00 9. " USB_TXLOADEP1B ,Load endpoint 1, buffer B for transmit" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x00 8. " USB_TXLOADEP0B ,Load endpoint 0, buffer B for transmit" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x00 6. " USB_TXLOADEP6A ,Load endpoint 6, buffer A for transmit" "No effect,Load"
|
|
bitfld.long 0x00 5. " USB_TXLOADEP5A ,Load endpoint 5, buffer A for transmit" "No effect,Load"
|
|
bitfld.long 0x00 4. " USB_TXLOADEP4A ,Load endpoint 4, buffer A for transmit" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_TXLOADEP3A ,Load endpoint 3, buffer A for transmit" "No effect,Load"
|
|
bitfld.long 0x00 2. " USB_TXLOADEP2A ,Load endpoint 2, buffer A for transmit" "No effect,Load"
|
|
bitfld.long 0x00 1. " USB_TXLOADEP1A ,Load endpoint 1, buffer A for transmit" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " USB_TXLOADEP0A ,Load endpoint 0, buffer A for transmit" "No effect,Load"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USB_TXACTIVE,USB Buffer A and Buffer B Transmit Active Status Register"
|
|
bitfld.long 0x00 14. " USB_TXACTIVEEP6B ,Endpoint 6, buffer B is active" "Not active,Active"
|
|
bitfld.long 0x00 13. " USB_TXACTIVEEP5B ,Endpoint 5, buffer B is active" "Not active,Active"
|
|
bitfld.long 0x00 12. " USB_TXACTIVEEP4B ,Endpoint 4, buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USB_TXACTIVEEP3B ,Endpoint 3, buffer B is active" "Not active,Active"
|
|
bitfld.long 0x00 10. " USB_TXACTIVEEP2B ,Endpoint 2, buffer B is active" "Not active,Active"
|
|
bitfld.long 0x00 9. " USB_TXACTIVEEP1B ,Endpoint 1, buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " USB_TXACTIVEEP0B ,Endpoint 0, buffer B is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 6. " USA_TXACTIVEEP6A ,Endpoint 6, buffer A is active" "Not active,Active"
|
|
bitfld.long 0x00 5. " USA_TXACTIVEEP5A ,Endpoint 5, buffer A is active" "Not active,Active"
|
|
bitfld.long 0x00 4. " USA_TXACTIVEEP4A ,Endpoint 4, buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USA_TXACTIVEEP3A ,Endpoint 3, buffer A is active" "Not active,Active"
|
|
bitfld.long 0x00 2. " USA_TXACTIVEEP2A ,Endpoint 2, buffer A is active" "Not active,Active"
|
|
bitfld.long 0x00 1. " USA_TXACTIVEEP1A ,Endpoint 1, buffer A is active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " USA_TXACTIVEEP0A ,Endpoint 0, buffer A is active" "Not active,Active"
|
|
textline ""
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USB_TXBUFSIZEEP0A,Number of Bytes to Transmit for Endpoint 0, Buffer A Register"
|
|
bitfld.long 0x00 0.--3. " USB_TXBUFSIZEEP0A ,Size of data to transmit for endpoint 0, buffer A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USB_TXBUFSIZEEP1A,Number of Bytes to Transmit for Endpoint 1, Buffer A Register"
|
|
bitfld.long 0x00 0.--3. " USB_TXBUFSIZEEP1A ,Size of data to transmit for endpoint 1, buffer A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USB_TXBUFSIZEEP2A,Number of Bytes to Transmit for Endpoint 2, Buffer A Register"
|
|
bitfld.long 0x00 0.--3. " USB_TXBUFSIZEEP2A ,Size of data to transmit for endpoint 2, buffer A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "USB_TXBUFSIZEEP3A,Number of Bytes to Transmit for Endpoint 3, Buffer A Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " USB_TXBUFSIZEEP3A ,Size of data to transmit for endpoint 3, buffer A"
|
|
line.long 0x04 "USB_TXBUFSIZEEP4A,Number of Bytes to Transmit for Endpoint 4, Buffer A Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " USB_TXBUFSIZEEP4A ,Size of data to transmit for endpoint 4, buffer A"
|
|
line.long 0x08 "USB_TXBUFSIZEEP5A,Number of Bytes to Transmit for Endpoint 5, Buffer A Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " USB_TXBUFSIZEEP5A ,Size of data to transmit for endpoint 5, buffer A"
|
|
line.long 0x0C "USB_TXBUFSIZEEP6A,Number of Bytes to Transmit for Endpoint 6, Buffer A Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " USB_TXBUFSIZEEP6A ,Size of data to transmit for endpoint 6, buffer A"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "USB_RXBUFSIZEEP0A,Number of Bytes Received in Endpoint 0, Buffer A Register"
|
|
bitfld.long 0x00 0.--3. " USB_RXBUFSIZEEP0A ,Size of data received on endpoint 0, buffer A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x7C++0x17
|
|
line.long 0x00 "USB_RXBUFSIZEEP1A,Number of Bytes Received in Endpoint 1, Buffer A Register"
|
|
bitfld.long 0x00 0.--3. " USB_RXBUFSIZEEP1A ,Size of data received on endpoint 1, buffer A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "USB_RXBUFSIZEEP2A,Number of Bytes Received in Endpoint 2, Buffer A Register"
|
|
bitfld.long 0x04 0.--3. " USB_RXBUFSIZEEP2A ,Size of data received on endpoint 2, buffer A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "USB_RXBUFSIZEEP3A,Number of Bytes Received in Endpoint 3, Buffer A Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " USB_RXBUFSIZEEP3A ,Size of data received on endpoint 3, buffer A"
|
|
line.long 0x0C "USB_RXBUFSIZEEP4A,Number of Bytes Received in Endpoint 4, Buffer A Register"
|
|
hexmask.long.byte 0x0C 0.--5. 1. " USB_RXBUFSIZEEP4A ,Size of data received on endpoint 4, buffer A"
|
|
line.long 0x10 "USB_RXBUFSIZEEP5A,Number of Bytes Received in Endpoint 5, Buffer A Register"
|
|
hexmask.long.byte 0x10 0.--6. 1. " USB_RXBUFSIZEEP5A ,Size of data received on endpoint 5, buffer A"
|
|
line.long 0x14 "USB_RXBUFSIZEEP6A,Number of Bytes Received in Endpoint 6, Buffer A Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " USB_RXBUFSIZEEP6A ,Size of data received on endpoint 6, buffer A"
|
|
textline ""
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "USB_TXBUFSIZEEP0B,Number of Bytes to Transmit for Endpoint 0, Buffer B Register"
|
|
bitfld.long 0x00 0.--3. " USB_TXBUFSIZEEP0B ,Size of data to transmit for endpoint 0, buffer B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "USB_TXBUFSIZEEP1B,Number of Bytes to Transmit for Endpoint 1, Buffer B Register"
|
|
bitfld.long 0x00 0.--3. " USB_TXBUFSIZEEP1B ,Size of data to transmit for endpoint 1, buffer B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "USB_TXBUFSIZEEP2B,Number of Bytes to Transmit for Endpoint 2, Buffer B Register"
|
|
bitfld.long 0x00 0.--3. " USB_TXBUFSIZEEP2B ,Size of data to transmit for endpoint 2, buffer B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "USB_TXBUFSIZEEP3B,Number of Bytes to Transmit for Endpoint 3, Buffer B Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " USB_TXBUFSIZEEP3B ,Size of data to transmit for endpoint 3, buffer B"
|
|
line.long 0x04 "USB_TXBUFSIZEEP4B,Number of Bytes to Transmit for Endpoint 4, Buffer B Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " USB_TXBUFSIZEEP4B ,Size of data to transmit for endpoint 4, buffer B"
|
|
line.long 0x08 "USB_TXBUFSIZEEP5B,Number of Bytes to Transmit for Endpoint 5, Buffer B Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " USB_TXBUFSIZEEP5B ,Size of data to transmit for endpoint 5, buffer B"
|
|
line.long 0x0C "USB_TXBUFSIZEEP6B,Number of Bytes to Transmit for Endpoint 6, Buffer B Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " USB_TXBUFSIZEEP6B ,Size of data to transmit for endpoint 6, buffer B"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "USB_RXBUFSIZEEP0B,Number of Bytes Received in Endpoint 0, Buffer B Register"
|
|
bitfld.long 0x00 0.--3. " USB_RXBUFSIZEEP0B ,Size of data received on endpoint 0, buffer B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "USB_RXBUFSIZEEP1B,Number of Bytes Received in Endpoint 1, Buffer B Register"
|
|
bitfld.long 0x00 0.--3. " USB_RXBUFSIZEEP1B ,Size of data received on endpoint 1, buffer B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "USB_RXBUFSIZEEP2B,Number of Bytes Received in Endpoint 2, Buffer B Register"
|
|
bitfld.long 0x00 0.--3. " USB_RXBUFSIZEEP2B ,Size of data received on endpoint 2, buffer B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "USB_RXBUFSIZEEP3B,Number of Bytes Received in Endpoint 3, Buffer B Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " USB_RXBUFSIZEEP3B ,Size of data received on endpoint 3, buffer B"
|
|
line.long 0x04 "USB_RXBUFSIZEEP4B,Number of Bytes Received in Endpoint 4, Buffer B Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " USB_RXBUFSIZEEP4B ,Size of data received on endpoint 4, buffer B"
|
|
line.long 0x08 "USB_RXBUFSIZEEP5B,Number of Bytes Received in Endpoint 5, Buffer B Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " USB_RXBUFSIZEEP5B ,Size of data received on endpoint 5, buffer B"
|
|
line.long 0x0C "USB_RXBUFSIZEEP6B,Number of Bytes Received in Endpoint 6, Buffer B Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " USB_RXBUFSIZEEP6B ,Size of data received on endpoint 6, buffer B"
|
|
textline ""
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "USB_RXVALID,USB Buffer A and Buffer B Reception Valid Status Register"
|
|
bitfld.long 0x00 14. " USB_RXVALIDEP6B ,Endpoint 6, buffer B reception is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " USB_RXVALIDEP5B ,Endpoint 5, buffer B reception is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 12. " USB_RXVALIDEP4B ,Endpoint 4, buffer B reception is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USB_RXVALIDEP3B ,Endpoint 3, buffer B reception is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " USB_RXVALIDEP2B ,Endpoint 2, buffer B reception is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " USB_RXVALIDEP1B ,Endpoint 1, buffer B reception is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 8. " USB_RXVALIDEP0B ,Endpoint 0, buffer B reception is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 6. " USB_RXVALIDEP6A ,Endpoint 6, buffer A reception is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " USB_RXVALIDEP5A ,Endpoint 5, buffer A reception is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " USB_RXVALIDEP4A ,Endpoint 4, buffer A reception is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_RXVALIDEP3A ,Endpoint 3, buffer A reception is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 2. " USB_RXVALIDEP2A ,Endpoint 2, buffer A reception is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " USB_RXVALIDEP1A ,Endpoint 1, buffer A reception is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0. " USB_RXVALIDEP0A ,Endpoint 0, buffer A reception is valid" "Not valid,Valid"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "USB_BUFCLR,USB IN Buffer Clear Register"
|
|
bitfld.long 0x00 6. " USB_BUFCLRINEP6 ,Force clearing of endpoint 6 in buffer" "No effect,Clear"
|
|
bitfld.long 0x00 5. " USB_BUFCLRINEP5 ,Force clearing of endpoint 5 in buffer" "No effect,Clear"
|
|
bitfld.long 0x00 4. " USB_BUFCLRINEP4 ,Force clearing of endpoint 4 in buffer" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_BUFCLRINEP3 ,Force clearing of endpoint 3 in buffer" "No effect,Clear"
|
|
bitfld.long 0x00 2. " USB_BUFCLRINEP2 ,Force clearing of endpoint 2 in buffer" "No effect,Clear"
|
|
bitfld.long 0x00 1. " USB_BUFCLRINEP1 ,Force clearing of endpoint 1 in buffer" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " USB_BUFCLRINEP0 ,Force clearing of endpoint 0 in buffer" "No effect,Clear"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "USB_STALLIN,USB Endpoint IN Stall Register"
|
|
bitfld.long 0x00 6. " USB_STALLINEP6 ,Stall endpoint 6 in" "No effect,Stall"
|
|
bitfld.long 0x00 5. " USB_STALLINEP5 ,Stall endpoint 5 in" "No effect,Stall"
|
|
bitfld.long 0x00 4. " USB_STALLINEP4 ,Stall endpoint 4 in" "No effect,Stall"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_STALLINEP3 ,Stall endpoint 3 in" "No effect,Stall"
|
|
bitfld.long 0x00 2. " USB_STALLINEP2 ,Stall endpoint 2 in" "No effect,Stall"
|
|
bitfld.long 0x00 1. " USB_STALLINEP1 ,Stall endpoint 1 in" "No effect,Stall"
|
|
textline " "
|
|
bitfld.long 0x00 0. " USB_STALLINEP0 ,Stall endpoint 0 in" "No effect,Stall"
|
|
line.long 0x00 "USB_STALLOUT,USB Endpoint OUT Stall Register"
|
|
bitfld.long 0x00 6. " USB_STALLOUTEP6 ,Stall endpoint 6 out" "No effect,Stall"
|
|
bitfld.long 0x00 5. " USB_STALLOUTEP5 ,Stall endpoint 5 out" "No effect,Stall"
|
|
bitfld.long 0x00 4. " USB_STALLOUTEP4 ,Stall endpoint 4 out" "No effect,Stall"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_STALLOUTEP3 ,Stall endpoint 3 out" "No effect,Stall"
|
|
bitfld.long 0x00 2. " USB_STALLOUTEP2 ,Stall endpoint 2 out" "No effect,Stall"
|
|
bitfld.long 0x00 1. " USB_STALLOUTEP1 ,Stall endpoint 1 out" "No effect,Stall"
|
|
textline " "
|
|
bitfld.long 0x00 0. " USB_STALLOUTEP0 ,Stall endpoint 0 out" "No effect,Stall"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "USB_RESUME,USB Resume Register"
|
|
bitfld.long 0x00 0. " USB_RESUME ,Resume from the suspended state (remote-wakeup)" "No effect,Resume"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "USB_PIPECLR,USB Force DMA Pipeline Clearing Register"
|
|
bitfld.long 0x00 1. " USB_RXPIPECLR ,Force clearing of the receive DMA pipeline" "No effect,Clear"
|
|
bitfld.long 0x00 0. " USB_TXPIPECLR ,Force clearing of the transmit DMA pipeline" "No effect,Clear"
|
|
base ad:0x4000A800
|
|
group.long 0x88++0x07 "Interrupt Registers"
|
|
line.long 0x00 "INT_USBFLAG,USB Interrupt Flag Register"
|
|
bitfld.long 0x00 23. " INT_USBWAKEUP ,A successful remote wakeup pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " INT_USBRESUME ,Resume on the bus pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " INT_USBSUSPEND ,Suspending this device pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INT_USBRESET ,USB reset pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " NT_USBSOF ,A start of frame packet pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " INT_USBNAK ,A NAK handshake packet pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INT_USBPIPERXOVF ,Pipeline reception overflow pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " INT_USBPIPETXUND ,Pipeline transmit underflow pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " INT_USBBUFRXOVF ,Buffer reception overflow pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " INT_USBBUFTXUND ,Buffer transmit underflow pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INT_USBRXVALIDEP6 ,The rising edge of either USB_RXVALIDEP6A/B bit pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " INT_USBRXVALIDEP5 ,The rising edge of either USB_RXVALIDEP5A/B bit pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " INT_USBRXVALIDEP4 ,The rising edge of either USB_RXVALIDEP4A/B bit pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INT_USBRXVALIDEP3 ,The rising edge of either USB_RXVALIDEP3A/B bit pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " INT_USBRXVALIDEP2 ,The rising edge of either USB_RXVALIDEP2A/B bit pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " INT_USBRXVALIDEP1 ,The rising edge of either USB_RXVALIDEP1A/B bit pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INT_USBRXVALIDEP0 ,The rising edge of either USB_RXVALIDEP0A/B bit pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INT_USBTXACTIVEEP6 ,The falling edge of either USB_TXACTIVEEP6A/B bit pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " INT_USBTXACTIVEEP5 ,The falling edge of either USB_TXACTIVEEP5A/B bit pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " INT_USBTXACTIVEEP4 ,The falling edge of either USB_TXACTIVEEP4A/B bit pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_USBTXACTIVEEP3 ,The falling edge of either USB_TXACTIVEEP3A/B bit pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " INT_USBTXACTIVEEP2 ,The falling edge of either USB_TXACTIVEEP2A/B bit pends interrupt" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " INT_USBTXACTIVEEP1 ,The falling edge of either USB_TXACTIVEEP1A/B bit pends interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INT_USBTXACTIVEEP0 ,The falling edge of either USB_TXACTIVEEP0A/B bit pends interrupt" "Not pending,Pending"
|
|
line.long 0x04 " INT_USBCFG,USB Interrupt Configuration Register"
|
|
bitfld.long 0x04 23. " INT_USBWAKEUP ,A successful remote wakeup by this device interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " INT_USBRESUME ,A resume on the bus interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " INT_USBSUSPEND ,Suspending this device interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " INT_USBRESET ,Core reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " NT_USBSOF ,A start of frame packet interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INT_USBNAK ,A NAK handshake packet interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INT_USBPIPERXOVF ,Pipeline reception overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " INT_USBPIPETXUND ,Pipeline transmit underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " INT_USBBUFRXOVF ,Buffer reception overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " INT_USBBUFTXUND ,Buffer transmit underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INT_USBRXVALIDEP6 ,The rising edge of either USB_RXVALIDEP6A/B bit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INT_USBRXVALIDEP5 ,The rising edge of either USB_RXVALIDEP5A/B bit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " INT_USBRXVALIDEP4 ,The rising edge of either USB_RXVALIDEP4A/B bit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " INT_USBRXVALIDEP3 ,The rising edge of either USB_RXVALIDEP3A/B bit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " INT_USBRXVALIDEP2 ,The rising edge of either USB_RXVALIDEP2A/B bit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INT_USBRXVALIDEP1 ,The rising edge of either USB_RXVALIDEP1A/B bit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INT_USBRXVALIDEP0 ,The rising edge of either USB_RXVALIDEP0A/B bit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INT_USBTXACTIVEEP6 ,The falling edge of either USB_TXACTIVEEP6A/B bit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " INT_USBTXACTIVEEP5 ,The falling edge of either USB_TXACTIVEEP5A/B bit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " INT_USBTXACTIVEEP4 ,The falling edge of either USB_TXACTIVEEP4A/B bit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INT_USBTXACTIVEEP3 ,The falling edge of either USB_TXACTIVEEP3A/B bit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INT_USBTXACTIVEEP2 ,The falling edge of either USB_TXACTIVEEP2A/B bit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INT_USBTXACTIVEEP1 ,The falling edge of either USB_TXACTIVEEP1A/B bit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INT_USBTXACTIVEEP0 ,The falling edge of either USB_TXACTIVEEP0A/B bit interrupt enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "General Purpose Timers"
|
|
tree "TIM1"
|
|
base ad:0x4000F000
|
|
width 12.
|
|
if (((per.l(ad:0x4000F000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIM1_CR1,Timer 1 Control Register 1"
|
|
bitfld.long 0x00 7. " TIM_ARBE ,Auto-reload buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " TIM_CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3"
|
|
bitfld.long 0x00 4. " TIM_DIR ,Timer direction" "Count up,Count down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIM_OPM ,One pulse mode" "Not stop,Stop"
|
|
bitfld.long 0x00 2. " TIM_URS ,Update request source" "Immediate,On over/under flow"
|
|
bitfld.long 0x00 1. " TIM_UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIM_CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
if (((per.l(ad:0x4000F000))&0x60)!=0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIM1_CR1,Timer 1 Control Register 1"
|
|
bitfld.long 0x00 7. " TIM_ARBE ,Auto-reload buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " TIM_CMS ,Center-aligned mode selection" ",Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3"
|
|
bitfld.long 0x00 4. " TIM_DIR ,Timer direction" "Count up,Count down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIM_OPM ,One pulse mode" "Not stop,Stop"
|
|
bitfld.long 0x00 2. " TIM_URS ,Update request source" "Immediate,On over/under flow"
|
|
bitfld.long 0x00 1. " TIM_UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIM_CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIM1_CR1,Timer 1 Control Register 1"
|
|
bitfld.long 0x00 7. " TIM_ARBE ,Auto-reload buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " TIM_CMS ,Center-aligned mode selection" "Edge-aligned,?..."
|
|
bitfld.long 0x00 4. " TIM_DIR ,Timer direction" "Count up,Count down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIM_OPM ,One pulse mode" "Not stop,Stop"
|
|
bitfld.long 0x00 2. " TIM_URS ,Update request source" "Immediate,On over/under flow"
|
|
bitfld.long 0x00 1. " TIM_UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIM_CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TIM1_CR2,Timer 1 Control Register 2"
|
|
bitfld.long 0x00 7. " TIM_TI1S ,TI1 Selection" "TI1 input,TI_HALL"
|
|
bitfld.long 0x00 4.--6. " TIM_MMS ,Master mode selection" "Reset,Enable,Update,Compare pulse,Compare with OC1REF,Compare with OC2REF,Compare with OC3REF,Compare with OC4REF"
|
|
if (((per.l(ad:0x4000F000+0x08))&0x07)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x08))&0x70)==0x40)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM1_SMCR,Timer 1 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " TIM_ETP ,External trigger polarity" "High level/Rising edge,Low level/Falling edge"
|
|
bitfld.long 0x00 14. " TIM_ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TIM_ETPS ,External trigger prescaler" "Disabled,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TIM_ETF ,External trigger filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 7. " TIM_MSM ,Master/slave mode" "No effect,Delay effect of TRGI"
|
|
bitfld.long 0x00 4.--6. " TIM_TS ,Trigger selection" "ITR0,,,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TIM_SMS ,Slave Mode Selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset mode,,Trigger mode,External clock mode 1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM1_SMCR,Timer 1 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " TIM_ETP ,External trigger polarity" "High level/Rising edge,Low level/Falling edge"
|
|
bitfld.long 0x00 14. " TIM_ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TIM_ETPS ,External trigger prescaler" "Disabled,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TIM_ETF ,External trigger filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 7. " TIM_MSM ,Master/slave mode" "No effect,Delay effect of TRGI"
|
|
bitfld.long 0x00 4.--6. " TIM_TS ,Trigger selection" "ITR0,,,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TIM_SMS ,Slave Mode Selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset mode,Gated mode,Trigger mode,External clock mode 1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x08))&0x70)==0x40)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM1_SMCR,Timer 1 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " TIM_ETP ,External trigger polarity" "High level/Rising edge,Low level/Falling edge"
|
|
bitfld.long 0x00 14. " TIM_ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TIM_ETPS ,External trigger prescaler" "Disabled,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TIM_ETF ,External trigger filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 7. " TIM_MSM ,Master/slave mode" "No effect,Delay effect of TRGI"
|
|
rbitfld.long 0x00 4.--6. " TIM_TS ,Trigger selection" "ITR0,,,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TIM_SMS ,Slave Mode Selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset mode,,Trigger mode,External clock mode 1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM1_SMCR,Timer 1 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " TIM_ETP ,External trigger polarity" "High level/Rising edge,Low level/Falling edge"
|
|
bitfld.long 0x00 14. " TIM_ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TIM_ETPS ,External trigger prescaler" "Disabled,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TIM_ETF ,External trigger filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 7. " TIM_MSM ,Master/slave mode" "No effect,Delay effect of TRGI"
|
|
rbitfld.long 0x00 4.--6. " TIM_TS ,Trigger selection" "ITR0,,,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TIM_SMS ,Slave Mode Selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset mode,Gated mode,Trigger mode,External clock mode 1"
|
|
endif
|
|
endif
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "TIM1_EGR,Timer 1 Event Generation Register"
|
|
bitfld.long 0x00 6. " TIM_TG ,Trigger generation" "No effect,Set TIM_TIF flag"
|
|
bitfld.long 0x00 4. " TIM_CC4G ,Capture/compare 4 generation" "No effect,Set TIM_CC4IF flag"
|
|
bitfld.long 0x00 3. " TIM_CC3G ,Capture/compare 3 generation" "No effect,Set TIM_CC3IF flag"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIM_CC2G ,Capture/compare 2 generation" "No effect,Set TIM_CC2IF flag"
|
|
bitfld.long 0x00 1. " TIM_CC1G ,Capture/compare 1 generation" "No effect,Set TIM_CC1IF flag"
|
|
bitfld.long 0x00 0. " TIM_UG ,Update generation" "No effect,Re-initializes"
|
|
textline ""
|
|
if (((per.l(ad:0x4000F000+0x20))&0x01)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x18))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x20))&0x010)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output compare 2 mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output Compare 2 Mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x20))&0x010)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output compare 2 mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output Compare 2 Mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x18))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x20))&0x010)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output compare 2 mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output Compare 2 Mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x20))&0x010)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output compare 2 mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output Compare 2 Mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM1_CCMR1,Timer 1 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4000F000+0x20))&0x100)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x20))&0x1000)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x20))&0x1000)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x20))&0x1000)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC2REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC2REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x20))&0x1000)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC2REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC2REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM1_CCMR2,Timer 1 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4000F000+0x18))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM1_CCER,Timer 1 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "TIM1_CNT,Timer 1 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CNT ,Counter value"
|
|
line.long 0x04 "TIM1_PSC,Timer 1 Prescaler Register"
|
|
bitfld.long 0x04 0.--3. " TIM_PSC ,Timer prescaler value" "fCK_PSC / 1,fCK_PSC / 2,fCK_PSC / 4,fCK_PSC / 8,fCK_PSC / 16,fCK_PSC / 32,fCK_PSC / 64,fCK_PSC / 128,fCK_PSC / 256,fCK_PSC / 512,fCK_PSC / 1024,fCK_PSC / 2048,fCK_PSC / 4096,fCK_PSC / 8192,fCK_PSC / 16384,fCK_PSC / 32768"
|
|
textline ""
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "TIM1_ARR,Timer 1 Auto-Reload Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
if (((per.l(ad:0x4000F000+0x18))&0x03)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TIM1_CCR1,Timer 1 Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,Buffer value to be loaded in the actual capture 1 register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TIM1_CCR1,Timer 1 Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,The counter value transferred by the last input capture 1 event"
|
|
endif
|
|
if (((per.l(ad:0x4000F000+0x18))&0x300)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TIM1_CCR2,Timer 1 Capture/Compare Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,Buffer value to be loaded in the actual capture 2 register"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TIM1_CCR2,Timer 1 Capture/Compare Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,The counter value transferred by the last input capture 2 event"
|
|
endif
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x03)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TIM1_CCR3,Timer 1 Capture/Compare Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,Buffer value to be loaded in the actual capture 3 register"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TIM1_CCR3,Timer 1 Capture/Compare Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,The counter value transferred by the last input capture 3 event"
|
|
endif
|
|
if (((per.l(ad:0x4000F000+0x1C))&0x300)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TIM1_CCR4,Timer 1 Capture/Compare Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,Buffer value to be loaded in the actual capture 4 register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TIM1_CCR4,Timer 1 Capture/Compare Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,The counter value transferred by the last input capture 4 event"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TIM1_OR,Timer 1 Option Register"
|
|
bitfld.long 0x00 2. " TIM_CLKMSKEN ,Enable TIM1MSK when TIM1CLK is selected as the external trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_EXTRIGSEL ,Selects the external trigger used in external clock mode 2" "PCLK,Callibrated 1kHz,32kHz reference,TIM1CLK pin"
|
|
width 14.
|
|
base ad:0x4000A800
|
|
group.long 0x40++0x03 "Interrupt Registers"
|
|
line.long 0x00 "INT_TIM1CFG,Timer 1 Interrupt Configuration Register"
|
|
bitfld.long 0x00 6. " INT_TIMTIF ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_TIMCC4IF ,Capture or compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_TIMCC3IF ,Capture or compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_TIMCC2IF ,Capture or compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_TIMCC1IF ,Capture or compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INT_TIMUIF ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_TIM1FLAG,Timer 1 Interrupt Flag Register"
|
|
rbitfld.long 0x00 9.--12. " INT_TIMRSVD ,May change during normal operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " INT_TIMTIF ,Trigger interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INT_TIMCC4IF ,Capture or compare 4 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_TIMCC3IF ,Capture or compare 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " INT_TIMCC2IF ,Capture or compare 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " INT_TIMCC1IF ,Capture or compare 1 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INT_TIMUIF ,Update interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "INT_TIM1MISS,Timer 1 Missed Interrupt Register"
|
|
bitfld.long 0x00 12. " INT_TIMMISSCC4IF ,Capture or compare 4 interrupt missed" "Not missed,Missed"
|
|
bitfld.long 0x00 11. " INT_TIMMISSCC3IF ,Capture or compare 3 interrupt missed" "Not missed,Missed"
|
|
bitfld.long 0x00 10. " INT_TIMMISSCC2IF ,Capture or compare 2 interrupt missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INT_TIMMISSCC1IF ,Capture or compare 1 interrupt missed" "Not missed,Missed"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INT_TIMMISSRSVD ,May change during normal operation"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM2"
|
|
base ad:0x40010000
|
|
width 12.
|
|
if (((per.l(ad:0x40010000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIM2_CR1,Timer 2 Control Register 1"
|
|
bitfld.long 0x00 7. " TIM_ARBE ,Auto-reload buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " TIM_CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3"
|
|
bitfld.long 0x00 4. " TIM_DIR ,Timer direction" "Count up,Count down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIM_OPM ,One pulse mode" "Not stop,Stop"
|
|
bitfld.long 0x00 2. " TIM_URS ,Update request source" "Immediate,On over/under flow"
|
|
bitfld.long 0x00 1. " TIM_UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIM_CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
if (((per.l(ad:0x40010000))&0x60)!=0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIM2_CR1,Timer 2 Control Register 1"
|
|
bitfld.long 0x00 7. " TIM_ARBE ,Auto-reload buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " TIM_CMS ,Center-aligned mode selection" ",Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3"
|
|
bitfld.long 0x00 4. " TIM_DIR ,Timer direction" "Count up,Count down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIM_OPM ,One pulse mode" "Not stop,Stop"
|
|
bitfld.long 0x00 2. " TIM_URS ,Update request source" "Immediate,On over/under flow"
|
|
bitfld.long 0x00 1. " TIM_UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIM_CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIM2_CR1,Timer 2 Control Register 1"
|
|
bitfld.long 0x00 7. " TIM_ARBE ,Auto-reload buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " TIM_CMS ,Center-aligned mode selection" "Edge-aligned,?..."
|
|
bitfld.long 0x00 4. " TIM_DIR ,Timer direction" "Count up,Count down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIM_OPM ,One pulse mode" "Not stop,Stop"
|
|
bitfld.long 0x00 2. " TIM_URS ,Update request source" "Immediate,On over/under flow"
|
|
bitfld.long 0x00 1. " TIM_UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIM_CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TIM2_CR2,Timer 2 Control Register 2"
|
|
bitfld.long 0x00 7. " TIM_TI1S ,TI1 Selection" "TI1 input,TI_HALL"
|
|
bitfld.long 0x00 4.--6. " TIM_MMS ,Master mode selection" "Reset,Enable,Update,Compare pulse,Compare with OC1REF,Compare with OC2REF,Compare with OC3REF,Compare with OC4REF"
|
|
if (((per.l(ad:0x40010000+0x08))&0x07)==0x00)
|
|
if (((per.l(ad:0x40010000+0x08))&0x70)==0x40)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM2_SMCR,Timer 1 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " TIM_ETP ,External trigger polarity" "High level/Rising edge,Low level/Falling edge"
|
|
bitfld.long 0x00 14. " TIM_ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TIM_ETPS ,External trigger prescaler" "Disabled,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TIM_ETF ,External trigger filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 7. " TIM_MSM ,Master/slave mode" "No effect,Delay effect of TRGI"
|
|
bitfld.long 0x00 4.--6. " TIM_TS ,Trigger selection" "ITR0,,,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TIM_SMS ,Slave Mode Selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset mode,,Trigger mode,External clock mode 1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM2_SMCR,Timer 1 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " TIM_ETP ,External trigger polarity" "High level/Rising edge,Low level/Falling edge"
|
|
bitfld.long 0x00 14. " TIM_ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TIM_ETPS ,External trigger prescaler" "Disabled,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TIM_ETF ,External trigger filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 7. " TIM_MSM ,Master/slave mode" "No effect,Delay effect of TRGI"
|
|
bitfld.long 0x00 4.--6. " TIM_TS ,Trigger selection" "ITR0,,,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TIM_SMS ,Slave Mode Selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset mode,Gated mode,Trigger mode,External clock mode 1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x08))&0x70)==0x40)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM2_SMCR,Timer 1 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " TIM_ETP ,External trigger polarity" "High level/Rising edge,Low level/Falling edge"
|
|
bitfld.long 0x00 14. " TIM_ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TIM_ETPS ,External trigger prescaler" "Disabled,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TIM_ETF ,External trigger filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 7. " TIM_MSM ,Master/slave mode" "No effect,Delay effect of TRGI"
|
|
rbitfld.long 0x00 4.--6. " TIM_TS ,Trigger selection" "ITR0,,,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TIM_SMS ,Slave Mode Selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset mode,,Trigger mode,External clock mode 1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM2_SMCR,Timer 1 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " TIM_ETP ,External trigger polarity" "High level/Rising edge,Low level/Falling edge"
|
|
bitfld.long 0x00 14. " TIM_ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TIM_ETPS ,External trigger prescaler" "Disabled,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TIM_ETF ,External trigger filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 7. " TIM_MSM ,Master/slave mode" "No effect,Delay effect of TRGI"
|
|
rbitfld.long 0x00 4.--6. " TIM_TS ,Trigger selection" "ITR0,,,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TIM_SMS ,Slave Mode Selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset mode,Gated mode,Trigger mode,External clock mode 1"
|
|
endif
|
|
endif
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "TIM2_EGR,Timer 2 Event Generation Register"
|
|
bitfld.long 0x00 6. " TIM_TG ,Trigger generation" "No effect,Set TIM_TIF flag"
|
|
bitfld.long 0x00 4. " TIM_CC4G ,Capture/compare 4 generation" "No effect,Set TIM_CC4IF flag"
|
|
bitfld.long 0x00 3. " TIM_CC3G ,Capture/compare 3 generation" "No effect,Set TIM_CC3IF flag"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIM_CC2G ,Capture/compare 2 generation" "No effect,Set TIM_CC2IF flag"
|
|
bitfld.long 0x00 1. " TIM_CC1G ,Capture/compare 1 generation" "No effect,Set TIM_CC1IF flag"
|
|
bitfld.long 0x00 0. " TIM_UG ,Update generation" "No effect,Re-initializes"
|
|
textline ""
|
|
if (((per.l(ad:0x40010000+0x20))&0x01)==0x00)
|
|
if (((per.l(ad:0x40010000+0x18))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x20))&0x010)==0x00)
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output compare 2 mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output Compare 2 Mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x20))&0x010)==0x00)
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output compare 2 mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output Compare 2 Mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x18))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x20))&0x010)==0x00)
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output compare 2 mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output Compare 2 Mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC1M ,Output compare 1 mode" "Frozen,Set OC1REF to high on match,Set OC1REF to low on match,Toggle OC1REF,OC1REF inactive,OC1REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC1BE ,Output compare 1 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x20))&0x010)==0x00)
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output compare 2 mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. " TIM_OC2M ,Output Compare 2 Mode" "Frozen,Set OC2REF to high on match,Set OC2REF to low on match,Toggle OC2REF,OC2REF inactive,OC2REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC2BE ,Output compare 2 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC2FE ,Output compare 2 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Timer 2 Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " TIM_IC2F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " TIM_IC2PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC2S ,Capture/compare 2 selection" "Output,Input | mapped to TI2,Input | mapped to TI1,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC1F ,Input capture 1 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC1PSC ,Input capture 1 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC1S ,Capture/compare 1 selection" "Output,Input | mapped to TI1,Input | mapped to TI2,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x20))&0x100)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x20))&0x1000)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x20))&0x1000)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x20))&0x1000)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC2REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC4REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC3REF to high on match,Set OC3REF to low on match,Toggle OC3REF,OC3REF inactive,OC3REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIM_OC3M ,Output compare 3 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC2REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 3. " TIM_OC3BE ,Output compare 3 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM_OC3FE ,Output compare 3 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x20))&0x1000)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC2REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--14. " TIM_OC4M ,Output compare 4 mode" "Frozen,Set OC4REF to high on match,Set OC4REF to low on match,Toggle OC4REF,OC2REF inactive,OC4REF active,PWM mode 1,PWM mode 2"
|
|
bitfld.long 0x00 11. " TIM_OC4BE ,Output compare 4 buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIM_OC4FE ,Output compare 4 fast enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIM2_CCMR2,Timer 2 Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " TIM_IC4F ,Input capture 4 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x0 010.--11. " TIM_IC4PSC ,Input capture 4 prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 8.--9. " TIM_CC4S ,Capture/compare 4 selection" "Output,Input | mapped to TI4,Input | mapped to TI3,Input | mapped to TRGI"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TIM_IC3F ,Input capture 3 filter" "Fsampling=PCLK | no filtering,Fsampling=PCLK | N=2,Fsampling=PCLK | N=4,Fsampling=PCLK | N=8,Fsampling=PCLK/2 | N=6,Fsampling=PCLK/2 | N=8,Fsampling=PCLK/4 | N=6,Fsampling=PCLK/4 | N=8,Fsampling=PCLK/8 | N=6,Fsampling=PCLK/8 | N=8,Fsampling=PCLK/16 | N=5,Fsampling=PCLK/16 | N=6,Fsampling=PCLK/16 | N=8,Fsampling=PCLK/32 | N=5,Fsampling=PCLK/32 | N=6,Fsampling=PCLK/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " TIM_IC3PSC ,Input Capture 3 Prescaler" "No prescaling,Once every 2 events,Once every 4 events,Once every 8 events"
|
|
textfld " "
|
|
rbitfld.long 0x00 0.--1. " TIM_CC3S ,Capture/compare 3 selection" "Output,Input | mapped to TI3,Input | mapped to TI4,Input | mapped to TRGI"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x18))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x03)==0x00)
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Compare 3 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Compare 4 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIM2_CCER,Timer 2 Capture/Compare Enable Register"
|
|
bitfld.long 0x00 13. " TIM_CC4P ,Capture 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " TIM_CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIM_CC3P ,Capture 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8. " TIM_CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIM_CC2P ,Capture 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " TIM_CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM_CC1P ,Capture 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " TIM_CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "TIM2_CNT,Timer 2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CNT ,Counter value"
|
|
line.long 0x04 "TIM2_PSC,Timer 2 Prescaler Register"
|
|
bitfld.long 0x04 0.--3. " TIM_PSC ,Timer prescaler value" "fCK_PSC / 1,fCK_PSC / 2,fCK_PSC / 4,fCK_PSC / 8,fCK_PSC / 16,fCK_PSC / 32,fCK_PSC / 64,fCK_PSC / 128,fCK_PSC / 256,fCK_PSC / 512,fCK_PSC / 1024,fCK_PSC / 2048,fCK_PSC / 4096,fCK_PSC / 8192,fCK_PSC / 16384,fCK_PSC / 32768"
|
|
textline ""
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "TIM2_ARR,Timer 2 Auto-Reload Register"
|
|
textfld " "
|
|
in
|
|
textline ""
|
|
if (((per.l(ad:0x40010000+0x18))&0x03)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TIM2_CCR1,Timer 2 Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,Buffer value to be loaded in the actual capture 1 register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TIM2_CCR1,Timer 2 Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,The counter value transferred by the last input capture 1 event"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x18))&0x300)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TIM2_CCR2,Timer 2 Capture/Compare Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,Buffer value to be loaded in the actual capture 2 register"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TIM2_CCR2,Timer 2 Capture/Compare Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,The counter value transferred by the last input capture 2 event"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x1C))&0x03)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TIM2_CCR3,Timer 2 Capture/Compare Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,Buffer value to be loaded in the actual capture 3 register"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TIM2_CCR3,Timer 2 Capture/Compare Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,The counter value transferred by the last input capture 3 event"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x1C))&0x300)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TIM2_CCR4,Timer 2 Capture/Compare Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,Buffer value to be loaded in the actual capture 4 register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TIM2_CCR4,Timer 2 Capture/Compare Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_CCR ,The counter value transferred by the last input capture 4 event"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TIM2_OR,Timer 2 Option Register"
|
|
bitfld.long 0x00 7. " TIM_REMAPC4 ,Selects the GPIO used for TIM2C4" "PA2,PB4"
|
|
bitfld.long 0x00 6. " TIM_REMAPC3 ,Selects the GPIO used for TIM2C3" "PA1,PB3"
|
|
bitfld.long 0x00 5. " TIM_REMAPC2 ,Selects the GPIO used for TIM2C2" "PA3,PB2"
|
|
bitfld.long 0x00 4. " TIM_REMAPC1 ,Selects the GPIO used for TIM2C1" "PA0,PB1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIM_CLKMSKEN ,Enable TIM1MSK when TIM1CLK is selected as the external trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TIM_EXTRIGSEL ,Selects the external trigger used in external clock mode 2" "PCLK,Callibrated 1kHz,32kHz reference,TIM1CLK pin"
|
|
width 14.
|
|
base ad:0x4000A804
|
|
group.long 0x40++0x03 "Interrupt Registers"
|
|
line.long 0x00 "INT_TIM2CFG,Timer 2 Interrupt Configuration Register"
|
|
bitfld.long 0x00 6. " INT_TIMTIF ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_TIMCC4IF ,Capture or compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT_TIMCC3IF ,Capture or compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT_TIMCC2IF ,Capture or compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_TIMCC1IF ,Capture or compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INT_TIMUIF ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_TIM2FLAG,Timer 2 Interrupt Flag Register"
|
|
rbitfld.long 0x00 9.--12. " INT_TIMRSVD ,May change during normal operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " INT_TIMTIF ,Trigger interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INT_TIMCC4IF ,Capture or compare 4 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_TIMCC3IF ,Capture or compare 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " INT_TIMCC2IF ,Capture or compare 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " INT_TIMCC1IF ,Capture or compare 1 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INT_TIMUIF ,Update interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "INT_TIM2MISS,Timer 2 Missed Interrupt Register"
|
|
bitfld.long 0x00 12. " INT_TIMMISSCC4IF ,Capture or compare 4 interrupt missed" "Not missed,Missed"
|
|
bitfld.long 0x00 11. " INT_TIMMISSCC3IF ,Capture or compare 3 interrupt missed" "Not missed,Missed"
|
|
bitfld.long 0x00 10. " INT_TIMMISSCC2IF ,Capture or compare 2 interrupt missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INT_TIMMISSCC1IF ,Capture or compare 1 interrupt missed" "Not missed,Missed"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INT_TIMMISSRSVD ,May change during normal operation"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "ADC (Analog to Digital Converter)"
|
|
base ad:0x4000E000
|
|
width 9.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DATA,ADC Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_FIELD ,ADC conversion result"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "CFG,ADC Configuration Register"
|
|
bitfld.long 0x00 13.--15. " PERIOD ,ADC sample time (in clocks) and the equivalent significant bits in the conversion" "32 clocks | 7 bits,64 clocks | 8 bits,128 clocks | 9 bits,256 clocks | 10 bits,512 clocks | 11 bits,1024 clocks | 12 bits,2048 clocks | 13 bits,4096 clocks | 14 bits"
|
|
bitfld.long 0x00 7.--10. " MUXP ,Input selection for the P channel" "PB5 pin,PB6 pin,PB7 pin,PC1 pin,PA4 pin,PA5 pin,,,GND,VREF/2,VREF,VDD_PADSA/2,?..."
|
|
bitfld.long 0x00 3.--6. " MUXN ,Input selection for the N channel" "PB5 pin,PB6 pin,PB7 pin,PC1 pin,PA4 pin,PA5 pin,,,GND,VREF/2,VREF,VDD_PADSA/2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " 1MHZCLK ,Select ADC clock" "6MHz,1MHz"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable continuous conversions the ADC" "Disabled,Enabled"
|
|
line.long 0x04 "OFFSET,ADC Offset Register"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " OFFSET_FIELD ,Offset added to the basic ADC conversion result before gain correction is applied"
|
|
line.long 0x08 "GAIN,ADC Gain Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " GAIN_FIELD ,Gain factor that is multiplied by the offset-corrected ADC result to produce the output value"
|
|
textline ""
|
|
line.long 0x0C "DMACFG,ADC DMA Configuration Register"
|
|
bitfld.long 0x0C 4. " DMARST ,Reset the ADC DMA" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DMAAUTOWRAP ,Selects DMA mode" "Linear,Auto-wrap"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " DMALOAD ,Load the DMA buffer" "No effect,Start"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "DMASTAT,ADC DMA Status Register"
|
|
bitfld.long 0x00 1. " DMAOVF ,DMA overflow" "Not overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAACT ,DMA active status" "Not active,Active"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "DMABEG,ADC DMA Begin Address Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " DMABEG ,ADC buffer start address"
|
|
line.long 0x04 "DMASIZE,ADC DMA Buffer Size Register"
|
|
hexmask.long.word 0x04 0.--14. 1. " DMASIZE_FIELD ,ADC buffer size"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "DMACUR,ADC DMA Current Address Register"
|
|
hexmask.long.word 0x00 1.--15. 0x02 " DMACUR_FIELD ,Current DMA address"
|
|
line.long 0x04 "DMACNT,ADC DMA Count Register"
|
|
hexmask.long.word 0x04 0.--14. 1. " DMACNT_FIELD ,DMA count"
|
|
base ad:0x4000A800
|
|
group.long 0x10++0x03 "Interrupt Registers"
|
|
line.long 0x00 "ADCFLAG,ADC Interrupt Flag Register"
|
|
bitfld.long 0x00 4. " ADCOVF ,DMA buffer overflow interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " ADCSAT ,Gain correction saturation interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " ADCULDFULL ,DMA buffer full interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADCULDHALF ,DMA buffer half full interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " ADCDATA ,ADC_DATA register has data interrupt pending" "Not pending,Pending"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ADCCFG,ADC Interrupt Configuration Register"
|
|
bitfld.long 0x00 4. " ADCOVF ,DMA buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADCSAT ,Gain correction saturation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ADCULDFULL ,DMA buffer full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADCULDHALF ,DMA buffer half full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADCDATA ,ADC_DATA register has data interrupt enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
textline ""
|